From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1136FC433C1 for ; Tue, 30 Mar 2021 16:58:36 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B328C619CC for ; Tue, 30 Mar 2021 16:58:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B328C619CC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 491E16E920; Tue, 30 Mar 2021 16:58:35 +0000 (UTC) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 44B1E6E920 for ; Tue, 30 Mar 2021 16:58:34 +0000 (UTC) IronPort-SDR: 0IpmzqHG5RjSXvtD0vU/DdXTrtsrU8JcGHFsjtTsLAWeXr6DAKRYGD99F2mvEHtA/trlVZFkH8 1zGBJKgIcUiw== X-IronPort-AV: E=McAfee;i="6000,8403,9939"; a="191840769" X-IronPort-AV: E=Sophos;i="5.81,291,1610438400"; d="scan'208";a="191840769" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2021 09:58:31 -0700 IronPort-SDR: rRGHel/GG4eJV5GJvu9ZiVL0dz+cs3xhiNMLneG02drI6zMLP+xF21+zRsHVy7BN8KUpLtb/m1 MQ6cI1Lv2RDQ== X-IronPort-AV: E=Sophos;i="5.81,291,1610438400"; d="scan'208";a="393678542" Received: from invictus.jf.intel.com (HELO InViCtUs) ([10.165.21.205]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Mar 2021 09:58:31 -0700 Date: Tue, 30 Mar 2021 09:58:33 -0700 From: "Sripada, Radhakrishna" To: =?iso-8859-1?Q?Jos=E9?= Roberto de Souza Message-ID: <20210330165833.GB4484@InViCtUs> References: <20210322205805.62205-1-jose.souza@intel.com> <20210322205805.62205-2-jose.souza@intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210322205805.62205-2-jose.souza@intel.com> User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [Intel-gfx] [PATCH v2 2/3] drm/i915: Do not set any power wells when there is no display X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula , intel-gfx@lists.freedesktop.org, Lucas De Marchi Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, Mar 22, 2021 at 01:58:04PM -0700, Jos=E9 Roberto de Souza wrote: > Power wells are only part of display block and not necessary when > running a headless driver. > = > Cc: Lucas De Marchi Reviewed-by: Radhakrishna Sripada > Signed-off-by: Jos=E9 Roberto de Souza > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers= /gpu/drm/i915/display/intel_display_power.c > index 7e0eaa872350..e6a3b3e6b1f7 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_power.c > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c > @@ -4673,7 +4673,10 @@ int intel_power_domains_init(struct drm_i915_priva= te *dev_priv) > * The enabling order will be from lower to higher indexed wells, > * the disabling order is reversed. > */ > - if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { > + if (!HAS_DISPLAY(dev_priv)) { > + power_domains->power_well_count =3D 0; > + err =3D 0; > + } else if (IS_ALDERLAKE_S(dev_priv) || IS_DG1(dev_priv)) { > err =3D set_power_wells_mask(power_domains, tgl_power_wells, > BIT_ULL(TGL_DISP_PW_TC_COLD_OFF)); > } else if (IS_ROCKETLAKE(dev_priv)) { > -- = > 2.31.0 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx