From: Peng Ju Zhou <PengJu.Zhou@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: jianzh@amd.com
Subject: [PATCH 1/4] drm/amdgpu: indirect register access for nv12 sriov
Date: Wed, 31 Mar 2021 13:20:22 +0800 [thread overview]
Message-ID: <20210331052025.24200-1-PengJu.Zhou@amd.com> (raw)
unify host driver and guest driver indirect access
control bits names
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 097af4d3b6b1..3580a746ad9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -110,11 +110,11 @@ enum AMDGIM_FEATURE_FLAG {
enum AMDGIM_REG_ACCESS_FLAG {
/* Use PSP to program IH_RB_CNTL */
- AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
+ AMDGIM_FEATURE_IH_REG_PSP_EN = (1 << 0),
/* Use RLC to program MMHUB regs */
- AMDGIM_FEATURE_RLC_MMHUB_EN = (1 << 1),
+ AMDGIM_FEATURE_MMHUB_REG_RLC_EN = (1 << 1),
/* Use RLC to program GC regs */
- AMDGIM_FEATURE_RLC_GC_EN = (1 << 2),
+ AMDGIM_FEATURE_GC_REG_RLC_EN = (1 << 2),
};
struct amdgim_pf2vf_info_v1 {
--
2.17.1
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next reply other threads:[~2021-03-31 5:20 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-31 5:20 Peng Ju Zhou [this message]
2021-03-31 5:20 ` [PATCH 2/4] drm/amdgpu: indirect register access for nv12 sriov Peng Ju Zhou
2021-03-31 5:20 ` [PATCH 3/4] " Peng Ju Zhou
2021-03-31 5:20 ` [PATCH 4/4] " Peng Ju Zhou
2021-04-01 6:00 ` Deng, Emily
2021-04-04 14:18 ` Chen, Guchun
2021-04-05 23:08 ` Felix Kuehling
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