From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Glass Date: Wed, 7 Apr 2021 16:32:24 +1200 Subject: [PATCH 14/17] x86: coreboot: Document the memory map In-Reply-To: <20210407043228.2268429-1-sjg@chromium.org> References: <20210407043228.2268429-1-sjg@chromium.org> Message-ID: <20210407163159.14.Ib1dccc7a0ad38d4faae3e0a01fd647a35af74ceb@changeid> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Add information about memory usage when U-Boot is started from coreboot. This is useful when debugging. Also, since coreboot takes a chunk of memory in the middle of SDRAM for use by PCI devices, it can help avoid overwriting this with a loaded kernel by accident. Signed-off-by: Simon Glass --- doc/board/coreboot/coreboot.rst | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/doc/board/coreboot/coreboot.rst b/doc/board/coreboot/coreboot.rst index 9c44c025a48..e791b7e39f0 100644 --- a/doc/board/coreboot/coreboot.rst +++ b/doc/board/coreboot/coreboot.rst @@ -50,3 +50,22 @@ works by using a 32-bit SPL binary to switch to 64-bit for running U-Boot. It can be useful for running UEFI applications, for example. This has only been lightly tested. + + +Memory map +---------- + +:: + + ffffffff Top of ROM (and last byte of 32-bit address space) + 7a9fd000 Typical top of memory available to U-Boot + (use cbsysinfo to see where memory range 'table' starts) + 10000000 Memory reserved by coreboot for mapping PCI devices + (typical size 2151000, includes framebuffer) + 1920000 CONFIG_SYS_CAR_ADDR, fake Cache-as-RAM memory, used during startup + 1110000 CONFIG_SYS_TEXT_BASE (start address of U-Boot code, before reloc) + 110000 CONFIG_BLOBLIST_ADDR (before being relocated) + 100000 CONFIG_PRE_CON_BUF_ADDR + f0000 ACPI tables set up by U-Boot + (typically redirects to 7ab10030 or similar) + 500 Location of coreboot sysinfo table, used during startup -- 2.31.0.208.g409f899ff0-goog