From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F8DBC433B4 for ; Thu, 8 Apr 2021 18:57:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6281461041 for ; Thu, 8 Apr 2021 18:57:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232941AbhDHS6A (ORCPT ); Thu, 8 Apr 2021 14:58:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54952 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231676AbhDHS6A (ORCPT ); Thu, 8 Apr 2021 14:58:00 -0400 Received: from mail-out.m-online.net (mail-out.m-online.net [IPv6:2001:a60:0:28:0:1:25:1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A3E4C061760 for ; Thu, 8 Apr 2021 11:57:48 -0700 (PDT) Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4FGVrV6BKcz1s1JW; Thu, 8 Apr 2021 20:57:46 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4FGVrV55gFz1sP6L; Thu, 8 Apr 2021 20:57:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id LiaVNAZLBKFU; Thu, 8 Apr 2021 20:57:45 +0200 (CEST) X-Auth-Info: mKSswWMJwBizmZOvUfcTfxruhPUJhso+JrJkQB+c8pk= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 8 Apr 2021 20:57:44 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 2/7] clk: stm32mp1: The dev is always NULL, replace it with np Date: Thu, 8 Apr 2021 20:57:26 +0200 Message-Id: <20210408185731.135511-3-marex@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408185731.135511-1-marex@denx.de> References: <20210408185731.135511-1-marex@denx.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Instead of passing around $dev to all the registration functions, which is always NULL, pass around struct device_node pointer $np. This way it is possible to use of_clk_hw_register*() functions and/or register clock with associated $np pointer. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- drivers/clk/clk-stm32mp1.c | 56 +++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index a7c7f544ee5d..cf5a1d055c5a 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -317,7 +317,7 @@ struct clock_config { int num_parents; unsigned long flags; void *cfg; - struct clk_hw * (*func)(struct device *dev, + struct clk_hw * (*func)(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg); @@ -377,14 +377,14 @@ struct stm32_composite_cfg { }; static struct clk_hw * -_clk_hw_register_gate(struct device *dev, +_clk_hw_register_gate(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct gate_cfg *gate_cfg = cfg->cfg; - return clk_hw_register_gate(dev, + return clk_hw_register_gate(NULL, cfg->name, cfg->parent_name, cfg->flags, @@ -395,27 +395,27 @@ _clk_hw_register_gate(struct device *dev, } static struct clk_hw * -_clk_hw_register_fixed_factor(struct device *dev, +_clk_hw_register_fixed_factor(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct fixed_factor_cfg *ff_cfg = cfg->cfg; - return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name, + return clk_hw_register_fixed_factor(NULL, cfg->name, cfg->parent_name, cfg->flags, ff_cfg->mult, ff_cfg->div); } static struct clk_hw * -_clk_hw_register_divider_table(struct device *dev, +_clk_hw_register_divider_table(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct div_cfg *div_cfg = cfg->cfg; - return clk_hw_register_divider_table(dev, + return clk_hw_register_divider_table(NULL, cfg->name, cfg->parent_name, cfg->flags, @@ -428,14 +428,14 @@ _clk_hw_register_divider_table(struct device *dev, } static struct clk_hw * -_clk_hw_register_mux(struct device *dev, +_clk_hw_register_mux(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct mux_cfg *mux_cfg = cfg->cfg; - return clk_hw_register_mux(dev, cfg->name, cfg->parent_names, + return clk_hw_register_mux(NULL, cfg->name, cfg->parent_names, cfg->num_parents, cfg->flags, mux_cfg->reg_off + base, mux_cfg->shift, mux_cfg->width, mux_cfg->mux_flags, lock); @@ -570,7 +570,7 @@ _get_stm32_gate(void __iomem *base, } static struct clk_hw * -clk_stm32_register_gate_ops(struct device *dev, +clk_stm32_register_gate_ops(struct device_node *np, const char *name, const char *parent_name, unsigned long flags, @@ -598,7 +598,7 @@ clk_stm32_register_gate_ops(struct device *dev, hw->init = &init; - ret = clk_hw_register(dev, hw); + ret = clk_hw_register(NULL, hw); if (ret) hw = ERR_PTR(ret); @@ -606,7 +606,7 @@ clk_stm32_register_gate_ops(struct device *dev, } static struct clk_hw * -clk_stm32_register_composite(struct device *dev, +clk_stm32_register_composite(struct device_node *np, const char *name, const char * const *parent_names, int num_parents, void __iomem *base, const struct stm32_composite_cfg *cfg, @@ -655,7 +655,7 @@ clk_stm32_register_composite(struct device *dev, } } - return clk_hw_register_composite(dev, name, parent_names, num_parents, + return clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, mux_ops, div_hw, div_ops, gate_hw, gate_ops, flags); } @@ -863,7 +863,7 @@ static const struct clk_ops pll_ops = { .is_enabled = pll_is_enabled, }; -static struct clk_hw *clk_register_pll(struct device *dev, const char *name, +static struct clk_hw *clk_register_pll(struct device_node *np, const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, @@ -889,7 +889,7 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name, element->lock = lock; hw = &element->hw; - err = clk_hw_register(dev, hw); + err = clk_hw_register(NULL, hw); if (err) { kfree(element); @@ -993,7 +993,7 @@ static const struct clk_ops timer_ker_ops = { }; -static struct clk_hw *clk_register_cktim(struct device *dev, const char *name, +static struct clk_hw *clk_register_cktim(struct device_node *np, const char *name, const char *parent_name, unsigned long flags, void __iomem *apbdiv, @@ -1021,7 +1021,7 @@ static struct clk_hw *clk_register_cktim(struct device *dev, const char *name, tim_ker->timpre = timpre; hw = &tim_ker->hw; - err = clk_hw_register(dev, hw); + err = clk_hw_register(NULL, hw); if (err) { kfree(tim_ker); @@ -1035,14 +1035,14 @@ struct stm32_pll_cfg { u32 offset; }; -static struct clk_hw *_clk_register_pll(struct device *dev, +static struct clk_hw *_clk_register_pll(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg; - return clk_register_pll(dev, cfg->name, cfg->parent_name, + return clk_register_pll(np, cfg->name, cfg->parent_name, base + stm_pll_cfg->offset, cfg->flags, lock); } @@ -1051,25 +1051,25 @@ struct stm32_cktim_cfg { u32 offset_timpre; }; -static struct clk_hw *_clk_register_cktim(struct device *dev, +static struct clk_hw *_clk_register_cktim(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct stm32_cktim_cfg *cktim_cfg = cfg->cfg; - return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags, + return clk_register_cktim(np, cfg->name, cfg->parent_name, cfg->flags, cktim_cfg->offset_apbdiv + base, cktim_cfg->offset_timpre + base, lock); } static struct clk_hw * -_clk_stm32_register_gate(struct device *dev, +_clk_stm32_register_gate(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { - return clk_stm32_register_gate_ops(dev, + return clk_stm32_register_gate_ops(np, cfg->name, cfg->parent_name, cfg->flags, @@ -1079,12 +1079,12 @@ _clk_stm32_register_gate(struct device *dev, } static struct clk_hw * -_clk_stm32_register_composite(struct device *dev, +_clk_stm32_register_composite(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { - return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names, + return clk_stm32_register_composite(np, cfg->name, cfg->parent_names, cfg->num_parents, base, cfg->cfg, cfg->flags, lock); } @@ -2020,7 +2020,7 @@ static const struct of_device_id stm32mp1_match_data[] = { { } }; -static int stm32_register_hw_clk(struct device *dev, +static int stm32_register_hw_clk(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) @@ -2031,7 +2031,7 @@ static int stm32_register_hw_clk(struct device *dev, hws = clk_data->hws; if (cfg->func) - hw = (*cfg->func)(dev, clk_data, base, lock, cfg); + hw = (*cfg->func)(np, clk_data, base, lock, cfg); if (IS_ERR(hw)) { pr_err("Unable to register %s\n", cfg->name); @@ -2077,7 +2077,7 @@ static int stm32_rcc_init(struct device_node *np, hws[n] = ERR_PTR(-ENOENT); for (n = 0; n < data->num; n++) { - err = stm32_register_hw_clk(NULL, clk_data, base, &rlock, + err = stm32_register_hw_clk(np, clk_data, base, &rlock, &data->cfg[n]); if (err) { pr_err("%s: can't register %s\n", __func__, -- 2.30.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 933ADC43462 for ; Thu, 8 Apr 2021 19:00:16 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D122610CF for ; Thu, 8 Apr 2021 19:00:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0D122610CF Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Message-Id:Date: Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+EyNDW7l8z5mTqNYwT2qdjCM3Ko2aBuZly/pczLXeu8=; b=oewPfe8z5BuX4bx1pE+UrPTa/ 7R4cuMay934vm/rMBr5raFNmhkAonwV/lA6zuFv8I/NEVKDzSRNs5F3KJqPmSpagw79qPR7qZLNaR Q0udQ6xwU4WivBRvGN3UNfyx/B0PtKbgi8/EV2HM+cc7OeZxk/GXyCWVn59sIufnXoSfau7clNkeC J3nXfDyUqhjeWlPs/r/PGfCwa4ZMmlc7oLYuIBIp6CCdfJ4Pj//UFuMKYK9Ie/v1HNLRglOd/eGXc i+2SHlYnK2PYBLZTjnJQP5z1VUo4TzdphgjSEMd+YstUvgCu+1/B7lHBI3hvlTU8r5v3fLF/TQm/G 43htct6GA==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lUZr3-0091dh-DJ; Thu, 08 Apr 2021 18:58:13 +0000 Received: from mail-out.m-online.net ([212.18.0.10]) by desiato.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lUZqf-0091UG-Qv for linux-arm-kernel@lists.infradead.org; Thu, 08 Apr 2021 18:57:51 +0000 Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 4FGVrV6BKcz1s1JW; Thu, 8 Apr 2021 20:57:46 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 4FGVrV55gFz1sP6L; Thu, 8 Apr 2021 20:57:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id LiaVNAZLBKFU; Thu, 8 Apr 2021 20:57:45 +0200 (CEST) X-Auth-Info: mKSswWMJwBizmZOvUfcTfxruhPUJhso+JrJkQB+c8pk= Received: from tr.lan (ip-89-176-112-137.net.upcbroadband.cz [89.176.112.137]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 8 Apr 2021 20:57:44 +0200 (CEST) From: Marek Vasut To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Alexandre Torgue , Christophe Roullier , Gabriel Fernandez , Patrice Chotard , Patrick Delaunay , Stephen Boyd , linux-clk@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 2/7] clk: stm32mp1: The dev is always NULL, replace it with np Date: Thu, 8 Apr 2021 20:57:26 +0200 Message-Id: <20210408185731.135511-3-marex@denx.de> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210408185731.135511-1-marex@denx.de> References: <20210408185731.135511-1-marex@denx.de> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210408_195749_979252_89EF9D45 X-CRM114-Status: GOOD ( 16.93 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Instead of passing around $dev to all the registration functions, which is always NULL, pass around struct device_node pointer $np. This way it is possible to use of_clk_hw_register*() functions and/or register clock with associated $np pointer. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Christophe Roullier Cc: Gabriel Fernandez Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Stephen Boyd Cc: linux-clk@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org --- drivers/clk/clk-stm32mp1.c | 56 +++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c index a7c7f544ee5d..cf5a1d055c5a 100644 --- a/drivers/clk/clk-stm32mp1.c +++ b/drivers/clk/clk-stm32mp1.c @@ -317,7 +317,7 @@ struct clock_config { int num_parents; unsigned long flags; void *cfg; - struct clk_hw * (*func)(struct device *dev, + struct clk_hw * (*func)(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg); @@ -377,14 +377,14 @@ struct stm32_composite_cfg { }; static struct clk_hw * -_clk_hw_register_gate(struct device *dev, +_clk_hw_register_gate(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct gate_cfg *gate_cfg = cfg->cfg; - return clk_hw_register_gate(dev, + return clk_hw_register_gate(NULL, cfg->name, cfg->parent_name, cfg->flags, @@ -395,27 +395,27 @@ _clk_hw_register_gate(struct device *dev, } static struct clk_hw * -_clk_hw_register_fixed_factor(struct device *dev, +_clk_hw_register_fixed_factor(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct fixed_factor_cfg *ff_cfg = cfg->cfg; - return clk_hw_register_fixed_factor(dev, cfg->name, cfg->parent_name, + return clk_hw_register_fixed_factor(NULL, cfg->name, cfg->parent_name, cfg->flags, ff_cfg->mult, ff_cfg->div); } static struct clk_hw * -_clk_hw_register_divider_table(struct device *dev, +_clk_hw_register_divider_table(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct div_cfg *div_cfg = cfg->cfg; - return clk_hw_register_divider_table(dev, + return clk_hw_register_divider_table(NULL, cfg->name, cfg->parent_name, cfg->flags, @@ -428,14 +428,14 @@ _clk_hw_register_divider_table(struct device *dev, } static struct clk_hw * -_clk_hw_register_mux(struct device *dev, +_clk_hw_register_mux(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct mux_cfg *mux_cfg = cfg->cfg; - return clk_hw_register_mux(dev, cfg->name, cfg->parent_names, + return clk_hw_register_mux(NULL, cfg->name, cfg->parent_names, cfg->num_parents, cfg->flags, mux_cfg->reg_off + base, mux_cfg->shift, mux_cfg->width, mux_cfg->mux_flags, lock); @@ -570,7 +570,7 @@ _get_stm32_gate(void __iomem *base, } static struct clk_hw * -clk_stm32_register_gate_ops(struct device *dev, +clk_stm32_register_gate_ops(struct device_node *np, const char *name, const char *parent_name, unsigned long flags, @@ -598,7 +598,7 @@ clk_stm32_register_gate_ops(struct device *dev, hw->init = &init; - ret = clk_hw_register(dev, hw); + ret = clk_hw_register(NULL, hw); if (ret) hw = ERR_PTR(ret); @@ -606,7 +606,7 @@ clk_stm32_register_gate_ops(struct device *dev, } static struct clk_hw * -clk_stm32_register_composite(struct device *dev, +clk_stm32_register_composite(struct device_node *np, const char *name, const char * const *parent_names, int num_parents, void __iomem *base, const struct stm32_composite_cfg *cfg, @@ -655,7 +655,7 @@ clk_stm32_register_composite(struct device *dev, } } - return clk_hw_register_composite(dev, name, parent_names, num_parents, + return clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, mux_ops, div_hw, div_ops, gate_hw, gate_ops, flags); } @@ -863,7 +863,7 @@ static const struct clk_ops pll_ops = { .is_enabled = pll_is_enabled, }; -static struct clk_hw *clk_register_pll(struct device *dev, const char *name, +static struct clk_hw *clk_register_pll(struct device_node *np, const char *name, const char *parent_name, void __iomem *reg, unsigned long flags, @@ -889,7 +889,7 @@ static struct clk_hw *clk_register_pll(struct device *dev, const char *name, element->lock = lock; hw = &element->hw; - err = clk_hw_register(dev, hw); + err = clk_hw_register(NULL, hw); if (err) { kfree(element); @@ -993,7 +993,7 @@ static const struct clk_ops timer_ker_ops = { }; -static struct clk_hw *clk_register_cktim(struct device *dev, const char *name, +static struct clk_hw *clk_register_cktim(struct device_node *np, const char *name, const char *parent_name, unsigned long flags, void __iomem *apbdiv, @@ -1021,7 +1021,7 @@ static struct clk_hw *clk_register_cktim(struct device *dev, const char *name, tim_ker->timpre = timpre; hw = &tim_ker->hw; - err = clk_hw_register(dev, hw); + err = clk_hw_register(NULL, hw); if (err) { kfree(tim_ker); @@ -1035,14 +1035,14 @@ struct stm32_pll_cfg { u32 offset; }; -static struct clk_hw *_clk_register_pll(struct device *dev, +static struct clk_hw *_clk_register_pll(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct stm32_pll_cfg *stm_pll_cfg = cfg->cfg; - return clk_register_pll(dev, cfg->name, cfg->parent_name, + return clk_register_pll(np, cfg->name, cfg->parent_name, base + stm_pll_cfg->offset, cfg->flags, lock); } @@ -1051,25 +1051,25 @@ struct stm32_cktim_cfg { u32 offset_timpre; }; -static struct clk_hw *_clk_register_cktim(struct device *dev, +static struct clk_hw *_clk_register_cktim(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { struct stm32_cktim_cfg *cktim_cfg = cfg->cfg; - return clk_register_cktim(dev, cfg->name, cfg->parent_name, cfg->flags, + return clk_register_cktim(np, cfg->name, cfg->parent_name, cfg->flags, cktim_cfg->offset_apbdiv + base, cktim_cfg->offset_timpre + base, lock); } static struct clk_hw * -_clk_stm32_register_gate(struct device *dev, +_clk_stm32_register_gate(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { - return clk_stm32_register_gate_ops(dev, + return clk_stm32_register_gate_ops(np, cfg->name, cfg->parent_name, cfg->flags, @@ -1079,12 +1079,12 @@ _clk_stm32_register_gate(struct device *dev, } static struct clk_hw * -_clk_stm32_register_composite(struct device *dev, +_clk_stm32_register_composite(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) { - return clk_stm32_register_composite(dev, cfg->name, cfg->parent_names, + return clk_stm32_register_composite(np, cfg->name, cfg->parent_names, cfg->num_parents, base, cfg->cfg, cfg->flags, lock); } @@ -2020,7 +2020,7 @@ static const struct of_device_id stm32mp1_match_data[] = { { } }; -static int stm32_register_hw_clk(struct device *dev, +static int stm32_register_hw_clk(struct device_node *np, struct clk_hw_onecell_data *clk_data, void __iomem *base, spinlock_t *lock, const struct clock_config *cfg) @@ -2031,7 +2031,7 @@ static int stm32_register_hw_clk(struct device *dev, hws = clk_data->hws; if (cfg->func) - hw = (*cfg->func)(dev, clk_data, base, lock, cfg); + hw = (*cfg->func)(np, clk_data, base, lock, cfg); if (IS_ERR(hw)) { pr_err("Unable to register %s\n", cfg->name); @@ -2077,7 +2077,7 @@ static int stm32_rcc_init(struct device_node *np, hws[n] = ERR_PTR(-ENOENT); for (n = 0; n < data->num; n++) { - err = stm32_register_hw_clk(NULL, clk_data, base, &rlock, + err = stm32_register_hw_clk(np, clk_data, base, &rlock, &data->cfg[n]); if (err) { pr_err("%s: can't register %s\n", __func__, -- 2.30.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel