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From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com,
	LIU Zhiwei <zhiwei_liu@c-sky.com>,
	wxy194768@alibaba-inc.com
Subject: [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode
Date: Fri,  9 Apr 2021 15:48:52 +0800	[thread overview]
Message-ID: <20210409074857.166082-7-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com>

The new CLIC interrupt-handling mode is encoded as a new state in the
existing WARL xtvec register, where the low two bits of are 11.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/csr.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f6c84b9fe4..39ff72041a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -637,9 +637,18 @@ static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
 
 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
 {
-    /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+    /*
+     * bits [1:0] encode mode; 0 = direct, 1 = vectored, 3 = CLIC,
+     * others reserved
+     */
     if ((val & 3) < 2) {
         env->mtvec = val;
+    } else if ((val & 1) && env->clic) {
+        /*
+         * If only CLIC mode is supported, writes to bit 1 are also ignored and
+         * it is always set to one. CLIC mode hardwires xtvec bits 2-5 to zero.
+         */
+        env->mtvec = ((val & ~0x3f) << 6) | (0b000011);
     } else {
         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
     }
@@ -837,9 +846,18 @@ static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
 
 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
 {
-    /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+    /*
+     * bits [1:0] encode mode; 0 = direct, 1 = vectored, 3 = CLIC,
+     * others reserved
+     */
     if ((val & 3) < 2) {
         env->stvec = val;
+    } else if ((val & 1) && env->clic) {
+        /*
+         * If only CLIC mode is supported, writes to bit 1 are also ignored and
+         * it is always set to one. CLIC mode hardwires xtvec bits 2-5 to zero.
+         */
+        env->stvec = ((val & ~0x3f) << 6) | (0b000011);
     } else {
         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
     }
-- 
2.25.1



WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com,
	wxy194768@alibaba-inc.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode
Date: Fri,  9 Apr 2021 15:48:52 +0800	[thread overview]
Message-ID: <20210409074857.166082-7-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20210409074857.166082-1-zhiwei_liu@c-sky.com>

The new CLIC interrupt-handling mode is encoded as a new state in the
existing WARL xtvec register, where the low two bits of are 11.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/csr.c | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f6c84b9fe4..39ff72041a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -637,9 +637,18 @@ static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
 
 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
 {
-    /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+    /*
+     * bits [1:0] encode mode; 0 = direct, 1 = vectored, 3 = CLIC,
+     * others reserved
+     */
     if ((val & 3) < 2) {
         env->mtvec = val;
+    } else if ((val & 1) && env->clic) {
+        /*
+         * If only CLIC mode is supported, writes to bit 1 are also ignored and
+         * it is always set to one. CLIC mode hardwires xtvec bits 2-5 to zero.
+         */
+        env->mtvec = ((val & ~0x3f) << 6) | (0b000011);
     } else {
         qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
     }
@@ -837,9 +846,18 @@ static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
 
 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
 {
-    /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+    /*
+     * bits [1:0] encode mode; 0 = direct, 1 = vectored, 3 = CLIC,
+     * others reserved
+     */
     if ((val & 3) < 2) {
         env->stvec = val;
+    } else if ((val & 1) && env->clic) {
+        /*
+         * If only CLIC mode is supported, writes to bit 1 are also ignored and
+         * it is always set to one. CLIC mode hardwires xtvec bits 2-5 to zero.
+         */
+        env->stvec = ((val & ~0x3f) << 6) | (0b000011);
     } else {
         qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
     }
-- 
2.25.1



  parent reply	other threads:[~2021-04-09  7:51 UTC|newest]

Thread overview: 162+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-09  7:48 [RFC PATCH 00/11] RISC-V: support clic v0.9 specification LIU Zhiwei
2021-04-09  7:48 ` LIU Zhiwei
2021-04-09  7:48 ` [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-04-19 23:23   ` Alistair Francis
2021-04-19 23:23     ` Alistair Francis
2021-04-20  0:49     ` LIU Zhiwei
2021-04-20  0:49       ` LIU Zhiwei
2021-07-01  8:45       ` Frank Chang
2021-07-01  8:45         ` Frank Chang
2021-07-01  9:38         ` LIU Zhiwei
2021-07-01  9:38           ` LIU Zhiwei
2021-07-02  5:38         ` Alistair Francis
2021-07-02  5:38           ` Alistair Francis
2021-07-02  6:09           ` LIU Zhiwei
2021-07-02  6:09             ` LIU Zhiwei
2021-07-02  7:16             ` Alistair Francis
2021-07-02  7:16               ` Alistair Francis
2021-09-28  8:10               ` Frank Chang
2021-09-28  8:10                 ` Frank Chang
2021-09-29  3:55                 ` Alistair Francis
2021-09-29  3:55                   ` Alistair Francis
2021-04-09  7:48 ` [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-26 17:23   ` Frank Chang
2021-06-26 17:23     ` Frank Chang
2021-06-27  8:23     ` Frank Chang
2021-06-27  8:23       ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 03/11] hw/intc: Add CLIC device LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-04-19 23:25   ` Alistair Francis
2021-04-19 23:25     ` Alistair Francis
2021-04-20  0:57     ` LIU Zhiwei
2021-04-20  0:57       ` LIU Zhiwei
2021-04-22  0:16       ` Alistair Francis
2021-04-22  0:16         ` Alistair Francis
2021-06-13 10:10   ` Frank Chang
2021-06-13 10:10     ` Frank Chang
2021-06-16  2:56     ` LIU Zhiwei
2021-06-16  2:56       ` LIU Zhiwei
2021-06-26 12:56       ` Frank Chang
2021-06-26 12:56         ` Frank Chang
2021-06-28  7:15         ` LIU Zhiwei
2021-06-28  7:15           ` LIU Zhiwei
2021-06-28  7:23           ` Frank Chang
2021-06-28  7:23             ` Frank Chang
2021-06-28  7:39             ` LIU Zhiwei
2021-06-28  7:39               ` LIU Zhiwei
2021-06-28  7:49               ` Frank Chang
2021-06-28  7:49                 ` Frank Chang
2021-06-28  8:01                 ` LIU Zhiwei
2021-06-28  8:01                   ` LIU Zhiwei
2021-06-28  8:07                   ` Frank Chang
2021-06-28  8:07                     ` Frank Chang
2021-06-28  8:11                     ` LIU Zhiwei
2021-06-28  8:11                       ` LIU Zhiwei
2021-06-28  8:19                       ` Frank Chang
2021-06-28  8:19                         ` Frank Chang
2021-06-28  8:43                         ` LIU Zhiwei
2021-06-28  8:43                           ` LIU Zhiwei
2021-06-28  9:11                           ` Frank Chang
2021-06-28  9:11                             ` Frank Chang
2021-06-26 15:03   ` Frank Chang
2021-06-26 15:03     ` Frank Chang
2021-06-26 15:26     ` Frank Chang
2021-06-26 15:26       ` Frank Chang
2021-06-29  2:52       ` LIU Zhiwei
2021-06-29  2:52         ` LIU Zhiwei
2021-06-29  2:43     ` LIU Zhiwei
2021-06-29  2:43       ` LIU Zhiwei
2021-06-30  5:37       ` Frank Chang
2021-06-30  5:37         ` Frank Chang
2021-06-26 15:20   ` Frank Chang
2021-06-26 15:20     ` Frank Chang
2021-06-29  2:50     ` LIU Zhiwei
2021-06-29  2:50       ` LIU Zhiwei
2021-06-26 17:15   ` Frank Chang
2021-06-26 17:15     ` Frank Chang
2021-06-26 17:19     ` Frank Chang
2021-06-26 17:19       ` Frank Chang
2021-06-28 10:16   ` Frank Chang
2021-06-28 10:16     ` Frank Chang
2021-06-28 12:56     ` LIU Zhiwei
2021-06-28 12:56       ` LIU Zhiwei
2021-06-28 14:30       ` Frank Chang
2021-06-28 14:30         ` Frank Chang
2021-06-28 21:36         ` LIU Zhiwei
2021-06-28 21:36           ` LIU Zhiwei
2021-06-28 10:24   ` Frank Chang
2021-06-28 10:24     ` Frank Chang
2021-06-28 10:48     ` LIU Zhiwei
2021-06-28 10:48       ` LIU Zhiwei
2021-07-13  6:53   ` Frank Chang
2021-07-13  6:53     ` Frank Chang
2021-07-13  6:57     ` Frank Chang
2021-07-13  6:57       ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  6:50   ` Frank Chang
2021-06-27  6:50     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 05/11] target/riscv: Update CSR xip " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  6:45   ` Frank Chang
2021-06-27  6:45     ` Frank Chang
2021-04-09  7:48 ` LIU Zhiwei [this message]
2021-04-09  7:48   ` [RFC PATCH 06/11] target/riscv: Update CSR xtvec " LIU Zhiwei
2021-06-27  8:59   ` Frank Chang
2021-06-27  8:59     ` Frank Chang
2021-07-10 15:04   ` Frank Chang
2021-07-10 15:04     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 07/11] target/riscv: Update CSR xtvt " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27  8:33   ` Frank Chang
2021-06-27  8:33     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 08/11] target/riscv: Update CSR xnxti " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-11  8:15   ` Frank Chang
2021-06-11  8:15     ` Frank Chang
2021-06-11  8:30     ` LIU Zhiwei
2021-06-11  8:30       ` LIU Zhiwei
2021-06-11  8:42       ` Frank Chang
2021-06-11  8:42         ` Frank Chang
2021-06-11  8:56         ` LIU Zhiwei
2021-06-11  8:56           ` LIU Zhiwei
2021-06-11  9:07           ` Frank Chang
2021-06-11  9:07             ` Frank Chang
2021-06-11  9:26             ` LIU Zhiwei
2021-06-11  9:26               ` LIU Zhiwei
2021-06-15  7:45             ` Alistair Francis
2021-06-15  7:45               ` Alistair Francis
2021-06-27 10:07   ` Frank Chang
2021-06-27 10:07     ` Frank Chang
2021-07-10 14:59   ` Frank Chang
2021-07-10 14:59     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 09/11] target/riscv: Update CSR mclicbase " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-26 15:31   ` Frank Chang
2021-06-26 15:31     ` Frank Chang
2021-06-29  2:54     ` LIU Zhiwei
2021-06-29  2:54       ` LIU Zhiwei
2021-04-09  7:48 ` [RFC PATCH 10/11] target/riscv: Update interrupt handling " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27 15:39   ` Frank Chang
2021-06-27 15:39     ` Frank Chang
2021-04-09  7:48 ` [RFC PATCH 11/11] target/riscv: Update interrupt return " LIU Zhiwei
2021-04-09  7:48   ` LIU Zhiwei
2021-06-27 12:08   ` Frank Chang
2021-06-27 12:08     ` Frank Chang
2021-07-13  7:15   ` Frank Chang
2021-07-13  7:15     ` Frank Chang
2021-04-19 23:30 ` [RFC PATCH 00/11] RISC-V: support clic v0.9 specification Alistair Francis
2021-04-19 23:30   ` Alistair Francis
2021-04-20  1:44   ` LIU Zhiwei
2021-04-20  1:44     ` LIU Zhiwei
2021-04-20  6:26     ` Alistair Francis
2021-04-20  6:26       ` Alistair Francis
2021-04-20  7:20       ` LIU Zhiwei
2021-04-20  7:20         ` LIU Zhiwei
2021-04-22  0:21         ` Alistair Francis
2021-04-22  0:21           ` Alistair Francis
2021-06-27 15:55 ` Frank Chang
2021-06-27 15:55   ` Frank Chang

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