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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id t1sm1070337eds.53.2021.04.09.02.36.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Apr 2021 02:36:35 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH-for-6.1 v2 2/6] target/mips/cpu: Update CP0 clock when CPU clock is propagated Date: Fri, 9 Apr 2021 11:36:19 +0200 Message-Id: <20210409093623.2402750-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210409093623.2402750-1-f4bug@amsat.org> References: <20210409093623.2402750-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Aleksandar Rikalo , Luc Michel , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Hao Wu , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Setting the CP0 clock simply on CPU init is incorrect. First because the clock can not be yet propagated. Second because we aimed to support dynamic frequencies in commit a0713e85bfa, so the CPU frequency can be changed *after* init time. The correct way is to register a ClockCallback, which will update the CP0 period when the clock changes. Fixes: a0713e85bfa ("target/mips/cpu: Allow the CPU to use dynamic frequencies") Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index aa0b00256e6..db93d19c49a 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -604,6 +604,13 @@ static void mips_cp0_period_set(MIPSCPU *cpu) assert(env->cp0_count_ns); } +static void mips_cpu_clk_update(void *opaque, ClockEvent event) +{ + MIPSCPU *cpu = opaque; + + mips_cp0_period_set(cpu); +} + static void mips_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -624,7 +631,6 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) /* Initialize the frequency in case the clock remains unconnected. */ clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); } - mips_cp0_period_set(cpu); cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { @@ -653,7 +659,8 @@ static void mips_cpu_initfn(Object *obj) MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); cpu_set_cpustate_pointers(cpu); - cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); + cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", + mips_cpu_clk_update, cpu, ClockUpdate); env->cpu_model = mcc->cpu_def; } -- 2.26.3