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[88.21.201.17]) by smtp.gmail.com with ESMTPSA id y16sm1068851edc.62.2021.04.09.02.36.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Apr 2021 02:36:51 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH-for-6.1 v2 5/6] target/mips/cp0_timer: Use new clock_ns_to_ticks() Date: Fri, 9 Apr 2021 11:36:22 +0200 Message-Id: <20210409093623.2402750-6-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 In-Reply-To: <20210409093623.2402750-1-f4bug@amsat.org> References: <20210409093623.2402750-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Aleksandar Rikalo , Luc Michel , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Hao Wu , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Use the new clock_ns_to_ticks() function in cp0_timer where appropriate. This allows us to remove CPUMIPSState::cp0_count_ns and mips_cp0_period_set() and mips_cpu_clk_update(). Signed-off-by: Philippe Mathieu-Daudé --- target/mips/cpu.h | 1 - target/mips/cp0_timer.c | 41 ++++++++++++++++++++++++++++++----------- target/mips/cpu.c | 18 +----------------- 3 files changed, 31 insertions(+), 29 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 075c24abdad..10f10018b95 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1160,7 +1160,6 @@ struct CPUMIPSState { struct MIPSITUState *itu; MemoryRegion *itc_tag; /* ITC Configuration Tags */ target_ulong exception_base; /* ExceptionBase input to the core */ - uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */ }; /** diff --git a/target/mips/cp0_timer.c b/target/mips/cp0_timer.c index 85f2f85838d..3b76cc97f6a 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/cp0_timer.c @@ -27,26 +27,31 @@ #include "sysemu/kvm.h" #include "internal.h" -static uint32_t ns_to_count(CPUMIPSState *env, uint64_t ns) +static uint32_t tick_to_count(MIPSCPU *cpu, uint64_t ticks) { - return ns / env->cp0_count_ns; + return ticks / cpu->cp0_count_rate; } -static uint32_t ns_substract_to_count(CPUMIPSState *env, - uint32_t count, uint64_t ns) +static uint32_t tick_substract_to_count(MIPSCPU *cpu, + uint32_t count, uint64_t ticks) { - return count - ns_to_count(env, ns); + return count - tick_to_count(cpu, ticks); } /* MIPS R4K timer */ static void cpu_mips_timer_update(CPUMIPSState *env) { + MIPSCPU *cpu = env_archcpu(env); uint64_t now_ns, next_ns; uint32_t wait; + uint64_t now_ticks; now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - wait = ns_substract_to_count(env, env->CP0_Compare - env->CP0_Count, now_ns); - next_ns = now_ns + (uint64_t)wait * env->cp0_count_ns; + now_ticks = clock_ns_to_ticks(cpu->clock, now_ns); + wait = tick_substract_to_count(cpu, env->CP0_Compare - env->CP0_Count, + now_ticks); + next_ns = now_ns + (uint64_t)wait * clock_ticks_to_ns(cpu->clock, + cpu->cp0_count_rate); timer_mod(env->timer, next_ns); } @@ -65,6 +70,7 @@ uint32_t cpu_mips_get_count(CPUMIPSState *env) if (env->CP0_Cause & (1 << CP0Ca_DC)) { return env->CP0_Count; } else { + MIPSCPU *cpu = env_archcpu(env); uint64_t now_ns; now_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); @@ -74,12 +80,16 @@ uint32_t cpu_mips_get_count(CPUMIPSState *env) cpu_mips_timer_expire(env); } - return env->CP0_Count + ns_to_count(env, now_ns); + return env->CP0_Count + tick_to_count(cpu, + clock_ns_to_ticks(cpu->clock, + now_ns)); } } void cpu_mips_store_count(CPUMIPSState *env, uint32_t count) { + MIPSCPU *cpu = env_archcpu(env); + /* * This gets called from cpu_state_reset(), potentially before timer init. * So env->timer may be NULL, which is also the case with KVM enabled so @@ -88,9 +98,13 @@ void cpu_mips_store_count(CPUMIPSState *env, uint32_t count) if (env->CP0_Cause & (1 << CP0Ca_DC) || !env->timer) { env->CP0_Count = count; } else { + uint64_t cp0_count_ticks; + + cp0_count_ticks = clock_ns_to_ticks(cpu->clock, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); /* Store new count register */ - env->CP0_Count = ns_substract_to_count(env, count, - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + env->CP0_Count = tick_substract_to_count(cpu, count, cp0_count_ticks); + /* Update timer timer */ cpu_mips_timer_update(env); } @@ -115,8 +129,13 @@ void cpu_mips_start_count(CPUMIPSState *env) void cpu_mips_stop_count(CPUMIPSState *env) { + MIPSCPU *cpu = env_archcpu(env); + uint64_t cp0_count_ticks; + + cp0_count_ticks = clock_ns_to_ticks(cpu->clock, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); /* Store the current value */ - env->CP0_Count += ns_to_count(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + env->CP0_Count += tick_to_count(cpu, cp0_count_ticks); } static void mips_timer_cb(void *opaque) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index db93d19c49a..a66caa44bee 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -595,22 +595,6 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) #define CPU_FREQ_HZ_DEFAULT 200000000 #define CP0_COUNT_RATE_DEFAULT 2 -static void mips_cp0_period_set(MIPSCPU *cpu) -{ - CPUMIPSState *env = &cpu->env; - - env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock, - cpu->cp0_count_rate); - assert(env->cp0_count_ns); -} - -static void mips_cpu_clk_update(void *opaque, ClockEvent event) -{ - MIPSCPU *cpu = opaque; - - mips_cp0_period_set(cpu); -} - static void mips_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -660,7 +644,7 @@ static void mips_cpu_initfn(Object *obj) cpu_set_cpustate_pointers(cpu); cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", - mips_cpu_clk_update, cpu, ClockUpdate); + NULL, NULL, ClockUpdate); env->cpu_model = mcc->cpu_def; } -- 2.26.3