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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Hervé Poussineau" <hpoussin@reactos.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PULL 3/3] target/mips: Fix TCG temporary leak in gen_cache_operation()
Date: Tue, 13 Apr 2021 12:11:31 +0200	[thread overview]
Message-ID: <20210413101131.3480173-4-f4bug@amsat.org> (raw)
In-Reply-To: <20210413101131.3480173-1-f4bug@amsat.org>

Fix a TCG temporary leak when translating CACHE opcode.

Fixes: 0d74a222c27 ("make ITC Configuration Tags accessible to the CPU")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210406202857.1440744-1-f4bug@amsat.org>
---
 target/mips/translate.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/mips/translate.c b/target/mips/translate.c
index c518bf3963b..71fa5ec1973 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -12804,6 +12804,8 @@ static void gen_cache_operation(DisasContext *ctx, uint32_t op, int base,
     TCGv t1 = tcg_temp_new();
     gen_base_offset_addr(ctx, t1, base, offset);
     gen_helper_cache(cpu_env, t1, t0);
+    tcg_temp_free(t1);
+    tcg_temp_free_i32(t0);
 }
 
 #if defined(TARGET_MIPS64)
-- 
2.26.3



  parent reply	other threads:[~2021-04-13 10:14 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-13 10:11 [PULL 0/3] MIPS patches for 2021-04-13 Philippe Mathieu-Daudé
2021-04-13 10:11 ` [PULL 1/3] hw/isa/Kconfig: Add missing dependency VIA VT82C686 -> APM Philippe Mathieu-Daudé
2021-04-13 10:11 ` [PULL 2/3] hw/isa/piix4: Migrate Reset Control Register Philippe Mathieu-Daudé
2021-04-13 10:11 ` Philippe Mathieu-Daudé [this message]
2021-04-13 15:50 ` [PULL 0/3] MIPS patches for 2021-04-13 Peter Maydell

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