From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5A51EC433B4 for ; Fri, 16 Apr 2021 09:44:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3C44A6115B for ; Fri, 16 Apr 2021 09:44:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242028AbhDPJpM (ORCPT ); Fri, 16 Apr 2021 05:45:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36440 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238871AbhDPJpL (ORCPT ); Fri, 16 Apr 2021 05:45:11 -0400 Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37700C061574 for ; Fri, 16 Apr 2021 02:44:47 -0700 (PDT) Received: from ptx.hi.pengutronix.de ([2001:67c:670:100:1d::c0]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lXL1c-0004Kv-Br; Fri, 16 Apr 2021 11:44:32 +0200 Received: from ukl by ptx.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1lXL1Y-0003fo-Dj; Fri, 16 Apr 2021 11:44:28 +0200 Date: Fri, 16 Apr 2021 11:44:26 +0200 From: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= To: Nobuhiro Iwamatsu Cc: Rob Herring , Thierry Reding , Lee Jones , devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 2/2] pwm: visconti: Add Toshiba Visconti SoC PWM support Message-ID: <20210416094426.x4gyw3drp2fcwczs@pengutronix.de> References: <20210409230837.1919744-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20210409230837.1919744-3-nobuhiro1.iwamatsu@toshiba.co.jp> <20210410135321.oissremqropvrpd3@pengutronix.de> <20210412025536.i5chpp6sighunvfx@toshiba.co.jp> <20210412070232.6q3cgqvuj53p4cmi@pengutronix.de> <20210416080721.oa7xdvu22w2b2rkf@toshiba.co.jp> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="t42vctr7z7mwa3qh" Content-Disposition: inline In-Reply-To: <20210416080721.oa7xdvu22w2b2rkf@toshiba.co.jp> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org --t42vctr7z7mwa3qh Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hello Nobuhiro, On Fri, Apr 16, 2021 at 05:07:21PM +0900, Nobuhiro Iwamatsu wrote: > On Mon, Apr 12, 2021 at 09:02:32AM +0200, Uwe Kleine-K=F6nig wrote: > > On Mon, Apr 12, 2021 at 11:55:36AM +0900, Nobuhiro Iwamatsu wrote: > > > On Sat, Apr 10, 2021 at 03:53:21PM +0200, Uwe Kleine-K=F6nig wrote: > > > > Can you please put a paragraph analogous to the one in pwm-sifive i= n the > > > > same format. This simplified keeping an overview about the oddities= of > > > > the various supported chips. > > >=20 > > > OK, I will check pwm-sifive's, and add. >=20 > I will add the following : >=20 > * Limitations: > * - PIPGM_PWMC is a 2-bit divider (00: 1, 01: 2, 10: 4, 11: 8) for the i= nput > * clock running at 1 MHz. I would strip that to: - Fixed input clock running at 1 MHz > * - When the settings of the PWM are modified, the new values are shadow= ed > * in hardware until the PIPGM_PCSR register is written and the current= ly > * running period is completed. This way the hardware switches atomical= ly > * from the old setting to the new. > * - Disabling the hardware completes the currently running period and ke= eps > * the output at low level at all times. This looks fine. =20 > > For me the critical (and only) difference between "off" and > > "duty cycle =3D 0" is that when a new configuration is to be applied. In > > the "off" state a new period can (and should) start immediately, while > > with "duty_cycle =3D 0" the rising edge should be delayed until the > > currently running period is over.[1] > >=20 > > So the thing to do here (IMHO) is: > >=20 > > Iff with PIPGM_PCSR =3D 0 configuring a new setting (that is finalized > > with writing a non-zero value to PIPGM_PCSR) completes the currently > > running period, then always assume the PWM as enabled. >=20 > Yes, this device works that way. OK, then please use state->enabled =3D true unconditionally in visconti_pwm_get_state(). Best regards Uwe --=20 Pengutronix e.K. | Uwe Kleine-K=F6nig | Industrial Linux Solutions | https://www.pengutronix.de/ | --t42vctr7z7mwa3qh Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEfnIqFpAYrP8+dKQLwfwUeK3K7AkFAmB5XHYACgkQwfwUeK3K 7AnT3Qf/UxtGaRC2PkiqZqydmy5iwe/ufofn1G4HLEcTektGyzPwAuCYp21GNVm3 aBTM7yjUKzm9tI3oxD3wWuSdEAyBp9rwPmyk/376GB7ZHcd2noXSH0DM8d0cYjMg l/vekoyFUOAPUMirdO4kdeukZeOU+Caskxd5y/UaZ+Gc9LI70ARXi6QnJbiL/4C2 ej53UHhf2JZqKYpdPRdkSLuULpJ8mrbQQG1RSP/6YylyGB5aA1X84cw3kwyg7R0o LjccDhLne0qkSEi80EMCr3aW29sJjKMiMybOJkwyY62RdXHp1Cdd7c5BS1/+Bhnd CeTfOmimMouYVue4qyJstkswR/gHbg== =gYIm -----END PGP SIGNATURE----- --t42vctr7z7mwa3qh-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF4DCC433B4 for ; Fri, 16 Apr 2021 09:56:33 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 83C8C61152 for ; Fri, 16 Apr 2021 09:56:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 83C8C61152 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Type: List-Subscribe:List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: In-Reply-To:MIME-Version:References:Message-ID:Subject:Cc:To:From:Date: Reply-To:Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date :Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; 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bh=/COkqkPXItq3p5xawaoLVfegWeoFmG5WVceZ+TLVkgE=; b=y+Su09Ou/adQL0QmgqR1IYGKrJ CW5amnim7UhQMSPygKRFYYDTC5ZUQGKozkP/YggksrMhdv19qKGEL63pBGU6qzk6Y62V3KRqgSTd9 rdWHvbCwLGFnCeEnIRlnbFiWXHbax0eGdjvxaxLUaFr9oCBYy7YdMtHBIskvJ4DRJirm/KCPK0yuO rsuMRUtBZVqhXD8tcybi96vy86WZw6xCZZWXnZ0lIMQ3TACBbF6Sy1Dj4PEmFR+0+swxnDZuEfO5p cfr6HH1YIWiCofPHZDB0xCkdMbiTAFDkY/HGMK7c5kLVcH+zI0qlyj9oRQR8UYpw33T9eqwufOE+3 0ygqtXgQ==; Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.94 #2 (Red Hat Linux)) id 1lXL1o-009Ffi-7n for linux-arm-kernel@lists.infradead.org; Fri, 16 Apr 2021 09:44:46 +0000 Received: from ptx.hi.pengutronix.de ([2001:67c:670:100:1d::c0]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lXL1c-0004Kv-Br; Fri, 16 Apr 2021 11:44:32 +0200 Received: from ukl by ptx.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1lXL1Y-0003fo-Dj; Fri, 16 Apr 2021 11:44:28 +0200 Date: Fri, 16 Apr 2021 11:44:26 +0200 From: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= To: Nobuhiro Iwamatsu Cc: Rob Herring , Thierry Reding , Lee Jones , devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 2/2] pwm: visconti: Add Toshiba Visconti SoC PWM support Message-ID: <20210416094426.x4gyw3drp2fcwczs@pengutronix.de> References: <20210409230837.1919744-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20210409230837.1919744-3-nobuhiro1.iwamatsu@toshiba.co.jp> <20210410135321.oissremqropvrpd3@pengutronix.de> <20210412025536.i5chpp6sighunvfx@toshiba.co.jp> <20210412070232.6q3cgqvuj53p4cmi@pengutronix.de> <20210416080721.oa7xdvu22w2b2rkf@toshiba.co.jp> MIME-Version: 1.0 In-Reply-To: <20210416080721.oa7xdvu22w2b2rkf@toshiba.co.jp> X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210416_024444_306834_D6D0B6B6 X-CRM114-Status: GOOD ( 27.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: multipart/mixed; boundary="===============5468486913848315287==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============5468486913848315287== Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="t42vctr7z7mwa3qh" Content-Disposition: inline --t42vctr7z7mwa3qh Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hello Nobuhiro, On Fri, Apr 16, 2021 at 05:07:21PM +0900, Nobuhiro Iwamatsu wrote: > On Mon, Apr 12, 2021 at 09:02:32AM +0200, Uwe Kleine-K=F6nig wrote: > > On Mon, Apr 12, 2021 at 11:55:36AM +0900, Nobuhiro Iwamatsu wrote: > > > On Sat, Apr 10, 2021 at 03:53:21PM +0200, Uwe Kleine-K=F6nig wrote: > > > > Can you please put a paragraph analogous to the one in pwm-sifive i= n the > > > > same format. This simplified keeping an overview about the oddities= of > > > > the various supported chips. > > >=20 > > > OK, I will check pwm-sifive's, and add. >=20 > I will add the following : >=20 > * Limitations: > * - PIPGM_PWMC is a 2-bit divider (00: 1, 01: 2, 10: 4, 11: 8) for the i= nput > * clock running at 1 MHz. I would strip that to: - Fixed input clock running at 1 MHz > * - When the settings of the PWM are modified, the new values are shadow= ed > * in hardware until the PIPGM_PCSR register is written and the current= ly > * running period is completed. This way the hardware switches atomical= ly > * from the old setting to the new. > * - Disabling the hardware completes the currently running period and ke= eps > * the output at low level at all times. This looks fine. =20 > > For me the critical (and only) difference between "off" and > > "duty cycle =3D 0" is that when a new configuration is to be applied. In > > the "off" state a new period can (and should) start immediately, while > > with "duty_cycle =3D 0" the rising edge should be delayed until the > > currently running period is over.[1] > >=20 > > So the thing to do here (IMHO) is: > >=20 > > Iff with PIPGM_PCSR =3D 0 configuring a new setting (that is finalized > > with writing a non-zero value to PIPGM_PCSR) completes the currently > > running period, then always assume the PWM as enabled. >=20 > Yes, this device works that way. OK, then please use state->enabled =3D true unconditionally in visconti_pwm_get_state(). Best regards Uwe --=20 Pengutronix e.K. | Uwe Kleine-K=F6nig | Industrial Linux Solutions | https://www.pengutronix.de/ | --t42vctr7z7mwa3qh Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEfnIqFpAYrP8+dKQLwfwUeK3K7AkFAmB5XHYACgkQwfwUeK3K 7AnT3Qf/UxtGaRC2PkiqZqydmy5iwe/ufofn1G4HLEcTektGyzPwAuCYp21GNVm3 aBTM7yjUKzm9tI3oxD3wWuSdEAyBp9rwPmyk/376GB7ZHcd2noXSH0DM8d0cYjMg l/vekoyFUOAPUMirdO4kdeukZeOU+Caskxd5y/UaZ+Gc9LI70ARXi6QnJbiL/4C2 ej53UHhf2JZqKYpdPRdkSLuULpJ8mrbQQG1RSP/6YylyGB5aA1X84cw3kwyg7R0o LjccDhLne0qkSEi80EMCr3aW29sJjKMiMybOJkwyY62RdXHp1Cdd7c5BS1/+Bhnd CeTfOmimMouYVue4qyJstkswR/gHbg== =gYIm -----END PGP SIGNATURE----- --t42vctr7z7mwa3qh-- --===============5468486913848315287== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============5468486913848315287==--