From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C91E7C43461 for ; Fri, 16 Apr 2021 12:15:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9FC62611AB for ; Fri, 16 Apr 2021 12:15:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243314AbhDPMQK (ORCPT ); Fri, 16 Apr 2021 08:16:10 -0400 Received: from mo-csw1514.securemx.jp ([210.130.202.153]:40234 "EHLO mo-csw.securemx.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232130AbhDPMQJ (ORCPT ); Fri, 16 Apr 2021 08:16:09 -0400 Received: by mo-csw.securemx.jp (mx-mo-csw1514) id 13GCFQJd029781; Fri, 16 Apr 2021 21:15:26 +0900 X-Iguazu-Qid: 34trSOSPthsRJckbCs X-Iguazu-QSIG: v=2; s=0; t=1618575326; q=34trSOSPthsRJckbCs; m=7HPJQplQYDVdOr5qiRc8LTUir5zBahKRvEqdYSEGzxQ= Received: from imx2-a.toshiba.co.jp (imx2-a.toshiba.co.jp [106.186.93.35]) by relay.securemx.jp (mx-mr1512) id 13GCFPEU030896 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128 verify=NOT); Fri, 16 Apr 2021 21:15:25 +0900 Received: from enc01.toshiba.co.jp (enc01.toshiba.co.jp [106.186.93.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by imx2-a.toshiba.co.jp (Postfix) with ESMTPS id 0C1031000DC; Fri, 16 Apr 2021 21:15:25 +0900 (JST) Received: from hop001.toshiba.co.jp ([133.199.164.63]) by enc01.toshiba.co.jp with ESMTP id 13GCFOLS011662; Fri, 16 Apr 2021 21:15:24 +0900 Date: Fri, 16 Apr 2021 21:15:23 +0900 From: Nobuhiro Iwamatsu To: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= Cc: Rob Herring , Thierry Reding , Lee Jones , devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 2/2] pwm: visconti: Add Toshiba Visconti SoC PWM support X-TSB-HOP: ON Message-ID: <20210416121523.c34trzsrlcjuzirl@toshiba.co.jp> References: <20210409230837.1919744-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20210409230837.1919744-3-nobuhiro1.iwamatsu@toshiba.co.jp> <20210410135321.oissremqropvrpd3@pengutronix.de> <20210412025536.i5chpp6sighunvfx@toshiba.co.jp> <20210412070232.6q3cgqvuj53p4cmi@pengutronix.de> <20210416080721.oa7xdvu22w2b2rkf@toshiba.co.jp> <20210416094426.x4gyw3drp2fcwczs@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210416094426.x4gyw3drp2fcwczs@pengutronix.de> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Uwe, Thanks for your comment. On Fri, Apr 16, 2021 at 11:44:26AM +0200, Uwe Kleine-König wrote: > Hello Nobuhiro, > > On Fri, Apr 16, 2021 at 05:07:21PM +0900, Nobuhiro Iwamatsu wrote: > > On Mon, Apr 12, 2021 at 09:02:32AM +0200, Uwe Kleine-König wrote: > > > On Mon, Apr 12, 2021 at 11:55:36AM +0900, Nobuhiro Iwamatsu wrote: > > > > On Sat, Apr 10, 2021 at 03:53:21PM +0200, Uwe Kleine-König wrote: > > > > > Can you please put a paragraph analogous to the one in pwm-sifive in the > > > > > same format. This simplified keeping an overview about the oddities of > > > > > the various supported chips. > > > > > > > > OK, I will check pwm-sifive's, and add. > > > > I will add the following : > > > > * Limitations: > > * - PIPGM_PWMC is a 2-bit divider (00: 1, 01: 2, 10: 4, 11: 8) for the input > > * clock running at 1 MHz. > > I would strip that to: > > - Fixed input clock running at 1 MHz > OK, I will update. > > * - When the settings of the PWM are modified, the new values are shadowed > > * in hardware until the PIPGM_PCSR register is written and the currently > > * running period is completed. This way the hardware switches atomically > > * from the old setting to the new. > > * - Disabling the hardware completes the currently running period and keeps > > * the output at low level at all times. > > This looks fine. > > > > For me the critical (and only) difference between "off" and > > > "duty cycle = 0" is that when a new configuration is to be applied. In > > > the "off" state a new period can (and should) start immediately, while > > > with "duty_cycle = 0" the rising edge should be delayed until the > > > currently running period is over.[1] > > > > > > So the thing to do here (IMHO) is: > > > > > > Iff with PIPGM_PCSR = 0 configuring a new setting (that is finalized > > > with writing a non-zero value to PIPGM_PCSR) completes the currently > > > running period, then always assume the PWM as enabled. > > > > Yes, this device works that way. > > OK, then please use > > state->enabled = true > > unconditionally in visconti_pwm_get_state(). > Please let me check. If I unconditionally add 'state->enabled = true' to visconti_pwm_get_state(), state->enabled is set to true because visconti_pwm_get_state() is called when the device is created (this is when I write the device number to the export of /sys/class/pwm/pwmchip0 ). And since PIPGM_PCSR is 0 in this state, the pulse by PWM is not output. However, I think this means that the device is working as this driver. Is this correct? > Best regards > Uwe > Best regards, Nobuhiro From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A2E1C433B4 for ; Fri, 16 Apr 2021 12:19:08 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 848E7610FA for ; Fri, 16 Apr 2021 12:19:07 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 848E7610FA Authentication-Results: mail.kernel.org; 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Fri, 16 Apr 2021 21:15:24 +0900 Date: Fri, 16 Apr 2021 21:15:23 +0900 From: Nobuhiro Iwamatsu To: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= Cc: Rob Herring , Thierry Reding , Lee Jones , devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 2/2] pwm: visconti: Add Toshiba Visconti SoC PWM support X-TSB-HOP: ON Message-ID: <20210416121523.c34trzsrlcjuzirl@toshiba.co.jp> References: <20210409230837.1919744-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20210409230837.1919744-3-nobuhiro1.iwamatsu@toshiba.co.jp> <20210410135321.oissremqropvrpd3@pengutronix.de> <20210412025536.i5chpp6sighunvfx@toshiba.co.jp> <20210412070232.6q3cgqvuj53p4cmi@pengutronix.de> <20210416080721.oa7xdvu22w2b2rkf@toshiba.co.jp> <20210416094426.x4gyw3drp2fcwczs@pengutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210416094426.x4gyw3drp2fcwczs@pengutronix.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210416_051535_679027_C4DDE2A1 X-CRM114-Status: GOOD ( 33.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Uwe, Thanks for your comment. On Fri, Apr 16, 2021 at 11:44:26AM +0200, Uwe Kleine-K=F6nig wrote: > Hello Nobuhiro, > = > On Fri, Apr 16, 2021 at 05:07:21PM +0900, Nobuhiro Iwamatsu wrote: > > On Mon, Apr 12, 2021 at 09:02:32AM +0200, Uwe Kleine-K=F6nig wrote: > > > On Mon, Apr 12, 2021 at 11:55:36AM +0900, Nobuhiro Iwamatsu wrote: > > > > On Sat, Apr 10, 2021 at 03:53:21PM +0200, Uwe Kleine-K=F6nig wrote: > > > > > Can you please put a paragraph analogous to the one in pwm-sifive= in the > > > > > same format. This simplified keeping an overview about the odditi= es of > > > > > the various supported chips. > > > > = > > > > OK, I will check pwm-sifive's, and add. > > = > > I will add the following : > > = > > * Limitations: > > * - PIPGM_PWMC is a 2-bit divider (00: 1, 01: 2, 10: 4, 11: 8) for the= input > > * clock running at 1 MHz. > = > I would strip that to: > = > - Fixed input clock running at 1 MHz > = OK, I will update. > > * - When the settings of the PWM are modified, the new values are shad= owed > > * in hardware until the PIPGM_PCSR register is written and the curre= ntly > > * running period is completed. This way the hardware switches atomic= ally > > * from the old setting to the new. > > * - Disabling the hardware completes the currently running period and = keeps > > * the output at low level at all times. > = > This looks fine. > = > > > For me the critical (and only) difference between "off" and > > > "duty cycle =3D 0" is that when a new configuration is to be applied.= In > > > the "off" state a new period can (and should) start immediately, while > > > with "duty_cycle =3D 0" the rising edge should be delayed until the > > > currently running period is over.[1] > > > = > > > So the thing to do here (IMHO) is: > > > = > > > Iff with PIPGM_PCSR =3D 0 configuring a new setting (that is finalized > > > with writing a non-zero value to PIPGM_PCSR) completes the currently > > > running period, then always assume the PWM as enabled. > > = > > Yes, this device works that way. > = > OK, then please use > = > state->enabled =3D true > = > unconditionally in visconti_pwm_get_state(). > = Please let me check. If I unconditionally add 'state->enabled =3D true' to visconti_pwm_get_stat= e(), state->enabled is set to true because visconti_pwm_get_state() is called wh= en the device is created (this is when I write the device number to the export= of /sys/class/pwm/pwmchip0 ). And since PIPGM_PCSR is 0 in this state, the pulse by PWM is not output. However, I think this means that the device is working as this driver. Is this correct? > Best regards > Uwe > = Best regards, Nobuhiro _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel