From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33D84C433B4 for ; Sun, 18 Apr 2021 11:08:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 0D10F6120C for ; Sun, 18 Apr 2021 11:08:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230518AbhDRLI0 (ORCPT ); Sun, 18 Apr 2021 07:08:26 -0400 Received: from mo-csw1115.securemx.jp ([210.130.202.157]:58788 "EHLO mo-csw.securemx.jp" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230321AbhDRLIV (ORCPT ); Sun, 18 Apr 2021 07:08:21 -0400 Received: by mo-csw.securemx.jp (mx-mo-csw1115) id 13IB7LAG008523; Sun, 18 Apr 2021 20:07:22 +0900 X-Iguazu-Qid: 2wHHhVLfD3Y5mc3bes X-Iguazu-QSIG: v=2; s=0; t=1618744041; q=2wHHhVLfD3Y5mc3bes; m=f4EreB5GRMyV2IrbzmhIs4qW2c5qsOFBc0nTtuWq2Lk= Received: from imx2-a.toshiba.co.jp (imx2-a.toshiba.co.jp [106.186.93.35]) by relay.securemx.jp (mx-mr1112) id 13IB7KHX004202 (version=TLSv1.2 cipher=AES128-GCM-SHA256 bits=128 verify=NOT); Sun, 18 Apr 2021 20:07:20 +0900 Received: from enc01.toshiba.co.jp (enc01.toshiba.co.jp [106.186.93.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by imx2-a.toshiba.co.jp (Postfix) with ESMTPS id 3B0971000A8; Sun, 18 Apr 2021 20:07:20 +0900 (JST) Received: from hop001.toshiba.co.jp ([133.199.164.63]) by enc01.toshiba.co.jp with ESMTP id 13IB7JlO007932; Sun, 18 Apr 2021 20:07:19 +0900 Date: Sun, 18 Apr 2021 20:07:18 +0900 From: Nobuhiro Iwamatsu To: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= Cc: Rob Herring , Thierry Reding , Lee Jones , devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 2/2] pwm: visconti: Add Toshiba Visconti SoC PWM support X-TSB-HOP: ON Message-ID: <20210418110718.4zrh665anbz3wmqc@toshiba.co.jp> References: <20210409230837.1919744-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20210409230837.1919744-3-nobuhiro1.iwamatsu@toshiba.co.jp> <20210410135321.oissremqropvrpd3@pengutronix.de> <20210412025536.i5chpp6sighunvfx@toshiba.co.jp> <20210412070232.6q3cgqvuj53p4cmi@pengutronix.de> <20210416080721.oa7xdvu22w2b2rkf@toshiba.co.jp> <20210416094426.x4gyw3drp2fcwczs@pengutronix.de> <20210416121523.c34trzsrlcjuzirl@toshiba.co.jp> <20210417155009.vnqxx3fn2yjzp3qc@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210417155009.vnqxx3fn2yjzp3qc@pengutronix.de> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Uwe, On Sat, Apr 17, 2021 at 05:50:09PM +0200, Uwe Kleine-König wrote: > Hello Nobuhiro, > > On Fri, Apr 16, 2021 at 09:15:23PM +0900, Nobuhiro Iwamatsu wrote: > > > > > For me the critical (and only) difference between "off" and > > > > > "duty cycle = 0" is that when a new configuration is to be applied. In > > > > > the "off" state a new period can (and should) start immediately, while > > > > > with "duty_cycle = 0" the rising edge should be delayed until the > > > > > currently running period is over.[1] > > > > > > > > > > So the thing to do here (IMHO) is: > > > > > > > > > > Iff with PIPGM_PCSR = 0 configuring a new setting (that is finalized > > > > > with writing a non-zero value to PIPGM_PCSR) completes the currently > > > > > running period, then always assume the PWM as enabled. > > > > > > > > Yes, this device works that way. > > > > > > OK, then please use > > > > > > state->enabled = true > > > > > > unconditionally in visconti_pwm_get_state(). > > > > Please let me check. > > If I unconditionally add 'state->enabled = true' to visconti_pwm_get_state(), > > state->enabled is set to true because visconti_pwm_get_state() is called when > > the device is created (this is when I write the device number to the export of > > /sys/class/pwm/pwmchip0 ). > > And since PIPGM_PCSR is 0 in this state, the pulse by PWM is not output. > > A PWM that is currently configured with .enabled = true and .duty_cycle > = 0 doesn't have a pulse, so this is fine. > I understood, thanks. > > However, I think this means that the device is working as this driver. > > I don't understand this sentence. The description of the struct pwm_state says "PWM enabled status". I thought 'state-> enabled' would hold the working state of the hardware. > > Best regards > Uwe Best regards, Nobuhiro From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1FF65C433ED for ; Sun, 18 Apr 2021 11:09:29 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9A83761354 for ; Sun, 18 Apr 2021 11:09:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9A83761354 Authentication-Results: mail.kernel.org; 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Sun, 18 Apr 2021 20:07:19 +0900 Date: Sun, 18 Apr 2021 20:07:18 +0900 From: Nobuhiro Iwamatsu To: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= Cc: Rob Herring , Thierry Reding , Lee Jones , devicetree@vger.kernel.org, linux-pwm@vger.kernel.org, punit1.agrawal@toshiba.co.jp, yuji2.ishikawa@toshiba.co.jp, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 2/2] pwm: visconti: Add Toshiba Visconti SoC PWM support X-TSB-HOP: ON Message-ID: <20210418110718.4zrh665anbz3wmqc@toshiba.co.jp> References: <20210409230837.1919744-1-nobuhiro1.iwamatsu@toshiba.co.jp> <20210409230837.1919744-3-nobuhiro1.iwamatsu@toshiba.co.jp> <20210410135321.oissremqropvrpd3@pengutronix.de> <20210412025536.i5chpp6sighunvfx@toshiba.co.jp> <20210412070232.6q3cgqvuj53p4cmi@pengutronix.de> <20210416080721.oa7xdvu22w2b2rkf@toshiba.co.jp> <20210416094426.x4gyw3drp2fcwczs@pengutronix.de> <20210416121523.c34trzsrlcjuzirl@toshiba.co.jp> <20210417155009.vnqxx3fn2yjzp3qc@pengutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210417155009.vnqxx3fn2yjzp3qc@pengutronix.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210418_040737_211556_8875BB21 X-CRM114-Status: GOOD ( 29.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Uwe, On Sat, Apr 17, 2021 at 05:50:09PM +0200, Uwe Kleine-K=F6nig wrote: > Hello Nobuhiro, > = > On Fri, Apr 16, 2021 at 09:15:23PM +0900, Nobuhiro Iwamatsu wrote: > > > > > For me the critical (and only) difference between "off" and > > > > > "duty cycle =3D 0" is that when a new configuration is to be appl= ied. In > > > > > the "off" state a new period can (and should) start immediately, = while > > > > > with "duty_cycle =3D 0" the rising edge should be delayed until t= he > > > > > currently running period is over.[1] > > > > > = > > > > > So the thing to do here (IMHO) is: > > > > > = > > > > > Iff with PIPGM_PCSR =3D 0 configuring a new setting (that is fina= lized > > > > > with writing a non-zero value to PIPGM_PCSR) completes the curren= tly > > > > > running period, then always assume the PWM as enabled. > > > > = > > > > Yes, this device works that way. > > > = > > > OK, then please use > > > = > > > state->enabled =3D true > > > = > > > unconditionally in visconti_pwm_get_state(). > > = > > Please let me check. > > If I unconditionally add 'state->enabled =3D true' to visconti_pwm_get_= state(), > > state->enabled is set to true because visconti_pwm_get_state() is calle= d when > > the device is created (this is when I write the device number to the ex= port of > > /sys/class/pwm/pwmchip0 ). > > And since PIPGM_PCSR is 0 in this state, the pulse by PWM is not output. > = > A PWM that is currently configured with .enabled =3D true and .duty_cycle > =3D 0 doesn't have a pulse, so this is fine. > = I understood, thanks. > > However, I think this means that the device is working as this driver. > = > I don't understand this sentence. The description of the struct pwm_state says "PWM enabled status". I thought 'state-> enabled' would hold the working state of the hardware. > = > Best regards > Uwe Best regards, Nobuhiro _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel