* [PATCH v5 00/31] target/arm: enforce alignment
@ 2021-04-19 20:22 Richard Henderson
2021-04-19 20:22 ` [PATCH v5 01/31] target/arm: Fix decode of align in VLDST_single Richard Henderson
` (31 more replies)
0 siblings, 32 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Based-on: 20210416183106.1516563-1-richard.henderson@linaro.org
("[PATCH v5 for-6.1 0/9] target/arm mte fixes")
Changes for v5:
* Address review issues.
* Use cpu_abort in assert_hflags_rebuild_correctly
The only patch lacking review is the new one:
07-target-arm-Use-cpu_abort-in-assert_hflags_rebuild.patch
r~
Richard Henderson (31):
target/arm: Fix decode of align in VLDST_single
target/arm: Rename TBFLAG_A32, SCTLR_B
target/arm: Rename TBFLAG_ANY, PSTATE_SS
target/arm: Add wrapper macros for accessing tbflags
target/arm: Introduce CPUARMTBFlags
target/arm: Move mode specific TB flags to tb->cs_base
target/arm: Use cpu_abort in assert_hflags_rebuild_correctly
target/arm: Move TBFLAG_AM32 bits to the top
target/arm: Move TBFLAG_ANY bits to the bottom
target/arm: Add ALIGN_MEM to TBFLAG_ANY
target/arm: Adjust gen_aa32_{ld,st}_i32 for align+endianness
target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64
target/arm: Fix SCTLR_B test for TCGv_i64 load/store
target/arm: Adjust gen_aa32_{ld,st}_i64 for align+endianness
target/arm: Enforce word alignment for LDRD/STRD
target/arm: Enforce alignment for LDA/LDAH/STL/STLH
target/arm: Enforce alignment for LDM/STM
target/arm: Enforce alignment for RFE
target/arm: Enforce alignment for SRS
target/arm: Enforce alignment for VLDM/VSTM
target/arm: Enforce alignment for VLDR/VSTR
target/arm: Enforce alignment for VLDn (all lanes)
target/arm: Enforce alignment for VLDn/VSTn (multiple)
target/arm: Enforce alignment for VLDn/VSTn (single)
target/arm: Use finalize_memop for aa64 gpr load/store
target/arm: Use finalize_memop for aa64 fpr load/store
target/arm: Enforce alignment for aa64 load-acq/store-rel
target/arm: Use MemOp for size + endian in aa64 vector ld/st
target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
target/arm: Enforce alignment for aa64 vector LDn/STn (single)
target/arm: Enforce alignment for sve LD1R
target/arm/cpu.h | 105 ++++++++-----
target/arm/translate.h | 38 +++++
target/arm/neon-ls.decode | 4 +-
target/arm/helper-a64.c | 2 +-
target/arm/helper.c | 163 ++++++++++----------
target/arm/translate-a64.c | 214 +++++++++++++-------------
target/arm/translate-sve.c | 2 +-
target/arm/translate.c | 258 +++++++++++++++++---------------
target/arm/translate-neon.c.inc | 117 ++++++++++++---
target/arm/translate-vfp.c.inc | 20 +--
10 files changed, 556 insertions(+), 367 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v5 01/31] target/arm: Fix decode of align in VLDST_single
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 02/31] target/arm: Rename TBFLAG_A32, SCTLR_B Richard Henderson
` (30 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
The encoding of size = 2 and size = 3 had the incorrect decode
for align, overlapping the stride field. This error was hidden
by what should have been unnecessary masking in translate.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/neon-ls.decode | 4 ++--
target/arm/translate-neon.c.inc | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
index c17f5019e3..0a2a0e15db 100644
--- a/target/arm/neon-ls.decode
+++ b/target/arm/neon-ls.decode
@@ -46,7 +46,7 @@ VLD_all_lanes 1111 0100 1 . 1 0 rn:4 .... 11 n:2 size:2 t:1 a:1 rm:4 \
VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 00 n:2 reg_idx:3 align:1 rm:4 \
vd=%vd_dp size=0 stride=1
-VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 align:2 rm:4 \
+VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 01 n:2 reg_idx:2 . align:1 rm:4 \
vd=%vd_dp size=1 stride=%imm1_5_p1
-VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 align:3 rm:4 \
+VLDST_single 1111 0100 1 . l:1 0 rn:4 .... 10 n:2 reg_idx:1 . align:2 rm:4 \
vd=%vd_dp size=2 stride=%imm1_6_p1
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index f6c68e30ab..0e5828744b 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -606,7 +606,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
switch (nregs) {
case 1:
if (((a->align & (1 << a->size)) != 0) ||
- (a->size == 2 && ((a->align & 3) == 1 || (a->align & 3) == 2))) {
+ (a->size == 2 && (a->align == 1 || a->align == 2))) {
return false;
}
break;
@@ -621,7 +621,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
}
break;
case 4:
- if ((a->size == 2) && ((a->align & 3) == 3)) {
+ if (a->size == 2 && a->align == 3) {
return false;
}
break;
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 02/31] target/arm: Rename TBFLAG_A32, SCTLR_B
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
2021-04-19 20:22 ` [PATCH v5 01/31] target/arm: Fix decode of align in VLDST_single Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 03/31] target/arm: Rename TBFLAG_ANY, PSTATE_SS Richard Henderson
` (29 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
We're about to rearrange the macro expansion surrounding tbflags,
and this field name will be expanded using the bit definition of
the same name, resulting in a token pasting error.
So SCTLR_B -> SCTLR__B in the 3 uses, and document it.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 2 +-
target/arm/helper.c | 2 +-
target/arm/translate.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 193a49ec7f..304e0a6af3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3423,7 +3423,7 @@ FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */
*/
FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */
-FIELD(TBFLAG_A32, SCTLR_B, 15, 1)
+FIELD(TBFLAG_A32, SCTLR__B, 15, 1) /* Cannot overlap with SCTLR_B */
FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
/*
* Indicates whether cp register reads and writes by guest code should access
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d9220be7c5..556b9d4f0a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13003,7 +13003,7 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
bool sctlr_b = arm_sctlr_b(env);
if (sctlr_b) {
- flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, 1);
+ flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR__B, 1);
}
if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7103da2d7a..0b56e060a5 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8879,7 +8879,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE;
dc->debug_target_el =
FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
- dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR_B);
+ dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR__B);
dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE);
dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS);
dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 03/31] target/arm: Rename TBFLAG_ANY, PSTATE_SS
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
2021-04-19 20:22 ` [PATCH v5 01/31] target/arm: Fix decode of align in VLDST_single Richard Henderson
2021-04-19 20:22 ` [PATCH v5 02/31] target/arm: Rename TBFLAG_A32, SCTLR_B Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 04/31] target/arm: Add wrapper macros for accessing tbflags Richard Henderson
` (28 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
We're about to rearrange the macro expansion surrounding tbflags,
and this field name will be expanded using the bit definition of
the same name, resulting in a token pasting error.
So PSTATE_SS -> PSTATE__SS in the uses, and document it.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 2 +-
target/arm/helper.c | 4 ++--
target/arm/translate-a64.c | 2 +-
target/arm/translate.c | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 304e0a6af3..4cbf2db3e3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3396,7 +3396,7 @@ typedef ARMCPU ArchCPU;
*/
FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
-FIELD(TBFLAG_ANY, PSTATE_SS, 29, 1) /* Not cached. */
+FIELD(TBFLAG_ANY, PSTATE__SS, 29, 1) /* Not cached. */
FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
/* Target EL if we take a floating-point-disabled exception */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 556b9d4f0a..cd8dec126f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13333,11 +13333,11 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
* 0 x Inactive (the TB flag for SS is always 0)
* 1 0 Active-pending
* 1 1 Active-not-pending
- * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB.
+ * SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
*/
if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) &&
(env->pstate & PSTATE_SS)) {
- flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1);
+ flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE__SS, 1);
}
*pflags = flags;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index f35a5e8174..64b3a5200c 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14733,7 +14733,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
* end the TB
*/
dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
- dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
+ dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS);
dc->is_ldex = false;
dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0b56e060a5..3c5ca9f7e5 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8909,7 +8909,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
* end the TB
*/
dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
- dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
+ dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS);
dc->is_ldex = false;
dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 04/31] target/arm: Add wrapper macros for accessing tbflags
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (2 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 03/31] target/arm: Rename TBFLAG_ANY, PSTATE_SS Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 05/31] target/arm: Introduce CPUARMTBFlags Richard Henderson
` (27 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
We're about to split tbflags into two parts. These macros
will ensure that the correct part is used with the correct
set of bits.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 22 +++++++++-
target/arm/helper-a64.c | 2 +-
target/arm/helper.c | 85 +++++++++++++++++---------------------
target/arm/translate-a64.c | 36 ++++++++--------
target/arm/translate.c | 48 ++++++++++-----------
5 files changed, 101 insertions(+), 92 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 4cbf2db3e3..b798ff8115 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3462,6 +3462,26 @@ FIELD(TBFLAG_A64, TCMA, 16, 2)
FIELD(TBFLAG_A64, MTE_ACTIVE, 18, 1)
FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
+/*
+ * Helpers for using the above.
+ */
+#define DP_TBFLAG_ANY(DST, WHICH, VAL) \
+ (DST = FIELD_DP32(DST, TBFLAG_ANY, WHICH, VAL))
+#define DP_TBFLAG_A64(DST, WHICH, VAL) \
+ (DST = FIELD_DP32(DST, TBFLAG_A64, WHICH, VAL))
+#define DP_TBFLAG_A32(DST, WHICH, VAL) \
+ (DST = FIELD_DP32(DST, TBFLAG_A32, WHICH, VAL))
+#define DP_TBFLAG_M32(DST, WHICH, VAL) \
+ (DST = FIELD_DP32(DST, TBFLAG_M32, WHICH, VAL))
+#define DP_TBFLAG_AM32(DST, WHICH, VAL) \
+ (DST = FIELD_DP32(DST, TBFLAG_AM32, WHICH, VAL))
+
+#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN, TBFLAG_ANY, WHICH)
+#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN, TBFLAG_A64, WHICH)
+#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN, TBFLAG_A32, WHICH)
+#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN, TBFLAG_M32, WHICH)
+#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN, TBFLAG_AM32, WHICH)
+
/**
* cpu_mmu_index:
* @env: The cpu environment
@@ -3472,7 +3492,7 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
*/
static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
{
- return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX);
+ return EX_TBFLAG_ANY(env->hflags, MMUIDX);
}
static inline bool bswap_code(bool sctlr_b)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index 061c8ff846..9cc3b066e2 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -1020,7 +1020,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
* the hflags rebuild, since we can pull the composite TBII field
* from there.
*/
- tbii = FIELD_EX32(env->hflags, TBFLAG_A64, TBII);
+ tbii = EX_TBFLAG_A64(env->hflags, TBII);
if ((tbii >> extract64(new_pc, 55, 1)) & 1) {
/* TBI is enabled. */
int core_mmu_idx = cpu_mmu_index(env, false);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index cd8dec126f..2769e6fd35 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12987,12 +12987,11 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
ARMMMUIdx mmu_idx, uint32_t flags)
{
- flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el);
- flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX,
- arm_to_core_mmu_idx(mmu_idx));
+ DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
+ DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
if (arm_singlestep_active(env)) {
- flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1);
+ DP_TBFLAG_ANY(flags, SS_ACTIVE, 1);
}
return flags;
}
@@ -13003,12 +13002,12 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
bool sctlr_b = arm_sctlr_b(env);
if (sctlr_b) {
- flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR__B, 1);
+ DP_TBFLAG_A32(flags, SCTLR__B, 1);
}
if (arm_cpu_data_is_big_endian_a32(env, sctlr_b)) {
- flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
+ DP_TBFLAG_ANY(flags, BE_DATA, 1);
}
- flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env));
+ DP_TBFLAG_A32(flags, NS, !access_secure_reg(env));
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
}
@@ -13019,7 +13018,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
uint32_t flags = 0;
if (arm_v7m_is_handler_mode(env)) {
- flags = FIELD_DP32(flags, TBFLAG_M32, HANDLER, 1);
+ DP_TBFLAG_M32(flags, HANDLER, 1);
}
/*
@@ -13030,7 +13029,7 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
if (arm_feature(env, ARM_FEATURE_V8) &&
!((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
(env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
- flags = FIELD_DP32(flags, TBFLAG_M32, STACKCHECK, 1);
+ DP_TBFLAG_M32(flags, STACKCHECK, 1);
}
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
@@ -13040,8 +13039,7 @@ static uint32_t rebuild_hflags_aprofile(CPUARMState *env)
{
int flags = 0;
- flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL,
- arm_debug_target_el(env));
+ DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env));
return flags;
}
@@ -13051,12 +13049,12 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el,
uint32_t flags = rebuild_hflags_aprofile(env);
if (arm_el_is_aa64(env, 1)) {
- flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
+ DP_TBFLAG_A32(flags, VFPEN, 1);
}
if (arm_current_el(env) < 2 && env->cp15.hstr_el2 &&
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
- flags = FIELD_DP32(flags, TBFLAG_A32, HSTR_ACTIVE, 1);
+ DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
}
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
@@ -13071,14 +13069,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
uint64_t sctlr;
int tbii, tbid;
- flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
+ DP_TBFLAG_ANY(flags, AARCH64_STATE, 1);
/* Get control bits for tagged addresses. */
tbid = aa64_va_parameter_tbi(tcr, mmu_idx);
tbii = tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx);
- flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
- flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid);
+ DP_TBFLAG_A64(flags, TBII, tbii);
+ DP_TBFLAG_A64(flags, TBID, tbid);
if (cpu_isar_feature(aa64_sve, env_archcpu(env))) {
int sve_el = sve_exception_el(env, el);
@@ -13093,14 +13091,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
} else {
zcr_len = sve_zcr_len_for_el(env, el);
}
- flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
- flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
+ DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el);
+ DP_TBFLAG_A64(flags, ZCR_LEN, zcr_len);
}
sctlr = regime_sctlr(env, stage1);
if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
- flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1);
+ DP_TBFLAG_ANY(flags, BE_DATA, 1);
}
if (cpu_isar_feature(aa64_pauth, env_archcpu(env))) {
@@ -13111,14 +13109,14 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
* The decision of which action to take is left to a helper.
*/
if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
- flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
+ DP_TBFLAG_A64(flags, PAUTH_ACTIVE, 1);
}
}
if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
/* Note that SCTLR_EL[23].BT == SCTLR_BT1. */
if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) {
- flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1);
+ DP_TBFLAG_A64(flags, BT, 1);
}
}
@@ -13130,7 +13128,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
case ARMMMUIdx_SE10_1:
case ARMMMUIdx_SE10_1_PAN:
/* TODO: ARMv8.3-NV */
- flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
+ DP_TBFLAG_A64(flags, UNPRIV, 1);
break;
case ARMMMUIdx_E20_2:
case ARMMMUIdx_E20_2_PAN:
@@ -13141,7 +13139,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
* gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
*/
if (env->cp15.hcr_el2 & HCR_TGE) {
- flags = FIELD_DP32(flags, TBFLAG_A64, UNPRIV, 1);
+ DP_TBFLAG_A64(flags, UNPRIV, 1);
}
break;
default:
@@ -13159,24 +13157,23 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
* 4) If no Allocation Tag Access, then all accesses are Unchecked.
*/
if (allocation_tag_access_enabled(env, el, sctlr)) {
- flags = FIELD_DP32(flags, TBFLAG_A64, ATA, 1);
+ DP_TBFLAG_A64(flags, ATA, 1);
if (tbid
&& !(env->pstate & PSTATE_TCO)
&& (sctlr & (el == 0 ? SCTLR_TCF0 : SCTLR_TCF))) {
- flags = FIELD_DP32(flags, TBFLAG_A64, MTE_ACTIVE, 1);
+ DP_TBFLAG_A64(flags, MTE_ACTIVE, 1);
}
}
/* And again for unprivileged accesses, if required. */
- if (FIELD_EX32(flags, TBFLAG_A64, UNPRIV)
+ if (EX_TBFLAG_A64(flags, UNPRIV)
&& tbid
&& !(env->pstate & PSTATE_TCO)
&& (sctlr & SCTLR_TCF0)
&& allocation_tag_access_enabled(env, 0, sctlr)) {
- flags = FIELD_DP32(flags, TBFLAG_A64, MTE0_ACTIVE, 1);
+ DP_TBFLAG_A64(flags, MTE0_ACTIVE, 1);
}
/* Cache TCMA as well as TBI. */
- flags = FIELD_DP32(flags, TBFLAG_A64, TCMA,
- aa64_va_parameter_tcma(tcr, mmu_idx));
+ DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx));
}
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
@@ -13272,10 +13269,10 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
*cs_base = 0;
assert_hflags_rebuild_correctly(env);
- if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) {
+ if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) {
*pc = env->pc;
if (cpu_isar_feature(aa64_bti, env_archcpu(env))) {
- flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype);
+ DP_TBFLAG_A64(flags, BTYPE, env->btype);
}
} else {
*pc = env->regs[15];
@@ -13284,7 +13281,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
if (arm_feature(env, ARM_FEATURE_M_SECURITY) &&
FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S)
!= env->v7m.secure) {
- flags = FIELD_DP32(flags, TBFLAG_M32, FPCCR_S_WRONG, 1);
+ DP_TBFLAG_M32(flags, FPCCR_S_WRONG, 1);
}
if ((env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) &&
@@ -13296,12 +13293,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
* active FP context; we must create a new FP context before
* executing any FP insn.
*/
- flags = FIELD_DP32(flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED, 1);
+ DP_TBFLAG_M32(flags, NEW_FP_CTXT_NEEDED, 1);
}
bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK;
if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) {
- flags = FIELD_DP32(flags, TBFLAG_M32, LSPACT, 1);
+ DP_TBFLAG_M32(flags, LSPACT, 1);
}
} else {
/*
@@ -13309,21 +13306,18 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
* Note that VECLEN+VECSTRIDE are RES0 for M-profile.
*/
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
- flags = FIELD_DP32(flags, TBFLAG_A32,
- XSCALE_CPAR, env->cp15.c15_cpar);
+ DP_TBFLAG_A32(flags, XSCALE_CPAR, env->cp15.c15_cpar);
} else {
- flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN,
- env->vfp.vec_len);
- flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE,
- env->vfp.vec_stride);
+ DP_TBFLAG_A32(flags, VECLEN, env->vfp.vec_len);
+ DP_TBFLAG_A32(flags, VECSTRIDE, env->vfp.vec_stride);
}
if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
- flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1);
+ DP_TBFLAG_A32(flags, VFPEN, 1);
}
}
- flags = FIELD_DP32(flags, TBFLAG_AM32, THUMB, env->thumb);
- flags = FIELD_DP32(flags, TBFLAG_AM32, CONDEXEC, env->condexec_bits);
+ DP_TBFLAG_AM32(flags, THUMB, env->thumb);
+ DP_TBFLAG_AM32(flags, CONDEXEC, env->condexec_bits);
}
/*
@@ -13335,9 +13329,8 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
* 1 1 Active-not-pending
* SS_ACTIVE is set in hflags; PSTATE__SS is computed every TB.
*/
- if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) &&
- (env->pstate & PSTATE_SS)) {
- flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE__SS, 1);
+ if (EX_TBFLAG_ANY(flags, SS_ACTIVE) && (env->pstate & PSTATE_SS)) {
+ DP_TBFLAG_ANY(flags, PSTATE__SS, 1);
}
*pflags = flags;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 64b3a5200c..05d83a5f7a 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14684,28 +14684,28 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
!arm_el_is_aa64(env, 3);
dc->thumb = 0;
dc->sctlr_b = 0;
- dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE;
+ dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE;
dc->condexec_mask = 0;
dc->condexec_cond = 0;
- core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX);
+ core_mmu_idx = EX_TBFLAG_ANY(tb_flags, MMUIDX);
dc->mmu_idx = core_to_aa64_mmu_idx(core_mmu_idx);
- dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII);
- dc->tbid = FIELD_EX32(tb_flags, TBFLAG_A64, TBID);
- dc->tcma = FIELD_EX32(tb_flags, TBFLAG_A64, TCMA);
+ dc->tbii = EX_TBFLAG_A64(tb_flags, TBII);
+ dc->tbid = EX_TBFLAG_A64(tb_flags, TBID);
+ dc->tcma = EX_TBFLAG_A64(tb_flags, TCMA);
dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
#if !defined(CONFIG_USER_ONLY)
dc->user = (dc->current_el == 0);
#endif
- dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL);
- dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL);
- dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16;
- dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE);
- dc->bt = FIELD_EX32(tb_flags, TBFLAG_A64, BT);
- dc->btype = FIELD_EX32(tb_flags, TBFLAG_A64, BTYPE);
- dc->unpriv = FIELD_EX32(tb_flags, TBFLAG_A64, UNPRIV);
- dc->ata = FIELD_EX32(tb_flags, TBFLAG_A64, ATA);
- dc->mte_active[0] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE_ACTIVE);
- dc->mte_active[1] = FIELD_EX32(tb_flags, TBFLAG_A64, MTE0_ACTIVE);
+ dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
+ dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
+ dc->sve_len = (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16;
+ dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE);
+ dc->bt = EX_TBFLAG_A64(tb_flags, BT);
+ dc->btype = EX_TBFLAG_A64(tb_flags, BTYPE);
+ dc->unpriv = EX_TBFLAG_A64(tb_flags, UNPRIV);
+ dc->ata = EX_TBFLAG_A64(tb_flags, ATA);
+ dc->mte_active[0] = EX_TBFLAG_A64(tb_flags, MTE_ACTIVE);
+ dc->mte_active[1] = EX_TBFLAG_A64(tb_flags, MTE0_ACTIVE);
dc->vec_len = 0;
dc->vec_stride = 0;
dc->cp_regs = arm_cpu->cp_regs;
@@ -14732,10 +14732,10 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
* emit code to generate a software step exception
* end the TB
*/
- dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
- dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS);
+ dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE);
+ dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS);
dc->is_ldex = false;
- dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
+ dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL);
/* Bound the number of insns to execute to those left on the page. */
bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 3c5ca9f7e5..2c8abaa694 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8848,46 +8848,42 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
*/
dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
!arm_el_is_aa64(env, 3);
- dc->thumb = FIELD_EX32(tb_flags, TBFLAG_AM32, THUMB);
- dc->be_data = FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE;
- condexec = FIELD_EX32(tb_flags, TBFLAG_AM32, CONDEXEC);
+ dc->thumb = EX_TBFLAG_AM32(tb_flags, THUMB);
+ dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE;
+ condexec = EX_TBFLAG_AM32(tb_flags, CONDEXEC);
dc->condexec_mask = (condexec & 0xf) << 1;
dc->condexec_cond = condexec >> 4;
- core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX);
+ core_mmu_idx = EX_TBFLAG_ANY(tb_flags, MMUIDX);
dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx);
dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
#if !defined(CONFIG_USER_ONLY)
dc->user = (dc->current_el == 0);
#endif
- dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL);
+ dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
if (arm_feature(env, ARM_FEATURE_M)) {
dc->vfp_enabled = 1;
dc->be_data = MO_TE;
- dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_M32, HANDLER);
+ dc->v7m_handler_mode = EX_TBFLAG_M32(tb_flags, HANDLER);
dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
regime_is_secure(env, dc->mmu_idx);
- dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_M32, STACKCHECK);
- dc->v8m_fpccr_s_wrong =
- FIELD_EX32(tb_flags, TBFLAG_M32, FPCCR_S_WRONG);
+ dc->v8m_stackcheck = EX_TBFLAG_M32(tb_flags, STACKCHECK);
+ dc->v8m_fpccr_s_wrong = EX_TBFLAG_M32(tb_flags, FPCCR_S_WRONG);
dc->v7m_new_fp_ctxt_needed =
- FIELD_EX32(tb_flags, TBFLAG_M32, NEW_FP_CTXT_NEEDED);
- dc->v7m_lspact = FIELD_EX32(tb_flags, TBFLAG_M32, LSPACT);
+ EX_TBFLAG_M32(tb_flags, NEW_FP_CTXT_NEEDED);
+ dc->v7m_lspact = EX_TBFLAG_M32(tb_flags, LSPACT);
} else {
- dc->be_data =
- FIELD_EX32(tb_flags, TBFLAG_ANY, BE_DATA) ? MO_BE : MO_LE;
- dc->debug_target_el =
- FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
- dc->sctlr_b = FIELD_EX32(tb_flags, TBFLAG_A32, SCTLR__B);
- dc->hstr_active = FIELD_EX32(tb_flags, TBFLAG_A32, HSTR_ACTIVE);
- dc->ns = FIELD_EX32(tb_flags, TBFLAG_A32, NS);
- dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN);
+ dc->debug_target_el = EX_TBFLAG_ANY(tb_flags, DEBUG_TARGET_EL);
+ dc->sctlr_b = EX_TBFLAG_A32(tb_flags, SCTLR__B);
+ dc->hstr_active = EX_TBFLAG_A32(tb_flags, HSTR_ACTIVE);
+ dc->ns = EX_TBFLAG_A32(tb_flags, NS);
+ dc->vfp_enabled = EX_TBFLAG_A32(tb_flags, VFPEN);
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
- dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR);
+ dc->c15_cpar = EX_TBFLAG_A32(tb_flags, XSCALE_CPAR);
} else {
- dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN);
- dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE);
+ dc->vec_len = EX_TBFLAG_A32(tb_flags, VECLEN);
+ dc->vec_stride = EX_TBFLAG_A32(tb_flags, VECSTRIDE);
}
}
dc->cp_regs = cpu->cp_regs;
@@ -8908,8 +8904,8 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
* emit code to generate a software step exception
* end the TB
*/
- dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
- dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE__SS);
+ dc->ss_active = EX_TBFLAG_ANY(tb_flags, SS_ACTIVE);
+ dc->pstate_ss = EX_TBFLAG_ANY(tb_flags, PSTATE__SS);
dc->is_ldex = false;
dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
@@ -9348,11 +9344,11 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
DisasContext dc = { };
const TranslatorOps *ops = &arm_translator_ops;
- if (FIELD_EX32(tb->flags, TBFLAG_AM32, THUMB)) {
+ if (EX_TBFLAG_AM32(tb->flags, THUMB)) {
ops = &thumb_translator_ops;
}
#ifdef TARGET_AARCH64
- if (FIELD_EX32(tb->flags, TBFLAG_ANY, AARCH64_STATE)) {
+ if (EX_TBFLAG_ANY(tb->flags, AARCH64_STATE)) {
ops = &aarch64_translator_ops;
}
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 05/31] target/arm: Introduce CPUARMTBFlags
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (3 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 04/31] target/arm: Add wrapper macros for accessing tbflags Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 06/31] target/arm: Move mode specific TB flags to tb->cs_base Richard Henderson
` (26 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
In preparation for splitting tb->flags across multiple
fields, introduce a structure to hold the value(s).
So far this only migrates the one uint32_t and fixes
all of the places that require adjustment to match.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 26 ++++++++++++---------
target/arm/translate.h | 11 +++++++++
target/arm/helper.c | 48 +++++++++++++++++++++-----------------
target/arm/translate-a64.c | 2 +-
target/arm/translate.c | 7 +++---
5 files changed, 57 insertions(+), 37 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index b798ff8115..79af9a7c62 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -225,6 +225,10 @@ typedef struct ARMPACKey {
} ARMPACKey;
#endif
+/* See the commentary above the TBFLAG field definitions. */
+typedef struct CPUARMTBFlags {
+ uint32_t flags;
+} CPUARMTBFlags;
typedef struct CPUARMState {
/* Regs for current mode. */
@@ -253,7 +257,7 @@ typedef struct CPUARMState {
uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */
/* Cached TBFLAGS state. See below for which bits are included. */
- uint32_t hflags;
+ CPUARMTBFlags hflags;
/* Frequently accessed CPSR bits are stored separately for efficiency.
This contains all the other bits. Use cpsr_{read,write} to access
@@ -3466,21 +3470,21 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
* Helpers for using the above.
*/
#define DP_TBFLAG_ANY(DST, WHICH, VAL) \
- (DST = FIELD_DP32(DST, TBFLAG_ANY, WHICH, VAL))
+ (DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
#define DP_TBFLAG_A64(DST, WHICH, VAL) \
- (DST = FIELD_DP32(DST, TBFLAG_A64, WHICH, VAL))
+ (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A64, WHICH, VAL))
#define DP_TBFLAG_A32(DST, WHICH, VAL) \
- (DST = FIELD_DP32(DST, TBFLAG_A32, WHICH, VAL))
+ (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A32, WHICH, VAL))
#define DP_TBFLAG_M32(DST, WHICH, VAL) \
- (DST = FIELD_DP32(DST, TBFLAG_M32, WHICH, VAL))
+ (DST.flags = FIELD_DP32(DST.flags, TBFLAG_M32, WHICH, VAL))
#define DP_TBFLAG_AM32(DST, WHICH, VAL) \
- (DST = FIELD_DP32(DST, TBFLAG_AM32, WHICH, VAL))
+ (DST.flags = FIELD_DP32(DST.flags, TBFLAG_AM32, WHICH, VAL))
-#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN, TBFLAG_ANY, WHICH)
-#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN, TBFLAG_A64, WHICH)
-#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN, TBFLAG_A32, WHICH)
-#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN, TBFLAG_M32, WHICH)
-#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN, TBFLAG_AM32, WHICH)
+#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
+#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A64, WHICH)
+#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A32, WHICH)
+#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_M32, WHICH)
+#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_AM32, WHICH)
/**
* cpu_mmu_index:
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 423b0e08df..f30287e554 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -394,6 +394,17 @@ typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
+/**
+ * arm_tbflags_from_tb:
+ * @tb: the TranslationBlock
+ *
+ * Extract the flag values from @tb.
+ */
+static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
+{
+ return (CPUARMTBFlags){ tb->flags };
+}
+
/*
* Enum for argument to fpstatus_ptr().
*/
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2769e6fd35..f564e59084 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12984,8 +12984,9 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
}
#endif
-static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
- ARMMMUIdx mmu_idx, uint32_t flags)
+static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el,
+ ARMMMUIdx mmu_idx,
+ CPUARMTBFlags flags)
{
DP_TBFLAG_ANY(flags, FPEXC_EL, fp_el);
DP_TBFLAG_ANY(flags, MMUIDX, arm_to_core_mmu_idx(mmu_idx));
@@ -12996,8 +12997,9 @@ static uint32_t rebuild_hflags_common(CPUARMState *env, int fp_el,
return flags;
}
-static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
- ARMMMUIdx mmu_idx, uint32_t flags)
+static CPUARMTBFlags rebuild_hflags_common_32(CPUARMState *env, int fp_el,
+ ARMMMUIdx mmu_idx,
+ CPUARMTBFlags flags)
{
bool sctlr_b = arm_sctlr_b(env);
@@ -13012,10 +13014,10 @@ static uint32_t rebuild_hflags_common_32(CPUARMState *env, int fp_el,
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
}
-static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
- ARMMMUIdx mmu_idx)
+static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
+ ARMMMUIdx mmu_idx)
{
- uint32_t flags = 0;
+ CPUARMTBFlags flags = {};
if (arm_v7m_is_handler_mode(env)) {
DP_TBFLAG_M32(flags, HANDLER, 1);
@@ -13035,18 +13037,18 @@ static uint32_t rebuild_hflags_m32(CPUARMState *env, int fp_el,
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
}
-static uint32_t rebuild_hflags_aprofile(CPUARMState *env)
+static CPUARMTBFlags rebuild_hflags_aprofile(CPUARMState *env)
{
- int flags = 0;
+ CPUARMTBFlags flags = {};
DP_TBFLAG_ANY(flags, DEBUG_TARGET_EL, arm_debug_target_el(env));
return flags;
}
-static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el,
- ARMMMUIdx mmu_idx)
+static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
+ ARMMMUIdx mmu_idx)
{
- uint32_t flags = rebuild_hflags_aprofile(env);
+ CPUARMTBFlags flags = rebuild_hflags_aprofile(env);
if (arm_el_is_aa64(env, 1)) {
DP_TBFLAG_A32(flags, VFPEN, 1);
@@ -13060,10 +13062,10 @@ static uint32_t rebuild_hflags_a32(CPUARMState *env, int fp_el,
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
}
-static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
- ARMMMUIdx mmu_idx)
+static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
+ ARMMMUIdx mmu_idx)
{
- uint32_t flags = rebuild_hflags_aprofile(env);
+ CPUARMTBFlags flags = rebuild_hflags_aprofile(env);
ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
uint64_t sctlr;
@@ -13179,7 +13181,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
return rebuild_hflags_common(env, fp_el, mmu_idx, flags);
}
-static uint32_t rebuild_hflags_internal(CPUARMState *env)
+static CPUARMTBFlags rebuild_hflags_internal(CPUARMState *env)
{
int el = arm_current_el(env);
int fp_el = fp_exception_el(env, el);
@@ -13208,6 +13210,7 @@ void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
int el = arm_current_el(env);
int fp_el = fp_exception_el(env, el);
ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el);
+
env->hflags = rebuild_hflags_m32(env, fp_el, mmu_idx);
}
@@ -13250,12 +13253,12 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, int el)
static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
{
#ifdef CONFIG_DEBUG_TCG
- uint32_t env_flags_current = env->hflags;
- uint32_t env_flags_rebuilt = rebuild_hflags_internal(env);
+ CPUARMTBFlags c = env->hflags;
+ CPUARMTBFlags r = rebuild_hflags_internal(env);
- if (unlikely(env_flags_current != env_flags_rebuilt)) {
+ if (unlikely(c.flags != r.flags)) {
fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
- env_flags_current, env_flags_rebuilt);
+ c.flags, r.flags);
abort();
}
#endif
@@ -13264,10 +13267,11 @@ static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{
- uint32_t flags = env->hflags;
+ CPUARMTBFlags flags;
*cs_base = 0;
assert_hflags_rebuild_correctly(env);
+ flags = env->hflags;
if (EX_TBFLAG_ANY(flags, AARCH64_STATE)) {
*pc = env->pc;
@@ -13333,7 +13337,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
DP_TBFLAG_ANY(flags, PSTATE__SS, 1);
}
- *pflags = flags;
+ *pflags = flags.flags;
}
#ifdef TARGET_AARCH64
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 05d83a5f7a..b32ff56666 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14670,7 +14670,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cpu->env_ptr;
ARMCPU *arm_cpu = env_archcpu(env);
- uint32_t tb_flags = dc->base.tb->flags;
+ CPUARMTBFlags tb_flags = arm_tbflags_from_tb(dc->base.tb);
int bound, core_mmu_idx;
dc->isar = &arm_cpu->isar;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2c8abaa694..418715fe13 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8836,7 +8836,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
DisasContext *dc = container_of(dcbase, DisasContext, base);
CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = env_archcpu(env);
- uint32_t tb_flags = dc->base.tb->flags;
+ CPUARMTBFlags tb_flags = arm_tbflags_from_tb(dc->base.tb);
uint32_t condexec, core_mmu_idx;
dc->isar = &cpu->isar;
@@ -9343,12 +9343,13 @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
{
DisasContext dc = { };
const TranslatorOps *ops = &arm_translator_ops;
+ CPUARMTBFlags tb_flags = arm_tbflags_from_tb(tb);
- if (EX_TBFLAG_AM32(tb->flags, THUMB)) {
+ if (EX_TBFLAG_AM32(tb_flags, THUMB)) {
ops = &thumb_translator_ops;
}
#ifdef TARGET_AARCH64
- if (EX_TBFLAG_ANY(tb->flags, AARCH64_STATE)) {
+ if (EX_TBFLAG_ANY(tb_flags, AARCH64_STATE)) {
ops = &aarch64_translator_ops;
}
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 06/31] target/arm: Move mode specific TB flags to tb->cs_base
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (4 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 05/31] target/arm: Introduce CPUARMTBFlags Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 07/31] target/arm: Use cpu_abort in assert_hflags_rebuild_correctly Richard Henderson
` (25 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Now that we have all of the proper macros defined, expanding
the CPUARMTBFlags structure and populating the two TB fields
is relatively simple.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v5: Adjust assert_hflags_rebuild_correctly.
---
target/arm/cpu.h | 49 ++++++++++++++++++++++++------------------
target/arm/translate.h | 2 +-
target/arm/helper.c | 10 +++++----
3 files changed, 35 insertions(+), 26 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 79af9a7c62..a8da7c55a6 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -228,6 +228,7 @@ typedef struct ARMPACKey {
/* See the commentary above the TBFLAG field definitions. */
typedef struct CPUARMTBFlags {
uint32_t flags;
+ target_ulong flags2;
} CPUARMTBFlags;
typedef struct CPUARMState {
@@ -3381,20 +3382,26 @@ typedef ARMCPU ArchCPU;
#include "exec/cpu-all.h"
/*
- * Bit usage in the TB flags field: bit 31 indicates whether we are
- * in 32 or 64 bit mode. The meaning of the other bits depends on that.
- * We put flags which are shared between 32 and 64 bit mode at the top
- * of the word, and flags which apply to only one mode at the bottom.
+ * We have more than 32-bits worth of state per TB, so we split the data
+ * between tb->flags and tb->cs_base, which is otherwise unused for ARM.
+ * We collect these two parts in CPUARMTBFlags where they are named
+ * flags and flags2 respectively.
*
- * 31 20 18 14 9 0
- * +--------------+-----+-----+----------+--------------+
- * | | | TBFLAG_A32 | |
- * | | +-----+----------+ TBFLAG_AM32 |
- * | TBFLAG_ANY | |TBFLAG_M32| |
- * | +-----------+----------+--------------|
- * | | TBFLAG_A64 |
- * +--------------+-------------------------------------+
- * 31 20 0
+ * The flags that are shared between all execution modes, TBFLAG_ANY,
+ * are stored in flags. The flags that are specific to a given mode
+ * are stores in flags2. Since cs_base is sized on the configured
+ * address size, flags2 always has 64-bits for A64, and a minimum of
+ * 32-bits for A32 and M32.
+ *
+ * The bits for 32-bit A-profile and M-profile partially overlap:
+ *
+ * 18 9 0
+ * +----------------+--------------+
+ * | TBFLAG_A32 | |
+ * +-----+----------+ TBFLAG_AM32 |
+ * | |TBFLAG_M32| |
+ * +-----+----------+--------------+
+ * 14 9 0
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
@@ -3472,19 +3479,19 @@ FIELD(TBFLAG_A64, MTE0_ACTIVE, 19, 1)
#define DP_TBFLAG_ANY(DST, WHICH, VAL) \
(DST.flags = FIELD_DP32(DST.flags, TBFLAG_ANY, WHICH, VAL))
#define DP_TBFLAG_A64(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A64, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A64, WHICH, VAL))
#define DP_TBFLAG_A32(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_A32, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_A32, WHICH, VAL))
#define DP_TBFLAG_M32(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_M32, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_M32, WHICH, VAL))
#define DP_TBFLAG_AM32(DST, WHICH, VAL) \
- (DST.flags = FIELD_DP32(DST.flags, TBFLAG_AM32, WHICH, VAL))
+ (DST.flags2 = FIELD_DP32(DST.flags2, TBFLAG_AM32, WHICH, VAL))
#define EX_TBFLAG_ANY(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_ANY, WHICH)
-#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A64, WHICH)
-#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_A32, WHICH)
-#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_M32, WHICH)
-#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags, TBFLAG_AM32, WHICH)
+#define EX_TBFLAG_A64(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A64, WHICH)
+#define EX_TBFLAG_A32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_A32, WHICH)
+#define EX_TBFLAG_M32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_M32, WHICH)
+#define EX_TBFLAG_AM32(IN, WHICH) FIELD_EX32(IN.flags2, TBFLAG_AM32, WHICH)
/**
* cpu_mmu_index:
diff --git a/target/arm/translate.h b/target/arm/translate.h
index f30287e554..50c2aba066 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -402,7 +402,7 @@ typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
*/
static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
{
- return (CPUARMTBFlags){ tb->flags };
+ return (CPUARMTBFlags){ tb->flags, tb->cs_base };
}
/*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f564e59084..4aa7650d3a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13256,9 +13256,11 @@ static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
CPUARMTBFlags c = env->hflags;
CPUARMTBFlags r = rebuild_hflags_internal(env);
- if (unlikely(c.flags != r.flags)) {
- fprintf(stderr, "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n",
- c.flags, r.flags);
+ if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
+ fprintf(stderr, "TCG hflags mismatch "
+ "(current:(0x%08x,0x" TARGET_FMT_lx ")"
+ " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
+ c.flags, c.flags2, r.flags, r.flags2);
abort();
}
#endif
@@ -13269,7 +13271,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
{
CPUARMTBFlags flags;
- *cs_base = 0;
assert_hflags_rebuild_correctly(env);
flags = env->hflags;
@@ -13338,6 +13339,7 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
}
*pflags = flags.flags;
+ *cs_base = flags.flags2;
}
#ifdef TARGET_AARCH64
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 07/31] target/arm: Use cpu_abort in assert_hflags_rebuild_correctly
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (5 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 06/31] target/arm: Move mode specific TB flags to tb->cs_base Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-20 9:07 ` Peter Maydell
2021-04-19 20:22 ` [PATCH v5 08/31] target/arm: Move TBFLAG_AM32 bits to the top Richard Henderson
` (24 subsequent siblings)
31 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-arm
Using cpu_abort takes care of things like unregistering a
SIGABRT handler for user-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 4aa7650d3a..8275eb2e65 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13257,11 +13257,10 @@ static inline void assert_hflags_rebuild_correctly(CPUARMState *env)
CPUARMTBFlags r = rebuild_hflags_internal(env);
if (unlikely(c.flags != r.flags || c.flags2 != r.flags2)) {
- fprintf(stderr, "TCG hflags mismatch "
- "(current:(0x%08x,0x" TARGET_FMT_lx ")"
- " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
- c.flags, c.flags2, r.flags, r.flags2);
- abort();
+ cpu_abort(env_cpu(env), "TCG hflags mismatch "
+ "(current:(0x%08x,0x" TARGET_FMT_lx ")"
+ " rebuilt:(0x%08x,0x" TARGET_FMT_lx ")\n",
+ c.flags, c.flags2, r.flags, r.flags2);
}
#endif
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 08/31] target/arm: Move TBFLAG_AM32 bits to the top
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (6 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 07/31] target/arm: Use cpu_abort in assert_hflags_rebuild_correctly Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 09/31] target/arm: Move TBFLAG_ANY bits to the bottom Richard Henderson
` (23 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Now that these bits have been moved out of tb->flags,
where TBFLAG_ANY was filling from the top, move AM32
to fill from the top, and A32 and M32 to fill from the
bottom. This means fewer changes when adding new bits.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 42 +++++++++++++++++++++---------------------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index a8da7c55a6..15104e1440 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3395,13 +3395,13 @@ typedef ARMCPU ArchCPU;
*
* The bits for 32-bit A-profile and M-profile partially overlap:
*
- * 18 9 0
- * +----------------+--------------+
- * | TBFLAG_A32 | |
- * +-----+----------+ TBFLAG_AM32 |
- * | |TBFLAG_M32| |
- * +-----+----------+--------------+
- * 14 9 0
+ * 31 23 11 10 0
+ * +-------------+----------+----------------+
+ * | | | TBFLAG_A32 |
+ * | TBFLAG_AM32 | +-----+----------+
+ * | | |TBFLAG_M32|
+ * +-------------+----------------+----------+
+ * 31 23 5 4 0
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
@@ -3418,44 +3418,44 @@ FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
/*
* Bit usage when in AArch32 state, both A- and M-profile.
*/
-FIELD(TBFLAG_AM32, CONDEXEC, 0, 8) /* Not cached. */
-FIELD(TBFLAG_AM32, THUMB, 8, 1) /* Not cached. */
+FIELD(TBFLAG_AM32, CONDEXEC, 24, 8) /* Not cached. */
+FIELD(TBFLAG_AM32, THUMB, 23, 1) /* Not cached. */
/*
* Bit usage when in AArch32 state, for A-profile only.
*/
-FIELD(TBFLAG_A32, VECLEN, 9, 3) /* Not cached. */
-FIELD(TBFLAG_A32, VECSTRIDE, 12, 2) /* Not cached. */
+FIELD(TBFLAG_A32, VECLEN, 0, 3) /* Not cached. */
+FIELD(TBFLAG_A32, VECSTRIDE, 3, 2) /* Not cached. */
/*
* We store the bottom two bits of the CPAR as TB flags and handle
* checks on the other bits at runtime. This shares the same bits as
* VECSTRIDE, which is OK as no XScale CPU has VFP.
* Not cached, because VECLEN+VECSTRIDE are not cached.
*/
-FIELD(TBFLAG_A32, XSCALE_CPAR, 12, 2)
-FIELD(TBFLAG_A32, VFPEN, 14, 1) /* Partially cached, minus FPEXC. */
-FIELD(TBFLAG_A32, SCTLR__B, 15, 1) /* Cannot overlap with SCTLR_B */
-FIELD(TBFLAG_A32, HSTR_ACTIVE, 16, 1)
+FIELD(TBFLAG_A32, XSCALE_CPAR, 5, 2)
+FIELD(TBFLAG_A32, VFPEN, 7, 1) /* Partially cached, minus FPEXC. */
+FIELD(TBFLAG_A32, SCTLR__B, 8, 1) /* Cannot overlap with SCTLR_B */
+FIELD(TBFLAG_A32, HSTR_ACTIVE, 9, 1)
/*
* Indicates whether cp register reads and writes by guest code should access
* the secure or nonsecure bank of banked registers; note that this is not
* the same thing as the current security state of the processor!
*/
-FIELD(TBFLAG_A32, NS, 17, 1)
+FIELD(TBFLAG_A32, NS, 10, 1)
/*
* Bit usage when in AArch32 state, for M-profile only.
*/
/* Handler (ie not Thread) mode */
-FIELD(TBFLAG_M32, HANDLER, 9, 1)
+FIELD(TBFLAG_M32, HANDLER, 0, 1)
/* Whether we should generate stack-limit checks */
-FIELD(TBFLAG_M32, STACKCHECK, 10, 1)
+FIELD(TBFLAG_M32, STACKCHECK, 1, 1)
/* Set if FPCCR.LSPACT is set */
-FIELD(TBFLAG_M32, LSPACT, 11, 1) /* Not cached. */
+FIELD(TBFLAG_M32, LSPACT, 2, 1) /* Not cached. */
/* Set if we must create a new FP context */
-FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 12, 1) /* Not cached. */
+FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */
/* Set if FPCCR.S does not match current security state */
-FIELD(TBFLAG_M32, FPCCR_S_WRONG, 13, 1) /* Not cached. */
+FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */
/*
* Bit usage when in AArch64 state
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 09/31] target/arm: Move TBFLAG_ANY bits to the bottom
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (7 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 08/31] target/arm: Move TBFLAG_AM32 bits to the top Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 10/31] target/arm: Add ALIGN_MEM to TBFLAG_ANY Richard Henderson
` (22 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Now that other bits have been moved out of tb->flags,
there's no point in filling from the top.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 15104e1440..5e0131be1a 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3405,15 +3405,15 @@ typedef ARMCPU ArchCPU;
*
* Unless otherwise noted, these bits are cached in env->hflags.
*/
-FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1)
-FIELD(TBFLAG_ANY, SS_ACTIVE, 30, 1)
-FIELD(TBFLAG_ANY, PSTATE__SS, 29, 1) /* Not cached. */
-FIELD(TBFLAG_ANY, BE_DATA, 28, 1)
-FIELD(TBFLAG_ANY, MMUIDX, 24, 4)
+FIELD(TBFLAG_ANY, AARCH64_STATE, 0, 1)
+FIELD(TBFLAG_ANY, SS_ACTIVE, 1, 1)
+FIELD(TBFLAG_ANY, PSTATE__SS, 2, 1) /* Not cached. */
+FIELD(TBFLAG_ANY, BE_DATA, 3, 1)
+FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
/* Target EL if we take a floating-point-disabled exception */
-FIELD(TBFLAG_ANY, FPEXC_EL, 22, 2)
+FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
/* For A-profile only, target EL for debug exceptions. */
-FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 20, 2)
+FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2)
/*
* Bit usage when in AArch32 state, both A- and M-profile.
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 10/31] target/arm: Add ALIGN_MEM to TBFLAG_ANY
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (8 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 09/31] target/arm: Move TBFLAG_ANY bits to the bottom Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 11/31] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Richard Henderson
` (21 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Use this to signal when memory access alignment is required.
This value comes from the CCR register for M-profile, and
from the SCTLR register for A-profile.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 2 ++
target/arm/translate.h | 2 ++
target/arm/helper.c | 19 +++++++++++++++++--
target/arm/translate-a64.c | 1 +
target/arm/translate.c | 7 +++----
5 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5e0131be1a..616b393253 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3414,6 +3414,8 @@ FIELD(TBFLAG_ANY, MMUIDX, 4, 4)
FIELD(TBFLAG_ANY, FPEXC_EL, 8, 2)
/* For A-profile only, target EL for debug exceptions. */
FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 10, 2)
+/* Memory operations require alignment: SCTLR_ELx.A or CCR.UNALIGN_TRP */
+FIELD(TBFLAG_ANY, ALIGN_MEM, 12, 1)
/*
* Bit usage when in AArch32 state, both A- and M-profile.
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 50c2aba066..b185c14a03 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -87,6 +87,8 @@ typedef struct DisasContext {
bool bt;
/* True if any CP15 access is trapped by HSTR_EL2 */
bool hstr_active;
+ /* True if memory operations require alignment */
+ bool align_mem;
/*
* >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
* < 0, set by the current instruction.
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8275eb2e65..cb542d4300 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -13018,6 +13018,12 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
ARMMMUIdx mmu_idx)
{
CPUARMTBFlags flags = {};
+ uint32_t ccr = env->v7m.ccr[env->v7m.secure];
+
+ /* Without HaveMainExt, CCR.UNALIGN_TRP is RES1. */
+ if (ccr & R_V7M_CCR_UNALIGN_TRP_MASK) {
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
+ }
if (arm_v7m_is_handler_mode(env)) {
DP_TBFLAG_M32(flags, HANDLER, 1);
@@ -13030,7 +13036,7 @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
*/
if (arm_feature(env, ARM_FEATURE_V8) &&
!((mmu_idx & ARM_MMU_IDX_M_NEGPRI) &&
- (env->v7m.ccr[env->v7m.secure] & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
+ (ccr & R_V7M_CCR_STKOFHFNMIGN_MASK))) {
DP_TBFLAG_M32(flags, STACKCHECK, 1);
}
@@ -13049,12 +13055,17 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el,
ARMMMUIdx mmu_idx)
{
CPUARMTBFlags flags = rebuild_hflags_aprofile(env);
+ int el = arm_current_el(env);
+
+ if (arm_sctlr(env, el) & SCTLR_A) {
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
+ }
if (arm_el_is_aa64(env, 1)) {
DP_TBFLAG_A32(flags, VFPEN, 1);
}
- if (arm_current_el(env) < 2 && env->cp15.hstr_el2 &&
+ if (el < 2 && env->cp15.hstr_el2 &&
(arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
DP_TBFLAG_A32(flags, HSTR_ACTIVE, 1);
}
@@ -13099,6 +13110,10 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
sctlr = regime_sctlr(env, stage1);
+ if (sctlr & SCTLR_A) {
+ DP_TBFLAG_ANY(flags, ALIGN_MEM, 1);
+ }
+
if (arm_cpu_data_is_big_endian_a64(el, sctlr)) {
DP_TBFLAG_ANY(flags, BE_DATA, 1);
}
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b32ff56666..92a62b1a75 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14697,6 +14697,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
dc->user = (dc->current_el == 0);
#endif
dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
+ dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
dc->sve_excp_el = EX_TBFLAG_A64(tb_flags, SVEEXC_EL);
dc->sve_len = (EX_TBFLAG_A64(tb_flags, ZCR_LEN) + 1) * 16;
dc->pauth_active = EX_TBFLAG_A64(tb_flags, PAUTH_ACTIVE);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 418715fe13..e918c2e1a4 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -933,8 +933,7 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
{
TCGv addr;
- if (arm_dc_feature(s, ARM_FEATURE_M) &&
- !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {
+ if (s->align_mem) {
opc |= MO_ALIGN;
}
@@ -948,8 +947,7 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
{
TCGv addr;
- if (arm_dc_feature(s, ARM_FEATURE_M) &&
- !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {
+ if (s->align_mem) {
opc |= MO_ALIGN;
}
@@ -8861,6 +8859,7 @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
dc->user = (dc->current_el == 0);
#endif
dc->fp_excp_el = EX_TBFLAG_ANY(tb_flags, FPEXC_EL);
+ dc->align_mem = EX_TBFLAG_ANY(tb_flags, ALIGN_MEM);
if (arm_feature(env, ARM_FEATURE_M)) {
dc->vfp_enabled = 1;
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 11/31] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (9 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 10/31] target/arm: Add ALIGN_MEM to TBFLAG_ANY Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 12/31] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Richard Henderson
` (20 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Create a finalize_memop function that computes alignment and
endianness and returns the final MemOp for the operation.
Split out gen_aa32_{ld,st}_internal_i32 which bypasses any special
handling of endianness or alignment. Adjust gen_aa32_{ld,st}_i32
so that s->be_data is not added by the callers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.h | 24 ++++++++
target/arm/translate.c | 100 +++++++++++++++++---------------
target/arm/translate-neon.c.inc | 9 +--
3 files changed, 79 insertions(+), 54 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index b185c14a03..0c60b83b3d 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -459,4 +459,28 @@ static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
return statusptr;
}
+/**
+ * finalize_memop:
+ * @s: DisasContext
+ * @opc: size+sign+align of the memory operation
+ *
+ * Build the complete MemOp for a memory operation, including alignment
+ * and endianness.
+ *
+ * If (op & MO_AMASK) then the operation already contains the required
+ * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally
+ * unaligned operation, e.g. for AccType_NORMAL.
+ *
+ * In the latter case, there are configuration bits that require alignment,
+ * and this is applied here. Note that there is no way to indicate that
+ * no alignment should ever be enforced; this must be handled manually.
+ */
+static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
+{
+ if (s->align_mem && !(opc & MO_AMASK)) {
+ opc |= MO_ALIGN;
+ }
+ return opc | s->be_data;
+}
+
#endif /* TARGET_ARM_TRANSLATE_H */
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e918c2e1a4..d46030248a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -908,7 +908,8 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
#define IS_USER_ONLY 0
#endif
-/* Abstractions of "generate code to do a guest load/store for
+/*
+ * Abstractions of "generate code to do a guest load/store for
* AArch32", where a vaddr is always 32 bits (and is zero
* extended if we're a 64 bit core) and data is also
* 32 bits unless specifically doing a 64 bit access.
@@ -916,7 +917,7 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
* that the address argument is TCGv_i32 rather than TCGv.
*/
-static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)
+static TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)
{
TCGv addr = tcg_temp_new();
tcg_gen_extu_i32_tl(addr, a32);
@@ -928,47 +929,51 @@ static inline TCGv gen_aa32_addr(DisasContext *s, TCGv_i32 a32, MemOp op)
return addr;
}
+/*
+ * Internal routines are used for NEON cases where the endianness
+ * and/or alignment has already been taken into account and manipulated.
+ */
+static void gen_aa32_ld_internal_i32(DisasContext *s, TCGv_i32 val,
+ TCGv_i32 a32, int index, MemOp opc)
+{
+ TCGv addr = gen_aa32_addr(s, a32, opc);
+ tcg_gen_qemu_ld_i32(val, addr, index, opc);
+ tcg_temp_free(addr);
+}
+
+static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
+ TCGv_i32 a32, int index, MemOp opc)
+{
+ TCGv addr = gen_aa32_addr(s, a32, opc);
+ tcg_gen_qemu_st_i32(val, addr, index, opc);
+ tcg_temp_free(addr);
+}
+
static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
int index, MemOp opc)
{
- TCGv addr;
-
- if (s->align_mem) {
- opc |= MO_ALIGN;
- }
-
- addr = gen_aa32_addr(s, a32, opc);
- tcg_gen_qemu_ld_i32(val, addr, index, opc);
- tcg_temp_free(addr);
+ gen_aa32_ld_internal_i32(s, val, a32, index, finalize_memop(s, opc));
}
static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
int index, MemOp opc)
{
- TCGv addr;
+ gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc));
+}
- if (s->align_mem) {
- opc |= MO_ALIGN;
+#define DO_GEN_LD(SUFF, OPC) \
+ static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
+ TCGv_i32 a32, int index) \
+ { \
+ gen_aa32_ld_i32(s, val, a32, index, OPC); \
}
- addr = gen_aa32_addr(s, a32, opc);
- tcg_gen_qemu_st_i32(val, addr, index, opc);
- tcg_temp_free(addr);
-}
-
-#define DO_GEN_LD(SUFF, OPC) \
-static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
- TCGv_i32 a32, int index) \
-{ \
- gen_aa32_ld_i32(s, val, a32, index, OPC | s->be_data); \
-}
-
-#define DO_GEN_ST(SUFF, OPC) \
-static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
- TCGv_i32 a32, int index) \
-{ \
- gen_aa32_st_i32(s, val, a32, index, OPC | s->be_data); \
-}
+#define DO_GEN_ST(SUFF, OPC) \
+ static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, \
+ TCGv_i32 a32, int index) \
+ { \
+ gen_aa32_st_i32(s, val, a32, index, OPC); \
+ }
static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
{
@@ -6456,7 +6461,7 @@ static bool op_load_rr(DisasContext *s, arg_ldst_rr *a,
addr = op_addr_rr_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop);
disas_set_da_iss(s, mop, issinfo);
/*
@@ -6477,7 +6482,7 @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a,
addr = op_addr_rr_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, mop);
disas_set_da_iss(s, mop, issinfo);
tcg_temp_free_i32(tmp);
@@ -6500,13 +6505,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
addr = op_addr_rr_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
store_reg(s, a->rt, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
store_reg(s, a->rt + 1, tmp);
/* LDRD w/ base writeback is undefined if the registers overlap. */
@@ -6529,13 +6534,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
addr = op_addr_rr_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, a->rt + 1);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
tcg_temp_free_i32(tmp);
op_addr_rr_post(s, a, addr, -4);
@@ -6600,7 +6605,7 @@ static bool op_load_ri(DisasContext *s, arg_ldst_ri *a,
addr = op_addr_ri_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop | s->be_data);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, mop);
disas_set_da_iss(s, mop, issinfo);
/*
@@ -6621,7 +6626,7 @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a,
addr = op_addr_ri_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, mop | s->be_data);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, mop);
disas_set_da_iss(s, mop, issinfo);
tcg_temp_free_i32(tmp);
@@ -6637,13 +6642,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
addr = op_addr_ri_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
store_reg(s, a->rt, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
store_reg(s, rt2, tmp);
/* LDRD w/ base writeback is undefined if the registers overlap. */
@@ -6676,13 +6681,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
addr = op_addr_ri_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, rt2);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | s->be_data);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
tcg_temp_free_i32(tmp);
op_addr_ri_post(s, a, addr, -4);
@@ -6908,7 +6913,7 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop)
addr = load_reg(s, a->rn);
tmp = load_reg(s, a->rt);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data);
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop);
disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite);
tcg_temp_free_i32(tmp);
@@ -7064,7 +7069,7 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop)
addr = load_reg(s, a->rn);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data);
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop);
disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel);
tcg_temp_free_i32(addr);
@@ -8248,8 +8253,7 @@ static bool op_tbranch(DisasContext *s, arg_tbranch *a, bool half)
addr = load_reg(s, a->rn);
tcg_gen_add_i32(addr, addr, tmp);
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
- half ? MO_UW | s->be_data : MO_UB);
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), half ? MO_UW : MO_UB);
tcg_temp_free_i32(addr);
tcg_gen_add_i32(tmp, tmp, tmp);
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index 0e5828744b..c82aa1412e 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -559,8 +559,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
addr = tcg_temp_new_i32();
load_reg_var(s, addr, a->rn);
for (reg = 0; reg < nregs; reg++) {
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
- s->be_data | size);
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), size);
if ((vd & 1) && vec_size == 16) {
/*
* We cannot write 16 bytes at once because the
@@ -650,13 +649,11 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
*/
for (reg = 0; reg < nregs; reg++) {
if (a->l) {
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s),
- s->be_data | a->size);
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), a->size);
neon_store_element(vd, a->reg_idx, a->size, tmp);
} else { /* Store */
neon_load_element(tmp, vd, a->reg_idx, a->size);
- gen_aa32_st_i32(s, tmp, addr, get_mem_index(s),
- s->be_data | a->size);
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), a->size);
}
vd += a->stride;
tcg_gen_addi_i32(addr, addr, 1 << a->size);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 12/31] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (10 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 11/31] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 13/31] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Richard Henderson
` (19 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
This is the only caller. Adjust some commentary to talk
about SCTLR_B instead of the vanishing function.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 37 ++++++++++++++++---------------------
1 file changed, 16 insertions(+), 21 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d46030248a..b47a58ee9a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -975,20 +975,17 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
gen_aa32_st_i32(s, val, a32, index, OPC); \
}
-static inline void gen_aa32_frob64(DisasContext *s, TCGv_i64 val)
-{
- /* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b) {
- tcg_gen_rotri_i64(val, val, 32);
- }
-}
-
static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
int index, MemOp opc)
{
TCGv addr = gen_aa32_addr(s, a32, opc);
tcg_gen_qemu_ld_i64(val, addr, index, opc);
- gen_aa32_frob64(s, val);
+
+ /* Not needed for user-mode BE32, where we use MO_BE instead. */
+ if (!IS_USER_ONLY && s->sctlr_b) {
+ tcg_gen_rotri_i64(val, val, 32);
+ }
+
tcg_temp_free(addr);
}
@@ -4987,16 +4984,13 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
TCGv_i32 tmp2 = tcg_temp_new_i32();
TCGv_i64 t64 = tcg_temp_new_i64();
- /* For AArch32, architecturally the 32-bit word at the lowest
+ /*
+ * For AArch32, architecturally the 32-bit word at the lowest
* address is always Rt and the one at addr+4 is Rt2, even if
* the CPU is big-endian. That means we don't want to do a
- * gen_aa32_ld_i64(), which invokes gen_aa32_frob64() as if
- * for an architecturally 64-bit access, but instead do a
- * 64-bit access using MO_BE if appropriate and then split
- * the two halves.
- * This only makes a difference for BE32 user-mode, where
- * frob64() must not flip the two halves of the 64-bit data
- * but this code must treat BE32 user-mode like BE32 system.
+ * gen_aa32_ld_i64(), which checks SCTLR_B as if for an
+ * architecturally 64-bit access, but instead do a 64-bit access
+ * using MO_BE if appropriate and then split the two halves.
*/
TCGv taddr = gen_aa32_addr(s, addr, opc);
@@ -5056,14 +5050,15 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
TCGv_i64 n64 = tcg_temp_new_i64();
t2 = load_reg(s, rt2);
- /* For AArch32, architecturally the 32-bit word at the lowest
+
+ /*
+ * For AArch32, architecturally the 32-bit word at the lowest
* address is always Rt and the one at addr+4 is Rt2, even if
* the CPU is big-endian. Since we're going to treat this as a
* single 64-bit BE store, we need to put the two halves in the
* opposite order for BE to LE, so that they end up in the right
- * places.
- * We don't want gen_aa32_frob64() because that does the wrong
- * thing for BE32 usermode.
+ * places. We don't want gen_aa32_st_i64, because that checks
+ * SCTLR_B as if for an architectural 64-bit access.
*/
if (s->be_data == MO_BE) {
tcg_gen_concat_i32_i64(n64, t2, t1);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 13/31] target/arm: Fix SCTLR_B test for TCGv_i64 load/store
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (11 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 12/31] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 14/31] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Richard Henderson
` (18 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Just because operating on a TCGv_i64 temporary does not
mean that we're performing a 64-bit operation. Restrict
the frobbing to actual 64-bit operations.
This bug is not currently visible because all current
users of these two functions always pass MO_64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b47a58ee9a..d37a3dfa4a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -982,7 +982,7 @@ static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
tcg_gen_qemu_ld_i64(val, addr, index, opc);
/* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b) {
+ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
tcg_gen_rotri_i64(val, val, 32);
}
@@ -1001,7 +1001,7 @@ static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
TCGv addr = gen_aa32_addr(s, a32, opc);
/* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b) {
+ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_rotri_i64(tmp, val, 32);
tcg_gen_qemu_st_i64(tmp, addr, index, opc);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 14/31] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (12 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 13/31] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 15/31] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
` (17 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Adjust the interface to match what has been done to the
TCGv_i32 load/store functions.
This is less obvious, because at present the only user of
these functions, trans_VLDST_multiple, also wants to manipulate
the endianness to speed up loading multiple bytes. Thus we
retain an "internal" interface which is identical to the
current gen_aa32_{ld,st}_i64 interface.
The "new" interface will gain users as we remove the legacy
interfaces, gen_aa32_ld64 and gen_aa32_st64.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 78 +++++++++++++++++++--------------
target/arm/translate-neon.c.inc | 6 ++-
2 files changed, 49 insertions(+), 35 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index d37a3dfa4a..6171347d6d 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -949,6 +949,37 @@ static void gen_aa32_st_internal_i32(DisasContext *s, TCGv_i32 val,
tcg_temp_free(addr);
}
+static void gen_aa32_ld_internal_i64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index, MemOp opc)
+{
+ TCGv addr = gen_aa32_addr(s, a32, opc);
+
+ tcg_gen_qemu_ld_i64(val, addr, index, opc);
+
+ /* Not needed for user-mode BE32, where we use MO_BE instead. */
+ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
+ tcg_gen_rotri_i64(val, val, 32);
+ }
+ tcg_temp_free(addr);
+}
+
+static void gen_aa32_st_internal_i64(DisasContext *s, TCGv_i64 val,
+ TCGv_i32 a32, int index, MemOp opc)
+{
+ TCGv addr = gen_aa32_addr(s, a32, opc);
+
+ /* Not needed for user-mode BE32, where we use MO_BE instead. */
+ if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ tcg_gen_rotri_i64(tmp, val, 32);
+ tcg_gen_qemu_st_i64(tmp, addr, index, opc);
+ tcg_temp_free_i64(tmp);
+ } else {
+ tcg_gen_qemu_st_i64(val, addr, index, opc);
+ }
+ tcg_temp_free(addr);
+}
+
static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
int index, MemOp opc)
{
@@ -961,6 +992,18 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
gen_aa32_st_internal_i32(s, val, a32, index, finalize_memop(s, opc));
}
+static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+ int index, MemOp opc)
+{
+ gen_aa32_ld_internal_i64(s, val, a32, index, finalize_memop(s, opc));
+}
+
+static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
+ int index, MemOp opc)
+{
+ gen_aa32_st_internal_i64(s, val, a32, index, finalize_memop(s, opc));
+}
+
#define DO_GEN_LD(SUFF, OPC) \
static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, \
TCGv_i32 a32, int index) \
@@ -975,47 +1018,16 @@ static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
gen_aa32_st_i32(s, val, a32, index, OPC); \
}
-static void gen_aa32_ld_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
- int index, MemOp opc)
-{
- TCGv addr = gen_aa32_addr(s, a32, opc);
- tcg_gen_qemu_ld_i64(val, addr, index, opc);
-
- /* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
- tcg_gen_rotri_i64(val, val, 32);
- }
-
- tcg_temp_free(addr);
-}
-
static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val,
TCGv_i32 a32, int index)
{
- gen_aa32_ld_i64(s, val, a32, index, MO_Q | s->be_data);
-}
-
-static void gen_aa32_st_i64(DisasContext *s, TCGv_i64 val, TCGv_i32 a32,
- int index, MemOp opc)
-{
- TCGv addr = gen_aa32_addr(s, a32, opc);
-
- /* Not needed for user-mode BE32, where we use MO_BE instead. */
- if (!IS_USER_ONLY && s->sctlr_b && (opc & MO_SIZE) == MO_64) {
- TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_rotri_i64(tmp, val, 32);
- tcg_gen_qemu_st_i64(tmp, addr, index, opc);
- tcg_temp_free_i64(tmp);
- } else {
- tcg_gen_qemu_st_i64(val, addr, index, opc);
- }
- tcg_temp_free(addr);
+ gen_aa32_ld_i64(s, val, a32, index, MO_Q);
}
static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val,
TCGv_i32 a32, int index)
{
- gen_aa32_st_i64(s, val, a32, index, MO_Q | s->be_data);
+ gen_aa32_st_i64(s, val, a32, index, MO_Q);
}
DO_GEN_LD(8u, MO_UB)
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index c82aa1412e..18d9042130 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -494,11 +494,13 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
int tt = a->vd + reg + spacing * xs;
if (a->l) {
- gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size);
+ gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx,
+ endian | size);
neon_store_element64(tt, n, size, tmp64);
} else {
neon_load_element64(tmp64, tt, n, size);
- gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size);
+ gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx,
+ endian | size);
}
tcg_gen_add_i32(addr, addr, tmp);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 15/31] target/arm: Enforce word alignment for LDRD/STRD
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (13 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 14/31] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 16/31] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
` (16 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Buglink: https://bugs.launchpad.net/qemu/+bug/1905356
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6171347d6d..1b0951c45b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6512,13 +6512,13 @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
addr = op_addr_rr_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt + 1, tmp);
/* LDRD w/ base writeback is undefined if the registers overlap. */
@@ -6541,13 +6541,13 @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
addr = op_addr_rr_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, a->rt + 1);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
op_addr_rr_post(s, a, addr, -4);
@@ -6649,13 +6649,13 @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
addr = op_addr_ri_pre(s, a);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, a->rt, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
store_reg(s, rt2, tmp);
/* LDRD w/ base writeback is undefined if the registers overlap. */
@@ -6688,13 +6688,13 @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
addr = op_addr_ri_pre(s, a);
tmp = load_reg(s, a->rt);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, rt2);
- gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
op_addr_ri_post(s, a, addr, -4);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 16/31] target/arm: Enforce alignment for LDA/LDAH/STL/STLH
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (14 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 15/31] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM Richard Henderson
` (15 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1b0951c45b..29fbbb84b2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -6920,7 +6920,7 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp mop)
addr = load_reg(s, a->rn);
tmp = load_reg(s, a->rt);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop);
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN);
disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel | ISSIsWrite);
tcg_temp_free_i32(tmp);
@@ -7076,7 +7076,7 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp mop)
addr = load_reg(s, a->rn);
tmp = tcg_temp_new_i32();
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop);
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | MO_ALIGN);
disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel);
tcg_temp_free_i32(addr);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (15 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 16/31] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-08-31 0:51 ` Nathan Chancellor
2021-04-19 20:22 ` [PATCH v5 18/31] target/arm: Enforce alignment for RFE Richard Henderson
` (14 subsequent siblings)
31 siblings, 1 reply; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 29fbbb84b2..f58ac4f018 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7868,7 +7868,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
} else {
tmp = load_reg(s, i);
}
- gen_aa32_st32(s, tmp, addr, mem_idx);
+ gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
/* No need to add after the last transfer. */
@@ -7943,7 +7943,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
}
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(s, tmp, addr, mem_idx);
+ gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
if (user) {
tmp2 = tcg_const_i32(i);
gen_helper_set_user_reg(cpu_env, tmp2, tmp);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 18/31] target/arm: Enforce alignment for RFE
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (16 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 19/31] target/arm: Enforce alignment for SRS Richard Henderson
` (13 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index f58ac4f018..2cdf58daa1 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8341,10 +8341,10 @@ static bool trans_RFE(DisasContext *s, arg_RFE *a)
/* Load PC into tmp and CPSR into tmp2. */
t1 = tcg_temp_new_i32();
- gen_aa32_ld32u(s, t1, addr, get_mem_index(s));
+ gen_aa32_ld_i32(s, t1, addr, get_mem_index(s), MO_UL | MO_ALIGN);
tcg_gen_addi_i32(addr, addr, 4);
t2 = tcg_temp_new_i32();
- gen_aa32_ld32u(s, t2, addr, get_mem_index(s));
+ gen_aa32_ld_i32(s, t2, addr, get_mem_index(s), MO_UL | MO_ALIGN);
if (a->w) {
/* Base writeback. */
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 19/31] target/arm: Enforce alignment for SRS
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (17 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 18/31] target/arm: Enforce alignment for RFE Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 20/31] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
` (12 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2cdf58daa1..4decb2610e 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5200,11 +5200,11 @@ static void gen_srs(DisasContext *s,
}
tcg_gen_addi_i32(addr, addr, offset);
tmp = load_reg(s, 14);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
tmp = load_cpu_field(spsr);
tcg_gen_addi_i32(addr, addr, 4);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN);
tcg_temp_free_i32(tmp);
if (writeback) {
switch (amode) {
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 20/31] target/arm: Enforce alignment for VLDM/VSTM
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (18 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 19/31] target/arm: Enforce alignment for SRS Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 21/31] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
` (11 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.c.inc | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index 10766f210c..f50afb23e7 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -1503,12 +1503,12 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
for (i = 0; i < n; i++) {
if (a->l) {
/* load */
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN);
vfp_store_reg32(tmp, a->vd + i);
} else {
/* store */
vfp_load_reg32(tmp, a->vd + i);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN);
}
tcg_gen_addi_i32(addr, addr, offset);
}
@@ -1586,12 +1586,12 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
for (i = 0; i < n; i++) {
if (a->l) {
/* load */
- gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4);
vfp_store_reg64(tmp, a->vd + i);
} else {
/* store */
vfp_load_reg64(tmp, a->vd + i);
- gen_aa32_st64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4);
}
tcg_gen_addi_i32(addr, addr, offset);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 21/31] target/arm: Enforce alignment for VLDR/VSTR
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (19 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 20/31] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 22/31] target/arm: Enforce alignment for VLDn (all lanes) Richard Henderson
` (10 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-vfp.c.inc | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
index f50afb23e7..e20d9c7ba6 100644
--- a/target/arm/translate-vfp.c.inc
+++ b/target/arm/translate-vfp.c.inc
@@ -1364,11 +1364,11 @@ static bool trans_VLDR_VSTR_hp(DisasContext *s, arg_VLDR_VSTR_sp *a)
addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i32();
if (a->l) {
- gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UW | MO_ALIGN);
vfp_store_reg32(tmp, a->vd);
} else {
vfp_load_reg32(tmp, a->vd);
- gen_aa32_st16(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UW | MO_ALIGN);
}
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(addr);
@@ -1398,11 +1398,11 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i32();
if (a->l) {
- gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN);
vfp_store_reg32(tmp, a->vd);
} else {
vfp_load_reg32(tmp, a->vd);
- gen_aa32_st32(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), MO_UL | MO_ALIGN);
}
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(addr);
@@ -1439,11 +1439,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
addr = add_reg_for_lit(s, a->rn, offset);
tmp = tcg_temp_new_i64();
if (a->l) {
- gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_ld_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4);
vfp_store_reg64(tmp, a->vd);
} else {
vfp_load_reg64(tmp, a->vd);
- gen_aa32_st64(s, tmp, addr, get_mem_index(s));
+ gen_aa32_st_i64(s, tmp, addr, get_mem_index(s), MO_Q | MO_ALIGN_4);
}
tcg_temp_free_i64(tmp);
tcg_temp_free_i32(addr);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 22/31] target/arm: Enforce alignment for VLDn (all lanes)
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (20 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 21/31] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 23/31] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
` (9 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Fix alignment for n in {2, 4}.
---
target/arm/translate.h | 1 +
target/arm/translate.c | 15 +++++++++++++
target/arm/translate-neon.c.inc | 37 +++++++++++++++++++++++++--------
3 files changed, 44 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 0c60b83b3d..ccf60c96d8 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -204,6 +204,7 @@ void arm_test_cc(DisasCompare *cmp, int cc);
void arm_free_cc(DisasCompare *cmp);
void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
void arm_gen_test_cc(int cc, TCGLabel *label);
+MemOp pow2_align(unsigned i);
/* Return state of Alternate Half-precision flag, caller frees result */
static inline TCGv_i32 get_ahp_flag(void)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4decb2610e..0cf6da7e79 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -908,6 +908,21 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var)
#define IS_USER_ONLY 0
#endif
+MemOp pow2_align(unsigned i)
+{
+ static const MemOp mop_align[] = {
+ 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16,
+ /*
+ * FIXME: TARGET_PAGE_BITS_MIN affects TLB_FLAGS_MASK such
+ * that 256-bit alignment (MO_ALIGN_32) cannot be supported:
+ * see get_alignment_bits(). Enforce only 128-bit alignment for now.
+ */
+ MO_ALIGN_16
+ };
+ g_assert(i < ARRAY_SIZE(mop_align));
+ return mop_align[i];
+}
+
/*
* Abstractions of "generate code to do a guest load/store for
* AArch32", where a vaddr is always 32 bits (and is zero
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index 18d9042130..9c2b076027 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -522,6 +522,7 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
int size = a->size;
int nregs = a->n + 1;
TCGv_i32 addr, tmp;
+ MemOp mop, align;
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
@@ -532,18 +533,33 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
return false;
}
+ align = 0;
if (size == 3) {
if (nregs != 4 || a->a == 0) {
return false;
}
/* For VLD4 size == 3 a == 1 means 32 bits at 16 byte alignment */
- size = 2;
- }
- if (nregs == 1 && a->a == 1 && size == 0) {
- return false;
- }
- if (nregs == 3 && a->a == 1) {
- return false;
+ size = MO_32;
+ align = MO_ALIGN_16;
+ } else if (a->a) {
+ switch (nregs) {
+ case 1:
+ if (size == 0) {
+ return false;
+ }
+ align = MO_ALIGN;
+ break;
+ case 2:
+ align = pow2_align(size + 1);
+ break;
+ case 3:
+ return false;
+ case 4:
+ align = pow2_align(size + 2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
}
if (!vfp_access_check(s)) {
@@ -556,12 +572,12 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
*/
stride = a->t ? 2 : 1;
vec_size = nregs == 1 ? stride * 8 : 8;
-
+ mop = size | align;
tmp = tcg_temp_new_i32();
addr = tcg_temp_new_i32();
load_reg_var(s, addr, a->rn);
for (reg = 0; reg < nregs; reg++) {
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), size);
+ gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop);
if ((vd & 1) && vec_size == 16) {
/*
* We cannot write 16 bytes at once because the
@@ -577,6 +593,9 @@ static bool trans_VLD_all_lanes(DisasContext *s, arg_VLD_all_lanes *a)
}
tcg_gen_addi_i32(addr, addr, 1 << size);
vd += stride;
+
+ /* Subsequent memory operations inherit alignment */
+ mop &= ~MO_AMASK;
}
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(addr);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 23/31] target/arm: Enforce alignment for VLDn/VSTn (multiple)
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (21 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 22/31] target/arm: Enforce alignment for VLDn (all lanes) Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 24/31] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
` (8 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-neon.c.inc | 27 ++++++++++++++++++++++-----
1 file changed, 22 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index 9c2b076027..e706c37c80 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -429,7 +429,7 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
{
/* Neon load/store multiple structures */
int nregs, interleave, spacing, reg, n;
- MemOp endian = s->be_data;
+ MemOp mop, align, endian;
int mmu_idx = get_mem_index(s);
int size = a->size;
TCGv_i64 tmp64;
@@ -473,20 +473,36 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
}
/* For our purposes, bytes are always little-endian. */
+ endian = s->be_data;
if (size == 0) {
endian = MO_LE;
}
+
+ /* Enforce alignment requested by the instruction */
+ if (a->align) {
+ align = pow2_align(a->align + 2); /* 4 ** a->align */
+ } else {
+ align = s->align_mem ? MO_ALIGN : 0;
+ }
+
/*
* Consecutive little-endian elements from a single register
* can be promoted to a larger little-endian operation.
*/
if (interleave == 1 && endian == MO_LE) {
+ /* Retain any natural alignment. */
+ if (align == MO_ALIGN) {
+ align = pow2_align(size);
+ }
size = 3;
}
+
tmp64 = tcg_temp_new_i64();
addr = tcg_temp_new_i32();
tmp = tcg_const_i32(1 << size);
load_reg_var(s, addr, a->rn);
+
+ mop = endian | size | align;
for (reg = 0; reg < nregs; reg++) {
for (n = 0; n < 8 >> size; n++) {
int xs;
@@ -494,15 +510,16 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
int tt = a->vd + reg + spacing * xs;
if (a->l) {
- gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx,
- endian | size);
+ gen_aa32_ld_internal_i64(s, tmp64, addr, mmu_idx, mop);
neon_store_element64(tt, n, size, tmp64);
} else {
neon_load_element64(tmp64, tt, n, size);
- gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx,
- endian | size);
+ gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, mop);
}
tcg_gen_add_i32(addr, addr, tmp);
+
+ /* Subsequent memory operations inherit alignment */
+ mop &= ~MO_AMASK;
}
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 24/31] target/arm: Enforce alignment for VLDn/VSTn (single)
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (22 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 23/31] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 25/31] target/arm: Use finalize_memop for aa64 gpr load/store Richard Henderson
` (7 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-neon.c.inc | 48 ++++++++++++++++++++++++++++-----
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc
index e706c37c80..a02b8369a1 100644
--- a/target/arm/translate-neon.c.inc
+++ b/target/arm/translate-neon.c.inc
@@ -629,6 +629,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
int nregs = a->n + 1;
int vd = a->vd;
TCGv_i32 addr, tmp;
+ MemOp mop;
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return false;
@@ -678,23 +679,58 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLDST_single *a)
return true;
}
+ /* Pick up SCTLR settings */
+ mop = finalize_memop(s, a->size);
+
+ if (a->align) {
+ MemOp align_op;
+
+ switch (nregs) {
+ case 1:
+ /* For VLD1, use natural alignment. */
+ align_op = MO_ALIGN;
+ break;
+ case 2:
+ /* For VLD2, use double alignment. */
+ align_op = pow2_align(a->size + 1);
+ break;
+ case 4:
+ if (a->size == MO_32) {
+ /*
+ * For VLD4.32, align = 1 is double alignment, align = 2 is
+ * quad alignment; align = 3 is rejected above.
+ */
+ align_op = pow2_align(a->size + a->align);
+ } else {
+ /* For VLD4.8 and VLD.16, we want quad alignment. */
+ align_op = pow2_align(a->size + 2);
+ }
+ break;
+ default:
+ /* For VLD3, the alignment field is zero and rejected above. */
+ g_assert_not_reached();
+ }
+
+ mop = (mop & ~MO_AMASK) | align_op;
+ }
+
tmp = tcg_temp_new_i32();
addr = tcg_temp_new_i32();
load_reg_var(s, addr, a->rn);
- /*
- * TODO: if we implemented alignment exceptions, we should check
- * addr against the alignment encoded in a->align here.
- */
+
for (reg = 0; reg < nregs; reg++) {
if (a->l) {
- gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), a->size);
+ gen_aa32_ld_internal_i32(s, tmp, addr, get_mem_index(s), mop);
neon_store_element(vd, a->reg_idx, a->size, tmp);
} else { /* Store */
neon_load_element(tmp, vd, a->reg_idx, a->size);
- gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), a->size);
+ gen_aa32_st_internal_i32(s, tmp, addr, get_mem_index(s), mop);
}
vd += a->stride;
tcg_gen_addi_i32(addr, addr, 1 << a->size);
+
+ /* Subsequent memory operations inherit alignment */
+ mop &= ~MO_AMASK;
}
tcg_temp_free_i32(addr);
tcg_temp_free_i32(tmp);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 25/31] target/arm: Use finalize_memop for aa64 gpr load/store
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (23 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 24/31] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 26/31] target/arm: Use finalize_memop for aa64 fpr load/store Richard Henderson
` (6 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
In the case of gpr load, merge the size and is_signed arguments;
otherwise, simply convert size to memop.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 78 ++++++++++++++++----------------------
1 file changed, 33 insertions(+), 45 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 92a62b1a75..f2995d2b74 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -886,19 +886,19 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
* Store from GPR register to memory.
*/
static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source,
- TCGv_i64 tcg_addr, int size, int memidx,
+ TCGv_i64 tcg_addr, MemOp memop, int memidx,
bool iss_valid,
unsigned int iss_srt,
bool iss_sf, bool iss_ar)
{
- g_assert(size <= 3);
- tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size);
+ memop = finalize_memop(s, memop);
+ tcg_gen_qemu_st_i64(source, tcg_addr, memidx, memop);
if (iss_valid) {
uint32_t syn;
syn = syn_data_abort_with_iss(0,
- size,
+ (memop & MO_SIZE),
false,
iss_srt,
iss_sf,
@@ -909,37 +909,28 @@ static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source,
}
static void do_gpr_st(DisasContext *s, TCGv_i64 source,
- TCGv_i64 tcg_addr, int size,
+ TCGv_i64 tcg_addr, MemOp memop,
bool iss_valid,
unsigned int iss_srt,
bool iss_sf, bool iss_ar)
{
- do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s),
+ do_gpr_st_memidx(s, source, tcg_addr, memop, get_mem_index(s),
iss_valid, iss_srt, iss_sf, iss_ar);
}
/*
* Load from memory to GPR register
*/
-static void do_gpr_ld_memidx(DisasContext *s,
- TCGv_i64 dest, TCGv_i64 tcg_addr,
- int size, bool is_signed,
- bool extend, int memidx,
+static void do_gpr_ld_memidx(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
+ MemOp memop, bool extend, int memidx,
bool iss_valid, unsigned int iss_srt,
bool iss_sf, bool iss_ar)
{
- MemOp memop = s->be_data + size;
-
- g_assert(size <= 3);
-
- if (is_signed) {
- memop += MO_SIGN;
- }
-
+ memop = finalize_memop(s, memop);
tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop);
- if (extend && is_signed) {
- g_assert(size < 3);
+ if (extend && (memop & MO_SIGN)) {
+ g_assert((memop & MO_SIZE) <= MO_32);
tcg_gen_ext32u_i64(dest, dest);
}
@@ -947,8 +938,8 @@ static void do_gpr_ld_memidx(DisasContext *s,
uint32_t syn;
syn = syn_data_abort_with_iss(0,
- size,
- is_signed,
+ (memop & MO_SIZE),
+ (memop & MO_SIGN) != 0,
iss_srt,
iss_sf,
iss_ar,
@@ -957,14 +948,12 @@ static void do_gpr_ld_memidx(DisasContext *s,
}
}
-static void do_gpr_ld(DisasContext *s,
- TCGv_i64 dest, TCGv_i64 tcg_addr,
- int size, bool is_signed, bool extend,
+static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
+ MemOp memop, bool extend,
bool iss_valid, unsigned int iss_srt,
bool iss_sf, bool iss_ar)
{
- do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend,
- get_mem_index(s),
+ do_gpr_ld_memidx(s, dest, tcg_addr, memop, extend, get_mem_index(s),
iss_valid, iss_srt, iss_sf, iss_ar);
}
@@ -2717,7 +2706,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
}
clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
false, rn != 31, size);
- do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true, rt,
+ do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt,
disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
return;
@@ -2830,8 +2819,8 @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
/* Only unsigned 32bit loads target 32bit registers. */
bool iss_sf = opc != 0;
- do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, false,
- true, rt, iss_sf, false);
+ do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
+ false, true, rt, iss_sf, false);
}
tcg_temp_free_i64(clean_addr);
}
@@ -2989,11 +2978,11 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
/* Do not modify tcg_rt before recognizing any exception
* from the second load.
*/
- do_gpr_ld(s, tmp, clean_addr, size, is_signed, false,
- false, 0, false, false);
+ do_gpr_ld(s, tmp, clean_addr, size + is_signed * MO_SIGN,
+ false, false, 0, false, false);
tcg_gen_addi_i64(clean_addr, clean_addr, 1 << size);
- do_gpr_ld(s, tcg_rt2, clean_addr, size, is_signed, false,
- false, 0, false, false);
+ do_gpr_ld(s, tcg_rt2, clean_addr, size + is_signed * MO_SIGN,
+ false, false, 0, false, false);
tcg_gen_mov_i64(tcg_rt, tmp);
tcg_temp_free_i64(tmp);
@@ -3124,8 +3113,8 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
do_gpr_st_memidx(s, tcg_rt, clean_addr, size, memidx,
iss_valid, rt, iss_sf, false);
} else {
- do_gpr_ld_memidx(s, tcg_rt, clean_addr, size,
- is_signed, is_extended, memidx,
+ do_gpr_ld_memidx(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
+ is_extended, memidx,
iss_valid, rt, iss_sf, false);
}
}
@@ -3229,9 +3218,8 @@ static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
do_gpr_st(s, tcg_rt, clean_addr, size,
true, rt, iss_sf, false);
} else {
- do_gpr_ld(s, tcg_rt, clean_addr, size,
- is_signed, is_extended,
- true, rt, iss_sf, false);
+ do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
+ is_extended, true, rt, iss_sf, false);
}
}
}
@@ -3314,8 +3302,8 @@ static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
do_gpr_st(s, tcg_rt, clean_addr, size,
true, rt, iss_sf, false);
} else {
- do_gpr_ld(s, tcg_rt, clean_addr, size, is_signed, is_extended,
- true, rt, iss_sf, false);
+ do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN,
+ is_extended, true, rt, iss_sf, false);
}
}
}
@@ -3402,7 +3390,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
* full load-acquire (we only need "load-acquire processor consistent"),
* but we choose to implement them as full LDAQ.
*/
- do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false,
+ do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false,
true, rt, disas_ldst_compute_iss_sf(size, false, 0), true);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
return;
@@ -3475,7 +3463,7 @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn,
is_wback || rn != 31, size);
tcg_rt = cpu_reg(s, rt);
- do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false,
+ do_gpr_ld(s, tcg_rt, clean_addr, size,
/* extend */ false, /* iss_valid */ !is_wback,
/* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false);
@@ -3560,8 +3548,8 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
* Load-AcquirePC semantics; we implement as the slightly more
* restrictive Load-Acquire.
*/
- do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend,
- true, rt, iss_sf, true);
+ do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size + is_signed * MO_SIGN,
+ extend, true, rt, iss_sf, true);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 26/31] target/arm: Use finalize_memop for aa64 fpr load/store
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (24 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 25/31] target/arm: Use finalize_memop for aa64 gpr load/store Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 27/31] target/arm: Enforce alignment for aa64 load-acq/store-rel Richard Henderson
` (5 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
For 128-bit load/store, use 16-byte alignment. This
requires that we perform the two operations in the
correct order so that we generate the alignment fault
before modifying memory.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 42 +++++++++++++++++++++++---------------
1 file changed, 26 insertions(+), 16 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index f2995d2b74..b90d6880e7 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -963,25 +963,33 @@ static void do_gpr_ld(DisasContext *s, TCGv_i64 dest, TCGv_i64 tcg_addr,
static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size)
{
/* This writes the bottom N bits of a 128 bit wide vector to memory */
- TCGv_i64 tmp = tcg_temp_new_i64();
- tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64));
+ TCGv_i64 tmplo = tcg_temp_new_i64();
+ MemOp mop;
+
+ tcg_gen_ld_i64(tmplo, cpu_env, fp_reg_offset(s, srcidx, MO_64));
+
if (size < 4) {
- tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s),
- s->be_data + size);
+ mop = finalize_memop(s, size);
+ tcg_gen_qemu_st_i64(tmplo, tcg_addr, get_mem_index(s), mop);
} else {
bool be = s->be_data == MO_BE;
TCGv_i64 tcg_hiaddr = tcg_temp_new_i64();
+ TCGv_i64 tmphi = tcg_temp_new_i64();
+ tcg_gen_ld_i64(tmphi, cpu_env, fp_reg_hi_offset(s, srcidx));
+
+ mop = s->be_data | MO_Q;
+ tcg_gen_qemu_st_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s),
+ mop | (s->align_mem ? MO_ALIGN_16 : 0));
tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
- tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
- s->be_data | MO_Q);
- tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx));
- tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
- s->be_data | MO_Q);
+ tcg_gen_qemu_st_i64(be ? tmplo : tmphi, tcg_hiaddr,
+ get_mem_index(s), mop);
+
tcg_temp_free_i64(tcg_hiaddr);
+ tcg_temp_free_i64(tmphi);
}
- tcg_temp_free_i64(tmp);
+ tcg_temp_free_i64(tmplo);
}
/*
@@ -992,10 +1000,11 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
/* This always zero-extends and writes to a full 128 bit wide vector */
TCGv_i64 tmplo = tcg_temp_new_i64();
TCGv_i64 tmphi = NULL;
+ MemOp mop;
if (size < 4) {
- MemOp memop = s->be_data + size;
- tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop);
+ mop = finalize_memop(s, size);
+ tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), mop);
} else {
bool be = s->be_data == MO_BE;
TCGv_i64 tcg_hiaddr;
@@ -1003,11 +1012,12 @@ static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size)
tmphi = tcg_temp_new_i64();
tcg_hiaddr = tcg_temp_new_i64();
+ mop = s->be_data | MO_Q;
+ tcg_gen_qemu_ld_i64(be ? tmphi : tmplo, tcg_addr, get_mem_index(s),
+ mop | (s->align_mem ? MO_ALIGN_16 : 0));
tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8);
- tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s),
- s->be_data | MO_Q);
- tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s),
- s->be_data | MO_Q);
+ tcg_gen_qemu_ld_i64(be ? tmplo : tmphi, tcg_hiaddr,
+ get_mem_index(s), mop);
tcg_temp_free_i64(tcg_hiaddr);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 27/31] target/arm: Enforce alignment for aa64 load-acq/store-rel
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (25 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 26/31] target/arm: Use finalize_memop for aa64 fpr load/store Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 28/31] target/arm: Use MemOp for size + endian in aa64 vector ld/st Richard Henderson
` (4 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b90d6880e7..ac60dcf760 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -2699,7 +2699,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
true, rn != 31, size);
- do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt,
+ /* TODO: ARMv8.4-LSE SCTLR.nAA */
+ do_gpr_st(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, true, rt,
disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
return;
@@ -2716,8 +2717,9 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
}
clean_addr = gen_mte_check1(s, cpu_reg_sp(s, rn),
false, rn != 31, size);
- do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, true, rt,
- disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
+ /* TODO: ARMv8.4-LSE SCTLR.nAA */
+ do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size | MO_ALIGN, false, true,
+ rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
return;
@@ -3505,15 +3507,18 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
int size = extract32(insn, 30, 2);
TCGv_i64 clean_addr, dirty_addr;
bool is_store = false;
- bool is_signed = false;
bool extend = false;
bool iss_sf;
+ MemOp mop;
if (!dc_isar_feature(aa64_rcpc_8_4, s)) {
unallocated_encoding(s);
return;
}
+ /* TODO: ARMv8.4-LSE SCTLR.nAA */
+ mop = size | MO_ALIGN;
+
switch (opc) {
case 0: /* STLURB */
is_store = true;
@@ -3525,21 +3530,21 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
unallocated_encoding(s);
return;
}
- is_signed = true;
+ mop |= MO_SIGN;
break;
case 3: /* LDAPURS* 32-bit variant */
if (size > 1) {
unallocated_encoding(s);
return;
}
- is_signed = true;
+ mop |= MO_SIGN;
extend = true; /* zero-extend 32->64 after signed load */
break;
default:
g_assert_not_reached();
}
- iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc);
+ iss_sf = disas_ldst_compute_iss_sf(size, (mop & MO_SIGN) != 0, opc);
if (rn == 31) {
gen_check_sp_alignment(s);
@@ -3552,13 +3557,13 @@ static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn)
if (is_store) {
/* Store-Release semantics */
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
- do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, true);
+ do_gpr_st(s, cpu_reg(s, rt), clean_addr, mop, true, rt, iss_sf, true);
} else {
/*
* Load-AcquirePC semantics; we implement as the slightly more
* restrictive Load-Acquire.
*/
- do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size + is_signed * MO_SIGN,
+ do_gpr_ld(s, cpu_reg(s, rt), clean_addr, mop,
extend, true, rt, iss_sf, true);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 28/31] target/arm: Use MemOp for size + endian in aa64 vector ld/st
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (26 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 27/31] target/arm: Enforce alignment for aa64 load-acq/store-rel Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 29/31] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Richard Henderson
` (3 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index ac60dcf760..d3bda16ecd 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1146,24 +1146,24 @@ static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src,
/* Store from vector register to memory */
static void do_vec_st(DisasContext *s, int srcidx, int element,
- TCGv_i64 tcg_addr, int size, MemOp endian)
+ TCGv_i64 tcg_addr, MemOp mop)
{
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
- read_vec_element(s, tcg_tmp, srcidx, element, size);
- tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size);
+ read_vec_element(s, tcg_tmp, srcidx, element, mop & MO_SIZE);
+ tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), mop);
tcg_temp_free_i64(tcg_tmp);
}
/* Load from memory to vector register */
static void do_vec_ld(DisasContext *s, int destidx, int element,
- TCGv_i64 tcg_addr, int size, MemOp endian)
+ TCGv_i64 tcg_addr, MemOp mop)
{
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), endian | size);
- write_vec_element(s, tcg_tmp, destidx, element, size);
+ tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), mop);
+ write_vec_element(s, tcg_tmp, destidx, element, mop & MO_SIZE);
tcg_temp_free_i64(tcg_tmp);
}
@@ -3734,9 +3734,9 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
for (xs = 0; xs < selem; xs++) {
int tt = (rt + r + xs) % 32;
if (is_store) {
- do_vec_st(s, tt, e, clean_addr, size, endian);
+ do_vec_st(s, tt, e, clean_addr, size | endian);
} else {
- do_vec_ld(s, tt, e, clean_addr, size, endian);
+ do_vec_ld(s, tt, e, clean_addr, size | endian);
}
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
}
@@ -3885,9 +3885,9 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
} else {
/* Load/store one element per register */
if (is_load) {
- do_vec_ld(s, rt, index, clean_addr, scale, s->be_data);
+ do_vec_ld(s, rt, index, clean_addr, scale | s->be_data);
} else {
- do_vec_st(s, rt, index, clean_addr, scale, s->be_data);
+ do_vec_st(s, rt, index, clean_addr, scale | s->be_data);
}
}
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 29/31] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple)
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (27 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 28/31] target/arm: Use MemOp for size + endian in aa64 vector ld/st Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 30/31] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Richard Henderson
` (2 subsequent siblings)
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index d3bda16ecd..2a82dbbd6d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3635,7 +3635,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
bool is_postidx = extract32(insn, 23, 1);
bool is_q = extract32(insn, 30, 1);
TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
- MemOp endian = s->be_data;
+ MemOp endian, align, mop;
int total; /* total bytes */
int elements; /* elements per vector */
@@ -3703,6 +3703,7 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
}
/* For our purposes, bytes are always little-endian. */
+ endian = s->be_data;
if (size == 0) {
endian = MO_LE;
}
@@ -3721,11 +3722,17 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
* Consecutive little-endian elements from a single register
* can be promoted to a larger little-endian operation.
*/
+ align = MO_ALIGN;
if (selem == 1 && endian == MO_LE) {
+ align = pow2_align(size);
size = 3;
}
- elements = (is_q ? 16 : 8) >> size;
+ if (!s->align_mem) {
+ align = 0;
+ }
+ mop = endian | size | align;
+ elements = (is_q ? 16 : 8) >> size;
tcg_ebytes = tcg_const_i64(1 << size);
for (r = 0; r < rpt; r++) {
int e;
@@ -3734,9 +3741,9 @@ static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn)
for (xs = 0; xs < selem; xs++) {
int tt = (rt + r + xs) % 32;
if (is_store) {
- do_vec_st(s, tt, e, clean_addr, size | endian);
+ do_vec_st(s, tt, e, clean_addr, mop);
} else {
- do_vec_ld(s, tt, e, clean_addr, size | endian);
+ do_vec_ld(s, tt, e, clean_addr, mop);
}
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 30/31] target/arm: Enforce alignment for aa64 vector LDn/STn (single)
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (28 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 29/31] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-19 20:22 ` [PATCH v5 31/31] target/arm: Enforce alignment for sve LD1R Richard Henderson
2021-04-20 10:27 ` [PATCH v5 00/31] target/arm: enforce alignment Peter Maydell
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-a64.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2a82dbbd6d..95897e63af 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -3815,6 +3815,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
int index = is_q << 3 | S << 2 | size;
int xs, total;
TCGv_i64 clean_addr, tcg_rn, tcg_ebytes;
+ MemOp mop;
if (extract32(insn, 31, 1)) {
unallocated_encoding(s);
@@ -3876,6 +3877,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
clean_addr = gen_mte_checkN(s, tcg_rn, !is_load, is_postidx || rn != 31,
total);
+ mop = finalize_memop(s, scale);
tcg_ebytes = tcg_const_i64(1 << scale);
for (xs = 0; xs < selem; xs++) {
@@ -3883,8 +3885,7 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
/* Load and replicate to all elements */
TCGv_i64 tcg_tmp = tcg_temp_new_i64();
- tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr,
- get_mem_index(s), s->be_data + scale);
+ tcg_gen_qemu_ld_i64(tcg_tmp, clean_addr, get_mem_index(s), mop);
tcg_gen_gvec_dup_i64(scale, vec_full_reg_offset(s, rt),
(is_q + 1) * 8, vec_full_reg_size(s),
tcg_tmp);
@@ -3892,9 +3893,9 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
} else {
/* Load/store one element per register */
if (is_load) {
- do_vec_ld(s, rt, index, clean_addr, scale | s->be_data);
+ do_vec_ld(s, rt, index, clean_addr, mop);
} else {
- do_vec_st(s, rt, index, clean_addr, scale | s->be_data);
+ do_vec_st(s, rt, index, clean_addr, mop);
}
}
tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes);
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* [PATCH v5 31/31] target/arm: Enforce alignment for sve LD1R
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (29 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 30/31] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Richard Henderson
@ 2021-04-19 20:22 ` Richard Henderson
2021-04-20 10:27 ` [PATCH v5 00/31] target/arm: enforce alignment Peter Maydell
31 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-04-19 20:22 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, qemu-arm
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/translate-sve.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 584c4d047c..864ed669c4 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -5001,7 +5001,7 @@ static bool trans_LD1R_zpri(DisasContext *s, arg_rpri_load *a)
clean_addr = gen_mte_check1(s, temp, false, true, msz);
tcg_gen_qemu_ld_i64(temp, clean_addr, get_mem_index(s),
- s->be_data | dtype_mop[a->dtype]);
+ finalize_memop(s, dtype_mop[a->dtype]));
/* Broadcast to *all* elements. */
tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd),
--
2.25.1
^ permalink raw reply related [flat|nested] 40+ messages in thread
* Re: [PATCH v5 07/31] target/arm: Use cpu_abort in assert_hflags_rebuild_correctly
2021-04-19 20:22 ` [PATCH v5 07/31] target/arm: Use cpu_abort in assert_hflags_rebuild_correctly Richard Henderson
@ 2021-04-20 9:07 ` Peter Maydell
0 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2021-04-20 9:07 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, QEMU Developers
On Mon, 19 Apr 2021 at 21:36, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Using cpu_abort takes care of things like unregistering a
> SIGABRT handler for user-only.
I would find this argument more persuasive if we didn't have a
ton of other places where we call abort() or assert() or
g_assert_not_reached(). Either we should have a consistent
mechanism for assertions in linux-user turning off the SIGABRT
handler, or we should just not worry about it on the basis that it's
a "can't happen" error anyway...
thanks
-- PMM
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 00/31] target/arm: enforce alignment
2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
` (30 preceding siblings ...)
2021-04-19 20:22 ` [PATCH v5 31/31] target/arm: Enforce alignment for sve LD1R Richard Henderson
@ 2021-04-20 10:27 ` Peter Maydell
31 siblings, 0 replies; 40+ messages in thread
From: Peter Maydell @ 2021-04-20 10:27 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-arm, QEMU Developers
On Mon, 19 Apr 2021 at 21:24, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Based-on: 20210416183106.1516563-1-richard.henderson@linaro.org
> ("[PATCH v5 for-6.1 0/9] target/arm mte fixes")
>
> Changes for v5:
> * Address review issues.
> * Use cpu_abort in assert_hflags_rebuild_correctly
>
> The only patch lacking review is the new one:
> 07-target-arm-Use-cpu_abort-in-assert_hflags_rebuild.patch
I've applied all except for patch 7 to target-arm.next for 6.1.
thanks
-- PMM
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM
2021-04-19 20:22 ` [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM Richard Henderson
@ 2021-08-31 0:51 ` Nathan Chancellor
0 siblings, 0 replies; 40+ messages in thread
From: Nathan Chancellor @ 2021-08-31 0:51 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, Peter Maydell, qemu-arm, llvm
Hi Richard,
On Mon, Apr 19, 2021 at 01:22:43PM -0700, Richard Henderson wrote:
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 29fbbb84b2..f58ac4f018 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -7868,7 +7868,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
> } else {
> tmp = load_reg(s, i);
> }
> - gen_aa32_st32(s, tmp, addr, mem_idx);
> + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
> tcg_temp_free_i32(tmp);
>
> /* No need to add after the last transfer. */
> @@ -7943,7 +7943,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
> }
>
> tmp = tcg_temp_new_i32();
> - gen_aa32_ld32u(s, tmp, addr, mem_idx);
> + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
> if (user) {
> tmp2 = tcg_const_i32(i);
> gen_helper_set_user_reg(cpu_env, tmp2, tmp);
> --
> 2.25.1
I just bisected a boot hang with an LLVM-built multi_v7_defconfig +
CONFIG_THUMB2_KERNEL=y kernel down to this commit. I do not see the same
hang when the kernel is compiled with GCC 11.2.0 and binutils 2.37 nor
do I see a hang with multi_v7_defconfig by itself. Is there something
that LLVM is doing wrong when compiling/assembling/linking the kernel or
is there something wrong/too aggressive with this commit? I can
reproduce this with current QEMU HEAD (ad22d05833).
My QEMU invocation is:
$ qemu-system-arm \
-append "console=ttyAMA0 earlycon" \
-display none \
-initrd rootfs.cpio \
-kernel zImage \
-M virt \
-m 512m \
-nodefaults \
-no-reboot \
-serial mon:stdio
and the rootfs.cpio and zImage files can be found here:
https://github.com/nathanchance/bug-files/tree/15c1fd6e44622a3c27823d2c5c3083dfc7246146/qemu-2e1f39e29bf9a6b28eaee9fc0949aab50dbad94a
Cheers,
Nathan
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM
@ 2021-08-31 0:51 ` Nathan Chancellor
0 siblings, 0 replies; 40+ messages in thread
From: Nathan Chancellor @ 2021-08-31 0:51 UTC (permalink / raw)
To: Richard Henderson; +Cc: Peter Maydell, qemu-arm, llvm, qemu-devel
Hi Richard,
On Mon, Apr 19, 2021 at 01:22:43PM -0700, Richard Henderson wrote:
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
> target/arm/translate.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 29fbbb84b2..f58ac4f018 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -7868,7 +7868,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
> } else {
> tmp = load_reg(s, i);
> }
> - gen_aa32_st32(s, tmp, addr, mem_idx);
> + gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
> tcg_temp_free_i32(tmp);
>
> /* No need to add after the last transfer. */
> @@ -7943,7 +7943,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
> }
>
> tmp = tcg_temp_new_i32();
> - gen_aa32_ld32u(s, tmp, addr, mem_idx);
> + gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
> if (user) {
> tmp2 = tcg_const_i32(i);
> gen_helper_set_user_reg(cpu_env, tmp2, tmp);
> --
> 2.25.1
I just bisected a boot hang with an LLVM-built multi_v7_defconfig +
CONFIG_THUMB2_KERNEL=y kernel down to this commit. I do not see the same
hang when the kernel is compiled with GCC 11.2.0 and binutils 2.37 nor
do I see a hang with multi_v7_defconfig by itself. Is there something
that LLVM is doing wrong when compiling/assembling/linking the kernel or
is there something wrong/too aggressive with this commit? I can
reproduce this with current QEMU HEAD (ad22d05833).
My QEMU invocation is:
$ qemu-system-arm \
-append "console=ttyAMA0 earlycon" \
-display none \
-initrd rootfs.cpio \
-kernel zImage \
-M virt \
-m 512m \
-nodefaults \
-no-reboot \
-serial mon:stdio
and the rootfs.cpio and zImage files can be found here:
https://github.com/nathanchance/bug-files/tree/15c1fd6e44622a3c27823d2c5c3083dfc7246146/qemu-2e1f39e29bf9a6b28eaee9fc0949aab50dbad94a
Cheers,
Nathan
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM
2021-08-31 0:51 ` Nathan Chancellor
@ 2021-09-07 13:44 ` Richard Henderson
-1 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-09-07 13:44 UTC (permalink / raw)
To: Nathan Chancellor; +Cc: qemu-devel, Peter Maydell, qemu-arm, llvm
On 8/31/21 2:51 AM, Nathan Chancellor wrote:
> I just bisected a boot hang with an LLVM-built multi_v7_defconfig +
> CONFIG_THUMB2_KERNEL=y kernel down to this commit. I do not see the same
> hang when the kernel is compiled with GCC 11.2.0 and binutils 2.37 nor
> do I see a hang with multi_v7_defconfig by itself. Is there something
> that LLVM is doing wrong when compiling/assembling/linking the kernel or
> is there something wrong/too aggressive with this commit? I can
> reproduce this with current QEMU HEAD (ad22d05833).
>
> My QEMU invocation is:
>
> $ qemu-system-arm \
> -append "console=ttyAMA0 earlycon" \
> -display none \
> -initrd rootfs.cpio \
> -kernel zImage \
> -M virt \
> -m 512m \
> -nodefaults \
> -no-reboot \
> -serial mon:stdio
>
> and the rootfs.cpio and zImage files can be found here:
>
> https://github.com/nathanchance/bug-files/tree/15c1fd6e44622a3c27823d2c5c3083dfc7246146/qemu-2e1f39e29bf9a6b28eaee9fc0949aab50dbad94a
Hmm. I see
IN:
0xc13038e2: e890 008c ldm.w r0, {r2, r3, r7}
R00=c13077ca R01=c11a8058 R02=c11a8058 R03=c031737f
R04=48379000 R05=00000024 R06=c031748d R07=c03174bb
R08=412fc0f1 R09=c0ce9308 R10=50c5387d R11=00000000
R12=00000009 R13=c1501f88 R14=c0301739 R15=c13038e2
PSR=200001f3 --C- T svc32
Taking exception 4 [Data Abort]
...from EL1 to EL1
...with ESR 0x25/0x9600003f
...with DFSR 0x1 DFAR 0xc13077ca
So, yes, it's a ldm from an address % 4 = 2, so it is correct that we should trap. You
should see the same trap on real hw.
r~
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM
@ 2021-09-07 13:44 ` Richard Henderson
0 siblings, 0 replies; 40+ messages in thread
From: Richard Henderson @ 2021-09-07 13:44 UTC (permalink / raw)
To: Nathan Chancellor; +Cc: Peter Maydell, qemu-arm, llvm, qemu-devel
On 8/31/21 2:51 AM, Nathan Chancellor wrote:
> I just bisected a boot hang with an LLVM-built multi_v7_defconfig +
> CONFIG_THUMB2_KERNEL=y kernel down to this commit. I do not see the same
> hang when the kernel is compiled with GCC 11.2.0 and binutils 2.37 nor
> do I see a hang with multi_v7_defconfig by itself. Is there something
> that LLVM is doing wrong when compiling/assembling/linking the kernel or
> is there something wrong/too aggressive with this commit? I can
> reproduce this with current QEMU HEAD (ad22d05833).
>
> My QEMU invocation is:
>
> $ qemu-system-arm \
> -append "console=ttyAMA0 earlycon" \
> -display none \
> -initrd rootfs.cpio \
> -kernel zImage \
> -M virt \
> -m 512m \
> -nodefaults \
> -no-reboot \
> -serial mon:stdio
>
> and the rootfs.cpio and zImage files can be found here:
>
> https://github.com/nathanchance/bug-files/tree/15c1fd6e44622a3c27823d2c5c3083dfc7246146/qemu-2e1f39e29bf9a6b28eaee9fc0949aab50dbad94a
Hmm. I see
IN:
0xc13038e2: e890 008c ldm.w r0, {r2, r3, r7}
R00=c13077ca R01=c11a8058 R02=c11a8058 R03=c031737f
R04=48379000 R05=00000024 R06=c031748d R07=c03174bb
R08=412fc0f1 R09=c0ce9308 R10=50c5387d R11=00000000
R12=00000009 R13=c1501f88 R14=c0301739 R15=c13038e2
PSR=200001f3 --C- T svc32
Taking exception 4 [Data Abort]
...from EL1 to EL1
...with ESR 0x25/0x9600003f
...with DFSR 0x1 DFAR 0xc13077ca
So, yes, it's a ldm from an address % 4 = 2, so it is correct that we should trap. You
should see the same trap on real hw.
r~
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM
2021-09-07 13:44 ` Richard Henderson
@ 2021-09-15 1:13 ` Nick Desaulniers
-1 siblings, 0 replies; 40+ messages in thread
From: Nick Desaulniers @ 2021-09-15 1:13 UTC (permalink / raw)
To: Richard Henderson, Nathan Chancellor
Cc: qemu-devel, Peter Maydell, qemu-arm, llvm
On Tue, Sep 7, 2021 at 6:44 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 8/31/21 2:51 AM, Nathan Chancellor wrote:
> > I just bisected a boot hang with an LLVM-built multi_v7_defconfig +
> > CONFIG_THUMB2_KERNEL=y kernel down to this commit. I do not see the same
> > hang when the kernel is compiled with GCC 11.2.0 and binutils 2.37 nor
> > do I see a hang with multi_v7_defconfig by itself. Is there something
> > that LLVM is doing wrong when compiling/assembling/linking the kernel or
> > is there something wrong/too aggressive with this commit? I can
> > reproduce this with current QEMU HEAD (ad22d05833).
> >
> > My QEMU invocation is:
> >
> > $ qemu-system-arm \
> > -append "console=ttyAMA0 earlycon" \
> > -display none \
> > -initrd rootfs.cpio \
> > -kernel zImage \
> > -M virt \
> > -m 512m \
> > -nodefaults \
> > -no-reboot \
> > -serial mon:stdio
> >
> > and the rootfs.cpio and zImage files can be found here:
> >
> > https://github.com/nathanchance/bug-files/tree/15c1fd6e44622a3c27823d2c5c3083dfc7246146/qemu-2e1f39e29bf9a6b28eaee9fc0949aab50dbad94a
>
> Hmm. I see
>
> IN:
> 0xc13038e2: e890 008c ldm.w r0, {r2, r3, r7}
>
> R00=c13077ca R01=c11a8058 R02=c11a8058 R03=c031737f
> R04=48379000 R05=00000024 R06=c031748d R07=c03174bb
> R08=412fc0f1 R09=c0ce9308 R10=50c5387d R11=00000000
> R12=00000009 R13=c1501f88 R14=c0301739 R15=c13038e2
> PSR=200001f3 --C- T svc32
> Taking exception 4 [Data Abort]
> ...from EL1 to EL1
> ...with ESR 0x25/0x9600003f
> ...with DFSR 0x1 DFAR 0xc13077ca
>
> So, yes, it's a ldm from an address % 4 = 2, so it is correct that we should trap. You
> should see the same trap on real hw.
Makes sense. I guess if we can find which label that's in, we can look
closer into the code generated by the compiler.
scripts/extract-vmlinux doesn't seem to be able to extract a vmlinux
from either zImage artifact though; not sure yet we'll be able to
disassemble those.
Oh, I guess GDB can show us. Looks like 0xc13038e2 is...hard to tell,
there's no debug info so we just have jumps to addresses in hex, not
symbols. I don't know my way around GDB well enough to get a sense
for where we are in the source code.
https://gist.github.com/nickdesaulniers/764ac9afab04775846ffa6c90c5a266a
If I rebuild QEMU from source, I don't get any disassembly that looks
similar, probably as a result of different compiler versions, and
maybe adding debug info.
--
Thanks,
~Nick Desaulniers
^ permalink raw reply [flat|nested] 40+ messages in thread
* Re: [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM
@ 2021-09-15 1:13 ` Nick Desaulniers
0 siblings, 0 replies; 40+ messages in thread
From: Nick Desaulniers @ 2021-09-15 1:13 UTC (permalink / raw)
To: Richard Henderson, Nathan Chancellor
Cc: qemu-devel, Peter Maydell, qemu-arm, llvm
On Tue, Sep 7, 2021 at 6:44 AM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 8/31/21 2:51 AM, Nathan Chancellor wrote:
> > I just bisected a boot hang with an LLVM-built multi_v7_defconfig +
> > CONFIG_THUMB2_KERNEL=y kernel down to this commit. I do not see the same
> > hang when the kernel is compiled with GCC 11.2.0 and binutils 2.37 nor
> > do I see a hang with multi_v7_defconfig by itself. Is there something
> > that LLVM is doing wrong when compiling/assembling/linking the kernel or
> > is there something wrong/too aggressive with this commit? I can
> > reproduce this with current QEMU HEAD (ad22d05833).
> >
> > My QEMU invocation is:
> >
> > $ qemu-system-arm \
> > -append "console=ttyAMA0 earlycon" \
> > -display none \
> > -initrd rootfs.cpio \
> > -kernel zImage \
> > -M virt \
> > -m 512m \
> > -nodefaults \
> > -no-reboot \
> > -serial mon:stdio
> >
> > and the rootfs.cpio and zImage files can be found here:
> >
> > https://github.com/nathanchance/bug-files/tree/15c1fd6e44622a3c27823d2c5c3083dfc7246146/qemu-2e1f39e29bf9a6b28eaee9fc0949aab50dbad94a
>
> Hmm. I see
>
> IN:
> 0xc13038e2: e890 008c ldm.w r0, {r2, r3, r7}
>
> R00=c13077ca R01=c11a8058 R02=c11a8058 R03=c031737f
> R04=48379000 R05=00000024 R06=c031748d R07=c03174bb
> R08=412fc0f1 R09=c0ce9308 R10=50c5387d R11=00000000
> R12=00000009 R13=c1501f88 R14=c0301739 R15=c13038e2
> PSR=200001f3 --C- T svc32
> Taking exception 4 [Data Abort]
> ...from EL1 to EL1
> ...with ESR 0x25/0x9600003f
> ...with DFSR 0x1 DFAR 0xc13077ca
>
> So, yes, it's a ldm from an address % 4 = 2, so it is correct that we should trap. You
> should see the same trap on real hw.
Makes sense. I guess if we can find which label that's in, we can look
closer into the code generated by the compiler.
scripts/extract-vmlinux doesn't seem to be able to extract a vmlinux
from either zImage artifact though; not sure yet we'll be able to
disassemble those.
Oh, I guess GDB can show us. Looks like 0xc13038e2 is...hard to tell,
there's no debug info so we just have jumps to addresses in hex, not
symbols. I don't know my way around GDB well enough to get a sense
for where we are in the source code.
https://gist.github.com/nickdesaulniers/764ac9afab04775846ffa6c90c5a266a
If I rebuild QEMU from source, I don't get any disassembly that looks
similar, probably as a result of different compiler versions, and
maybe adding debug info.
--
Thanks,
~Nick Desaulniers
^ permalink raw reply [flat|nested] 40+ messages in thread
end of thread, other threads:[~2021-09-15 1:16 UTC | newest]
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2021-04-19 20:22 [PATCH v5 00/31] target/arm: enforce alignment Richard Henderson
2021-04-19 20:22 ` [PATCH v5 01/31] target/arm: Fix decode of align in VLDST_single Richard Henderson
2021-04-19 20:22 ` [PATCH v5 02/31] target/arm: Rename TBFLAG_A32, SCTLR_B Richard Henderson
2021-04-19 20:22 ` [PATCH v5 03/31] target/arm: Rename TBFLAG_ANY, PSTATE_SS Richard Henderson
2021-04-19 20:22 ` [PATCH v5 04/31] target/arm: Add wrapper macros for accessing tbflags Richard Henderson
2021-04-19 20:22 ` [PATCH v5 05/31] target/arm: Introduce CPUARMTBFlags Richard Henderson
2021-04-19 20:22 ` [PATCH v5 06/31] target/arm: Move mode specific TB flags to tb->cs_base Richard Henderson
2021-04-19 20:22 ` [PATCH v5 07/31] target/arm: Use cpu_abort in assert_hflags_rebuild_correctly Richard Henderson
2021-04-20 9:07 ` Peter Maydell
2021-04-19 20:22 ` [PATCH v5 08/31] target/arm: Move TBFLAG_AM32 bits to the top Richard Henderson
2021-04-19 20:22 ` [PATCH v5 09/31] target/arm: Move TBFLAG_ANY bits to the bottom Richard Henderson
2021-04-19 20:22 ` [PATCH v5 10/31] target/arm: Add ALIGN_MEM to TBFLAG_ANY Richard Henderson
2021-04-19 20:22 ` [PATCH v5 11/31] target/arm: Adjust gen_aa32_{ld, st}_i32 for align+endianness Richard Henderson
2021-04-19 20:22 ` [PATCH v5 12/31] target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 Richard Henderson
2021-04-19 20:22 ` [PATCH v5 13/31] target/arm: Fix SCTLR_B test for TCGv_i64 load/store Richard Henderson
2021-04-19 20:22 ` [PATCH v5 14/31] target/arm: Adjust gen_aa32_{ld, st}_i64 for align+endianness Richard Henderson
2021-04-19 20:22 ` [PATCH v5 15/31] target/arm: Enforce word alignment for LDRD/STRD Richard Henderson
2021-04-19 20:22 ` [PATCH v5 16/31] target/arm: Enforce alignment for LDA/LDAH/STL/STLH Richard Henderson
2021-04-19 20:22 ` [PATCH v5 17/31] target/arm: Enforce alignment for LDM/STM Richard Henderson
2021-08-31 0:51 ` Nathan Chancellor
2021-08-31 0:51 ` Nathan Chancellor
2021-09-07 13:44 ` Richard Henderson
2021-09-07 13:44 ` Richard Henderson
2021-09-15 1:13 ` Nick Desaulniers
2021-09-15 1:13 ` Nick Desaulniers
2021-04-19 20:22 ` [PATCH v5 18/31] target/arm: Enforce alignment for RFE Richard Henderson
2021-04-19 20:22 ` [PATCH v5 19/31] target/arm: Enforce alignment for SRS Richard Henderson
2021-04-19 20:22 ` [PATCH v5 20/31] target/arm: Enforce alignment for VLDM/VSTM Richard Henderson
2021-04-19 20:22 ` [PATCH v5 21/31] target/arm: Enforce alignment for VLDR/VSTR Richard Henderson
2021-04-19 20:22 ` [PATCH v5 22/31] target/arm: Enforce alignment for VLDn (all lanes) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 23/31] target/arm: Enforce alignment for VLDn/VSTn (multiple) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 24/31] target/arm: Enforce alignment for VLDn/VSTn (single) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 25/31] target/arm: Use finalize_memop for aa64 gpr load/store Richard Henderson
2021-04-19 20:22 ` [PATCH v5 26/31] target/arm: Use finalize_memop for aa64 fpr load/store Richard Henderson
2021-04-19 20:22 ` [PATCH v5 27/31] target/arm: Enforce alignment for aa64 load-acq/store-rel Richard Henderson
2021-04-19 20:22 ` [PATCH v5 28/31] target/arm: Use MemOp for size + endian in aa64 vector ld/st Richard Henderson
2021-04-19 20:22 ` [PATCH v5 29/31] target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 30/31] target/arm: Enforce alignment for aa64 vector LDn/STn (single) Richard Henderson
2021-04-19 20:22 ` [PATCH v5 31/31] target/arm: Enforce alignment for sve LD1R Richard Henderson
2021-04-20 10:27 ` [PATCH v5 00/31] target/arm: enforce alignment Peter Maydell
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