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Tue, 20 Apr 2021 01:20:28 -0700 Envelope-to: git@xilinx.com, robh+dt@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, chinnikishore369@gmail.com Received: from [10.140.6.60] (port=45276 helo=xhdnavam40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1lYlcR-0007C5-4j; Tue, 20 Apr 2021 01:20:27 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , Subject: [PATCH 2/5] misc: zynq: Add afi config driver Date: Tue, 20 Apr 2021 13:41:50 +0530 Message-ID: <20210420081153.17020-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210420081153.17020-1-nava.manne@xilinx.com> References: <20210420081153.17020-1-nava.manne@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e12b6698-a878-49ce-bba4-08d903d52c21 X-MS-TrafficTypeDiagnostic: SN6PR02MB5022: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4714; 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X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2021 08:20:35.2311 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e12b6698-a878-49ce-bba4-08d903d52c21 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.62.198];Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT033.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5022 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This patch adds zynq afi config driver. This is useful for the configuration of the PS-PL interface on zynq platform. Signed-off-by: Nava kishore Manne --- drivers/misc/Kconfig | 11 ++++++ drivers/misc/Makefile | 1 + drivers/misc/zynq-afi.c | 81 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+) create mode 100644 drivers/misc/zynq-afi.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index f532c59bb59b..877b43b3377d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -445,6 +445,17 @@ config HISI_HIKEY_USB switching between the dual-role USB-C port and the USB-A host ports using only one USB controller. +config ZYNQ_AFI + tristate "Xilinx ZYNQ AFI support" + help + Zynq AFI driver support for writing to the AFI registers + for configuring PS_PL Bus-width. Xilinx Zynq SoC connect + the PS to the programmable logic (PL) through the AXI port. + This AXI port helps to establish the data path between the + PS and PL.In-order to establish the proper communication path + between PS and PL, the AXI port data path should be configured + with the proper Bus-width values + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 99b6f15a3c70..e9b03843100f 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -56,3 +56,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/ obj-$(CONFIG_UACCE) += uacce/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o +obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o diff --git a/drivers/misc/zynq-afi.c b/drivers/misc/zynq-afi.c new file mode 100644 index 000000000000..04317d1bdb98 --- /dev/null +++ b/drivers/misc/zynq-afi.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx ZYNQ AFI driver. + * Copyright (c) 2018-2021 Xilinx Inc. + */ + +#include +#include +#include +#include +#include + +/* Registers and special values for doing register-based operations */ +#define AFI_RDCHAN_CTRL_OFFSET 0x00 +#define AFI_WRCHAN_CTRL_OFFSET 0x14 + +#define AFI_BUSWIDTH_MASK 0x01 + +/** + * struct afi_fpga - AFI register description + * @membase: pointer to register struct + * @afi_width: AFI bus width to be written + */ +struct zynq_afi_fpga { + void __iomem *membase; + u32 afi_width; +}; + +static int zynq_afi_fpga_probe(struct platform_device *pdev) +{ + struct zynq_afi_fpga *afi_fpga; + struct resource *res; + u32 reg_val; + u32 val; + + afi_fpga = devm_kzalloc(&pdev->dev, sizeof(*afi_fpga), GFP_KERNEL); + if (!afi_fpga) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + afi_fpga->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(afi_fpga->membase)) + return PTR_ERR(afi_fpga->membase); + + val = device_property_read_u32(&pdev->dev, "xlnx,afi-width", + &afi_fpga->afi_width); + if (val) { + dev_err(&pdev->dev, "failed to get the afi bus width\n"); + return -EINVAL; + } + + reg_val = readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); + reg_val &= ~AFI_BUSWIDTH_MASK; + writel(reg_val | afi_fpga->afi_width, + afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); + reg_val = readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); + reg_val &= ~AFI_BUSWIDTH_MASK; + writel(reg_val | afi_fpga->afi_width, + afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); + + return 0; +} + +static const struct of_device_id zynq_afi_fpga_ids[] = { + { .compatible = "xlnx,zynq-afi-fpga" }, + { }, +}; +MODULE_DEVICE_TABLE(of, zynq_afi_fpga_ids); + +static struct platform_driver zynq_afi_fpga_driver = { + .driver = { + .name = "zynq-afi-fpga", + .of_match_table = zynq_afi_fpga_ids, + }, + .probe = zynq_afi_fpga_probe, +}; +module_platform_driver(zynq_afi_fpga_driver); + +MODULE_DESCRIPTION("ZYNQ FPGA AFI module"); +MODULE_AUTHOR("Nava kishore Manne "); +MODULE_LICENSE("GPL v2"); -- 2.18.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFCB8C433B4 for ; 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Tue, 20 Apr 2021 01:20:27 -0700 From: Nava kishore Manne To: , , , , , , , , , , , , , , , Subject: [PATCH 2/5] misc: zynq: Add afi config driver Date: Tue, 20 Apr 2021 13:41:50 +0530 Message-ID: <20210420081153.17020-3-nava.manne@xilinx.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20210420081153.17020-1-nava.manne@xilinx.com> References: <20210420081153.17020-1-nava.manne@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e12b6698-a878-49ce-bba4-08d903d52c21 X-MS-TrafficTypeDiagnostic: SN6PR02MB5022: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ETa1Cm+ljiRLwBeL6+BtrSIiCQiFCpxJeSCCq6E3lTuTB0C55bUensUR7/M4FyNCovWzUqpsp2g9DQ6d9h5J8H12PoYt1UnAhQ4OgP7VX2sq0RLOlActCqi82pheX5bdNgj/apFNA/dcSjorFXLCtjZHZZaWrV8407pnK1c6fGdYjYR1nQoc37Ok0qLdstxAVZBvQCG/xehPr58THChjqGkMjDygsi8yBNCS9BwRNnoB77Fwj5dy3DIM1qJflaHQtL92PNt94WB8t3npw3a7rsExweykmqUd4HrZpcjPtRyP2C6D0WDX0SIe74AmlY3cmc/JSKyist+8MrZJRE97gsV6yRQryo8czUV94ldIxZFlx2zE4XYv79QbgYmjD/WP1bMeC4He6MSFUP3ZdTxljEBvt0OsRI+/Ouq6eROjogm8u4MZ9eyTLS53mHd4sEXFvsss+HQN8a3oy3xvVWQSXhWrtt64Kwgej7+Uxo7Au3asIK17yVHNJN5jWxRFHZm5RAXD4U78jhPH9f4NOp3wKqHVUveS29EwZaXrE2+RmMELmWPTaz+K79D5dKi52RuKYWdQxBztxoIjK98F53KCTiehTXLcaU6dYiYIeh+urMYzZskI4BrHSmZT7zO3EqosvtdUAKm9GpSfmJmwMPOj1uqE7oy9MgHkEwKq/gz+D0jC4kA3FS5nTgE3fxqlNGEf7l9xlPtAuw6jCscPVKjkQK0fSEsT5SCsymU/ACCY713bDyQLdnT6MczotxnPhKq+ X-Forefront-Antispam-Report: CIP:149.199.62.198; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This patch adds zynq afi config driver. This is useful for the configuration of the PS-PL interface on zynq platform. Signed-off-by: Nava kishore Manne --- drivers/misc/Kconfig | 11 ++++++ drivers/misc/Makefile | 1 + drivers/misc/zynq-afi.c | 81 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 93 insertions(+) create mode 100644 drivers/misc/zynq-afi.c diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index f532c59bb59b..877b43b3377d 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -445,6 +445,17 @@ config HISI_HIKEY_USB switching between the dual-role USB-C port and the USB-A host ports using only one USB controller. +config ZYNQ_AFI + tristate "Xilinx ZYNQ AFI support" + help + Zynq AFI driver support for writing to the AFI registers + for configuring PS_PL Bus-width. Xilinx Zynq SoC connect + the PS to the programmable logic (PL) through the AXI port. + This AXI port helps to establish the data path between the + PS and PL.In-order to establish the proper communication path + between PS and PL, the AXI port data path should be configured + with the proper Bus-width values + source "drivers/misc/c2port/Kconfig" source "drivers/misc/eeprom/Kconfig" source "drivers/misc/cb710/Kconfig" diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 99b6f15a3c70..e9b03843100f 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -56,3 +56,4 @@ obj-$(CONFIG_HABANA_AI) += habanalabs/ obj-$(CONFIG_UACCE) += uacce/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o +obj-$(CONFIG_ZYNQ_AFI) += zynq-afi.o diff --git a/drivers/misc/zynq-afi.c b/drivers/misc/zynq-afi.c new file mode 100644 index 000000000000..04317d1bdb98 --- /dev/null +++ b/drivers/misc/zynq-afi.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Xilinx ZYNQ AFI driver. + * Copyright (c) 2018-2021 Xilinx Inc. + */ + +#include +#include +#include +#include +#include + +/* Registers and special values for doing register-based operations */ +#define AFI_RDCHAN_CTRL_OFFSET 0x00 +#define AFI_WRCHAN_CTRL_OFFSET 0x14 + +#define AFI_BUSWIDTH_MASK 0x01 + +/** + * struct afi_fpga - AFI register description + * @membase: pointer to register struct + * @afi_width: AFI bus width to be written + */ +struct zynq_afi_fpga { + void __iomem *membase; + u32 afi_width; +}; + +static int zynq_afi_fpga_probe(struct platform_device *pdev) +{ + struct zynq_afi_fpga *afi_fpga; + struct resource *res; + u32 reg_val; + u32 val; + + afi_fpga = devm_kzalloc(&pdev->dev, sizeof(*afi_fpga), GFP_KERNEL); + if (!afi_fpga) + return -ENOMEM; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + afi_fpga->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(afi_fpga->membase)) + return PTR_ERR(afi_fpga->membase); + + val = device_property_read_u32(&pdev->dev, "xlnx,afi-width", + &afi_fpga->afi_width); + if (val) { + dev_err(&pdev->dev, "failed to get the afi bus width\n"); + return -EINVAL; + } + + reg_val = readl(afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); + reg_val &= ~AFI_BUSWIDTH_MASK; + writel(reg_val | afi_fpga->afi_width, + afi_fpga->membase + AFI_RDCHAN_CTRL_OFFSET); + reg_val = readl(afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); + reg_val &= ~AFI_BUSWIDTH_MASK; + writel(reg_val | afi_fpga->afi_width, + afi_fpga->membase + AFI_WRCHAN_CTRL_OFFSET); + + return 0; +} + +static const struct of_device_id zynq_afi_fpga_ids[] = { + { .compatible = "xlnx,zynq-afi-fpga" }, + { }, +}; +MODULE_DEVICE_TABLE(of, zynq_afi_fpga_ids); + +static struct platform_driver zynq_afi_fpga_driver = { + .driver = { + .name = "zynq-afi-fpga", + .of_match_table = zynq_afi_fpga_ids, + }, + .probe = zynq_afi_fpga_probe, +}; +module_platform_driver(zynq_afi_fpga_driver); + +MODULE_DESCRIPTION("ZYNQ FPGA AFI module"); +MODULE_AUTHOR("Nava kishore Manne "); +MODULE_LICENSE("GPL v2"); -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel