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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Apr 2021 09:01:34.6007 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb6747ec-c826-4858-fd76-08d904a4107f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT028.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB2372 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ramakrishna Saripalli Certain AMD processors feature a new technology called Predictive Store Forwarding (PSF). PSF is a micro-architectural optimization designed to improve the performance of code execution by predicting dependencies between loads and stores. Incorrect PSF predictions can occur due to two reasons. - It is possible that the load/store pair may have had dependency for a while but the dependency has stopped because the address in the load/store pair has changed. - Second source of incorrect PSF prediction can occur because of an alias in the PSF predictor structure stored in the microarchitectural state. PSF predictor tracks load/store pair based on portions of instruction pointer. It is possible that a load/store pair which does have a dependency may be aliased by another load/store pair which does not have the same dependency. This can result in incorrect speculation. Software may be able to detect this aliasing and perform side-channel attacks. These features are being introduced to support mitigation from these attacks. All CPUs that implement PSF provide one bit to disable this feature. If the bit to disable this feature is available, it means that the CPU implements PSF feature and is therefore vulnerable to PSF risks. The bits that are introduced X86_FEATURE_PSFD: CPUID_Fn80000008_EBX[28] ("PSF disable") If this bit is 1, CPU implements PSF and PSF mitigation is supported. Signed-off-by: Ramakrishna Saripalli --- arch/x86/include/asm/cpufeatures.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index cc96e26d69f7..078f46022293 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -309,6 +309,7 @@ #define X86_FEATURE_AMD_SSBD (13*32+24) /* "" Speculative Store Bypass Disable */ #define X86_FEATURE_VIRT_SSBD (13*32+25) /* Virtualized Speculative Store Bypass Disable */ #define X86_FEATURE_AMD_SSB_NO (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */ +#define X86_FEATURE_PSFD (13*32+28) /* Predictive Store Forward Disable */ /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */ #define X86_FEATURE_DTHERM (14*32+ 0) /* Digital Thermal Sensor */ -- 2.25.1