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[31.30.174.132]) by smtp.gmail.com with ESMTPSA id j7sm1987322edv.40.2021.04.27.02.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Apr 2021 02:49:26 -0700 (PDT) Date: Tue, 27 Apr 2021 11:49:24 +0200 From: Andrew Jones To: Peter Maydell Subject: Re: [PATCH RESEND v2 5/6] target/arm/cpu: Enable 'el2' to work with host/max cpu Message-ID: <20210427094924.pgivurjrgtzovcwa@gator.home> References: <37df1b1872f15086dd1d066e53dc1eedaf114051.1617281290.git.haibo.xu@linaro.org> <20210427092423.q3ktw4kkd5xhapad@gator.home> MIME-Version: 1.0 In-Reply-To: Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=drjones@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=216.205.24.124; envelope-from=drjones@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.219, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , QEMU Developers , Andrea Bolognani , qemu-arm , Haibo Xu , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Tue, Apr 27, 2021 at 10:38:00AM +0100, Peter Maydell wrote: > On Tue, 27 Apr 2021 at 10:24, Andrew Jones wrote: > > I feel like there are way too many ways to track this feature now. If I > > didn't lose count we have > > > > 1) cpu->has_el2 > > 2) cpu->env & ARM_FEATURE_EL2 > > 3) (for mach-virt) vms->virt > > 4) possibly (and probably should) some ID register bits > > > > I realize the first three are already in use for TCG, but I'm guessing > > we'll want to clean those up. What's the plan going forward? I presume > > it'll be (4), but maybe something like (1) and/or (3) will stick around > > for convenience. I'm pretty sure we want to avoid (2). > > For new features added we want to use ID register bits. However, > a lot of older pre-existing features are keyed off ARM_FEATURE_FOO > flag bits. Trying to convert an ARM_FEATURE flag to use ID registers > isn't necessarily 100% trivial (for instance, the ARM_FEATURE flag > is always checkable regardless of AArch64 vs AArch32, but the ID > register checks often need to be split up into separate ones checking > the AArch32 or the AArch64 ID register value). So we aren't really > doing conversion of existing flags. (I did a few which were easy > because there were only a handful of checks of them.) As a side note, > some features really can't be checked in ID registers, like > ARM_FEATURE_V8_1M, so env->features is not going to go away completely. > > The only use of cpu->has_foo should be for the QOM property -- the > arm_cpu_realizefn() should look at it and then either clear the > ARM_FEATURE flag or update the ID register bits depending on > which one the feature is using. > > vms->virt is for the board code (and controls more things than > just whether the CPU itself has EL2). > Thanks for the summary, Peter. For this series, do you recommend attempting to convert from ARM_FEATURE_EL2 to feature bits first? Or keep the ARM_FEATURE flag? Also, while I agree we can't use vms->virt for the same purposes as the CPU feature (however that's tracked), do you agree vms->virt should be true when the CPU feature is enabled? Thanks, drew