From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HK_RANDOM_FROM,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5380C433ED for ; Tue, 27 Apr 2021 14:05:33 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id 7C08661002 for ; Tue, 27 Apr 2021 14:05:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7C08661002 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C134F4125F; Tue, 27 Apr 2021 16:05:24 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mails.dpdk.org (Postfix) with ESMTP id 4E73741253 for ; Tue, 27 Apr 2021 16:05:22 +0200 (CEST) IronPort-SDR: w1yBUz8pW3DRPUIgTzUWaIO9XO3taNJQZ2YGqY/trfUmgpSft8K+hAKJhT0Kr86Ooo/kVPip4E i/9/GT5U88kg== X-IronPort-AV: E=McAfee;i="6200,9189,9967"; a="183994840" X-IronPort-AV: E=Sophos;i="5.82,254,1613462400"; d="scan'208";a="183994840" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2021 07:05:21 -0700 IronPort-SDR: 8rfGOCutDCc+TIZHjgLD7x7HYNR4tfk0j5ITcCtJ7mnH1KUW6uLWH/8VR8pOgeLSUOCbPxTuw9 xHpmLWtCTaAg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,254,1613462400"; d="scan'208";a="457656370" Received: from npg-dpdk-haiyue-2.sh.intel.com ([10.67.119.63]) by fmsmga002.fm.intel.com with ESMTP; 27 Apr 2021 07:05:19 -0700 From: Haiyue Wang To: dev@dpdk.org Cc: qi.z.zhang@intel.com, liang-min.wang@intel.com, david.marchand@redhat.com, Haiyue Wang , Jingjing Wu , Beilei Xing Date: Tue, 27 Apr 2021 21:39:11 +0800 Message-Id: <20210427133912.261993-3-haiyue.wang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210427133912.261993-1-haiyue.wang@intel.com> References: <20210421050243.130585-1-haiyue.wang@intel.com> <20210427133912.261993-1-haiyue.wang@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v4 2/3] net/iavf: enable PCI bus master after reset X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The VF reset can be triggerred by the PF reset event, in this case, the PCI bus master will be cleared, then the VF is not allowed to issue any Memory or I/O Requests. So after the reset event is detected, always enable the PCI bus master. Signed-off-by: Haiyue Wang --- drivers/net/iavf/iavf_ethdev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c index d523a0618..9a0a20a29 100644 --- a/drivers/net/iavf/iavf_ethdev.c +++ b/drivers/net/iavf/iavf_ethdev.c @@ -2255,6 +2255,9 @@ iavf_dev_close(struct rte_eth_dev *dev) rte_free(vf->aq_resp); vf->aq_resp = NULL; + if (vf->vf_reset) + rte_pci_set_bus_master(pci_dev, true); + vf->vf_reset = false; return ret; -- 2.31.1