[PATCH v2 0/2] hw: Convert mc146818rtc & etraxfs_timer to 3-phase reset interface

[PATCH v2 0/2] hw: Convert mc146818rtc & etraxfs_timer to 3-phase reset interface

[Philippe Mathieu-Daudé]

Remove qemu_register_reset() when a qdev type has a qbus parent,
implementing the 3-phase Resettable interface.

Since v1:
- Use 3-phase reset interface instead of qdev one (Laurent)

Supersedes: <20210423233652.3042941-1-f4bug@amsat.org>

Philippe Mathieu-Daudé (2):
  hw/timer/etraxfs_timer: Convert to 3-phase reset (Resettable
    interface)
  hw/rtc/mc146818rtc: Convert to 3-phase reset (Resettable interface)

 hw/rtc/mc146818rtc.c     | 42 +++++++++++++++++++++-------------------
 hw/timer/etraxfs_timer.c | 14 +++++++++++---
 2 files changed, 33 insertions(+), 23 deletions(-)

-- 
2.26.3

[PATCH v2 1/2] hw/timer/etraxfs_timer: Convert to 3-phase reset (Resettable interface)

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
handler is called automatically when its qbus parent is reset
(we don't need to register it manually).

Convert the generic reset to a enter/exit resettable ones, and
remove the qemu_register_reset() call.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/timer/etraxfs_timer.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
index 5379006086f..7dd3daf6771 100644
--- a/hw/timer/etraxfs_timer.c
+++ b/hw/timer/etraxfs_timer.c
@@ -309,9 +309,9 @@ static const MemoryRegionOps timer_ops = {
     }
 };
 
-static void etraxfs_timer_reset(void *opaque)
+static void etraxfs_timer_reset_enter(Object *obj, ResetType type)
 {
-    ETRAXTimerState *t = opaque;
+    ETRAXTimerState *t = ETRAX_TIMER(obj);
 
     ptimer_transaction_begin(t->ptimer_t0);
     ptimer_stop(t->ptimer_t0);
@@ -325,6 +325,12 @@ static void etraxfs_timer_reset(void *opaque)
     t->rw_wd_ctrl = 0;
     t->r_intr = 0;
     t->rw_intr_mask = 0;
+}
+
+static void etraxfs_timer_reset_exit(Object *obj)
+{
+    ETRAXTimerState *t = ETRAX_TIMER(obj);
+
     qemu_irq_lower(t->irq);
 }
 
@@ -343,14 +349,16 @@ static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
     memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
                           "etraxfs-timer", 0x5c);
     sysbus_init_mmio(sbd, &t->mmio);
-    qemu_register_reset(etraxfs_timer_reset, t);
 }
 
 static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
 
     dc->realize = etraxfs_timer_realize;
+    rc->phases.enter = etraxfs_timer_reset_enter;
+    rc->phases.exit = etraxfs_timer_reset_exit;
 }
 
 static const TypeInfo etraxfs_timer_info = {
-- 
2.26.3

[PATCH v2 2/2] hw/rtc/mc146818rtc: Convert to 3-phase reset (Resettable interface)

[Philippe Mathieu-Daudé]

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

TYPE_MC146818_RTC is an ISA device, so its DeviceClass::reset()
handler is called automatically when its qbus parent is reset
(we don't need to register it manually).

We have 2 reset() methods: a generic one and the qdev one.
Merge them into a reset_enter handler (keeping the IRQ lowering
to a reset_exit one), and remove the qemu_register_reset() call.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 hw/rtc/mc146818rtc.c | 42 ++++++++++++++++++++++--------------------
 1 file changed, 22 insertions(+), 20 deletions(-)

diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
index 5d0fcacd0c0..6bf075ba8ce 100644
--- a/hw/rtc/mc146818rtc.c
+++ b/hw/rtc/mc146818rtc.c
@@ -872,22 +872,6 @@ static void rtc_notify_suspend(Notifier *notifier, void *data)
     rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE);
 }
 
-static void rtc_reset(void *opaque)
-{
-    RTCState *s = opaque;
-
-    s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
-    s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
-    check_update_timer(s);
-
-    qemu_irq_lower(s->irq);
-
-    if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
-        s->irq_coalesced = 0;
-        s->irq_reinject_on_ack_count = 0;
-    }
-}
-
 static const MemoryRegionOps cmos_ops = {
     .read = cmos_ioport_read,
     .write = cmos_ioport_write,
@@ -962,7 +946,6 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
     memory_region_add_coalescing(&s->coalesced_io, 0, 1);
 
     qdev_set_legacy_instance_id(dev, RTC_ISA_BASE, 3);
-    qemu_register_reset(rtc_reset, s);
 
     object_property_add_tm(OBJECT(s), "date", rtc_get_date);
 
@@ -998,15 +981,32 @@ static Property mc146818rtc_properties[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
-static void rtc_resetdev(DeviceState *d)
+static void rtc_reset_enter(Object *obj, ResetType type)
 {
-    RTCState *s = MC146818_RTC(d);
+    RTCState *s = MC146818_RTC(obj);
 
     /* Reason: VM do suspend self will set 0xfe
      * Reset any values other than 0xfe(Guest suspend case) */
     if (s->cmos_data[0x0f] != 0xfe) {
         s->cmos_data[0x0f] = 0x00;
     }
+
+    s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
+    s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
+    check_update_timer(s);
+
+
+    if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) {
+        s->irq_coalesced = 0;
+        s->irq_reinject_on_ack_count = 0;
+    }
+}
+
+static void rtc_reset_exit(Object *obj)
+{
+    RTCState *s = MC146818_RTC(obj);
+
+    qemu_irq_lower(s->irq);
 }
 
 static void rtc_build_aml(ISADevice *isadev, Aml *scope)
@@ -1033,11 +1033,13 @@ static void rtc_build_aml(ISADevice *isadev, Aml *scope)
 static void rtc_class_initfn(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
+    ResettableClass *rc = RESETTABLE_CLASS(klass);
     ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
 
     dc->realize = rtc_realizefn;
-    dc->reset = rtc_resetdev;
     dc->vmsd = &vmstate_rtc;
+    rc->phases.enter = rtc_reset_enter;
+    rc->phases.exit = rtc_reset_exit;
     isa->build_aml = rtc_build_aml;
     device_class_set_props(dc, mc146818rtc_properties);
 }
-- 
2.26.3

Re: [PATCH v2 1/2] hw/timer/etraxfs_timer: Convert to 3-phase reset (Resettable interface)

[Edgar E. Iglesias]

On Sun, May 02, 2021 at 12:13:49AM +0200, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
> 
> TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
> handler is called automatically when its qbus parent is reset
> (we don't need to register it manually).
> 
> Convert the generic reset to a enter/exit resettable ones, and
> remove the qemu_register_reset() call.

Hi Philippe,

The interrupt should be updated in the reset_hold phase, otherwise
interrupts stay asserted while the device is in reset.

Otherwise this looks good to me.

Cheers,
Edgar


> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  hw/timer/etraxfs_timer.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
> index 5379006086f..7dd3daf6771 100644
> --- a/hw/timer/etraxfs_timer.c
> +++ b/hw/timer/etraxfs_timer.c
> @@ -309,9 +309,9 @@ static const MemoryRegionOps timer_ops = {
>      }
>  };
>  
> -static void etraxfs_timer_reset(void *opaque)
> +static void etraxfs_timer_reset_enter(Object *obj, ResetType type)
>  {
> -    ETRAXTimerState *t = opaque;
> +    ETRAXTimerState *t = ETRAX_TIMER(obj);
>  
>      ptimer_transaction_begin(t->ptimer_t0);
>      ptimer_stop(t->ptimer_t0);
> @@ -325,6 +325,12 @@ static void etraxfs_timer_reset(void *opaque)
>      t->rw_wd_ctrl = 0;
>      t->r_intr = 0;
>      t->rw_intr_mask = 0;
> +}
> +
> +static void etraxfs_timer_reset_exit(Object *obj)
> +{
> +    ETRAXTimerState *t = ETRAX_TIMER(obj);
> +
>      qemu_irq_lower(t->irq);
>  }
>  
> @@ -343,14 +349,16 @@ static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
>      memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
>                            "etraxfs-timer", 0x5c);
>      sysbus_init_mmio(sbd, &t->mmio);
> -    qemu_register_reset(etraxfs_timer_reset, t);
>  }
>  
>  static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
> +    ResettableClass *rc = RESETTABLE_CLASS(klass);
>  
>      dc->realize = etraxfs_timer_realize;
> +    rc->phases.enter = etraxfs_timer_reset_enter;
> +    rc->phases.exit = etraxfs_timer_reset_exit;
>  }
>  
>  static const TypeInfo etraxfs_timer_info = {
> -- 
> 2.26.3
> 

Re: [PATCH v2 1/2] hw/timer/etraxfs_timer: Convert to 3-phase reset (Resettable interface)

[Edgar E. Iglesias]

On Sun, May 02, 2021 at 12:13:49AM +0200, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
> 
> TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
> handler is called automatically when its qbus parent is reset
> (we don't need to register it manually).
> 
> Convert the generic reset to a enter/exit resettable ones, and
> remove the qemu_register_reset() call.

Same comment here regarding reset_exit -> reset_hold.

Cheers,
Edgar


> 
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  hw/timer/etraxfs_timer.c | 14 +++++++++++---
>  1 file changed, 11 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
> index 5379006086f..7dd3daf6771 100644
> --- a/hw/timer/etraxfs_timer.c
> +++ b/hw/timer/etraxfs_timer.c
> @@ -309,9 +309,9 @@ static const MemoryRegionOps timer_ops = {
>      }
>  };
>  
> -static void etraxfs_timer_reset(void *opaque)
> +static void etraxfs_timer_reset_enter(Object *obj, ResetType type)
>  {
> -    ETRAXTimerState *t = opaque;
> +    ETRAXTimerState *t = ETRAX_TIMER(obj);
>  
>      ptimer_transaction_begin(t->ptimer_t0);
>      ptimer_stop(t->ptimer_t0);
> @@ -325,6 +325,12 @@ static void etraxfs_timer_reset(void *opaque)
>      t->rw_wd_ctrl = 0;
>      t->r_intr = 0;
>      t->rw_intr_mask = 0;
> +}
> +
> +static void etraxfs_timer_reset_exit(Object *obj)
> +{
> +    ETRAXTimerState *t = ETRAX_TIMER(obj);
> +
>      qemu_irq_lower(t->irq);
>  }
>  
> @@ -343,14 +349,16 @@ static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
>      memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
>                            "etraxfs-timer", 0x5c);
>      sysbus_init_mmio(sbd, &t->mmio);
> -    qemu_register_reset(etraxfs_timer_reset, t);
>  }
>  
>  static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(klass);
> +    ResettableClass *rc = RESETTABLE_CLASS(klass);
>  
>      dc->realize = etraxfs_timer_realize;
> +    rc->phases.enter = etraxfs_timer_reset_enter;
> +    rc->phases.exit = etraxfs_timer_reset_exit;
>  }
>  
>  static const TypeInfo etraxfs_timer_info = {
> -- 
> 2.26.3
> 

Re: [PATCH v2 1/2] hw/timer/etraxfs_timer: Convert to 3-phase reset (Resettable interface)

[Philippe Mathieu-Daudé]

Hi Edgar,

+Damien/Luc/Markus

On 5/2/21 8:21 AM, Edgar E. Iglesias wrote:
> On Sun, May 02, 2021 at 12:13:49AM +0200, Philippe Mathieu-Daudé wrote:
>> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>>
>> TYPE_ETRAX_FS_TIMER is a sysbus device, so its DeviceClass::reset()
>> handler is called automatically when its qbus parent is reset
>> (we don't need to register it manually).
>>
>> Convert the generic reset to a enter/exit resettable ones, and
>> remove the qemu_register_reset() call.
> 
> Hi Philippe,
> 
> The interrupt should be updated in the reset_hold phase, otherwise
> interrupts stay asserted while the device is in reset.

OK. I took some time to understand in which handler the IRQ call had
to go, so I think to documentation is not clear enough:

 * @phases.hold: This phase is called for entry into reset, once every
object
 * in the system which is being reset has had its @phases.enter method
called.
 * At this point devices can do actions that affect other objects.
 *
 * @phases.exit: This phase is called when the object leaves the reset
state.
 * Actions affecting other objects are permitted.

Do you mind sending a patch to clarify? Personally I find listing what
can be done where easier to understand (explicit list) rather than
being generic and letting the developer choose.

> 
> Otherwise this looks good to me.
> 
> Cheers,
> Edgar