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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PATCH v6 13/26] tcg/tci: Emit setcond before brcond
Date: Sun,  2 May 2021 16:57:14 -0700	[thread overview]
Message-ID: <20210502235727.1979457-14-richard.henderson@linaro.org> (raw)
In-Reply-To: <20210502235727.1979457-1-richard.henderson@linaro.org>

The encoding planned for tci does not have enough room for
brcond2, with 4 registers and a condition as input as well
as the label.  Resolve the condition into TCG_REG_TMP, and
relax brcond to one register plus a label, considering the
condition to always be reg != 0.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/tci.c                | 68 ++++++++++------------------------------
 tcg/tci/tcg-target.c.inc | 52 +++++++++++-------------------
 2 files changed, 35 insertions(+), 85 deletions(-)

diff --git a/tcg/tci.c b/tcg/tci.c
index 743c12af67..5677c3544a 100644
--- a/tcg/tci.c
+++ b/tcg/tci.c
@@ -145,6 +145,16 @@ static void tci_args_nll(const uint8_t **tb_ptr, uint8_t *n0,
     check_size(start, tb_ptr);
 }
 
+static void tci_args_rl(const uint8_t **tb_ptr, TCGReg *r0, void **l1)
+{
+    const uint8_t *start = *tb_ptr;
+
+    *r0 = tci_read_r(tb_ptr);
+    *l1 = (void *)tci_read_label(tb_ptr);
+
+    check_size(start, tb_ptr);
+}
+
 static void tci_args_rr(const uint8_t **tb_ptr,
                         TCGReg *r0, TCGReg *r1)
 {
@@ -216,19 +226,6 @@ static void tci_args_rrs(const uint8_t **tb_ptr,
     check_size(start, tb_ptr);
 }
 
-static void tci_args_rrcl(const uint8_t **tb_ptr,
-                          TCGReg *r0, TCGReg *r1, TCGCond *c2, void **l3)
-{
-    const uint8_t *start = *tb_ptr;
-
-    *r0 = tci_read_r(tb_ptr);
-    *r1 = tci_read_r(tb_ptr);
-    *c2 = tci_read_b(tb_ptr);
-    *l3 = (void *)tci_read_label(tb_ptr);
-
-    check_size(start, tb_ptr);
-}
-
 static void tci_args_rrrc(const uint8_t **tb_ptr,
                           TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3)
 {
@@ -297,21 +294,6 @@ static void tci_args_rrrr(const uint8_t **tb_ptr,
     check_size(start, tb_ptr);
 }
 
-static void tci_args_rrrrcl(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
-                            TCGReg *r2, TCGReg *r3, TCGCond *c4, void **l5)
-{
-    const uint8_t *start = *tb_ptr;
-
-    *r0 = tci_read_r(tb_ptr);
-    *r1 = tci_read_r(tb_ptr);
-    *r2 = tci_read_r(tb_ptr);
-    *r3 = tci_read_r(tb_ptr);
-    *c4 = tci_read_b(tb_ptr);
-    *l5 = (void *)tci_read_label(tb_ptr);
-
-    check_size(start, tb_ptr);
-}
-
 static void tci_args_rrrrrc(const uint8_t **tb_ptr, TCGReg *r0, TCGReg *r1,
                             TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5)
 {
@@ -707,8 +689,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
             break;
 #endif
         case INDEX_op_brcond_i32:
-            tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
-            if (tci_compare32(regs[r0], regs[r1], condition)) {
+            tci_args_rl(&tb_ptr, &r0, &ptr);
+            if ((uint32_t)regs[r0]) {
                 tb_ptr = ptr;
             }
             break;
@@ -725,15 +707,6 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
             T2 = tci_uint64(regs[r5], regs[r4]);
             tci_write_reg64(regs, r1, r0, T1 - T2);
             break;
-        case INDEX_op_brcond2_i32:
-            tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &condition, &ptr);
-            T1 = tci_uint64(regs[r1], regs[r0]);
-            T2 = tci_uint64(regs[r3], regs[r2]);
-            if (tci_compare64(T1, T2, condition)) {
-                tb_ptr = ptr;
-                continue;
-            }
-            break;
         case INDEX_op_mulu2_i32:
             tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
             tci_write_reg64(regs, r1, r0, (uint64_t)regs[r2] * regs[r3]);
@@ -861,8 +834,8 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
             break;
 #endif
         case INDEX_op_brcond_i64:
-            tci_args_rrcl(&tb_ptr, &r0, &r1, &condition, &ptr);
-            if (tci_compare64(regs[r0], regs[r1], condition)) {
+            tci_args_rl(&tb_ptr, &r0, &ptr);
+            if (regs[r0]) {
                 tb_ptr = ptr;
             }
             break;
@@ -1173,9 +1146,9 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
 
     case INDEX_op_brcond_i32:
     case INDEX_op_brcond_i64:
-        tci_args_rrcl(&tb_ptr, &r0, &r1, &c, &ptr);
-        info->fprintf_func(info->stream, "%-12s  %s, %s, %s, %p",
-                           op_name, str_r(r0), str_r(r1), str_c(c), ptr);
+        tci_args_rl(&tb_ptr, &r0, &ptr);
+        info->fprintf_func(info->stream, "%-12s  %s, 0, ne, %p",
+                           op_name, str_r(r0), ptr);
         break;
 
     case INDEX_op_setcond_i32:
@@ -1300,13 +1273,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
                            str_r(r3), str_r(r4), str_c(c));
         break;
 
-    case INDEX_op_brcond2_i32:
-        tci_args_rrrrcl(&tb_ptr, &r0, &r1, &r2, &r3, &c, &ptr);
-        info->fprintf_func(info->stream, "%-12s  %s, %s, %s, %s, %s, %p",
-                           op_name, str_r(r0), str_r(r1),
-                           str_r(r2), str_r(r3), str_c(c), ptr);
-        break;
-
     case INDEX_op_mulu2_i32:
         tci_args_rrrr(&tb_ptr, &r0, &r1, &r2, &r3);
         info->fprintf_func(info->stream, "%-12s  %s, %s, %s, %s",
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index d80fec3488..4841787e5f 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -337,6 +337,17 @@ static void tcg_out_op_rI(TCGContext *s, TCGOpcode op,
 }
 #endif
 
+static void tcg_out_op_rl(TCGContext *s, TCGOpcode op, TCGReg r0, TCGLabel *l1)
+{
+    uint8_t *old_code_ptr = s->code_ptr;
+
+    tcg_out_op_t(s, op);
+    tcg_out_r(s, r0);
+    tci_out_label(s, l1);
+
+    old_code_ptr[1] = s->code_ptr - old_code_ptr;
+}
+
 static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1)
 {
     uint8_t *old_code_ptr = s->code_ptr;
@@ -388,20 +399,6 @@ static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op,
     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 }
 
-static void tcg_out_op_rrcl(TCGContext *s, TCGOpcode op,
-                            TCGReg r0, TCGReg r1, TCGCond c2, TCGLabel *l3)
-{
-    uint8_t *old_code_ptr = s->code_ptr;
-
-    tcg_out_op_t(s, op);
-    tcg_out_r(s, r0);
-    tcg_out_r(s, r1);
-    tcg_out8(s, c2);
-    tci_out_label(s, l3);
-
-    old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
 static void tcg_out_op_rrrc(TCGContext *s, TCGOpcode op,
                             TCGReg r0, TCGReg r1, TCGReg r2, TCGCond c3)
 {
@@ -475,23 +472,6 @@ static void tcg_out_op_rrrr(TCGContext *s, TCGOpcode op,
     old_code_ptr[1] = s->code_ptr - old_code_ptr;
 }
 
-static void tcg_out_op_rrrrcl(TCGContext *s, TCGOpcode op,
-                              TCGReg r0, TCGReg r1, TCGReg r2, TCGReg r3,
-                              TCGCond c4, TCGLabel *l5)
-{
-    uint8_t *old_code_ptr = s->code_ptr;
-
-    tcg_out_op_t(s, op);
-    tcg_out_r(s, r0);
-    tcg_out_r(s, r1);
-    tcg_out_r(s, r2);
-    tcg_out_r(s, r3);
-    tcg_out8(s, c4);
-    tci_out_label(s, l5);
-
-    old_code_ptr[1] = s->code_ptr - old_code_ptr;
-}
-
 static void tcg_out_op_rrrrrc(TCGContext *s, TCGOpcode op,
                               TCGReg r0, TCGReg r1, TCGReg r2,
                               TCGReg r3, TCGReg r4, TCGCond c5)
@@ -697,7 +677,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         break;
 
     CASE_32_64(brcond)
-        tcg_out_op_rrcl(s, opc, args[0], args[1], args[2], arg_label(args[3]));
+        tcg_out_op_rrrc(s, (opc == INDEX_op_brcond_i32
+                            ? INDEX_op_setcond_i32 : INDEX_op_setcond_i64),
+                        TCG_REG_TMP, args[0], args[1], args[2]);
+        tcg_out_op_rl(s, opc, TCG_REG_TMP, arg_label(args[3]));
         break;
 
     CASE_32_64(neg)      /* Optional (TCG_TARGET_HAS_neg_*). */
@@ -723,8 +706,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
                           args[3], args[4], args[5]);
         break;
     case INDEX_op_brcond2_i32:
-        tcg_out_op_rrrrcl(s, opc, args[0], args[1], args[2],
-                          args[3], args[4], arg_label(args[5]));
+        tcg_out_op_rrrrrc(s, INDEX_op_setcond2_i32, TCG_REG_TMP,
+                          args[0], args[1], args[2], args[3], args[4]);
+        tcg_out_op_rl(s, INDEX_op_brcond_i32, TCG_REG_TMP, arg_label(args[5]));
         break;
     case INDEX_op_mulu2_i32:
         tcg_out_op_rrrr(s, opc, args[0], args[1], args[2], args[3]);
-- 
2.25.1



  parent reply	other threads:[~2021-05-03  0:04 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-02 23:57 [PATCH v6 00/26] TCI fixes and cleanups Richard Henderson
2021-05-02 23:57 ` [PATCH v6 01/26] tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode Richard Henderson
2021-05-15  9:10   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 02/26] tcg: Add tcg_call_flags Richard Henderson
2021-05-03 21:39   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 03/26] accel/tcg/plugin-gen: Drop inline markers Richard Henderson
2021-05-03 21:40   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 04/26] plugins: Drop tcg_flags from struct qemu_plugin_dyn_cb Richard Henderson
2021-05-16 12:53   ` Philippe Mathieu-Daudé
2021-05-17 16:13     ` Richard Henderson
2021-05-02 23:57 ` [PATCH v6 05/26] accel/tcg: Add tcg call flags to plugins helpers Richard Henderson
2021-05-15  9:02   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 06/26] tcg: Store the TCGHelperInfo in the TCGOp for call Richard Henderson
2021-05-15  9:00   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 07/26] tcg: Add tcg_call_func Richard Henderson
2021-05-03 21:50   ` Philippe Mathieu-Daudé
2021-05-16  1:21     ` Richard Henderson
2021-05-16 12:48       ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 08/26] tcg: Build ffi data structures for helpers Richard Henderson
2021-05-31 18:55   ` Philippe Mathieu-Daudé
2021-06-01 14:33     ` Richard Henderson
2021-05-02 23:57 ` [PATCH v6 09/26] tcg/tci: Improve tcg_target_call_clobber_regs Richard Henderson
2021-05-02 23:57 ` [PATCH v6 10/26] tcg/tci: Move call-return regs to end of tcg_target_reg_alloc_order Richard Henderson
2021-05-15  9:01   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 11/26] tcg/tci: Use ffi for calls Richard Henderson
2021-06-01  5:18   ` Philippe Mathieu-Daudé
2021-06-01 14:38     ` Richard Henderson
2021-05-02 23:57 ` [PATCH v6 12/26] tcg/tci: Reserve r13 for a temporary Richard Henderson
2021-05-02 23:57 ` Richard Henderson [this message]
2021-05-02 23:57 ` [PATCH v6 14/26] tcg/tci: Remove tci_write_reg Richard Henderson
2021-05-03 21:53   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 15/26] tcg/tci: Change encoding to uint32_t units Richard Henderson
2021-05-02 23:57 ` [PATCH v6 16/26] tcg/tci: Implement goto_ptr Richard Henderson
2021-05-02 23:57 ` [PATCH v6 17/26] tcg/tci: Implement movcond Richard Henderson
2021-05-15  9:34   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 18/26] tcg/tci: Implement andc, orc, eqv, nand, nor Richard Henderson
2021-05-03 22:13   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 19/26] tcg/tci: Implement extract, sextract Richard Henderson
2021-05-03 22:04   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 20/26] tcg/tci: Implement clz, ctz, ctpop Richard Henderson
2021-05-03 22:10   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 21/26] tcg/tci: Implement mulu2, muls2 Richard Henderson
2021-05-02 23:57 ` [PATCH v6 22/26] tcg/tci: Implement add2, sub2 Richard Henderson
2021-05-02 23:57 ` [PATCH v6 23/26] tcg/tci: Split out tci_qemu_ld, tci_qemu_st Richard Henderson
2021-05-15  8:56   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 24/26] tests/tcg: Increase timeout for TCI Richard Henderson
2021-05-15  9:14   ` Philippe Mathieu-Daudé
2021-05-02 23:57 ` [PATCH v6 25/26] gitlab: Rename ACCEL_CONFIGURE_OPTS to EXTRA_CONFIGURE_OPTS Richard Henderson
2021-05-03 16:21   ` Willian Rampazzo
2021-05-02 23:57 ` [PATCH v6 26/26] gitlab: Enable cross-i386 builds of TCI Richard Henderson
2021-05-03 16:22   ` Willian Rampazzo
2021-05-03  0:30 ` [PATCH v6 00/26] TCI fixes and cleanups no-reply
2021-05-15 11:01 ` Philippe Mathieu-Daudé

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