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* [PATCH 0/2] QOMify Sifive UART model
@ 2021-05-04 15:34 ` Lukas Jünger
  0 siblings, 0 replies; 18+ messages in thread
From: Lukas Jünger @ 2021-05-04 15:34 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, bin.meng, mark.burton, marcandre.lureau, palmer,
	pbonzini, alistair.francis, Lukas Jünger, luc.michel

Hello,

This patch QOMifies the Sifive UART model.
It is split into two commits.
The first commit makes the sifive uart read and write function names
more consistent.
The second commit QOMifies the model.

Looking forward to hear from you,
Lukas

Lukas Jünger (2):
  Consistent function names for sifive uart read and write function
  QOMify sifive_uart model

 include/hw/char/sifive_uart.h |  6 +--
 hw/char/sifive_uart.c         | 84 ++++++++++++++++++++++++++++-------
 2 files changed, 71 insertions(+), 19 deletions(-)

-- 
2.30.2



^ permalink raw reply	[flat|nested] 18+ messages in thread
* [PATCH 0/2] QOMify Sifive UART model
@ 2021-05-04 15:34 ` Lukas Jünger
  0 siblings, 0 replies; 18+ messages in thread
From: Lukas Jünger @ 2021-05-04 15:34 UTC (permalink / raw)
  To: qemu-devel
  Cc: alistair.francis, bin.meng, palmer, qemu-riscv, marcandre.lureau,
	pbonzini, luc.michel, mark.burton, Lukas Jünger

Hello,

This patch QOMifies the Sifive UART model.
It is split into two commits.
The first commit makes the sifive uart read and write function names
more consistent.
The second commit QOMifies the model.

Looking forward to hear from you,
Lukas

Lukas Jünger (2):
  Consistent function names for sifive uart read and write function
  QOMify sifive_uart model

 include/hw/char/sifive_uart.h |  6 +--
 hw/char/sifive_uart.c         | 84 ++++++++++++++++++++++++++++-------
 2 files changed, 71 insertions(+), 19 deletions(-)

-- 
2.30.2



^ permalink raw reply	[flat|nested] 18+ messages in thread
* [PATCH 1/2] Consistent function names for sifive uart read and write function
  2021-05-04 15:34 ` Lukas Jünger
@ 2021-05-04 15:34   ` Lukas Jünger
  -1 siblings, 0 replies; 18+ messages in thread
From: Lukas Jünger @ 2021-05-04 15:34 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, bin.meng, mark.burton, marcandre.lureau, palmer,
	pbonzini, alistair.francis, Lukas Jünger, luc.michel

Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
---
 hw/char/sifive_uart.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index 3a00ba7f00..cb70374ead 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -65,7 +65,7 @@ static void update_irq(SiFiveUARTState *s)
 }
 
 static uint64_t
-uart_read(void *opaque, hwaddr addr, unsigned int size)
+sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
 {
     SiFiveUARTState *s = opaque;
     unsigned char r;
@@ -101,8 +101,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
 }
 
 static void
-uart_write(void *opaque, hwaddr addr,
-           uint64_t val64, unsigned int size)
+sifive_uart_write(void *opaque, hwaddr addr,
+                  uint64_t val64, unsigned int size)
 {
     SiFiveUARTState *s = opaque;
     uint32_t value = val64;
@@ -131,9 +131,9 @@ uart_write(void *opaque, hwaddr addr,
                   __func__, (int)addr, (int)value);
 }
 
-static const MemoryRegionOps uart_ops = {
-    .read = uart_read,
-    .write = uart_write,
+static const MemoryRegionOps sifive_uart_ops = {
+    .read = sifive_uart_read,
+    .write = sifive_uart_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
     .valid = {
         .min_access_size = 4,
@@ -187,7 +187,7 @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
     qemu_chr_fe_init(&s->chr, chr, &error_abort);
     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
         uart_be_change, s, NULL, true);
-    memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
+    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
                           TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
     memory_region_add_subregion(address_space, base, &s->mmio);
     return s;
-- 
2.30.2



^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [PATCH 1/2] Consistent function names for sifive uart read and write function
@ 2021-05-04 15:34   ` Lukas Jünger
  0 siblings, 0 replies; 18+ messages in thread
From: Lukas Jünger @ 2021-05-04 15:34 UTC (permalink / raw)
  To: qemu-devel
  Cc: alistair.francis, bin.meng, palmer, qemu-riscv, marcandre.lureau,
	pbonzini, luc.michel, mark.burton, Lukas Jünger

Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
---
 hw/char/sifive_uart.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index 3a00ba7f00..cb70374ead 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -65,7 +65,7 @@ static void update_irq(SiFiveUARTState *s)
 }
 
 static uint64_t
-uart_read(void *opaque, hwaddr addr, unsigned int size)
+sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
 {
     SiFiveUARTState *s = opaque;
     unsigned char r;
@@ -101,8 +101,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
 }
 
 static void
-uart_write(void *opaque, hwaddr addr,
-           uint64_t val64, unsigned int size)
+sifive_uart_write(void *opaque, hwaddr addr,
+                  uint64_t val64, unsigned int size)
 {
     SiFiveUARTState *s = opaque;
     uint32_t value = val64;
@@ -131,9 +131,9 @@ uart_write(void *opaque, hwaddr addr,
                   __func__, (int)addr, (int)value);
 }
 
-static const MemoryRegionOps uart_ops = {
-    .read = uart_read,
-    .write = uart_write,
+static const MemoryRegionOps sifive_uart_ops = {
+    .read = sifive_uart_read,
+    .write = sifive_uart_write,
     .endianness = DEVICE_NATIVE_ENDIAN,
     .valid = {
         .min_access_size = 4,
@@ -187,7 +187,7 @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
     qemu_chr_fe_init(&s->chr, chr, &error_abort);
     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
         uart_be_change, s, NULL, true);
-    memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
+    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
                           TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
     memory_region_add_subregion(address_space, base, &s->mmio);
     return s;
-- 
2.30.2



^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [PATCH 2/2] QOMify sifive_uart model
  2021-05-04 15:34 ` Lukas Jünger
@ 2021-05-04 15:34   ` Lukas Jünger
  -1 siblings, 0 replies; 18+ messages in thread
From: Lukas Jünger @ 2021-05-04 15:34 UTC (permalink / raw)
  To: qemu-devel
  Cc: qemu-riscv, bin.meng, mark.burton, marcandre.lureau, palmer,
	pbonzini, alistair.francis, Lukas Jünger, luc.michel

Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
---
 include/hw/char/sifive_uart.h |  6 +--
 hw/char/sifive_uart.c         | 72 ++++++++++++++++++++++++++++++-----
 2 files changed, 65 insertions(+), 13 deletions(-)

diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
index 3e962be659..45d66b1db5 100644
--- a/include/hw/char/sifive_uart.h
+++ b/include/hw/char/sifive_uart.h
@@ -21,6 +21,7 @@
 #define HW_SIFIVE_UART_H
 
 #include "chardev/char-fe.h"
+#include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
 #include "qom/object.h"
 
@@ -51,10 +52,7 @@ enum {
 #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
 
 #define TYPE_SIFIVE_UART "riscv.sifive.uart"
-
-typedef struct SiFiveUARTState SiFiveUARTState;
-DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
-                         TYPE_SIFIVE_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
 
 struct SiFiveUARTState {
     /*< private >*/
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index cb70374ead..0307568d0a 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -25,6 +25,7 @@
 #include "hw/hw.h"
 #include "hw/irq.h"
 #include "hw/char/sifive_uart.h"
+#include "hw/qdev-properties-system.h"
 
 /*
  * Not yet implemented:
@@ -176,19 +177,72 @@ static int uart_be_change(void *opaque)
     return 0;
 }
 
+static Property sifive_uart_properties[] = {
+    DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sifive_uart_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    SiFiveUARTState *s = SIFIVE_UART(obj);
+
+    memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
+                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
+    sysbus_init_mmio(sbd, &s->mmio);
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static void sifive_uart_realize(DeviceState *dev, Error **errp)
+{
+    SiFiveUARTState *s = SIFIVE_UART(dev);
+
+    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
+                             uart_be_change, s, NULL, true);
+
+}
+
+static void sifive_uart_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = sifive_uart_realize;
+    device_class_set_props(dc, sifive_uart_properties);
+}
+
+static const TypeInfo sifive_uart_info = {
+    .name          = TYPE_SIFIVE_UART,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(SiFiveUARTState),
+    .instance_init = sifive_uart_init,
+    .class_init    = sifive_uart_class_init,
+};
+
+static void sifive_uart_register_types(void)
+{
+    type_register_static(&sifive_uart_info);
+}
+
+type_init(sifive_uart_register_types)
+
 /*
  * Create UART device.
  */
 SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
     Chardev *chr, qemu_irq irq)
 {
-    SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
-    s->irq = irq;
-    qemu_chr_fe_init(&s->chr, chr, &error_abort);
-    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
-        uart_be_change, s, NULL, true);
-    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
-                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
-    memory_region_add_subregion(address_space, base, &s->mmio);
-    return s;
+    DeviceState *dev;
+    SysBusDevice *s;
+    SiFiveUARTState *r;
+
+    dev = qdev_new("riscv.sifive.uart");
+    s = SYS_BUS_DEVICE(dev);
+    qdev_prop_set_chr(dev, "chardev", chr);
+    sysbus_realize_and_unref(s, &error_fatal);
+    memory_region_add_subregion(address_space, base,
+                                sysbus_mmio_get_region(s, 0));
+    sysbus_connect_irq(s, 0, irq);
+
+    r = SIFIVE_UART(dev);
+    return r;
 }
-- 
2.30.2



^ permalink raw reply related	[flat|nested] 18+ messages in thread
* [PATCH 2/2] QOMify sifive_uart model
@ 2021-05-04 15:34   ` Lukas Jünger
  0 siblings, 0 replies; 18+ messages in thread
From: Lukas Jünger @ 2021-05-04 15:34 UTC (permalink / raw)
  To: qemu-devel
  Cc: alistair.francis, bin.meng, palmer, qemu-riscv, marcandre.lureau,
	pbonzini, luc.michel, mark.burton, Lukas Jünger

Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
---
 include/hw/char/sifive_uart.h |  6 +--
 hw/char/sifive_uart.c         | 72 ++++++++++++++++++++++++++++++-----
 2 files changed, 65 insertions(+), 13 deletions(-)

diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
index 3e962be659..45d66b1db5 100644
--- a/include/hw/char/sifive_uart.h
+++ b/include/hw/char/sifive_uart.h
@@ -21,6 +21,7 @@
 #define HW_SIFIVE_UART_H
 
 #include "chardev/char-fe.h"
+#include "hw/qdev-properties.h"
 #include "hw/sysbus.h"
 #include "qom/object.h"
 
@@ -51,10 +52,7 @@ enum {
 #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
 
 #define TYPE_SIFIVE_UART "riscv.sifive.uart"
-
-typedef struct SiFiveUARTState SiFiveUARTState;
-DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
-                         TYPE_SIFIVE_UART)
+OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
 
 struct SiFiveUARTState {
     /*< private >*/
diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
index cb70374ead..0307568d0a 100644
--- a/hw/char/sifive_uart.c
+++ b/hw/char/sifive_uart.c
@@ -25,6 +25,7 @@
 #include "hw/hw.h"
 #include "hw/irq.h"
 #include "hw/char/sifive_uart.h"
+#include "hw/qdev-properties-system.h"
 
 /*
  * Not yet implemented:
@@ -176,19 +177,72 @@ static int uart_be_change(void *opaque)
     return 0;
 }
 
+static Property sifive_uart_properties[] = {
+    DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void sifive_uart_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    SiFiveUARTState *s = SIFIVE_UART(obj);
+
+    memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
+                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
+    sysbus_init_mmio(sbd, &s->mmio);
+    sysbus_init_irq(sbd, &s->irq);
+}
+
+static void sifive_uart_realize(DeviceState *dev, Error **errp)
+{
+    SiFiveUARTState *s = SIFIVE_UART(dev);
+
+    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
+                             uart_be_change, s, NULL, true);
+
+}
+
+static void sifive_uart_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = sifive_uart_realize;
+    device_class_set_props(dc, sifive_uart_properties);
+}
+
+static const TypeInfo sifive_uart_info = {
+    .name          = TYPE_SIFIVE_UART,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(SiFiveUARTState),
+    .instance_init = sifive_uart_init,
+    .class_init    = sifive_uart_class_init,
+};
+
+static void sifive_uart_register_types(void)
+{
+    type_register_static(&sifive_uart_info);
+}
+
+type_init(sifive_uart_register_types)
+
 /*
  * Create UART device.
  */
 SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
     Chardev *chr, qemu_irq irq)
 {
-    SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
-    s->irq = irq;
-    qemu_chr_fe_init(&s->chr, chr, &error_abort);
-    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
-        uart_be_change, s, NULL, true);
-    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
-                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
-    memory_region_add_subregion(address_space, base, &s->mmio);
-    return s;
+    DeviceState *dev;
+    SysBusDevice *s;
+    SiFiveUARTState *r;
+
+    dev = qdev_new("riscv.sifive.uart");
+    s = SYS_BUS_DEVICE(dev);
+    qdev_prop_set_chr(dev, "chardev", chr);
+    sysbus_realize_and_unref(s, &error_fatal);
+    memory_region_add_subregion(address_space, base,
+                                sysbus_mmio_get_region(s, 0));
+    sysbus_connect_irq(s, 0, irq);
+
+    r = SIFIVE_UART(dev);
+    return r;
 }
-- 
2.30.2



^ permalink raw reply related	[flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] Consistent function names for sifive uart read and write function
  2021-05-04 15:34   ` Lukas Jünger
@ 2021-05-06  2:12     ` Alistair Francis
  -1 siblings, 0 replies; 18+ messages in thread
From: Alistair Francis @ 2021-05-06  2:12 UTC (permalink / raw)
  To: Lukas Jünger
  Cc: Alistair Francis, open list:RISC-V, Bin Meng, Mark Burton,
	qemu-devel@nongnu.org Developers, Palmer Dabbelt, Paolo Bonzini,
	Marc-André Lureau, Luc Michel

On Wed, May 5, 2021 at 2:50 AM Lukas Jünger <lukas.juenger@greensocs.com> wrote:
>
> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/char/sifive_uart.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index 3a00ba7f00..cb70374ead 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -65,7 +65,7 @@ static void update_irq(SiFiveUARTState *s)
>  }
>
>  static uint64_t
> -uart_read(void *opaque, hwaddr addr, unsigned int size)
> +sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
>  {
>      SiFiveUARTState *s = opaque;
>      unsigned char r;
> @@ -101,8 +101,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
>  }
>
>  static void
> -uart_write(void *opaque, hwaddr addr,
> -           uint64_t val64, unsigned int size)
> +sifive_uart_write(void *opaque, hwaddr addr,
> +                  uint64_t val64, unsigned int size)
>  {
>      SiFiveUARTState *s = opaque;
>      uint32_t value = val64;
> @@ -131,9 +131,9 @@ uart_write(void *opaque, hwaddr addr,
>                    __func__, (int)addr, (int)value);
>  }
>
> -static const MemoryRegionOps uart_ops = {
> -    .read = uart_read,
> -    .write = uart_write,
> +static const MemoryRegionOps sifive_uart_ops = {
> +    .read = sifive_uart_read,
> +    .write = sifive_uart_write,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>      .valid = {
>          .min_access_size = 4,
> @@ -187,7 +187,7 @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
>      qemu_chr_fe_init(&s->chr, chr, &error_abort);
>      qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
>          uart_be_change, s, NULL, true);
> -    memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
> +    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
>                            TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
>      memory_region_add_subregion(address_space, base, &s->mmio);
>      return s;
> --
> 2.30.2
>
>


^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] Consistent function names for sifive uart read and write function
@ 2021-05-06  2:12     ` Alistair Francis
  0 siblings, 0 replies; 18+ messages in thread
From: Alistair Francis @ 2021-05-06  2:12 UTC (permalink / raw)
  To: Lukas Jünger
  Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
	Mark Burton, Marc-André Lureau, Palmer Dabbelt,
	Paolo Bonzini, Alistair Francis, Luc Michel

On Wed, May 5, 2021 at 2:50 AM Lukas Jünger <lukas.juenger@greensocs.com> wrote:
>
> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/char/sifive_uart.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index 3a00ba7f00..cb70374ead 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -65,7 +65,7 @@ static void update_irq(SiFiveUARTState *s)
>  }
>
>  static uint64_t
> -uart_read(void *opaque, hwaddr addr, unsigned int size)
> +sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
>  {
>      SiFiveUARTState *s = opaque;
>      unsigned char r;
> @@ -101,8 +101,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
>  }
>
>  static void
> -uart_write(void *opaque, hwaddr addr,
> -           uint64_t val64, unsigned int size)
> +sifive_uart_write(void *opaque, hwaddr addr,
> +                  uint64_t val64, unsigned int size)
>  {
>      SiFiveUARTState *s = opaque;
>      uint32_t value = val64;
> @@ -131,9 +131,9 @@ uart_write(void *opaque, hwaddr addr,
>                    __func__, (int)addr, (int)value);
>  }
>
> -static const MemoryRegionOps uart_ops = {
> -    .read = uart_read,
> -    .write = uart_write,
> +static const MemoryRegionOps sifive_uart_ops = {
> +    .read = sifive_uart_read,
> +    .write = sifive_uart_write,
>      .endianness = DEVICE_NATIVE_ENDIAN,
>      .valid = {
>          .min_access_size = 4,
> @@ -187,7 +187,7 @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
>      qemu_chr_fe_init(&s->chr, chr, &error_abort);
>      qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
>          uart_be_change, s, NULL, true);
> -    memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
> +    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
>                            TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
>      memory_region_add_subregion(address_space, base, &s->mmio);
>      return s;
> --
> 2.30.2
>
>


^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] Consistent function names for sifive uart read and write function
  2021-05-04 15:34   ` Lukas Jünger
@ 2021-05-11 11:38     ` Luc Michel
  -1 siblings, 0 replies; 18+ messages in thread
From: Luc Michel @ 2021-05-11 11:38 UTC (permalink / raw)
  To: Lukas Jünger, qemu-devel
  Cc: qemu-riscv, bin.meng, mark.burton, marcandre.lureau, palmer,
	pbonzini, alistair.francis

On 5/4/21 5:34 PM, Lukas Jünger wrote:
> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>   hw/char/sifive_uart.c | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index 3a00ba7f00..cb70374ead 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -65,7 +65,7 @@ static void update_irq(SiFiveUARTState *s)
>   }
>   
>   static uint64_t
> -uart_read(void *opaque, hwaddr addr, unsigned int size)
> +sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
>   {
>       SiFiveUARTState *s = opaque;
>       unsigned char r;
> @@ -101,8 +101,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
>   }
>   
>   static void
> -uart_write(void *opaque, hwaddr addr,
> -           uint64_t val64, unsigned int size)
> +sifive_uart_write(void *opaque, hwaddr addr,
> +                  uint64_t val64, unsigned int size)
>   {
>       SiFiveUARTState *s = opaque;
>       uint32_t value = val64;
> @@ -131,9 +131,9 @@ uart_write(void *opaque, hwaddr addr,
>                     __func__, (int)addr, (int)value);
>   }
>   
> -static const MemoryRegionOps uart_ops = {
> -    .read = uart_read,
> -    .write = uart_write,
> +static const MemoryRegionOps sifive_uart_ops = {
> +    .read = sifive_uart_read,
> +    .write = sifive_uart_write,
>       .endianness = DEVICE_NATIVE_ENDIAN,
>       .valid = {
>           .min_access_size = 4,
> @@ -187,7 +187,7 @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
>       qemu_chr_fe_init(&s->chr, chr, &error_abort);
>       qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
>           uart_be_change, s, NULL, true);
> -    memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
> +    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
>                             TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
>       memory_region_add_subregion(address_space, base, &s->mmio);
>       return s;
> 


^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] Consistent function names for sifive uart read and write function
@ 2021-05-11 11:38     ` Luc Michel
  0 siblings, 0 replies; 18+ messages in thread
From: Luc Michel @ 2021-05-11 11:38 UTC (permalink / raw)
  To: Lukas Jünger, qemu-devel
  Cc: alistair.francis, bin.meng, palmer, qemu-riscv, marcandre.lureau,
	pbonzini, mark.burton

On 5/4/21 5:34 PM, Lukas Jünger wrote:
> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>   hw/char/sifive_uart.c | 14 +++++++-------
>   1 file changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index 3a00ba7f00..cb70374ead 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -65,7 +65,7 @@ static void update_irq(SiFiveUARTState *s)
>   }
>   
>   static uint64_t
> -uart_read(void *opaque, hwaddr addr, unsigned int size)
> +sifive_uart_read(void *opaque, hwaddr addr, unsigned int size)
>   {
>       SiFiveUARTState *s = opaque;
>       unsigned char r;
> @@ -101,8 +101,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
>   }
>   
>   static void
> -uart_write(void *opaque, hwaddr addr,
> -           uint64_t val64, unsigned int size)
> +sifive_uart_write(void *opaque, hwaddr addr,
> +                  uint64_t val64, unsigned int size)
>   {
>       SiFiveUARTState *s = opaque;
>       uint32_t value = val64;
> @@ -131,9 +131,9 @@ uart_write(void *opaque, hwaddr addr,
>                     __func__, (int)addr, (int)value);
>   }
>   
> -static const MemoryRegionOps uart_ops = {
> -    .read = uart_read,
> -    .write = uart_write,
> +static const MemoryRegionOps sifive_uart_ops = {
> +    .read = sifive_uart_read,
> +    .write = sifive_uart_write,
>       .endianness = DEVICE_NATIVE_ENDIAN,
>       .valid = {
>           .min_access_size = 4,
> @@ -187,7 +187,7 @@ SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
>       qemu_chr_fe_init(&s->chr, chr, &error_abort);
>       qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
>           uart_be_change, s, NULL, true);
> -    memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
> +    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
>                             TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
>       memory_region_add_subregion(address_space, base, &s->mmio);
>       return s;
> 


^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH 2/2] QOMify sifive_uart model
  2021-05-04 15:34   ` Lukas Jünger
@ 2021-05-11 11:39     ` Luc Michel
  -1 siblings, 0 replies; 18+ messages in thread
From: Luc Michel @ 2021-05-11 11:39 UTC (permalink / raw)
  To: Lukas Jünger, qemu-devel
  Cc: qemu-riscv, bin.meng, mark.burton, marcandre.lureau, palmer,
	pbonzini, alistair.francis

On 5/4/21 5:34 PM, Lukas Jünger wrote:
> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>   include/hw/char/sifive_uart.h |  6 +--
>   hw/char/sifive_uart.c         | 72 ++++++++++++++++++++++++++++++-----
>   2 files changed, 65 insertions(+), 13 deletions(-)
> 
> diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
> index 3e962be659..45d66b1db5 100644
> --- a/include/hw/char/sifive_uart.h
> +++ b/include/hw/char/sifive_uart.h
> @@ -21,6 +21,7 @@
>   #define HW_SIFIVE_UART_H
>   
>   #include "chardev/char-fe.h"
> +#include "hw/qdev-properties.h"
>   #include "hw/sysbus.h"
>   #include "qom/object.h"
>   
> @@ -51,10 +52,7 @@ enum {
>   #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
>   
>   #define TYPE_SIFIVE_UART "riscv.sifive.uart"
> -
> -typedef struct SiFiveUARTState SiFiveUARTState;
> -DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
> -                         TYPE_SIFIVE_UART)
> +OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
>   
>   struct SiFiveUARTState {
>       /*< private >*/
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index cb70374ead..0307568d0a 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -25,6 +25,7 @@
>   #include "hw/hw.h"
>   #include "hw/irq.h"
>   #include "hw/char/sifive_uart.h"
> +#include "hw/qdev-properties-system.h"
>   
>   /*
>    * Not yet implemented:
> @@ -176,19 +177,72 @@ static int uart_be_change(void *opaque)
>       return 0;
>   }
>   
> +static Property sifive_uart_properties[] = {
> +    DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void sifive_uart_init(Object *obj)
> +{
> +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> +    SiFiveUARTState *s = SIFIVE_UART(obj);
> +
> +    memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
> +                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
> +    sysbus_init_mmio(sbd, &s->mmio);
> +    sysbus_init_irq(sbd, &s->irq);
> +}
> +
> +static void sifive_uart_realize(DeviceState *dev, Error **errp)
> +{
> +    SiFiveUARTState *s = SIFIVE_UART(dev);
> +
> +    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
> +                             uart_be_change, s, NULL, true);
> +
> +}
> +
> +static void sifive_uart_class_init(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +
> +    dc->realize = sifive_uart_realize;
> +    device_class_set_props(dc, sifive_uart_properties);
> +}
> +
> +static const TypeInfo sifive_uart_info = {
> +    .name          = TYPE_SIFIVE_UART,
> +    .parent        = TYPE_SYS_BUS_DEVICE,
> +    .instance_size = sizeof(SiFiveUARTState),
> +    .instance_init = sifive_uart_init,
> +    .class_init    = sifive_uart_class_init,
> +};
> +
> +static void sifive_uart_register_types(void)
> +{
> +    type_register_static(&sifive_uart_info);
> +}
> +
> +type_init(sifive_uart_register_types)
> +
>   /*
>    * Create UART device.
>    */
>   SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
>       Chardev *chr, qemu_irq irq)
>   {
> -    SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
> -    s->irq = irq;
> -    qemu_chr_fe_init(&s->chr, chr, &error_abort);
> -    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
> -        uart_be_change, s, NULL, true);
> -    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
> -                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
> -    memory_region_add_subregion(address_space, base, &s->mmio);
> -    return s;
> +    DeviceState *dev;
> +    SysBusDevice *s;
> +    SiFiveUARTState *r;
> +
> +    dev = qdev_new("riscv.sifive.uart");
> +    s = SYS_BUS_DEVICE(dev);
> +    qdev_prop_set_chr(dev, "chardev", chr);
> +    sysbus_realize_and_unref(s, &error_fatal);
> +    memory_region_add_subregion(address_space, base,
> +                                sysbus_mmio_get_region(s, 0));
> +    sysbus_connect_irq(s, 0, irq);
> +
> +    r = SIFIVE_UART(dev);
> +    return r;
>   }
> 


^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH 2/2] QOMify sifive_uart model
@ 2021-05-11 11:39     ` Luc Michel
  0 siblings, 0 replies; 18+ messages in thread
From: Luc Michel @ 2021-05-11 11:39 UTC (permalink / raw)
  To: Lukas Jünger, qemu-devel
  Cc: alistair.francis, bin.meng, palmer, qemu-riscv, marcandre.lureau,
	pbonzini, mark.burton

On 5/4/21 5:34 PM, Lukas Jünger wrote:
> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>   include/hw/char/sifive_uart.h |  6 +--
>   hw/char/sifive_uart.c         | 72 ++++++++++++++++++++++++++++++-----
>   2 files changed, 65 insertions(+), 13 deletions(-)
> 
> diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h
> index 3e962be659..45d66b1db5 100644
> --- a/include/hw/char/sifive_uart.h
> +++ b/include/hw/char/sifive_uart.h
> @@ -21,6 +21,7 @@
>   #define HW_SIFIVE_UART_H
>   
>   #include "chardev/char-fe.h"
> +#include "hw/qdev-properties.h"
>   #include "hw/sysbus.h"
>   #include "qom/object.h"
>   
> @@ -51,10 +52,7 @@ enum {
>   #define SIFIVE_UART_GET_RXCNT(rxctrl)   ((rxctrl >> 16) & 0x7)
>   
>   #define TYPE_SIFIVE_UART "riscv.sifive.uart"
> -
> -typedef struct SiFiveUARTState SiFiveUARTState;
> -DECLARE_INSTANCE_CHECKER(SiFiveUARTState, SIFIVE_UART,
> -                         TYPE_SIFIVE_UART)
> +OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART)
>   
>   struct SiFiveUARTState {
>       /*< private >*/
> diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c
> index cb70374ead..0307568d0a 100644
> --- a/hw/char/sifive_uart.c
> +++ b/hw/char/sifive_uart.c
> @@ -25,6 +25,7 @@
>   #include "hw/hw.h"
>   #include "hw/irq.h"
>   #include "hw/char/sifive_uart.h"
> +#include "hw/qdev-properties-system.h"
>   
>   /*
>    * Not yet implemented:
> @@ -176,19 +177,72 @@ static int uart_be_change(void *opaque)
>       return 0;
>   }
>   
> +static Property sifive_uart_properties[] = {
> +    DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void sifive_uart_init(Object *obj)
> +{
> +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> +    SiFiveUARTState *s = SIFIVE_UART(obj);
> +
> +    memory_region_init_io(&s->mmio, OBJECT(s), &sifive_uart_ops, s,
> +                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
> +    sysbus_init_mmio(sbd, &s->mmio);
> +    sysbus_init_irq(sbd, &s->irq);
> +}
> +
> +static void sifive_uart_realize(DeviceState *dev, Error **errp)
> +{
> +    SiFiveUARTState *s = SIFIVE_UART(dev);
> +
> +    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
> +                             uart_be_change, s, NULL, true);
> +
> +}
> +
> +static void sifive_uart_class_init(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +
> +    dc->realize = sifive_uart_realize;
> +    device_class_set_props(dc, sifive_uart_properties);
> +}
> +
> +static const TypeInfo sifive_uart_info = {
> +    .name          = TYPE_SIFIVE_UART,
> +    .parent        = TYPE_SYS_BUS_DEVICE,
> +    .instance_size = sizeof(SiFiveUARTState),
> +    .instance_init = sifive_uart_init,
> +    .class_init    = sifive_uart_class_init,
> +};
> +
> +static void sifive_uart_register_types(void)
> +{
> +    type_register_static(&sifive_uart_info);
> +}
> +
> +type_init(sifive_uart_register_types)
> +
>   /*
>    * Create UART device.
>    */
>   SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
>       Chardev *chr, qemu_irq irq)
>   {
> -    SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
> -    s->irq = irq;
> -    qemu_chr_fe_init(&s->chr, chr, &error_abort);
> -    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
> -        uart_be_change, s, NULL, true);
> -    memory_region_init_io(&s->mmio, NULL, &sifive_uart_ops, s,
> -                          TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
> -    memory_region_add_subregion(address_space, base, &s->mmio);
> -    return s;
> +    DeviceState *dev;
> +    SysBusDevice *s;
> +    SiFiveUARTState *r;
> +
> +    dev = qdev_new("riscv.sifive.uart");
> +    s = SYS_BUS_DEVICE(dev);
> +    qdev_prop_set_chr(dev, "chardev", chr);
> +    sysbus_realize_and_unref(s, &error_fatal);
> +    memory_region_add_subregion(address_space, base,
> +                                sysbus_mmio_get_region(s, 0));
> +    sysbus_connect_irq(s, 0, irq);
> +
> +    r = SIFIVE_UART(dev);
> +    return r;
>   }
> 


^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH 2/2] QOMify sifive_uart model
  2021-05-04 15:34   ` Lukas Jünger
@ 2021-05-11 12:26     ` Philippe Mathieu-Daudé
  -1 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-11 12:26 UTC (permalink / raw)
  To: Lukas Jünger, qemu-devel
  Cc: alistair.francis, qemu-riscv, bin.meng, mark.burton, palmer,
	marcandre.lureau, pbonzini, luc.michel

Hi Lukas,

On 5/4/21 5:34 PM, Lukas Jünger wrote:
> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
> ---
>  include/hw/char/sifive_uart.h |  6 +--
>  hw/char/sifive_uart.c         | 72 ++++++++++++++++++++++++++++++-----
>  2 files changed, 65 insertions(+), 13 deletions(-)

> +static void sifive_uart_realize(DeviceState *dev, Error **errp)
> +{
> +    SiFiveUARTState *s = SIFIVE_UART(dev);
> +
> +    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
> +                             uart_be_change, s, NULL, true);
> +
> +}
> +
> +static void sifive_uart_class_init(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +
> +    dc->realize = sifive_uart_realize;
> +    device_class_set_props(dc, sifive_uart_properties);
> +}

You forgot to add the migration fields (VMState) of the SiFiveUARTState
structure. You might want to convert to the Fifo8 API (like the
SiFiveSPIState does) previous to this patch.

Regards,

Phil.


^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH 2/2] QOMify sifive_uart model
@ 2021-05-11 12:26     ` Philippe Mathieu-Daudé
  0 siblings, 0 replies; 18+ messages in thread
From: Philippe Mathieu-Daudé @ 2021-05-11 12:26 UTC (permalink / raw)
  To: Lukas Jünger, qemu-devel
  Cc: qemu-riscv, bin.meng, mark.burton, marcandre.lureau, palmer,
	pbonzini, alistair.francis, luc.michel

Hi Lukas,

On 5/4/21 5:34 PM, Lukas Jünger wrote:
> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
> ---
>  include/hw/char/sifive_uart.h |  6 +--
>  hw/char/sifive_uart.c         | 72 ++++++++++++++++++++++++++++++-----
>  2 files changed, 65 insertions(+), 13 deletions(-)

> +static void sifive_uart_realize(DeviceState *dev, Error **errp)
> +{
> +    SiFiveUARTState *s = SIFIVE_UART(dev);
> +
> +    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
> +                             uart_be_change, s, NULL, true);
> +
> +}
> +
> +static void sifive_uart_class_init(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +
> +    dc->realize = sifive_uart_realize;
> +    device_class_set_props(dc, sifive_uart_properties);
> +}

You forgot to add the migration fields (VMState) of the SiFiveUARTState
structure. You might want to convert to the Fifo8 API (like the
SiFiveSPIState does) previous to this patch.

Regards,

Phil.


^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] Consistent function names for sifive uart read and write function
  2021-05-04 15:34   ` Lukas Jünger
@ 2021-05-11 13:06     ` Bin Meng
  -1 siblings, 0 replies; 18+ messages in thread
From: Bin Meng @ 2021-05-11 13:06 UTC (permalink / raw)
  To: Lukas Jünger
  Cc: Alistair Francis, open list:RISC-V, Bin Meng, mark.burton,
	qemu-devel@nongnu.org Developers, Palmer Dabbelt, Paolo Bonzini,
	Marc-André Lureau, luc.michel

Hi Lukas,

On Wed, May 5, 2021 at 12:49 AM Lukas Jünger
<lukas.juenger@greensocs.com> wrote:
>

While we are here, could we make other functions sifive_ prefixed?

Also the commit title should include a tag of "hw/char: sifive_uart"

> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
> ---
>  hw/char/sifive_uart.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>

Regards,
Bin


^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] Consistent function names for sifive uart read and write function
@ 2021-05-11 13:06     ` Bin Meng
  0 siblings, 0 replies; 18+ messages in thread
From: Bin Meng @ 2021-05-11 13:06 UTC (permalink / raw)
  To: Lukas Jünger
  Cc: qemu-devel@nongnu.org Developers, open list:RISC-V, Bin Meng,
	mark.burton, Marc-André Lureau, Palmer Dabbelt,
	Paolo Bonzini, Alistair Francis, luc.michel

Hi Lukas,

On Wed, May 5, 2021 at 12:49 AM Lukas Jünger
<lukas.juenger@greensocs.com> wrote:
>

While we are here, could we make other functions sifive_ prefixed?

Also the commit title should include a tag of "hw/char: sifive_uart"

> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
> ---
>  hw/char/sifive_uart.c | 14 +++++++-------
>  1 file changed, 7 insertions(+), 7 deletions(-)
>

Regards,
Bin


^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH 2/2] QOMify sifive_uart model
  2021-05-11 12:26     ` Philippe Mathieu-Daudé
@ 2021-05-16 11:13       ` Lukas Jünger
  -1 siblings, 0 replies; 18+ messages in thread
From: Lukas Jünger @ 2021-05-16 11:13 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, Lukas Jünger, qemu-devel
  Cc: alistair.francis, qemu-riscv, bin.meng, mark.burton, palmer,
	marcandre.lureau, pbonzini, luc.michel

On 5/11/21 2:26 PM, Philippe Mathieu-Daudé wrote:
> Hi Lukas,
>
> On 5/4/21 5:34 PM, Lukas Jünger wrote:
>> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
>> ---
>>   include/hw/char/sifive_uart.h |  6 +--
>>   hw/char/sifive_uart.c         | 72 ++++++++++++++++++++++++++++++-----
>>   2 files changed, 65 insertions(+), 13 deletions(-)
>> +static void sifive_uart_realize(DeviceState *dev, Error **errp)
>> +{
>> +    SiFiveUARTState *s = SIFIVE_UART(dev);
>> +
>> +    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
>> +                             uart_be_change, s, NULL, true);
>> +
>> +}
>> +
>> +static void sifive_uart_class_init(ObjectClass *oc, void *data)
>> +{
>> +    DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> +    dc->realize = sifive_uart_realize;
>> +    device_class_set_props(dc, sifive_uart_properties);
>> +}
> You forgot to add the migration fields (VMState) of the SiFiveUARTState
> structure. You might want to convert to the Fifo8 API (like the
> SiFiveSPIState does) previous to this patch.
>
> Regards,
>
> Phil.

Thank you for your feedback. If I understand correctly, sifive_spi does 
not support migration currently. Would it be possible to merge this 
QOMification without the migration feature for now, as not all devices 
in sifive_u support it at the moment anyways? It seems it would be 
difficult to test on my end.

Best regards,

Lukas



^ permalink raw reply	[flat|nested] 18+ messages in thread
* Re: [PATCH 2/2] QOMify sifive_uart model
@ 2021-05-16 11:13       ` Lukas Jünger
  0 siblings, 0 replies; 18+ messages in thread
From: Lukas Jünger @ 2021-05-16 11:13 UTC (permalink / raw)
  To: Philippe Mathieu-Daudé, Lukas Jünger, qemu-devel
  Cc: qemu-riscv, bin.meng, mark.burton, marcandre.lureau, palmer,
	pbonzini, alistair.francis, luc.michel

On 5/11/21 2:26 PM, Philippe Mathieu-Daudé wrote:
> Hi Lukas,
>
> On 5/4/21 5:34 PM, Lukas Jünger wrote:
>> Signed-off-by: Lukas Jünger <lukas.juenger@greensocs.com>
>> ---
>>   include/hw/char/sifive_uart.h |  6 +--
>>   hw/char/sifive_uart.c         | 72 ++++++++++++++++++++++++++++++-----
>>   2 files changed, 65 insertions(+), 13 deletions(-)
>> +static void sifive_uart_realize(DeviceState *dev, Error **errp)
>> +{
>> +    SiFiveUARTState *s = SIFIVE_UART(dev);
>> +
>> +    qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
>> +                             uart_be_change, s, NULL, true);
>> +
>> +}
>> +
>> +static void sifive_uart_class_init(ObjectClass *oc, void *data)
>> +{
>> +    DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> +    dc->realize = sifive_uart_realize;
>> +    device_class_set_props(dc, sifive_uart_properties);
>> +}
> You forgot to add the migration fields (VMState) of the SiFiveUARTState
> structure. You might want to convert to the Fifo8 API (like the
> SiFiveSPIState does) previous to this patch.
>
> Regards,
>
> Phil.

Thank you for your feedback. If I understand correctly, sifive_spi does 
not support migration currently. Would it be possible to merge this 
QOMification without the migration feature for now, as not all devices 
in sifive_u support it at the moment anyways? It seems it would be 
difficult to test on my end.

Best regards,

Lukas



^ permalink raw reply	[flat|nested] 18+ messages in thread
end of thread, other threads:[~2021-05-16 14:05 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-04 15:34 [PATCH 0/2] QOMify Sifive UART model Lukas Jünger
2021-05-04 15:34 ` Lukas Jünger
2021-05-04 15:34 ` [PATCH 1/2] Consistent function names for sifive uart read and write function Lukas Jünger
2021-05-04 15:34   ` Lukas Jünger
2021-05-06  2:12   ` Alistair Francis
2021-05-06  2:12     ` Alistair Francis
2021-05-11 11:38   ` Luc Michel
2021-05-11 11:38     ` Luc Michel
2021-05-11 13:06   ` Bin Meng
2021-05-11 13:06     ` Bin Meng
2021-05-04 15:34 ` [PATCH 2/2] QOMify sifive_uart model Lukas Jünger
2021-05-04 15:34   ` Lukas Jünger
2021-05-11 11:39   ` Luc Michel
2021-05-11 11:39     ` Luc Michel
2021-05-11 12:26   ` Philippe Mathieu-Daudé
2021-05-11 12:26     ` Philippe Mathieu-Daudé
2021-05-16 11:13     ` Lukas Jünger
2021-05-16 11:13       ` Lukas Jünger

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