From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65E59C433ED for ; Wed, 5 May 2021 13:49:22 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 20AC06101C for ; Wed, 5 May 2021 13:49:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230170AbhEENuR (ORCPT ); Wed, 5 May 2021 09:50:17 -0400 Received: from foss.arm.com ([217.140.110.172]:44986 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230159AbhEENuQ (ORCPT ); Wed, 5 May 2021 09:50:16 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 03826ED1; Wed, 5 May 2021 06:49:20 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.28.242]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 506013F718; Wed, 5 May 2021 06:49:17 -0700 (PDT) Date: Wed, 5 May 2021 14:49:14 +0100 From: Mark Rutland To: Sudeep Holla Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, arve@google.com, Andrew Walbran , David Hartley , Achin Gupta , Jens Wiklander , Arunachalam Ganapathy , Marc Bonnici , Michael Kelley , Will Deacon Subject: Re: [PATCH v6 1/6] arm64: smccc: Add support for SMCCCv1.2 extended input/output registers Message-ID: <20210505134914.GB5605@C02TD0UTHF1T.local> References: <20210505093843.3308691-1-sudeep.holla@arm.com> <20210505093843.3308691-2-sudeep.holla@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20210505093843.3308691-2-sudeep.holla@arm.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Sudeep, On Wed, May 05, 2021 at 10:38:38AM +0100, Sudeep Holla wrote: > SMCCC v1.2 allows x8-x17 to be used as parameter registers and x4—x17 > to be used as result registers in SMC64/HVC64. Arm Firmware Framework > for Armv8-A specification makes use of x0-x7 as parameter and result > registers. There are other users like Hyper-V who intend to use beyond > x0-x7 as well. > > Current SMCCC interface in the kernel just use x0-x7 as parameter and > x0-x3 as result registers as required by SMCCCv1.0. Let us add new > interface to support this extended set of input/output registers namely > x0-x17 as both parameter and result registers. > > Cc: Michael Kelley > Cc: Will Deacon > Cc: Mark Rutland > Cc:Catalin Marinas > Signed-off-by: Sudeep Holla I have one minor comment below, otherwise this looks good to me, and regardless: Acked-by: Mark Rutland [...] > +/** > + * arm_smccc_1_2_hvc() - make HVC calls > + * @args: arguments passed via struct arm_smccc_1_2_regs > + * @res: result values via struct arm_smccc_1_2_regs > + * > + * This function is used to make HVC calls following SMC Calling Convention > + * v1.2 or above. The content of the supplied param are copied from the > + * structure to registers prior to the HVC instruction. The return values > + * are updated with the content from registers on return from the HVC > + * instruction. > + */ > +asmlinkage void arm_smccc_1_2_hvc(struct arm_smccc_1_2_regs *args, > + struct arm_smccc_1_2_regs *res); > + > +/** > + * arm_smccc_1_2_smc() - make SMC calls > + * @args: arguments passed via struct arm_smccc_1_2_regs > + * @res: result values via struct arm_smccc_1_2_regs > + * > + * This function is used to make SMC calls following SMC Calling Convention > + * v1.2 or above. The content of the supplied param are copied from the > + * structure to registers prior to the SMC instruction. The return values > + * are updated with the content from registers on return from the SMC > + * instruction. > + */ > +asmlinkage void arm_smccc_1_2_smc(struct arm_smccc_1_2_regs *args, > + struct arm_smccc_1_2_regs *res); > +#endif It might be worth making the args parameter to these const, since we never write to it in the asm. Thanks, Mark. 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charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org SGkgU3VkZWVwLAoKT24gV2VkLCBNYXkgMDUsIDIwMjEgYXQgMTA6Mzg6MzhBTSArMDEwMCwgU3Vk ZWVwIEhvbGxhIHdyb3RlOgo+IFNNQ0NDIHYxLjIgYWxsb3dzIHg4LXgxNyB0byBiZSB1c2VkIGFz IHBhcmFtZXRlciByZWdpc3RlcnMgYW5kIHg04oCUeDE3Cj4gdG8gYmUgdXNlZCBhcyByZXN1bHQg cmVnaXN0ZXJzIGluIFNNQzY0L0hWQzY0LiBBcm0gRmlybXdhcmUgRnJhbWV3b3JrCj4gZm9yIEFy bXY4LUEgc3BlY2lmaWNhdGlvbiBtYWtlcyB1c2Ugb2YgeDAteDcgYXMgcGFyYW1ldGVyIGFuZCBy ZXN1bHQKPiByZWdpc3RlcnMuIFRoZXJlIGFyZSBvdGhlciB1c2VycyBsaWtlIEh5cGVyLVYgd2hv IGludGVuZCB0byB1c2UgYmV5b25kCj4geDAteDcgYXMgd2VsbC4KPiAKPiBDdXJyZW50IFNNQ0ND IGludGVyZmFjZSBpbiB0aGUga2VybmVsIGp1c3QgdXNlIHgwLXg3IGFzIHBhcmFtZXRlciBhbmQK PiB4MC14MyBhcyByZXN1bHQgcmVnaXN0ZXJzIGFzIHJlcXVpcmVkIGJ5IFNNQ0NDdjEuMC4gTGV0 IHVzIGFkZCBuZXcKPiBpbnRlcmZhY2UgdG8gc3VwcG9ydCB0aGlzIGV4dGVuZGVkIHNldCBvZiBp bnB1dC9vdXRwdXQgcmVnaXN0ZXJzIG5hbWVseQo+IHgwLXgxNyBhcyBib3RoIHBhcmFtZXRlciBh bmQgcmVzdWx0IHJlZ2lzdGVycy4KPiAKPiBDYzogTWljaGFlbCBLZWxsZXkgPG1pa2VsbGV5QG1p Y3Jvc29mdC5jb20+Cj4gQ2M6IFdpbGwgRGVhY29uIDx3aWxsQGtlcm5lbC5vcmc+Cj4gQ2M6IE1h cmsgUnV0bGFuZCA8bWFyay5ydXRsYW5kQGFybS5jb20+Cj4gQ2M6Q2F0YWxpbiBNYXJpbmFzIDxj YXRhbGluLm1hcmluYXNAYXJtLmNvbT4KPiBTaWduZWQtb2ZmLWJ5OiBTdWRlZXAgSG9sbGEgPHN1 ZGVlcC5ob2xsYUBhcm0uY29tPgoKSSBoYXZlIG9uZSBtaW5vciBjb21tZW50IGJlbG93LCBvdGhl cndpc2UgdGhpcyBsb29rcyBnb29kIHRvIG1lLCBhbmQKcmVnYXJkbGVzczoKCkFja2VkLWJ5OiBN YXJrIFJ1dGxhbmQgPG1hcmsucnV0bGFuZEBhcm0uY29tPgoKWy4uLl0KCj4gKy8qKgo+ICsgKiBh cm1fc21jY2NfMV8yX2h2YygpIC0gbWFrZSBIVkMgY2FsbHMKPiArICogQGFyZ3M6IGFyZ3VtZW50 cyBwYXNzZWQgdmlhIHN0cnVjdCBhcm1fc21jY2NfMV8yX3JlZ3MKPiArICogQHJlczogcmVzdWx0 IHZhbHVlcyB2aWEgc3RydWN0IGFybV9zbWNjY18xXzJfcmVncwo+ICsgKgo+ICsgKiBUaGlzIGZ1 bmN0aW9uIGlzIHVzZWQgdG8gbWFrZSBIVkMgY2FsbHMgZm9sbG93aW5nIFNNQyBDYWxsaW5nIENv bnZlbnRpb24KPiArICogdjEuMiBvciBhYm92ZS4gVGhlIGNvbnRlbnQgb2YgdGhlIHN1cHBsaWVk IHBhcmFtIGFyZSBjb3BpZWQgZnJvbSB0aGUKPiArICogc3RydWN0dXJlIHRvIHJlZ2lzdGVycyBw cmlvciB0byB0aGUgSFZDIGluc3RydWN0aW9uLiBUaGUgcmV0dXJuIHZhbHVlcwo+ICsgKiBhcmUg dXBkYXRlZCB3aXRoIHRoZSBjb250ZW50IGZyb20gcmVnaXN0ZXJzIG9uIHJldHVybiBmcm9tIHRo ZSBIVkMKPiArICogaW5zdHJ1Y3Rpb24uCj4gKyAqLwo+ICthc21saW5rYWdlIHZvaWQgYXJtX3Nt Y2NjXzFfMl9odmMoc3RydWN0IGFybV9zbWNjY18xXzJfcmVncyAqYXJncywKPiArCQkJCSAgc3Ry dWN0IGFybV9zbWNjY18xXzJfcmVncyAqcmVzKTsKPiArCj4gKy8qKgo+ICsgKiBhcm1fc21jY2Nf MV8yX3NtYygpIC0gbWFrZSBTTUMgY2FsbHMKPiArICogQGFyZ3M6IGFyZ3VtZW50cyBwYXNzZWQg dmlhIHN0cnVjdCBhcm1fc21jY2NfMV8yX3JlZ3MKPiArICogQHJlczogcmVzdWx0IHZhbHVlcyB2 aWEgc3RydWN0IGFybV9zbWNjY18xXzJfcmVncwo+ICsgKgo+ICsgKiBUaGlzIGZ1bmN0aW9uIGlz IHVzZWQgdG8gbWFrZSBTTUMgY2FsbHMgZm9sbG93aW5nIFNNQyBDYWxsaW5nIENvbnZlbnRpb24K PiArICogdjEuMiBvciBhYm92ZS4gVGhlIGNvbnRlbnQgb2YgdGhlIHN1cHBsaWVkIHBhcmFtIGFy ZSBjb3BpZWQgZnJvbSB0aGUKPiArICogc3RydWN0dXJlIHRvIHJlZ2lzdGVycyBwcmlvciB0byB0 aGUgU01DIGluc3RydWN0aW9uLiBUaGUgcmV0dXJuIHZhbHVlcwo+ICsgKiBhcmUgdXBkYXRlZCB3 aXRoIHRoZSBjb250ZW50IGZyb20gcmVnaXN0ZXJzIG9uIHJldHVybiBmcm9tIHRoZSBTTUMKPiAr ICogaW5zdHJ1Y3Rpb24uCj4gKyAqLwo+ICthc21saW5rYWdlIHZvaWQgYXJtX3NtY2NjXzFfMl9z bWMoc3RydWN0IGFybV9zbWNjY18xXzJfcmVncyAqYXJncywKPiArCQkJCSAgc3RydWN0IGFybV9z bWNjY18xXzJfcmVncyAqcmVzKTsKPiArI2VuZGlmCgpJdCBtaWdodCBiZSB3b3J0aCBtYWtpbmcg dGhlIGFyZ3MgcGFyYW1ldGVyIHRvIHRoZXNlIGNvbnN0LCBzaW5jZSB3ZQpuZXZlciB3cml0ZSB0 byBpdCBpbiB0aGUgYXNtLgoKVGhhbmtzLApNYXJrLgoKX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGlu dXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQu b3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo=