From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tero Kristo Date: Wed, 5 May 2021 20:55:25 +0300 Subject: [PATCHv3 11/26] clk: fix set_rate to clean up cached rates for the hierarchy In-Reply-To: <20210505175540.15006-1-kristo@kernel.org> References: <20210505175540.15006-1-kristo@kernel.org> Message-ID: <20210505175540.15006-12-kristo@kernel.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Tero Kristo Clock rates are cached within the individual clock nodes, and right now if one changes a clock rate somewhere in the middle of the tree, none of its child clocks notice the change. To fix this, clear up all the cached rates for us and our child clocks. Signed-off-by: Tero Kristo Signed-off-by: Tero Kristo --- drivers/clk/clk-uclass.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c index 5ebf7a33cb..0e495a6a2e 100644 --- a/drivers/clk/clk-uclass.c +++ b/drivers/clk/clk-uclass.c @@ -565,6 +565,22 @@ ulong clk_round_rate(struct clk *clk, ulong rate) return ops->round_rate(clk, rate); } +static void clk_clean_rate_cache(struct clk *clk) +{ + struct udevice *child_dev; + struct clk *clkp; + + if (!clk) + return; + + clk->rate = 0; + + list_for_each_entry(child_dev, &clk->dev->child_head, sibling_node) { + clkp = dev_get_clk_ptr(child_dev); + clk_clean_rate_cache(clkp); + } +} + ulong clk_set_rate(struct clk *clk, ulong rate) { const struct clk_ops *ops; @@ -577,6 +593,9 @@ ulong clk_set_rate(struct clk *clk, ulong rate) if (!ops->set_rate) return -ENOSYS; + /* Clean up cached rates for us and all child clocks */ + clk_clean_rate_cache(clk); + return ops->set_rate(clk, rate); } -- 2.17.1