From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73CD5C43460 for ; Thu, 6 May 2021 18:58:20 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4106761001 for ; Thu, 6 May 2021 18:58:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4106761001 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4F93D6ECF1; Thu, 6 May 2021 18:57:17 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2BA446ECEF; Thu, 6 May 2021 18:57:11 +0000 (UTC) IronPort-SDR: OMxyhTqAuZjxQue1KRBBteHNzxqeQfsw/KsnHuBhvHJ/wHbl3G20R6bSX8OmdmLLhLqc5zE+Ta w4n6q++0fZ0g== X-IronPort-AV: E=McAfee;i="6200,9189,9976"; a="196530995" X-IronPort-AV: E=Sophos;i="5.82,278,1613462400"; d="scan'208";a="196530995" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2021 11:57:11 -0700 IronPort-SDR: ITPX8GQNrCjdK3chyKiIfJIvu93xq1o29j5d87xWRmiOzkg6cwDvLKHM25yEQ7Gn0ACySVhgMA S0ipp1aPw9WA== X-IronPort-AV: E=Sophos;i="5.82,278,1613462400"; d="scan'208";a="469583421" Received: from dhiatt-server.jf.intel.com ([10.54.81.3]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2021 11:57:09 -0700 From: Matthew Brost To: , Subject: [RFC PATCH 21/97] drm/i915/guc: Update MMIO based communication Date: Thu, 6 May 2021 12:13:35 -0700 Message-Id: <20210506191451.77768-22-matthew.brost@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210506191451.77768-1-matthew.brost@intel.com> References: <20210506191451.77768-1-matthew.brost@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: matthew.brost@intel.com, tvrtko.ursulin@intel.com, daniele.ceraolospurio@intel.com, jason.ekstrand@intel.com, jon.bloomfield@intel.com, daniel.vetter@intel.com, john.c.harrison@intel.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Michal Wajdeczko The MMIO based Host-to-GuC communication protocol has been updated to use unified HXG messages. Update our intel_guc_send_mmio() function by correctly handle BUSY, RETRY and FAILURE replies. Also update our documentation. GuC: 55.0.0 Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost Cc: Piotr PiĆ³rkowski Cc: Michal Winiarski --- .../gt/uc/abi/guc_communication_mmio_abi.h | 47 ++++-------- drivers/gpu/drm/i915/gt/uc/intel_guc.c | 75 ++++++++++++++----- 2 files changed, 70 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h index be066a62e9e0..fef51499386b 100644 --- a/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h +++ b/drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h @@ -7,44 +7,27 @@ #define _ABI_GUC_COMMUNICATION_MMIO_ABI_H /** - * DOC: MMIO based communication + * DOC: GuC MMIO based communication * - * The MMIO based communication between Host and GuC uses software scratch - * registers, where first register holds data treated as message header, - * and other registers are used to hold message payload. + * The MMIO based communication between Host and GuC relies on special + * hardware registers which format could be defined by the software + * (so called scratch registers). * - * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8, - * but no H2G command takes more than 8 parameters and the GuC FW - * itself uses an 8-element array to store the H2G message. - * - * +-----------+---------+---------+---------+ - * | MMIO[0] | MMIO[1] | ... | MMIO[n] | - * +-----------+---------+---------+---------+ - * | header | optional payload | - * +======+====+=========+=========+=========+ - * | 31:28|type| | | | - * +------+----+ | | | - * | 27:16|data| | | | - * +------+----+ | | | - * | 15:0|code| | | | - * +------+----+---------+---------+---------+ + * Each MMIO based message, both Host to GuC (H2G) and GuC to Host (G2H) + * messages, which maximum length depends on number of available scratch + * registers, is directly written into those scratch registers. * - * The message header consists of: - * - * - **type**, indicates message type - * - **code**, indicates message code, is specific for **type** - * - **data**, indicates message data, optional, depends on **code** + * For Gen9+, there are 16 software scratch registers 0xC180-0xC1B8, + * but no H2G command takes more than 8 parameters and the GuC firmware + * itself uses an 8-element array to store the H2G message. * - * The following message **types** are supported: + * For Gen11+, there are additional 4 registers 0x190240-0x19024C, which + * are, regardless on lower count, preffered over legacy ones. * - * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code - * must be priovided in **code** field. Optional action specific parameters - * can be provided in remaining payload registers or **data** field. + * The MMIO based communication is mainly used during driver initialization + * phase to setup the CTB based communication that will be used afterwards. * - * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request, - * action response status will be provided in **code** field. Optional - * response data can be returned in remaining payload registers or **data** - * field. + * Format of the MMIO messages follows definitions of `HXG Message`_. */ #define GUC_MAX_MMIO_MSG_LEN 8 diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c index ab2c8fe8cdfa..454c8d886499 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c @@ -385,29 +385,27 @@ void intel_guc_fini(struct intel_guc *guc) /* * This function implements the MMIO based host to GuC interface. */ -int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, +int intel_guc_send_mmio(struct intel_guc *guc, const u32 *request, u32 len, u32 *response_buf, u32 response_buf_size) { + struct drm_i915_private *i915 = guc_to_gt(guc)->i915; struct intel_uncore *uncore = guc_to_gt(guc)->uncore; - u32 status; + u32 header; int i; int ret; GEM_BUG_ON(!len); GEM_BUG_ON(len > guc->send_regs.count); - /* We expect only action code */ - GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK); - - /* If CT is available, we expect to use MMIO only during init/fini */ - GEM_BUG_ON(*action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER && - *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) != GUC_HXG_ORIGIN_HOST); + GEM_BUG_ON(FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) != GUC_HXG_TYPE_REQUEST); mutex_lock(&guc->send_mutex); intel_uncore_forcewake_get(uncore, guc->send_regs.fw_domains); +retry: for (i = 0; i < len; i++) - intel_uncore_write(uncore, guc_send_reg(guc, i), action[i]); + intel_uncore_write(uncore, guc_send_reg(guc, i), request[i]); intel_uncore_posting_read(uncore, guc_send_reg(guc, i - 1)); @@ -419,17 +417,54 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, */ ret = __intel_wait_for_register_fw(uncore, guc_send_reg(guc, 0), - INTEL_GUC_MSG_TYPE_MASK, - INTEL_GUC_MSG_TYPE_RESPONSE << - INTEL_GUC_MSG_TYPE_SHIFT, - 10, 10, &status); - /* If GuC explicitly returned an error, convert it to -EIO */ - if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status)) - ret = -EIO; + GUC_HXG_MSG_0_ORIGIN, + FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, + GUC_HXG_ORIGIN_GUC), + 10, 10, &header); + if (unlikely(ret)) { +timeout: + drm_err(&i915->drm, "mmio request %#x: no reply %x\n", + request[0], header); + goto out; + } - if (ret) { - DRM_ERROR("MMIO: GuC action %#x failed with error %d %#x\n", - action[0], ret, status); + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_BUSY) { +#define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \ + FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != GUC_HXG_ORIGIN_GUC || \ + FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_NO_RESPONSE_BUSY; }) + + ret = wait_for(done, 1000); + if (unlikely(ret)) + goto timeout; + if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != + GUC_HXG_ORIGIN_GUC)) + goto proto; +#undef done + } + + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_NO_RESPONSE_RETRY) { + u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); + + drm_dbg(&i915->drm, "mmio request %#x: retrying, reason %u\n", + request[0], reason); + goto retry; + } + + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == GUC_HXG_TYPE_RESPONSE_FAILURE) { + u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); + u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); + + drm_err(&i915->drm, "mmio request %#x: failure %x/%u\n", + request[0], error, hint); + ret = -ENXIO; + goto out; + } + + if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != GUC_HXG_TYPE_RESPONSE_SUCCESS) { +proto: + drm_err(&i915->drm, "mmio request %#x: unexpected reply %#x\n", + request[0], header); + ret = -EPROTO; goto out; } @@ -442,7 +477,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, } /* Use data from the GuC response as our return value */ - ret = INTEL_GUC_MSG_TO_DATA(status); + ret = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); out: intel_uncore_forcewake_put(uncore, guc->send_regs.fw_domains); -- 2.28.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57CBFC43461 for ; Thu, 6 May 2021 18:58:15 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 117CC6121F for ; Thu, 6 May 2021 18:58:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 117CC6121F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4DF2F6EDA2; Thu, 6 May 2021 18:57:18 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2BA446ECEF; Thu, 6 May 2021 18:57:11 +0000 (UTC) IronPort-SDR: OMxyhTqAuZjxQue1KRBBteHNzxqeQfsw/KsnHuBhvHJ/wHbl3G20R6bSX8OmdmLLhLqc5zE+Ta w4n6q++0fZ0g== X-IronPort-AV: E=McAfee;i="6200,9189,9976"; a="196530995" X-IronPort-AV: E=Sophos;i="5.82,278,1613462400"; d="scan'208";a="196530995" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2021 11:57:11 -0700 IronPort-SDR: ITPX8GQNrCjdK3chyKiIfJIvu93xq1o29j5d87xWRmiOzkg6cwDvLKHM25yEQ7Gn0ACySVhgMA S0ipp1aPw9WA== X-IronPort-AV: E=Sophos;i="5.82,278,1613462400"; d="scan'208";a="469583421" Received: from dhiatt-server.jf.intel.com ([10.54.81.3]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 May 2021 11:57:09 -0700 From: Matthew Brost To: , Date: Thu, 6 May 2021 12:13:35 -0700 Message-Id: <20210506191451.77768-22-matthew.brost@intel.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20210506191451.77768-1-matthew.brost@intel.com> References: <20210506191451.77768-1-matthew.brost@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [RFC PATCH 21/97] drm/i915/guc: Update MMIO based communication X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jason.ekstrand@intel.com, daniel.vetter@intel.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" RnJvbTogTWljaGFsIFdhamRlY3prbyA8bWljaGFsLndhamRlY3prb0BpbnRlbC5jb20+CgpUaGUg TU1JTyBiYXNlZCBIb3N0LXRvLUd1QyBjb21tdW5pY2F0aW9uIHByb3RvY29sIGhhcyBiZWVuCnVw ZGF0ZWQgdG8gdXNlIHVuaWZpZWQgSFhHIG1lc3NhZ2VzLgoKVXBkYXRlIG91ciBpbnRlbF9ndWNf c2VuZF9tbWlvKCkgZnVuY3Rpb24gYnkgY29ycmVjdGx5IGhhbmRsZQpCVVNZLCBSRVRSWSBhbmQg RkFJTFVSRSByZXBsaWVzLiBBbHNvIHVwZGF0ZSBvdXIgZG9jdW1lbnRhdGlvbi4KCkd1QzogNTUu MC4wClNpZ25lZC1vZmYtYnk6IE1pY2hhbCBXYWpkZWN6a28gPG1pY2hhbC53YWpkZWN6a29AaW50 ZWwuY29tPgpTaWduZWQtb2ZmLWJ5OiBNYXR0aGV3IEJyb3N0IDxtYXR0aGV3LmJyb3N0QGludGVs LmNvbT4KQ2M6IFBpb3RyIFBpw7Nya293c2tpIDxwaW90ci5waW9ya293c2tpQGludGVsLmNvbT4K Q2M6IE1pY2hhbCBXaW5pYXJza2kgPG1pY2hhbC53aW5pYXJza2lAaW50ZWwuY29tPgotLS0KIC4u Li9ndC91Yy9hYmkvZ3VjX2NvbW11bmljYXRpb25fbW1pb19hYmkuaCAgICB8IDQ3ICsrKystLS0t LS0tLQogZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxfZ3VjLmMgICAgICAgIHwgNzUg KysrKysrKysrKysrKystLS0tLQogMiBmaWxlcyBjaGFuZ2VkLCA3MCBpbnNlcnRpb25zKCspLCA1 MiBkZWxldGlvbnMoLSkKCmRpZmYgLS1naXQgYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9ndC91Yy9h YmkvZ3VjX2NvbW11bmljYXRpb25fbW1pb19hYmkuaCBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0 L3VjL2FiaS9ndWNfY29tbXVuaWNhdGlvbl9tbWlvX2FiaS5oCmluZGV4IGJlMDY2YTYyZTllMC4u ZmVmNTE0OTkzODZiIDEwMDY0NAotLS0gYS9kcml2ZXJzL2dwdS9kcm0vaTkxNS9ndC91Yy9hYmkv Z3VjX2NvbW11bmljYXRpb25fbW1pb19hYmkuaAorKysgYi9kcml2ZXJzL2dwdS9kcm0vaTkxNS9n dC91Yy9hYmkvZ3VjX2NvbW11bmljYXRpb25fbW1pb19hYmkuaApAQCAtNyw0NCArNywyNyBAQAog I2RlZmluZSBfQUJJX0dVQ19DT01NVU5JQ0FUSU9OX01NSU9fQUJJX0gKIAogLyoqCi0gKiBET0M6 IE1NSU8gYmFzZWQgY29tbXVuaWNhdGlvbgorICogRE9DOiBHdUMgTU1JTyBiYXNlZCBjb21tdW5p Y2F0aW9uCiAgKgotICogVGhlIE1NSU8gYmFzZWQgY29tbXVuaWNhdGlvbiBiZXR3ZWVuIEhvc3Qg YW5kIEd1QyB1c2VzIHNvZnR3YXJlIHNjcmF0Y2gKLSAqIHJlZ2lzdGVycywgd2hlcmUgZmlyc3Qg cmVnaXN0ZXIgaG9sZHMgZGF0YSB0cmVhdGVkIGFzIG1lc3NhZ2UgaGVhZGVyLAotICogYW5kIG90 aGVyIHJlZ2lzdGVycyBhcmUgdXNlZCB0byBob2xkIG1lc3NhZ2UgcGF5bG9hZC4KKyAqIFRoZSBN TUlPIGJhc2VkIGNvbW11bmljYXRpb24gYmV0d2VlbiBIb3N0IGFuZCBHdUMgcmVsaWVzIG9uIHNw ZWNpYWwKKyAqIGhhcmR3YXJlIHJlZ2lzdGVycyB3aGljaCBmb3JtYXQgY291bGQgYmUgZGVmaW5l ZCBieSB0aGUgc29mdHdhcmUKKyAqIChzbyBjYWxsZWQgc2NyYXRjaCByZWdpc3RlcnMpLgogICoK LSAqIEZvciBHZW45KywgR3VDIHVzZXMgc29mdHdhcmUgc2NyYXRjaCByZWdpc3RlcnMgMHhDMTgw LTB4QzFCOCwKLSAqIGJ1dCBubyBIMkcgY29tbWFuZCB0YWtlcyBtb3JlIHRoYW4gOCBwYXJhbWV0 ZXJzIGFuZCB0aGUgR3VDIEZXCi0gKiBpdHNlbGYgdXNlcyBhbiA4LWVsZW1lbnQgYXJyYXkgdG8g c3RvcmUgdGhlIEgyRyBtZXNzYWdlLgotICoKLSAqICAgICAgKy0tLS0tLS0tLS0tKy0tLS0tLS0t LSstLS0tLS0tLS0rLS0tLS0tLS0tKwotICogICAgICB8ICBNTUlPWzBdICB8IE1NSU9bMV0gfCAg IC4uLiAgIHwgTU1JT1tuXSB8Ci0gKiAgICAgICstLS0tLS0tLS0tLSstLS0tLS0tLS0rLS0tLS0t LS0tKy0tLS0tLS0tLSsKLSAqICAgICAgfCBoZWFkZXIgICAgfCAgICAgIG9wdGlvbmFsIHBheWxv YWQgICAgICAgfAotICogICAgICArPT09PT09Kz09PT0rPT09PT09PT09Kz09PT09PT09PSs9PT09 PT09PT0rCi0gKiAgICAgIHwgMzE6Mjh8dHlwZXwgICAgICAgICB8ICAgICAgICAgfCAgICAgICAg IHwKLSAqICAgICAgKy0tLS0tLSstLS0tKyAgICAgICAgIHwgICAgICAgICB8ICAgICAgICAgfAot ICogICAgICB8IDI3OjE2fGRhdGF8ICAgICAgICAgfCAgICAgICAgIHwgICAgICAgICB8Ci0gKiAg ICAgICstLS0tLS0rLS0tLSsgICAgICAgICB8ICAgICAgICAgfCAgICAgICAgIHwKLSAqICAgICAg fCAgMTU6MHxjb2RlfCAgICAgICAgIHwgICAgICAgICB8ICAgICAgICAgfAotICogICAgICArLS0t LS0tKy0tLS0rLS0tLS0tLS0tKy0tLS0tLS0tLSstLS0tLS0tLS0rCisgKiBFYWNoIE1NSU8gYmFz ZWQgbWVzc2FnZSwgYm90aCBIb3N0IHRvIEd1QyAoSDJHKSBhbmQgR3VDIHRvIEhvc3QgKEcySCkK KyAqIG1lc3NhZ2VzLCB3aGljaCBtYXhpbXVtIGxlbmd0aCBkZXBlbmRzIG9uIG51bWJlciBvZiBh dmFpbGFibGUgc2NyYXRjaAorICogcmVnaXN0ZXJzLCBpcyBkaXJlY3RseSB3cml0dGVuIGludG8g dGhvc2Ugc2NyYXRjaCByZWdpc3RlcnMuCiAgKgotICogVGhlIG1lc3NhZ2UgaGVhZGVyIGNvbnNp c3RzIG9mOgotICoKLSAqIC0gKip0eXBlKiosIGluZGljYXRlcyBtZXNzYWdlIHR5cGUKLSAqIC0g Kipjb2RlKiosIGluZGljYXRlcyBtZXNzYWdlIGNvZGUsIGlzIHNwZWNpZmljIGZvciAqKnR5cGUq KgotICogLSAqKmRhdGEqKiwgaW5kaWNhdGVzIG1lc3NhZ2UgZGF0YSwgb3B0aW9uYWwsIGRlcGVu ZHMgb24gKipjb2RlKioKKyAqIEZvciBHZW45KywgdGhlcmUgYXJlIDE2IHNvZnR3YXJlIHNjcmF0 Y2ggcmVnaXN0ZXJzIDB4QzE4MC0weEMxQjgsCisgKiBidXQgbm8gSDJHIGNvbW1hbmQgdGFrZXMg bW9yZSB0aGFuIDggcGFyYW1ldGVycyBhbmQgdGhlIEd1QyBmaXJtd2FyZQorICogaXRzZWxmIHVz ZXMgYW4gOC1lbGVtZW50IGFycmF5IHRvIHN0b3JlIHRoZSBIMkcgbWVzc2FnZS4KICAqCi0gKiBU aGUgZm9sbG93aW5nIG1lc3NhZ2UgKip0eXBlcyoqIGFyZSBzdXBwb3J0ZWQ6CisgKiBGb3IgR2Vu MTErLCB0aGVyZSBhcmUgYWRkaXRpb25hbCA0IHJlZ2lzdGVycyAweDE5MDI0MC0weDE5MDI0Qywg d2hpY2gKKyAqIGFyZSwgcmVnYXJkbGVzcyBvbiBsb3dlciBjb3VudCwgcHJlZmZlcmVkIG92ZXIg bGVnYWN5IG9uZXMuCiAgKgotICogLSAqKlJFUVVFU1QqKiwgaW5kaWNhdGVzIEhvc3QtdG8tR3VD IHJlcXVlc3QsIHJlcXVlc3RlZCBHdUMgYWN0aW9uIGNvZGUKLSAqICAgbXVzdCBiZSBwcmlvdmlk ZWQgaW4gKipjb2RlKiogZmllbGQuIE9wdGlvbmFsIGFjdGlvbiBzcGVjaWZpYyBwYXJhbWV0ZXJz Ci0gKiAgIGNhbiBiZSBwcm92aWRlZCBpbiByZW1haW5pbmcgcGF5bG9hZCByZWdpc3RlcnMgb3Ig KipkYXRhKiogZmllbGQuCisgKiBUaGUgTU1JTyBiYXNlZCBjb21tdW5pY2F0aW9uIGlzIG1haW5s eSB1c2VkIGR1cmluZyBkcml2ZXIgaW5pdGlhbGl6YXRpb24KKyAqIHBoYXNlIHRvIHNldHVwIHRo ZSBDVEIgYmFzZWQgY29tbXVuaWNhdGlvbiB0aGF0IHdpbGwgYmUgdXNlZCBhZnRlcndhcmRzLgog ICoKLSAqIC0gKipSRVNQT05TRSoqLCBpbmRpY2F0ZXMgR3VDLXRvLUhvc3QgcmVzcG9uc2UgZnJv bSBlYXJsaWVyIEd1QyByZXF1ZXN0LAotICogICBhY3Rpb24gcmVzcG9uc2Ugc3RhdHVzIHdpbGwg YmUgcHJvdmlkZWQgaW4gKipjb2RlKiogZmllbGQuIE9wdGlvbmFsCi0gKiAgIHJlc3BvbnNlIGRh dGEgY2FuIGJlIHJldHVybmVkIGluIHJlbWFpbmluZyBwYXlsb2FkIHJlZ2lzdGVycyBvciAqKmRh dGEqKgotICogICBmaWVsZC4KKyAqIEZvcm1hdCBvZiB0aGUgTU1JTyBtZXNzYWdlcyBmb2xsb3dz IGRlZmluaXRpb25zIG9mIGBIWEcgTWVzc2FnZWBfLgogICovCiAKICNkZWZpbmUgR1VDX01BWF9N TUlPX01TR19MRU4JCTgKZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2lu dGVsX2d1Yy5jIGIvZHJpdmVycy9ncHUvZHJtL2k5MTUvZ3QvdWMvaW50ZWxfZ3VjLmMKaW5kZXgg YWIyYzhmZThjZGZhLi40NTRjOGQ4ODY0OTkgMTAwNjQ0Ci0tLSBhL2RyaXZlcnMvZ3B1L2RybS9p OTE1L2d0L3VjL2ludGVsX2d1Yy5jCisrKyBiL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2d0L3VjL2lu dGVsX2d1Yy5jCkBAIC0zODUsMjkgKzM4NSwyNyBAQCB2b2lkIGludGVsX2d1Y19maW5pKHN0cnVj dCBpbnRlbF9ndWMgKmd1YykKIC8qCiAgKiBUaGlzIGZ1bmN0aW9uIGltcGxlbWVudHMgdGhlIE1N SU8gYmFzZWQgaG9zdCB0byBHdUMgaW50ZXJmYWNlLgogICovCi1pbnQgaW50ZWxfZ3VjX3NlbmRf bW1pbyhzdHJ1Y3QgaW50ZWxfZ3VjICpndWMsIGNvbnN0IHUzMiAqYWN0aW9uLCB1MzIgbGVuLAor aW50IGludGVsX2d1Y19zZW5kX21taW8oc3RydWN0IGludGVsX2d1YyAqZ3VjLCBjb25zdCB1MzIg KnJlcXVlc3QsIHUzMiBsZW4sCiAJCQl1MzIgKnJlc3BvbnNlX2J1ZiwgdTMyIHJlc3BvbnNlX2J1 Zl9zaXplKQogeworCXN0cnVjdCBkcm1faTkxNV9wcml2YXRlICppOTE1ID0gZ3VjX3RvX2d0KGd1 YyktPmk5MTU7CiAJc3RydWN0IGludGVsX3VuY29yZSAqdW5jb3JlID0gZ3VjX3RvX2d0KGd1Yykt PnVuY29yZTsKLQl1MzIgc3RhdHVzOworCXUzMiBoZWFkZXI7CiAJaW50IGk7CiAJaW50IHJldDsK IAogCUdFTV9CVUdfT04oIWxlbik7CiAJR0VNX0JVR19PTihsZW4gPiBndWMtPnNlbmRfcmVncy5j b3VudCk7CiAKLQkvKiBXZSBleHBlY3Qgb25seSBhY3Rpb24gY29kZSAqLwotCUdFTV9CVUdfT04o KmFjdGlvbiAmIH5JTlRFTF9HVUNfTVNHX0NPREVfTUFTSyk7Ci0KLQkvKiBJZiBDVCBpcyBhdmFp bGFibGUsIHdlIGV4cGVjdCB0byB1c2UgTU1JTyBvbmx5IGR1cmluZyBpbml0L2ZpbmkgKi8KLQlH RU1fQlVHX09OKCphY3Rpb24gIT0gSU5URUxfR1VDX0FDVElPTl9SRUdJU1RFUl9DT01NQU5EX1RS QU5TUE9SVF9CVUZGRVIgJiYKLQkJICAgKmFjdGlvbiAhPSBJTlRFTF9HVUNfQUNUSU9OX0RFUkVH SVNURVJfQ09NTUFORF9UUkFOU1BPUlRfQlVGRkVSKTsKKwlHRU1fQlVHX09OKEZJRUxEX0dFVChH VUNfSFhHX01TR18wX09SSUdJTiwgcmVxdWVzdFswXSkgIT0gR1VDX0hYR19PUklHSU5fSE9TVCk7 CisJR0VNX0JVR19PTihGSUVMRF9HRVQoR1VDX0hYR19NU0dfMF9UWVBFLCByZXF1ZXN0WzBdKSAh PSBHVUNfSFhHX1RZUEVfUkVRVUVTVCk7CiAKIAltdXRleF9sb2NrKCZndWMtPnNlbmRfbXV0ZXgp OwogCWludGVsX3VuY29yZV9mb3JjZXdha2VfZ2V0KHVuY29yZSwgZ3VjLT5zZW5kX3JlZ3MuZndf ZG9tYWlucyk7CiAKK3JldHJ5OgogCWZvciAoaSA9IDA7IGkgPCBsZW47IGkrKykKLQkJaW50ZWxf dW5jb3JlX3dyaXRlKHVuY29yZSwgZ3VjX3NlbmRfcmVnKGd1YywgaSksIGFjdGlvbltpXSk7CisJ CWludGVsX3VuY29yZV93cml0ZSh1bmNvcmUsIGd1Y19zZW5kX3JlZyhndWMsIGkpLCByZXF1ZXN0 W2ldKTsKIAogCWludGVsX3VuY29yZV9wb3N0aW5nX3JlYWQodW5jb3JlLCBndWNfc2VuZF9yZWco Z3VjLCBpIC0gMSkpOwogCkBAIC00MTksMTcgKzQxNyw1NCBAQCBpbnQgaW50ZWxfZ3VjX3NlbmRf bW1pbyhzdHJ1Y3QgaW50ZWxfZ3VjICpndWMsIGNvbnN0IHUzMiAqYWN0aW9uLCB1MzIgbGVuLAog CSAqLwogCXJldCA9IF9faW50ZWxfd2FpdF9mb3JfcmVnaXN0ZXJfZncodW5jb3JlLAogCQkJCQkg ICBndWNfc2VuZF9yZWcoZ3VjLCAwKSwKLQkJCQkJICAgSU5URUxfR1VDX01TR19UWVBFX01BU0ss Ci0JCQkJCSAgIElOVEVMX0dVQ19NU0dfVFlQRV9SRVNQT05TRSA8PAotCQkJCQkgICBJTlRFTF9H VUNfTVNHX1RZUEVfU0hJRlQsCi0JCQkJCSAgIDEwLCAxMCwgJnN0YXR1cyk7Ci0JLyogSWYgR3VD IGV4cGxpY2l0bHkgcmV0dXJuZWQgYW4gZXJyb3IsIGNvbnZlcnQgaXQgdG8gLUVJTyAqLwotCWlm ICghcmV0ICYmICFJTlRFTF9HVUNfTVNHX0lTX1JFU1BPTlNFX1NVQ0NFU1Moc3RhdHVzKSkKLQkJ cmV0ID0gLUVJTzsKKwkJCQkJICAgR1VDX0hYR19NU0dfMF9PUklHSU4sCisJCQkJCSAgIEZJRUxE X1BSRVAoR1VDX0hYR19NU0dfMF9PUklHSU4sCisJCQkJCQkgICAgICBHVUNfSFhHX09SSUdJTl9H VUMpLAorCQkJCQkgICAxMCwgMTAsICZoZWFkZXIpOworCWlmICh1bmxpa2VseShyZXQpKSB7Cit0 aW1lb3V0OgorCQlkcm1fZXJyKCZpOTE1LT5kcm0sICJtbWlvIHJlcXVlc3QgJSN4OiBubyByZXBs eSAleFxuIiwKKwkJCXJlcXVlc3RbMF0sIGhlYWRlcik7CisJCWdvdG8gb3V0OworCX0KIAotCWlm IChyZXQpIHsKLQkJRFJNX0VSUk9SKCJNTUlPOiBHdUMgYWN0aW9uICUjeCBmYWlsZWQgd2l0aCBl cnJvciAlZCAlI3hcbiIsCi0JCQkgIGFjdGlvblswXSwgcmV0LCBzdGF0dXMpOworCWlmIChGSUVM RF9HRVQoR1VDX0hYR19NU0dfMF9UWVBFLCBoZWFkZXIpID09IEdVQ19IWEdfVFlQRV9OT19SRVNQ T05TRV9CVVNZKSB7CisjZGVmaW5lIGRvbmUgKHsgaGVhZGVyID0gaW50ZWxfdW5jb3JlX3JlYWQo dW5jb3JlLCBndWNfc2VuZF9yZWcoZ3VjLCAwKSk7IFwKKwkJRklFTERfR0VUKEdVQ19IWEdfTVNH XzBfT1JJR0lOLCBoZWFkZXIpICE9IEdVQ19IWEdfT1JJR0lOX0dVQyB8fCBcCisJCUZJRUxEX0dF VChHVUNfSFhHX01TR18wX1RZUEUsIGhlYWRlcikgIT0gR1VDX0hYR19UWVBFX05PX1JFU1BPTlNF X0JVU1k7IH0pCisKKwkJcmV0ID0gd2FpdF9mb3IoZG9uZSwgMTAwMCk7CisJCWlmICh1bmxpa2Vs eShyZXQpKQorCQkJZ290byB0aW1lb3V0OworCQlpZiAodW5saWtlbHkoRklFTERfR0VUKEdVQ19I WEdfTVNHXzBfT1JJR0lOLCBoZWFkZXIpICE9CisJCQkJICAgICAgIEdVQ19IWEdfT1JJR0lOX0dV QykpCisJCQlnb3RvIHByb3RvOworI3VuZGVmIGRvbmUKKwl9CisKKwlpZiAoRklFTERfR0VUKEdV Q19IWEdfTVNHXzBfVFlQRSwgaGVhZGVyKSA9PSBHVUNfSFhHX1RZUEVfTk9fUkVTUE9OU0VfUkVU UlkpIHsKKwkJdTMyIHJlYXNvbiA9IEZJRUxEX0dFVChHVUNfSFhHX1JFVFJZX01TR18wX1JFQVNP TiwgaGVhZGVyKTsKKworCQlkcm1fZGJnKCZpOTE1LT5kcm0sICJtbWlvIHJlcXVlc3QgJSN4OiBy ZXRyeWluZywgcmVhc29uICV1XG4iLAorCQkJcmVxdWVzdFswXSwgcmVhc29uKTsKKwkJZ290byBy ZXRyeTsKKwl9CisKKwlpZiAoRklFTERfR0VUKEdVQ19IWEdfTVNHXzBfVFlQRSwgaGVhZGVyKSA9 PSBHVUNfSFhHX1RZUEVfUkVTUE9OU0VfRkFJTFVSRSkgeworCQl1MzIgaGludCA9IEZJRUxEX0dF VChHVUNfSFhHX0ZBSUxVUkVfTVNHXzBfSElOVCwgaGVhZGVyKTsKKwkJdTMyIGVycm9yID0gRklF TERfR0VUKEdVQ19IWEdfRkFJTFVSRV9NU0dfMF9FUlJPUiwgaGVhZGVyKTsKKworCQlkcm1fZXJy KCZpOTE1LT5kcm0sICJtbWlvIHJlcXVlc3QgJSN4OiBmYWlsdXJlICV4LyV1XG4iLAorCQkJcmVx dWVzdFswXSwgZXJyb3IsIGhpbnQpOworCQlyZXQgPSAtRU5YSU87CisJCWdvdG8gb3V0OworCX0K KworCWlmIChGSUVMRF9HRVQoR1VDX0hYR19NU0dfMF9UWVBFLCBoZWFkZXIpICE9IEdVQ19IWEdf VFlQRV9SRVNQT05TRV9TVUNDRVNTKSB7Citwcm90bzoKKwkJZHJtX2VycigmaTkxNS0+ZHJtLCAi bW1pbyByZXF1ZXN0ICUjeDogdW5leHBlY3RlZCByZXBseSAlI3hcbiIsCisJCQlyZXF1ZXN0WzBd LCBoZWFkZXIpOworCQlyZXQgPSAtRVBST1RPOwogCQlnb3RvIG91dDsKIAl9CiAKQEAgLTQ0Miw3 ICs0NzcsNyBAQCBpbnQgaW50ZWxfZ3VjX3NlbmRfbW1pbyhzdHJ1Y3QgaW50ZWxfZ3VjICpndWMs IGNvbnN0IHUzMiAqYWN0aW9uLCB1MzIgbGVuLAogCX0KIAogCS8qIFVzZSBkYXRhIGZyb20gdGhl IEd1QyByZXNwb25zZSBhcyBvdXIgcmV0dXJuIHZhbHVlICovCi0JcmV0ID0gSU5URUxfR1VDX01T R19UT19EQVRBKHN0YXR1cyk7CisJcmV0ID0gRklFTERfR0VUKEdVQ19IWEdfUkVTUE9OU0VfTVNH XzBfREFUQTAsIGhlYWRlcik7CiAKIG91dDoKIAlpbnRlbF91bmNvcmVfZm9yY2V3YWtlX3B1dCh1 bmNvcmUsIGd1Yy0+c2VuZF9yZWdzLmZ3X2RvbWFpbnMpOwotLSAKMi4yOC4wCgpfX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpJbnRlbC1nZnggbWFpbGluZyBs aXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVz a3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK