From: Miquel Raynal <miquel.raynal@bootlin.com> To: Rob Herring <robh+dt@kernel.org>, <devicetree@vger.kernel.org> Cc: Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Tudor Ambarus <Tudor.Ambarus@microchip.com>, <linux-mtd@lists.infradead.org>, Naga Sureshkumar Relli <nagasure@xilinx.com>, Michal Simek <monstr@monstr.eu>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Miquel Raynal <miquel.raynal@bootlin.com> Subject: [PATCH v2 4/5] mtd: rawnand: arasan: Ensure proper configuration for the asserted target Date: Mon, 10 May 2021 12:40:50 +0200 [thread overview] Message-ID: <20210510104051.9701-5-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20210510104051.9701-1-miquel.raynal@bootlin.com> The controller being always asserting one CS or the other, there is no need to actually select the right target before doing a page read/write. However, the anfc_select_target() helper actually also changes the timing configuration and clock in the case were two different NAND chips with different timing requirements would be used. In this situation, we must ensure proper configuration of the controller by calling it. As a consequence of this change, the anfc_select_target() helper is being moved earlier in the driver. Fixes: 88ffef1b65cf ("mtd: rawnand: arasan: Support the hardware BCH ECC engine") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/mtd/nand/raw/arasan-nand-controller.c | 90 ++++++++++++------- 1 file changed, 57 insertions(+), 33 deletions(-) diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c index 549aac00228e..390f8d719c25 100644 --- a/drivers/mtd/nand/raw/arasan-nand-controller.c +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c @@ -273,6 +273,37 @@ static int anfc_pkt_len_config(unsigned int len, unsigned int *steps, return 0; } +static int anfc_select_target(struct nand_chip *chip, int target) +{ + struct anand *anand = to_anand(chip); + struct arasan_nfc *nfc = to_anfc(chip->controller); + int ret; + + /* Update the controller timings and the potential ECC configuration */ + writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG); + + /* Update clock frequency */ + if (nfc->cur_clk != anand->clk) { + clk_disable_unprepare(nfc->controller_clk); + ret = clk_set_rate(nfc->controller_clk, anand->clk); + if (ret) { + dev_err(nfc->dev, "Failed to change clock rate\n"); + return ret; + } + + ret = clk_prepare_enable(nfc->controller_clk); + if (ret) { + dev_err(nfc->dev, + "Failed to re-enable the controller clock\n"); + return ret; + } + + nfc->cur_clk = anand->clk; + } + + return 0; +} + /* * When using the embedded hardware ECC engine, the controller is in charge of * feeding the engine with, first, the ECC residue present in the data array. @@ -401,6 +432,18 @@ static int anfc_read_page_hw_ecc(struct nand_chip *chip, u8 *buf, return 0; } +static int anfc_sel_read_page_hw_ecc(struct nand_chip *chip, u8 *buf, + int oob_required, int page) +{ + int ret; + + ret = anfc_select_target(chip, chip->cur_cs); + if (ret) + return ret; + + return anfc_read_page_hw_ecc(chip, buf, oob_required, page); +}; + static int anfc_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf, int oob_required, int page) { @@ -461,6 +504,18 @@ static int anfc_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf, return ret; } +static int anfc_sel_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf, + int oob_required, int page) +{ + int ret; + + ret = anfc_select_target(chip, chip->cur_cs); + if (ret) + return ret; + + return anfc_write_page_hw_ecc(chip, buf, oob_required, page); +}; + /* NAND framework ->exec_op() hooks and related helpers */ static int anfc_parse_instructions(struct nand_chip *chip, const struct nand_subop *subop, @@ -753,37 +808,6 @@ static const struct nand_op_parser anfc_op_parser = NAND_OP_PARSER( NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), ); -static int anfc_select_target(struct nand_chip *chip, int target) -{ - struct anand *anand = to_anand(chip); - struct arasan_nfc *nfc = to_anfc(chip->controller); - int ret; - - /* Update the controller timings and the potential ECC configuration */ - writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG); - - /* Update clock frequency */ - if (nfc->cur_clk != anand->clk) { - clk_disable_unprepare(nfc->controller_clk); - ret = clk_set_rate(nfc->controller_clk, anand->clk); - if (ret) { - dev_err(nfc->dev, "Failed to change clock rate\n"); - return ret; - } - - ret = clk_prepare_enable(nfc->controller_clk); - if (ret) { - dev_err(nfc->dev, - "Failed to re-enable the controller clock\n"); - return ret; - } - - nfc->cur_clk = anand->clk; - } - - return 0; -} - static int anfc_check_op(struct nand_chip *chip, const struct nand_operation *op) { @@ -1007,8 +1031,8 @@ static int anfc_init_hw_ecc_controller(struct arasan_nfc *nfc, if (!anand->bch) return -EINVAL; - ecc->read_page = anfc_read_page_hw_ecc; - ecc->write_page = anfc_write_page_hw_ecc; + ecc->read_page = anfc_sel_read_page_hw_ecc; + ecc->write_page = anfc_sel_write_page_hw_ecc; return 0; } -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com> To: Rob Herring <robh+dt@kernel.org>, <devicetree@vger.kernel.org> Cc: Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>, Tudor Ambarus <Tudor.Ambarus@microchip.com>, <linux-mtd@lists.infradead.org>, Naga Sureshkumar Relli <nagasure@xilinx.com>, Michal Simek <monstr@monstr.eu>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Miquel Raynal <miquel.raynal@bootlin.com> Subject: [PATCH v2 4/5] mtd: rawnand: arasan: Ensure proper configuration for the asserted target Date: Mon, 10 May 2021 12:40:50 +0200 [thread overview] Message-ID: <20210510104051.9701-5-miquel.raynal@bootlin.com> (raw) In-Reply-To: <20210510104051.9701-1-miquel.raynal@bootlin.com> The controller being always asserting one CS or the other, there is no need to actually select the right target before doing a page read/write. However, the anfc_select_target() helper actually also changes the timing configuration and clock in the case were two different NAND chips with different timing requirements would be used. In this situation, we must ensure proper configuration of the controller by calling it. As a consequence of this change, the anfc_select_target() helper is being moved earlier in the driver. Fixes: 88ffef1b65cf ("mtd: rawnand: arasan: Support the hardware BCH ECC engine") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- drivers/mtd/nand/raw/arasan-nand-controller.c | 90 ++++++++++++------- 1 file changed, 57 insertions(+), 33 deletions(-) diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c index 549aac00228e..390f8d719c25 100644 --- a/drivers/mtd/nand/raw/arasan-nand-controller.c +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c @@ -273,6 +273,37 @@ static int anfc_pkt_len_config(unsigned int len, unsigned int *steps, return 0; } +static int anfc_select_target(struct nand_chip *chip, int target) +{ + struct anand *anand = to_anand(chip); + struct arasan_nfc *nfc = to_anfc(chip->controller); + int ret; + + /* Update the controller timings and the potential ECC configuration */ + writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG); + + /* Update clock frequency */ + if (nfc->cur_clk != anand->clk) { + clk_disable_unprepare(nfc->controller_clk); + ret = clk_set_rate(nfc->controller_clk, anand->clk); + if (ret) { + dev_err(nfc->dev, "Failed to change clock rate\n"); + return ret; + } + + ret = clk_prepare_enable(nfc->controller_clk); + if (ret) { + dev_err(nfc->dev, + "Failed to re-enable the controller clock\n"); + return ret; + } + + nfc->cur_clk = anand->clk; + } + + return 0; +} + /* * When using the embedded hardware ECC engine, the controller is in charge of * feeding the engine with, first, the ECC residue present in the data array. @@ -401,6 +432,18 @@ static int anfc_read_page_hw_ecc(struct nand_chip *chip, u8 *buf, return 0; } +static int anfc_sel_read_page_hw_ecc(struct nand_chip *chip, u8 *buf, + int oob_required, int page) +{ + int ret; + + ret = anfc_select_target(chip, chip->cur_cs); + if (ret) + return ret; + + return anfc_read_page_hw_ecc(chip, buf, oob_required, page); +}; + static int anfc_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf, int oob_required, int page) { @@ -461,6 +504,18 @@ static int anfc_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf, return ret; } +static int anfc_sel_write_page_hw_ecc(struct nand_chip *chip, const u8 *buf, + int oob_required, int page) +{ + int ret; + + ret = anfc_select_target(chip, chip->cur_cs); + if (ret) + return ret; + + return anfc_write_page_hw_ecc(chip, buf, oob_required, page); +}; + /* NAND framework ->exec_op() hooks and related helpers */ static int anfc_parse_instructions(struct nand_chip *chip, const struct nand_subop *subop, @@ -753,37 +808,6 @@ static const struct nand_op_parser anfc_op_parser = NAND_OP_PARSER( NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), ); -static int anfc_select_target(struct nand_chip *chip, int target) -{ - struct anand *anand = to_anand(chip); - struct arasan_nfc *nfc = to_anfc(chip->controller); - int ret; - - /* Update the controller timings and the potential ECC configuration */ - writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG); - - /* Update clock frequency */ - if (nfc->cur_clk != anand->clk) { - clk_disable_unprepare(nfc->controller_clk); - ret = clk_set_rate(nfc->controller_clk, anand->clk); - if (ret) { - dev_err(nfc->dev, "Failed to change clock rate\n"); - return ret; - } - - ret = clk_prepare_enable(nfc->controller_clk); - if (ret) { - dev_err(nfc->dev, - "Failed to re-enable the controller clock\n"); - return ret; - } - - nfc->cur_clk = anand->clk; - } - - return 0; -} - static int anfc_check_op(struct nand_chip *chip, const struct nand_operation *op) { @@ -1007,8 +1031,8 @@ static int anfc_init_hw_ecc_controller(struct arasan_nfc *nfc, if (!anand->bch) return -EINVAL; - ecc->read_page = anfc_read_page_hw_ecc; - ecc->write_page = anfc_write_page_hw_ecc; + ecc->read_page = anfc_sel_read_page_hw_ecc; + ecc->write_page = anfc_sel_write_page_hw_ecc; return 0; } -- 2.27.0 ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2021-05-10 10:42 UTC|newest] Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-10 10:40 [PATCH v2 0/5] Bring GPIO CS support to the Arasan controller driver Miquel Raynal 2021-05-10 10:40 ` Miquel Raynal 2021-05-10 10:40 ` [PATCH v2 1/5] dt-binding: mtd: nand: Document gpio-cs property Miquel Raynal 2021-05-10 10:40 ` Miquel Raynal 2021-05-10 16:51 ` Rob Herring 2021-05-10 16:51 ` Rob Herring 2021-05-10 17:00 ` Miquel Raynal 2021-05-10 17:00 ` Miquel Raynal 2021-05-10 10:40 ` [PATCH v2 2/5] mtd: rawnand: Move struct gpio_desc declaration to the top Miquel Raynal 2021-05-10 10:40 ` Miquel Raynal 2021-05-26 9:03 ` Miquel Raynal 2021-05-26 9:03 ` Miquel Raynal 2021-05-26 9:34 ` Miquel Raynal 2021-05-26 9:34 ` Miquel Raynal 2021-05-10 10:40 ` [PATCH v2 3/5] mtd: rawnand: Add a helper to parse the gpio-cs DT property Miquel Raynal 2021-05-10 10:40 ` Miquel Raynal 2021-05-26 9:03 ` Miquel Raynal 2021-05-26 9:03 ` Miquel Raynal 2021-05-10 10:40 ` Miquel Raynal [this message] 2021-05-10 10:40 ` [PATCH v2 4/5] mtd: rawnand: arasan: Ensure proper configuration for the asserted target Miquel Raynal 2021-05-26 9:03 ` Miquel Raynal 2021-05-26 9:03 ` Miquel Raynal 2021-05-10 10:40 ` [PATCH v2 5/5] mtd: rawnand: arasan: Leverage additional GPIO CS Miquel Raynal 2021-05-10 10:40 ` Miquel Raynal 2021-05-10 16:00 ` kernel test robot 2021-05-10 16:00 ` kernel test robot 2021-05-10 16:00 ` kernel test robot 2021-05-26 9:03 ` Miquel Raynal 2021-05-26 9:03 ` Miquel Raynal
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