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Mon, 10 May 2021 12:24:39 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 2670D61432; Mon, 10 May 2021 12:24:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1620649477; bh=AMQhwyzZeJlCJdzvLfhtw0VYiGA1XCn7jgNICzvoI9M=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jPRtl30LFlbAYYzOdZUCjk+Wzd7R5PQUoy1XY9oDpAk5rbzGiD+G7vU02Q6Ex+v/z ltxpgsc6hABX7KG2pLy8aQBQlt+o8Wp3yb6vWWVT2+cn76EUpbS4yC7O0cytqRDAfX kC+xMJMxQG6528KgAcdKNIClQiK/THKqotzvTvt8foA17Kc18PFNIH4UVE9H6bKhsC /AjzTn9Tf9/wivw5MsEe7On0s8PgFLK8xz9C/Oi2Zq6bgdfSE34oOQtNGP9OtQdnbh rzFQGzHME9hd/8I7jjw4FZym7c4BnNw0uES/DhZmQ9YzPbKydYopE3gqv3YgrCvU5Y xXmzZSZIw27cQ== From: Mark Brown To: Catalin Marinas , Will Deacon Cc: Dave Martin , linux-arm-kernel@lists.infradead.org, Mark Brown Subject: [PATCH v1 3/3] arm64/sve: Skip flushing Z registers with 128 bit vectors Date: Mon, 10 May 2021 13:23:48 +0100 Message-Id: <20210510122348.56443-4-broonie@kernel.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20210510122348.56443-1-broonie@kernel.org> References: <20210510122348.56443-1-broonie@kernel.org> MIME-Version: 1.0 X-Patch-Hashes: v=1; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org When the SVE vector length is 128 bits then there are no bits in the Z registers which are not shared with the V registers so we can skip them when zeroing state not shared with FPSIMD, this results in a minor performance improvement. Signed-off-by: Mark Brown --- arch/arm64/include/asm/fpsimd.h | 2 +- arch/arm64/kernel/entry-fpsimd.S | 9 +++++++-- arch/arm64/kernel/fpsimd.c | 6 ++++-- 3 files changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h index 2599504674b5..c072161d5c65 100644 --- a/arch/arm64/include/asm/fpsimd.h +++ b/arch/arm64/include/asm/fpsimd.h @@ -69,7 +69,7 @@ static inline void *sve_pffr(struct thread_struct *thread) extern void sve_save_state(void *state, u32 *pfpsr); extern void sve_load_state(void const *state, u32 const *pfpsr, unsigned long vq_minus_1); -extern void sve_flush_live(void); +extern void sve_flush_live(unsigned long vq_minus_1); extern void sve_load_from_fpsimd_state(struct user_fpsimd_state const *state, unsigned long vq_minus_1); extern unsigned int sve_get_vl(void); diff --git a/arch/arm64/kernel/entry-fpsimd.S b/arch/arm64/kernel/entry-fpsimd.S index ee8773f4088b..090449e825e7 100644 --- a/arch/arm64/kernel/entry-fpsimd.S +++ b/arch/arm64/kernel/entry-fpsimd.S @@ -70,10 +70,15 @@ SYM_FUNC_START(sve_load_from_fpsimd_state) ret SYM_FUNC_END(sve_load_from_fpsimd_state) -/* Zero all SVE registers but the first 128-bits of each vector */ +/* + * Zero all SVE registers but the first 128-bits of each vector + * + * x0 = VQ - 1 + */ SYM_FUNC_START(sve_flush_live) + cbz x0, 1f // A VQ-1 of 0 is 128 bits so no extra Z state sve_flush_z - sve_flush_p +1: sve_flush_p sve_flush_ffr ret SYM_FUNC_END(sve_flush_live) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index ad3dd34a83cf..e57b23f95284 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -957,8 +957,10 @@ void do_sve_acc(unsigned int esr, struct pt_regs *regs) * disabling the trap, otherwise update our in-memory copy. */ if (!test_thread_flag(TIF_FOREIGN_FPSTATE)) { - sve_set_vq(sve_vq_from_vl(current->thread.sve_vl) - 1); - sve_flush_live(); + unsigned long vq_minus_one = + sve_vq_from_vl(current->thread.sve_vl) - 1; + sve_set_vq(vq_minus_one); + sve_flush_live(vq_minus_one); fpsimd_bind_task_to_cpu(); } else { fpsimd_to_sve(current); -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel