From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org
Subject: [PULL v3 00/42] riscv-to-apply queue
Date: Tue, 11 May 2021 20:19:09 +1000 [thread overview]
Message-ID: <20210511101951.165287-1-alistair.francis@wdc.com> (raw)
The following changes since commit e4f3ede95ce813d5705c65e1c0e1c80c70739ebb:
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210505-pull-request' into staging (2021-05-10 19:55:06 +0100)
are available in the Git repository at:
git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210511
for you to fetch changes up to c30a0757f094c107e491820e3d35224eb68859c7:
target/riscv: Fix the RV64H decode comment (2021-05-11 20:02:07 +1000)
----------------------------------------------------------------
A large collection of RISC-V fixes, improvements and features
- Clenaup some left over v1.9 code
- Documentation improvements
- Support for the shakti_c machine
- Internal cleanup of the CSR accesses
- Updates to the OpenTitan platform
- Support for the virtio-vga
- Fix for the saturate subtract in vector extensions
- Experimental support for the ePMP spec
- A range of other internal code cleanups and bug fixes
----------------------------------------------------------------
Alexander Wagner (1):
hw/riscv: Fix OT IBEX reset vector
Alistair Francis (22):
target/riscv: Convert the RISC-V exceptions to an enum
target/riscv: Use the RISCVException enum for CSR predicates
target/riscv: Fix 32-bit HS mode access permissions
target/riscv: Use the RISCVException enum for CSR operations
target/riscv: Use RISCVException enum for CSR access
MAINTAINERS: Update the RISC-V CPU Maintainers
hw/opentitan: Update the interrupt layout
hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
target/riscv: Fix the PMP is locked check when using TOR
target/riscv: Add the ePMP feature
target/riscv/pmp: Remove outdated comment
target/riscv: Add ePMP support for the Ibex CPU
target/riscv: Remove the hardcoded RVXLEN macro
target/riscv: Remove the hardcoded SSTATUS_SD macro
target/riscv: Remove the hardcoded HGATP_MODE macro
target/riscv: Remove the hardcoded MSTATUS_SD macro
target/riscv: Remove the hardcoded SATP_MODE macro
target/riscv: Remove the unused HSTATUS_WPRI macro
target/riscv: Remove an unused CASE_OP_32_64 macro
target/riscv: Consolidate RV32/64 32-bit instructions
target/riscv: Consolidate RV32/64 16-bit instructions
target/riscv: Fix the RV64H decode comment
Atish Patra (1):
target/riscv: Remove privilege v1.9 specific CSR related code
Axel Heider (1):
docs/system/generic-loader.rst: Fix style
Bin Meng (1):
hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
Dylan Jhong (1):
target/riscv: Align the data type of reset vector address
Emmanuel Blot (2):
target/riscv: fix exception index on instruction access fault
target/riscv: fix a typo with interrupt names
Frank Chang (2):
target/riscv: fix vrgather macro index variable type bug
fpu/softfloat: set invalid excp flag for RISC-V muladd instructions
Hou Weiying (4):
target/riscv: Define ePMP mseccfg
target/riscv: Add ePMP CSR access functions
target/riscv: Implementation of enhanced PMP (ePMP)
target/riscv: Add a config option for ePMP
Jade Fink (1):
riscv: don't look at SUM when accessing memory from a debugger context
LIU Zhiwei (1):
target/riscv: Fixup saturate subtract function
Vijai Kumar K (5):
target/riscv: Add Shakti C class CPU
riscv: Add initial support for Shakti C machine
hw/char: Add Shakti UART emulation
hw/riscv: Connect Shakti UART to Shakti platform
docs: Add documentation for shakti_c machine
docs/system/generic-loader.rst | 9 +-
docs/system/riscv/shakti-c.rst | 82 +++
docs/system/target-riscv.rst | 1 +
default-configs/devices/riscv64-softmmu.mak | 1 +
include/hw/char/shakti_uart.h | 74 +++
include/hw/riscv/opentitan.h | 16 +-
include/hw/riscv/shakti_c.h | 75 +++
target/riscv/cpu.h | 42 +-
target/riscv/cpu_bits.h | 114 +---
target/riscv/helper.h | 18 +-
target/riscv/pmp.h | 14 +
target/riscv/insn16-32.decode | 28 -
target/riscv/insn16-64.decode | 36 --
target/riscv/insn16.decode | 30 +
target/riscv/insn32-64.decode | 88 ---
target/riscv/insn32.decode | 67 ++-
hw/char/shakti_uart.c | 185 +++++++
hw/intc/ibex_plic.c | 20 +-
hw/riscv/opentitan.c | 10 +-
hw/riscv/shakti_c.c | 181 ++++++
hw/riscv/sifive_e.c | 2 +-
target/riscv/cpu.c | 26 +-
target/riscv/cpu_helper.c | 88 ++-
target/riscv/csr.c | 824 +++++++++++++++++-----------
target/riscv/fpu_helper.c | 16 +-
target/riscv/gdbstub.c | 8 +-
target/riscv/machine.c | 8 +-
target/riscv/monitor.c | 22 +-
target/riscv/op_helper.c | 18 +-
target/riscv/pmp.c | 218 +++++++-
target/riscv/translate.c | 38 +-
target/riscv/vector_helper.c | 18 +-
fpu/softfloat-specialize.c.inc | 6 +
target/riscv/insn_trans/trans_rva.c.inc | 14 +-
target/riscv/insn_trans/trans_rvd.c.inc | 17 +-
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
target/riscv/insn_trans/trans_rvh.c.inc | 8 +-
target/riscv/insn_trans/trans_rvi.c.inc | 22 +-
target/riscv/insn_trans/trans_rvm.c.inc | 12 +-
target/riscv/insn_trans/trans_rvv.c.inc | 39 +-
MAINTAINERS | 14 +-
hw/char/meson.build | 1 +
hw/char/trace-events | 4 +
hw/riscv/Kconfig | 11 +
hw/riscv/meson.build | 1 +
target/riscv/meson.build | 13 +-
target/riscv/trace-events | 3 +
47 files changed, 1759 insertions(+), 789 deletions(-)
create mode 100644 docs/system/riscv/shakti-c.rst
create mode 100644 include/hw/char/shakti_uart.h
create mode 100644 include/hw/riscv/shakti_c.h
delete mode 100644 target/riscv/insn16-32.decode
delete mode 100644 target/riscv/insn16-64.decode
delete mode 100644 target/riscv/insn32-64.decode
create mode 100644 hw/char/shakti_uart.c
create mode 100644 hw/riscv/shakti_c.c
next reply other threads:[~2021-05-11 10:26 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-11 10:19 Alistair Francis [this message]
2021-05-11 10:19 ` [PULL v3 01/42] target/riscv: Remove privilege v1.9 specific CSR related code Alistair Francis
2021-05-11 10:19 ` [PULL v3 02/42] docs/system/generic-loader.rst: Fix style Alistair Francis
2021-05-11 10:19 ` [PULL v3 03/42] target/riscv: Align the data type of reset vector address Alistair Francis
2021-05-11 10:19 ` [PULL v3 04/42] hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] Alistair Francis
2021-05-11 10:19 ` [PULL v3 05/42] target/riscv: Add Shakti C class CPU Alistair Francis
2021-05-11 10:19 ` [PULL v3 06/42] riscv: Add initial support for Shakti C machine Alistair Francis
2021-05-11 10:19 ` [PULL v3 07/42] hw/char: Add Shakti UART emulation Alistair Francis
2021-05-11 10:19 ` [PULL v3 08/42] hw/riscv: Connect Shakti UART to Shakti platform Alistair Francis
2021-05-11 10:19 ` [PULL v3 09/42] target/riscv: Convert the RISC-V exceptions to an enum Alistair Francis
2021-05-11 10:19 ` [PULL v3 10/42] target/riscv: Use the RISCVException enum for CSR predicates Alistair Francis
2021-05-11 10:19 ` [PULL v3 11/42] target/riscv: Fix 32-bit HS mode access permissions Alistair Francis
2021-05-11 10:19 ` [PULL v3 12/42] target/riscv: Use the RISCVException enum for CSR operations Alistair Francis
2021-05-11 10:19 ` [PULL v3 13/42] target/riscv: Use RISCVException enum for CSR access Alistair Francis
2021-05-11 10:19 ` [PULL v3 14/42] MAINTAINERS: Update the RISC-V CPU Maintainers Alistair Francis
2021-05-11 10:19 ` [PULL v3 15/42] hw/opentitan: Update the interrupt layout Alistair Francis
2021-05-11 10:19 ` [PULL v3 16/42] hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine Alistair Francis
2021-05-11 10:19 ` [PULL v3 17/42] riscv: don't look at SUM when accessing memory from a debugger context Alistair Francis
2021-05-11 10:19 ` [PULL v3 18/42] target/riscv: Fixup saturate subtract function Alistair Francis
2021-05-11 10:19 ` [PULL v3 19/42] docs: Add documentation for shakti_c machine Alistair Francis
2021-05-11 10:19 ` [PULL v3 20/42] target/riscv: Fix the PMP is locked check when using TOR Alistair Francis
2021-05-11 10:19 ` [PULL v3 21/42] target/riscv: Define ePMP mseccfg Alistair Francis
2021-05-11 10:19 ` [PULL v3 22/42] target/riscv: Add the ePMP feature Alistair Francis
2021-05-11 10:19 ` [PULL v3 23/42] target/riscv: Add ePMP CSR access functions Alistair Francis
2021-05-11 10:19 ` [PULL v3 24/42] target/riscv: Implementation of enhanced PMP (ePMP) Alistair Francis
2021-05-20 13:51 ` Peter Maydell
2021-05-20 22:38 ` Alistair Francis
2021-05-11 10:19 ` [PULL v3 25/42] target/riscv: Add a config option for ePMP Alistair Francis
2021-05-11 10:19 ` [PULL v3 26/42] target/riscv/pmp: Remove outdated comment Alistair Francis
2021-05-11 10:19 ` [PULL v3 27/42] target/riscv: Add ePMP support for the Ibex CPU Alistair Francis
2021-05-11 10:19 ` [PULL v3 28/42] target/riscv: fix vrgather macro index variable type bug Alistair Francis
2021-05-11 10:19 ` [PULL v3 29/42] target/riscv: fix exception index on instruction access fault Alistair Francis
2021-05-11 10:19 ` [PULL v3 30/42] hw/riscv: Fix OT IBEX reset vector Alistair Francis
2021-05-11 10:19 ` [PULL v3 31/42] fpu/softfloat: set invalid excp flag for RISC-V muladd instructions Alistair Francis
2021-05-11 10:19 ` [PULL v3 32/42] target/riscv: fix a typo with interrupt names Alistair Francis
2021-05-11 10:19 ` [PULL v3 33/42] target/riscv: Remove the hardcoded RVXLEN macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 34/42] target/riscv: Remove the hardcoded SSTATUS_SD macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 35/42] target/riscv: Remove the hardcoded HGATP_MODE macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 36/42] target/riscv: Remove the hardcoded MSTATUS_SD macro Alistair Francis
2021-05-20 13:55 ` Peter Maydell
2021-05-20 22:55 ` Alistair Francis
2021-05-21 2:07 ` LIU Zhiwei
2021-05-25 21:47 ` Alistair Francis
2021-05-11 10:19 ` [PULL v3 37/42] target/riscv: Remove the hardcoded SATP_MODE macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 38/42] target/riscv: Remove the unused HSTATUS_WPRI macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 39/42] target/riscv: Remove an unused CASE_OP_32_64 macro Alistair Francis
2021-05-11 10:19 ` [PULL v3 40/42] target/riscv: Consolidate RV32/64 32-bit instructions Alistair Francis
2021-05-11 10:19 ` [PULL v3 41/42] target/riscv: Consolidate RV32/64 16-bit instructions Alistair Francis
2021-05-11 10:19 ` [PULL v3 42/42] target/riscv: Fix the RV64H decode comment Alistair Francis
2021-05-12 18:46 ` [PULL v3 00/42] riscv-to-apply queue Peter Maydell
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