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11 May 2021 03:00:50 -0700 IronPort-SDR: xOpD93eXPHWFqOOtioJlAYWyaaB1ItWKj0OISja7oWhkGw3y2DLD53wCw5lREmI7tGC7ukLTZi Pqk+9v4gu1X0ajTdfFxOF/uX33uKVYMqrQH2sTlwJNRSa8A8b70+pEQYnjvhIJsv4W46Rqkgi1 qEc4C1ZZ51dguLzT0OZdPsd0Zxxd4JqNELvQY0n5aKeD5DwPfRs4dCFbtZNz9NTY0XUAMjWa1x 0VqLPkQIgETtAUVKJSZCmyHsRT1QTMWeDT+VovekAja9b8BSTnHw5xHyohZWT15amIh6/CymJV 5Bk= WDCIronportException: Internal Received: from unknown (HELO alistair-risc6-laptop.wdc.com) ([10.225.165.48]) by uls-op-cesaip01.wdc.com with ESMTP; 11 May 2021 03:20:49 -0700 From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v3 15/42] hw/opentitan: Update the interrupt layout Date: Tue, 11 May 2021 20:19:24 +1000 Message-Id: <20210511101951.165287-16-alistair.francis@wdc.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210511101951.165287-1-alistair.francis@wdc.com> References: <20210511101951.165287-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=7584e029c=alistair.francis@wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Bin Meng , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Update the OpenTitan interrupt layout to match the latest OpenTitan bitstreams. This involves changing the Ibex PLIC memory layout and the UART interrupts. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Message-id: e92b696f1809c9fa4410da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com --- include/hw/riscv/opentitan.h | 16 ++++++++-------- hw/intc/ibex_plic.c | 20 ++++++++++---------- hw/riscv/opentitan.c | 8 ++++---- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index a5ea3a5e4e..aab9bc9245 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -82,14 +82,14 @@ enum { }; enum { - IBEX_UART_RX_PARITY_ERR_IRQ = 0x28, - IBEX_UART_RX_TIMEOUT_IRQ = 0x27, - IBEX_UART_RX_BREAK_ERR_IRQ = 0x26, - IBEX_UART_RX_FRAME_ERR_IRQ = 0x25, - IBEX_UART_RX_OVERFLOW_IRQ = 0x24, - IBEX_UART_TX_EMPTY_IRQ = 0x23, - IBEX_UART_RX_WATERMARK_IRQ = 0x22, - IBEX_UART_TX_WATERMARK_IRQ = 0x21, + IBEX_UART0_RX_PARITY_ERR_IRQ = 8, + IBEX_UART0_RX_TIMEOUT_IRQ = 7, + IBEX_UART0_RX_BREAK_ERR_IRQ = 6, + IBEX_UART0_RX_FRAME_ERR_IRQ = 5, + IBEX_UART0_RX_OVERFLOW_IRQ = 4, + IBEX_UART0_TX_EMPTY_IRQ = 3, + IBEX_UART0_RX_WATERMARK_IRQ = 2, + IBEX_UART0_TX_WATERMARK_IRQ = 1, }; #endif diff --git a/hw/intc/ibex_plic.c b/hw/intc/ibex_plic.c index c1b72fcab0..edf76e4f61 100644 --- a/hw/intc/ibex_plic.c +++ b/hw/intc/ibex_plic.c @@ -225,23 +225,23 @@ static void ibex_plic_irq_request(void *opaque, int irq, int level) static Property ibex_plic_properties[] = { DEFINE_PROP_UINT32("num-cpus", IbexPlicState, num_cpus, 1), - DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 80), + DEFINE_PROP_UINT32("num-sources", IbexPlicState, num_sources, 176), DEFINE_PROP_UINT32("pending-base", IbexPlicState, pending_base, 0), - DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 3), + DEFINE_PROP_UINT32("pending-num", IbexPlicState, pending_num, 6), - DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x0c), - DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 3), + DEFINE_PROP_UINT32("source-base", IbexPlicState, source_base, 0x18), + DEFINE_PROP_UINT32("source-num", IbexPlicState, source_num, 6), - DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x18), - DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 80), + DEFINE_PROP_UINT32("priority-base", IbexPlicState, priority_base, 0x30), + DEFINE_PROP_UINT32("priority-num", IbexPlicState, priority_num, 177), - DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x200), - DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 3), + DEFINE_PROP_UINT32("enable-base", IbexPlicState, enable_base, 0x300), + DEFINE_PROP_UINT32("enable-num", IbexPlicState, enable_num, 6), - DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x20c), + DEFINE_PROP_UINT32("threshold-base", IbexPlicState, threshold_base, 0x318), - DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x210), + DEFINE_PROP_UINT32("claim-base", IbexPlicState, claim_base, 0x31c), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index dc9dea117e..557d73726b 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -148,16 +148,16 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, qdev_get_gpio_in(DEVICE(&s->plic), - IBEX_UART_TX_WATERMARK_IRQ)); + IBEX_UART0_TX_WATERMARK_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 1, qdev_get_gpio_in(DEVICE(&s->plic), - IBEX_UART_RX_WATERMARK_IRQ)); + IBEX_UART0_RX_WATERMARK_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 2, qdev_get_gpio_in(DEVICE(&s->plic), - IBEX_UART_TX_EMPTY_IRQ)); + IBEX_UART0_TX_EMPTY_IRQ)); sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 3, qdev_get_gpio_in(DEVICE(&s->plic), - IBEX_UART_RX_OVERFLOW_IRQ)); + IBEX_UART0_RX_OVERFLOW_IRQ)); create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); -- 2.31.1