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Wed, 12 May 2021 10:53:17 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DF0F431B; Wed, 12 May 2021 03:53:13 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.30.106]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B352D3F719; Wed, 12 May 2021 03:53:11 -0700 (PDT) Date: Wed, 12 May 2021 11:53:08 +0100 From: Mark Rutland To: Fuad Tabba Cc: "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)" , Will Deacon , Catalin Marinas , Marc Zyngier , Ard Biesheuvel , James Morse , Alexandru Elisei , Suzuki K Poulose Subject: Re: [PATCH v1 01/13] arm64: Do not enable uaccess for flush_icache_range Message-ID: <20210512105308.GE88854@C02TD0UTHF1T.local> References: <20210511144252.3779113-1-tabba@google.com> <20210511144252.3779113-2-tabba@google.com> <20210511152255.GD8933@C02TD0UTHF1T.local> <20210512095935.GA88854@C02TD0UTHF1T.local> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210512_035316_444368_6B1B5B02 X-CRM114-Status: GOOD ( 22.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, May 12, 2021 at 11:29:53AM +0100, Fuad Tabba wrote: > Hi Mark, > > On Wed, May 12, 2021 at 10:59 AM Mark Rutland wrote: > > > > On Wed, May 12, 2021 at 09:52:28AM +0100, Fuad Tabba wrote: > > > Hi Mark, > > > > > > > > No functional change intended. > > > > > > > > There is a performance change here, since the existing > > > > `__flush_cache_user_range` takes IDC and DIC into account, whereas > > > > `invalidate_icache_by_line` does not. > > > > > > You're right. There is a performance change in this patch and a couple > > > of the others, which I will note in v2. However, I don't think that > > > this patch changes the behavior when it comes to IDC and DIC, does it? > > > > It shouldn't be a functional problem, but it means that the new > > `__flush_icache_range` will always perform redundant I-cache maintenance > > rather than skipping this when the cpu has DIC=1. > > Sorry, but I can't quite see how this patch is making a difference in > that regard. The existing code has __flush_icache_range fallthrough to > __flush_cache_user_range, where the alternative_if > ARM64_HAS_CACHE_{IDC,DIC} are invoked. > > In this patch, __flush_icache_range and __flush_cache_user_range share > the same code via the macro, where the alternative_ifs and branches > over invalidate_icache_by_line are still there and behave the same: > the macro jumps to 8 if ARM64_HAS_CACHE_DIC, avoiding any redundant > cache maintenance. > > Am I missing something else? No; you're absolutely right. I had misread the patch and thought the IDC/DIC parts didn't go into the common macro. That all looks fine. Sorry again for the noise. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel