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From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
To: <linux-arm-kernel@lists.infradead.org>,
	<linux-acpi@vger.kernel.org>, <iommu@lists.linux-foundation.org>
Cc: <linuxarm@huawei.com>, <lorenzo.pieralisi@arm.com>,
	<joro@8bytes.org>, <robin.murphy@arm.com>,
	<wanghuiqiang@huawei.com>, <guohanjun@huawei.com>,
	<steven.price@arm.com>, <Sami.Mujawar@arm.com>,
	<jon@solid-run.com>, <eric.auger@redhat.com>,
	<yangyicong@huawei.com>
Subject: [PATCH v4 5/8] iommu/arm-smmu-v3: Add bypass flag to arm_smmu_write_strtab_ent()
Date: Thu, 13 May 2021 14:45:47 +0100	[thread overview]
Message-ID: <20210513134550.2117-6-shameerali.kolothum.thodi@huawei.com> (raw)
In-Reply-To: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com>

By default, disable_bypass is set and any dev without an iommu domain
installs STE with CFG_ABORT during arm_smmu_init_bypass_stes(). Introduce
a "bypass" flag to arm_smmu_write_strtab_ent() so that we can force it to
install CFG_BYPASS STE for specific SIDs. This will be useful in follow
up patch to install bypass for IORT RMR SIDs.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 754bad6092c1..f9195b740f48 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -1174,7 +1174,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
 }
 
 static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
-				      __le64 *dst)
+				      __le64 *dst, bool bypass)
 {
 	/*
 	 * This is hideously complicated, but we only really care about
@@ -1245,7 +1245,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
 
 	/* Bypass/fault */
 	if (!smmu_domain || !(s1_cfg || s2_cfg)) {
-		if (!smmu_domain && disable_bypass)
+		if (!smmu_domain && disable_bypass && !bypass)
 			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);
 		else
 			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
@@ -1320,7 +1320,7 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent)
 	unsigned int i;
 
 	for (i = 0; i < nent; ++i) {
-		arm_smmu_write_strtab_ent(NULL, -1, strtab);
+		arm_smmu_write_strtab_ent(NULL, -1, strtab, false);
 		strtab += STRTAB_STE_DWORDS;
 	}
 }
@@ -2097,7 +2097,7 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)
 		if (j < i)
 			continue;
 
-		arm_smmu_write_strtab_ent(master, sid, step);
+		arm_smmu_write_strtab_ent(master, sid, step, false);
 	}
 }
 
-- 
2.17.1


WARNING: multiple messages have this Message-ID
From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
To: <linux-arm-kernel@lists.infradead.org>,
	<linux-acpi@vger.kernel.org>, <iommu@lists.linux-foundation.org>
Cc: jon@solid-run.com, linuxarm@huawei.com, steven.price@arm.com,
	guohanjun@huawei.com, yangyicong@huawei.com,
	Sami.Mujawar@arm.com, robin.murphy@arm.com,
	wanghuiqiang@huawei.com
Subject: [PATCH v4 5/8] iommu/arm-smmu-v3: Add bypass flag to arm_smmu_write_strtab_ent()
Date: Thu, 13 May 2021 14:45:47 +0100	[thread overview]
Message-ID: <20210513134550.2117-6-shameerali.kolothum.thodi@huawei.com> (raw)
In-Reply-To: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com>

By default, disable_bypass is set and any dev without an iommu domain
installs STE with CFG_ABORT during arm_smmu_init_bypass_stes(). Introduce
a "bypass" flag to arm_smmu_write_strtab_ent() so that we can force it to
install CFG_BYPASS STE for specific SIDs. This will be useful in follow
up patch to install bypass for IORT RMR SIDs.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 754bad6092c1..f9195b740f48 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -1174,7 +1174,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
 }
 
 static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
-				      __le64 *dst)
+				      __le64 *dst, bool bypass)
 {
 	/*
 	 * This is hideously complicated, but we only really care about
@@ -1245,7 +1245,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
 
 	/* Bypass/fault */
 	if (!smmu_domain || !(s1_cfg || s2_cfg)) {
-		if (!smmu_domain && disable_bypass)
+		if (!smmu_domain && disable_bypass && !bypass)
 			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);
 		else
 			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
@@ -1320,7 +1320,7 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent)
 	unsigned int i;
 
 	for (i = 0; i < nent; ++i) {
-		arm_smmu_write_strtab_ent(NULL, -1, strtab);
+		arm_smmu_write_strtab_ent(NULL, -1, strtab, false);
 		strtab += STRTAB_STE_DWORDS;
 	}
 }
@@ -2097,7 +2097,7 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)
 		if (j < i)
 			continue;
 
-		arm_smmu_write_strtab_ent(master, sid, step);
+		arm_smmu_write_strtab_ent(master, sid, step, false);
 	}
 }
 
-- 
2.17.1

_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID
From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
To: <linux-arm-kernel@lists.infradead.org>,
	<linux-acpi@vger.kernel.org>, <iommu@lists.linux-foundation.org>
Cc: <linuxarm@huawei.com>, <lorenzo.pieralisi@arm.com>,
	<joro@8bytes.org>, <robin.murphy@arm.com>,
	<wanghuiqiang@huawei.com>, <guohanjun@huawei.com>,
	<steven.price@arm.com>, <Sami.Mujawar@arm.com>,
	<jon@solid-run.com>, <eric.auger@redhat.com>,
	<yangyicong@huawei.com>
Subject: [PATCH v4 5/8] iommu/arm-smmu-v3: Add bypass flag to arm_smmu_write_strtab_ent()
Date: Thu, 13 May 2021 14:45:47 +0100	[thread overview]
Message-ID: <20210513134550.2117-6-shameerali.kolothum.thodi@huawei.com> (raw)
In-Reply-To: <20210513134550.2117-1-shameerali.kolothum.thodi@huawei.com>

By default, disable_bypass is set and any dev without an iommu domain
installs STE with CFG_ABORT during arm_smmu_init_bypass_stes(). Introduce
a "bypass" flag to arm_smmu_write_strtab_ent() so that we can force it to
install CFG_BYPASS STE for specific SIDs. This will be useful in follow
up patch to install bypass for IORT RMR SIDs.

Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
---
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 754bad6092c1..f9195b740f48 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -1174,7 +1174,7 @@ static void arm_smmu_sync_ste_for_sid(struct arm_smmu_device *smmu, u32 sid)
 }
 
 static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
-				      __le64 *dst)
+				      __le64 *dst, bool bypass)
 {
 	/*
 	 * This is hideously complicated, but we only really care about
@@ -1245,7 +1245,7 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
 
 	/* Bypass/fault */
 	if (!smmu_domain || !(s1_cfg || s2_cfg)) {
-		if (!smmu_domain && disable_bypass)
+		if (!smmu_domain && disable_bypass && !bypass)
 			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT);
 		else
 			val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS);
@@ -1320,7 +1320,7 @@ static void arm_smmu_init_bypass_stes(__le64 *strtab, unsigned int nent)
 	unsigned int i;
 
 	for (i = 0; i < nent; ++i) {
-		arm_smmu_write_strtab_ent(NULL, -1, strtab);
+		arm_smmu_write_strtab_ent(NULL, -1, strtab, false);
 		strtab += STRTAB_STE_DWORDS;
 	}
 }
@@ -2097,7 +2097,7 @@ static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master)
 		if (j < i)
 			continue;
 
-		arm_smmu_write_strtab_ent(master, sid, step);
+		arm_smmu_write_strtab_ent(master, sid, step, false);
 	}
 }
 
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2021-05-13 13:47 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-13 13:45 [PATCH v4 0/8] ACPI/IORT: Support for IORT RMR node Shameer Kolothum
2021-05-13 13:45 ` Shameer Kolothum
2021-05-13 13:45 ` Shameer Kolothum
2021-05-13 13:45 ` [PATCH v4 1/8] ACPI/IORT: Add support for RMR node parsing Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-06-03 11:36   ` Lorenzo Pieralisi
2021-06-03 11:36     ` Lorenzo Pieralisi
2021-06-03 11:36     ` Lorenzo Pieralisi
2021-06-03 11:48     ` Shameerali Kolothum Thodi
2021-06-03 11:48       ` Shameerali Kolothum Thodi
2021-06-03 11:48       ` Shameerali Kolothum Thodi
2021-05-13 13:45 ` [PATCH v4 2/8] iommu/dma: Introduce generic helper to retrieve RMR info Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-18  8:49   ` Joerg Roedel
2021-05-18  8:49     ` Joerg Roedel
2021-05-18  8:49     ` Joerg Roedel
2021-05-19  9:30     ` Shameerali Kolothum Thodi
2021-05-19  9:30       ` Shameerali Kolothum Thodi
2021-05-19  9:30       ` Shameerali Kolothum Thodi
2021-05-19 11:48       ` Robin Murphy
2021-05-19 11:48         ` Robin Murphy
2021-05-19 11:48         ` Robin Murphy
2021-05-13 13:45 ` [PATCH v4 3/8] ACPI/IORT: Add a helper to retrieve RMR memory regions Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-06-03 11:20   ` Lorenzo Pieralisi
2021-06-03 11:20     ` Lorenzo Pieralisi
2021-06-03 11:20     ` Lorenzo Pieralisi
2021-05-13 13:45 ` [PATCH v4 4/8] iommu/arm-smmu-v3: Introduce strtab init helper Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-13 13:45 ` Shameer Kolothum [this message]
2021-05-13 13:45   ` [PATCH v4 5/8] iommu/arm-smmu-v3: Add bypass flag to arm_smmu_write_strtab_ent() Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-13 13:45 ` [PATCH v4 6/8] iommu/arm-smmu-v3: Get associated RMR info and install bypass STE Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-13 13:45 ` [PATCH v4 7/8] iommu/arm-smmu: Get associated RMR info and install bypass SMR Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-13 13:45 ` [PATCH v4 8/8] iommu/dma: Reserve any RMR regions associated with a dev Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-13 13:45   ` Shameer Kolothum
2021-05-21 12:55 ` [PATCH v4 0/8] ACPI/IORT: Support for IORT RMR node Steven Price
2021-05-21 12:55   ` Steven Price
2021-05-21 12:55   ` Steven Price
2021-05-21 13:12   ` Shameerali Kolothum Thodi
2021-05-21 13:12     ` Shameerali Kolothum Thodi
2021-05-21 13:12     ` Shameerali Kolothum Thodi

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