* [Nouveau] [PATCH v6 0/9] drm: Extract DPCD backlight helpers from i915, add support in nouveau
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau; +Cc: greg.depoire, Rajeev Nandan
This series:
* Cleans up i915's DPCD backlight code a little bit
* Extracts i915's DPCD backlight code into a set of shared DRM helpers
* Starts using those helpers in nouveau to add support to nouveau for
DPCD backlight control
v2 series-wide changes:
* Rebase
v3 series-wide changes:
* Split up the changes to intel's backlight code into separate patches
v4 series-wide changes:
* Don't forget to actually include the patch that starts using these
helpers in nouveau
v5 series-wide changes:
* Rebase
* Use new drm_dbg_*() logging helpers
v6 series-wide changes:
* Add a bunch of R-bs that got dropped by accident
Lyude Paul (9):
drm/i915/dpcd_bl: Remove redundant AUX backlight frequency
calculations
drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
drm/i915/dpcd_bl: Cache some backlight capabilities in
intel_panel.backlight
drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't
read PWMGEN_BIT_COUNT
drm/i915/dpcd_bl: Print return codes for VESA backlight failures
drm/dp: Extract i915's eDP backlight code into DRM helpers
drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
drivers/gpu/drm/drm_dp_helper.c | 347 ++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 2 +-
.../drm/i915/display/intel_dp_aux_backlight.c | 329 ++---------------
drivers/gpu/drm/nouveau/dispnv50/disp.c | 28 ++
drivers/gpu/drm/nouveau/nouveau_backlight.c | 166 ++++++++-
drivers/gpu/drm/nouveau/nouveau_connector.h | 9 +-
drivers/gpu/drm/nouveau/nouveau_encoder.h | 1 +
include/drm/drm_dp_helper.h | 48 +++
8 files changed, 622 insertions(+), 308 deletions(-)
--
2.31.1
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v6 0/9] drm: Extract DPCD backlight helpers from i915, add support in nouveau
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau; +Cc: greg.depoire, Rajeev Nandan
This series:
* Cleans up i915's DPCD backlight code a little bit
* Extracts i915's DPCD backlight code into a set of shared DRM helpers
* Starts using those helpers in nouveau to add support to nouveau for
DPCD backlight control
v2 series-wide changes:
* Rebase
v3 series-wide changes:
* Split up the changes to intel's backlight code into separate patches
v4 series-wide changes:
* Don't forget to actually include the patch that starts using these
helpers in nouveau
v5 series-wide changes:
* Rebase
* Use new drm_dbg_*() logging helpers
v6 series-wide changes:
* Add a bunch of R-bs that got dropped by accident
Lyude Paul (9):
drm/i915/dpcd_bl: Remove redundant AUX backlight frequency
calculations
drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
drm/i915/dpcd_bl: Cache some backlight capabilities in
intel_panel.backlight
drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't
read PWMGEN_BIT_COUNT
drm/i915/dpcd_bl: Print return codes for VESA backlight failures
drm/dp: Extract i915's eDP backlight code into DRM helpers
drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
drivers/gpu/drm/drm_dp_helper.c | 347 ++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 2 +-
.../drm/i915/display/intel_dp_aux_backlight.c | 329 ++---------------
drivers/gpu/drm/nouveau/dispnv50/disp.c | 28 ++
drivers/gpu/drm/nouveau/nouveau_backlight.c | 166 ++++++++-
drivers/gpu/drm/nouveau/nouveau_connector.h | 9 +-
drivers/gpu/drm/nouveau/nouveau_encoder.h | 1 +
include/drm/drm_dp_helper.h | 48 +++
8 files changed, 622 insertions(+), 308 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v6 0/9] drm: Extract DPCD backlight helpers from i915, add support in nouveau
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau; +Cc: greg.depoire, Rajeev Nandan
This series:
* Cleans up i915's DPCD backlight code a little bit
* Extracts i915's DPCD backlight code into a set of shared DRM helpers
* Starts using those helpers in nouveau to add support to nouveau for
DPCD backlight control
v2 series-wide changes:
* Rebase
v3 series-wide changes:
* Split up the changes to intel's backlight code into separate patches
v4 series-wide changes:
* Don't forget to actually include the patch that starts using these
helpers in nouveau
v5 series-wide changes:
* Rebase
* Use new drm_dbg_*() logging helpers
v6 series-wide changes:
* Add a bunch of R-bs that got dropped by accident
Lyude Paul (9):
drm/i915/dpcd_bl: Remove redundant AUX backlight frequency
calculations
drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
drm/i915/dpcd_bl: Cache some backlight capabilities in
intel_panel.backlight
drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't
read PWMGEN_BIT_COUNT
drm/i915/dpcd_bl: Print return codes for VESA backlight failures
drm/dp: Extract i915's eDP backlight code into DRM helpers
drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
drivers/gpu/drm/drm_dp_helper.c | 347 ++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 2 +-
.../drm/i915/display/intel_dp_aux_backlight.c | 329 ++---------------
drivers/gpu/drm/nouveau/dispnv50/disp.c | 28 ++
drivers/gpu/drm/nouveau/nouveau_backlight.c | 166 ++++++++-
drivers/gpu/drm/nouveau/nouveau_connector.h | 9 +-
drivers/gpu/drm/nouveau/nouveau_encoder.h | 1 +
include/drm/drm_dp_helper.h | 48 +++
8 files changed, 622 insertions(+), 308 deletions(-)
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
2021-05-14 18:14 ` Lyude Paul
(?)
(?)
@ 2021-05-14 18:14 ` Lyude Paul
-1 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Jani Nikula, Dave Airlie,
Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, David Airlie,
Daniel Vetter, Ville Syrjälä,
Imre Deak, Uma Shankar, Ramalingam C, Anshuman Gupta,
Dave Airlie, Gwan-gyeong Mun, Lucas De Marchi, Sean Paul,
open list
Noticed this while moving all of the VESA backlight code in i915 over to
DRM helpers: it would appear that we calculate the frequency value we want
to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
actually changes during runtime. So, let's simplify things by just caching
this value in intel_panel.backlight, and re-writing it as-needed.
Changes since v1:
* Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
.../drm/i915/display/intel_display_types.h | 1 +
.../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
2 files changed, 20 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9c0adfc60c6f..7054a37363fb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -311,6 +311,7 @@ struct intel_panel {
union {
struct {
u8 pwmgen_bit_count;
+ u8 pwm_freq_pre_divider;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 8e9ac9ba1d38..68bfe50ada59 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
}
}
-/*
- * Set PWM Frequency divider to match desired frequency in vbt.
- * The PWM Frequency is calculated as 27Mhz / (F x P).
- * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
- * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
- * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
- * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
- */
-static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
-{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
- int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
-
- freq = dev_priv->vbt.backlight.pwm_freq_hz;
- if (!freq) {
- drm_dbg_kms(&dev_priv->drm,
- "Use panel default backlight frequency\n");
- return false;
- }
-
- fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
- f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
- fxp_actual = f << pn;
-
- /* Ensure frequency is within 25% of desired value */
- fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
- fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
-
- if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
- drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
- return false;
- }
-
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
- drm_dbg_kms(&dev_priv->drm,
- "Failed to write aux backlight freq\n");
- return false;
- }
- return true;
-}
-
static void
intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
@@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
break;
}
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
- if (intel_dp_aux_vesa_set_pwm_freq(connector))
+ if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
+ panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
+ else
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
+ }
if (new_dpcd_buf != dpcd_buf) {
if (drm_dp_dpcd_writeb(&intel_dp->aux,
@@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
false);
}
+/*
+ * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
+ * The PWM Frequency is calculated as 27Mhz / (F x P).
+ * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
+ * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
+ * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
+ * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
+ */
static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
@@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ /* Ensure frequency is within 25% of desired value */
fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
+
if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
drm_dbg_kms(&i915->drm,
"VBT defined backlight frequency out of range\n");
@@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
"Failed to write aux pwmgen bit count\n");
return max_backlight;
}
+
panel->backlight.edp.vesa.pwmgen_bit_count = pn;
+ if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
+ panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
max_backlight = (1 << pn) - 1;
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Nouveau] [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Ramalingam C, David Airlie,
Joonas Lahtinen, Lucas De Marchi, open list, Jani Nikula,
Anshuman Gupta, Jani Nikula, Uma Shankar, Sean Paul,
Daniel Vetter, Rodrigo Vivi, Dave Airlie, Gwan-gyeong Mun,
Imre Deak, Ville Syrjälä
Noticed this while moving all of the VESA backlight code in i915 over to
DRM helpers: it would appear that we calculate the frequency value we want
to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
actually changes during runtime. So, let's simplify things by just caching
this value in intel_panel.backlight, and re-writing it as-needed.
Changes since v1:
* Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
.../drm/i915/display/intel_display_types.h | 1 +
.../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
2 files changed, 20 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9c0adfc60c6f..7054a37363fb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -311,6 +311,7 @@ struct intel_panel {
union {
struct {
u8 pwmgen_bit_count;
+ u8 pwm_freq_pre_divider;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 8e9ac9ba1d38..68bfe50ada59 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
}
}
-/*
- * Set PWM Frequency divider to match desired frequency in vbt.
- * The PWM Frequency is calculated as 27Mhz / (F x P).
- * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
- * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
- * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
- * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
- */
-static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
-{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
- int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
-
- freq = dev_priv->vbt.backlight.pwm_freq_hz;
- if (!freq) {
- drm_dbg_kms(&dev_priv->drm,
- "Use panel default backlight frequency\n");
- return false;
- }
-
- fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
- f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
- fxp_actual = f << pn;
-
- /* Ensure frequency is within 25% of desired value */
- fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
- fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
-
- if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
- drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
- return false;
- }
-
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
- drm_dbg_kms(&dev_priv->drm,
- "Failed to write aux backlight freq\n");
- return false;
- }
- return true;
-}
-
static void
intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
@@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
break;
}
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
- if (intel_dp_aux_vesa_set_pwm_freq(connector))
+ if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
+ panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
+ else
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
+ }
if (new_dpcd_buf != dpcd_buf) {
if (drm_dp_dpcd_writeb(&intel_dp->aux,
@@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
false);
}
+/*
+ * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
+ * The PWM Frequency is calculated as 27Mhz / (F x P).
+ * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
+ * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
+ * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
+ * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
+ */
static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
@@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ /* Ensure frequency is within 25% of desired value */
fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
+
if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
drm_dbg_kms(&i915->drm,
"VBT defined backlight frequency out of range\n");
@@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
"Failed to write aux pwmgen bit count\n");
return max_backlight;
}
+
panel->backlight.edp.vesa.pwmgen_bit_count = pn;
+ if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
+ panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
max_backlight = (1 << pn) - 1;
--
2.31.1
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, David Airlie, Lucas De Marchi,
open list, Anshuman Gupta, Jani Nikula, Uma Shankar, Sean Paul,
Rodrigo Vivi, Dave Airlie, Gwan-gyeong Mun
Noticed this while moving all of the VESA backlight code in i915 over to
DRM helpers: it would appear that we calculate the frequency value we want
to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
actually changes during runtime. So, let's simplify things by just caching
this value in intel_panel.backlight, and re-writing it as-needed.
Changes since v1:
* Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
.../drm/i915/display/intel_display_types.h | 1 +
.../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
2 files changed, 20 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9c0adfc60c6f..7054a37363fb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -311,6 +311,7 @@ struct intel_panel {
union {
struct {
u8 pwmgen_bit_count;
+ u8 pwm_freq_pre_divider;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 8e9ac9ba1d38..68bfe50ada59 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
}
}
-/*
- * Set PWM Frequency divider to match desired frequency in vbt.
- * The PWM Frequency is calculated as 27Mhz / (F x P).
- * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
- * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
- * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
- * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
- */
-static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
-{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
- int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
-
- freq = dev_priv->vbt.backlight.pwm_freq_hz;
- if (!freq) {
- drm_dbg_kms(&dev_priv->drm,
- "Use panel default backlight frequency\n");
- return false;
- }
-
- fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
- f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
- fxp_actual = f << pn;
-
- /* Ensure frequency is within 25% of desired value */
- fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
- fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
-
- if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
- drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
- return false;
- }
-
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
- drm_dbg_kms(&dev_priv->drm,
- "Failed to write aux backlight freq\n");
- return false;
- }
- return true;
-}
-
static void
intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
@@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
break;
}
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
- if (intel_dp_aux_vesa_set_pwm_freq(connector))
+ if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
+ panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
+ else
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
+ }
if (new_dpcd_buf != dpcd_buf) {
if (drm_dp_dpcd_writeb(&intel_dp->aux,
@@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
false);
}
+/*
+ * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
+ * The PWM Frequency is calculated as 27Mhz / (F x P).
+ * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
+ * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
+ * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
+ * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
+ */
static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
@@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ /* Ensure frequency is within 25% of desired value */
fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
+
if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
drm_dbg_kms(&i915->drm,
"VBT defined backlight frequency out of range\n");
@@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
"Failed to write aux pwmgen bit count\n");
return max_backlight;
}
+
panel->backlight.edp.vesa.pwmgen_bit_count = pn;
+ if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
+ panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
max_backlight = (1 << pn) - 1;
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, David Airlie, Lucas De Marchi,
open list, Jani Nikula, Sean Paul, Dave Airlie
Noticed this while moving all of the VESA backlight code in i915 over to
DRM helpers: it would appear that we calculate the frequency value we want
to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
actually changes during runtime. So, let's simplify things by just caching
this value in intel_panel.backlight, and re-writing it as-needed.
Changes since v1:
* Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
.../drm/i915/display/intel_display_types.h | 1 +
.../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
2 files changed, 20 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9c0adfc60c6f..7054a37363fb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -311,6 +311,7 @@ struct intel_panel {
union {
struct {
u8 pwmgen_bit_count;
+ u8 pwm_freq_pre_divider;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 8e9ac9ba1d38..68bfe50ada59 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
}
}
-/*
- * Set PWM Frequency divider to match desired frequency in vbt.
- * The PWM Frequency is calculated as 27Mhz / (F x P).
- * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
- * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
- * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
- * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
- */
-static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
-{
- struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
- int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
-
- freq = dev_priv->vbt.backlight.pwm_freq_hz;
- if (!freq) {
- drm_dbg_kms(&dev_priv->drm,
- "Use panel default backlight frequency\n");
- return false;
- }
-
- fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
- f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
- fxp_actual = f << pn;
-
- /* Ensure frequency is within 25% of desired value */
- fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
- fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
-
- if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
- drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
- return false;
- }
-
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
- drm_dbg_kms(&dev_priv->drm,
- "Failed to write aux backlight freq\n");
- return false;
- }
- return true;
-}
-
static void
intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
@@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
break;
}
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
- if (intel_dp_aux_vesa_set_pwm_freq(connector))
+ if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
+ panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
+ else
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
+ }
if (new_dpcd_buf != dpcd_buf) {
if (drm_dp_dpcd_writeb(&intel_dp->aux,
@@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
false);
}
+/*
+ * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
+ * The PWM Frequency is calculated as 27Mhz / (F x P).
+ * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
+ * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
+ * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
+ * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
+ */
static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
{
struct drm_i915_private *i915 = to_i915(connector->base.dev);
@@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ /* Ensure frequency is within 25% of desired value */
fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
+
if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
drm_dbg_kms(&i915->drm,
"VBT defined backlight frequency out of range\n");
@@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
"Failed to write aux pwmgen bit count\n");
return max_backlight;
}
+
panel->backlight.edp.vesa.pwmgen_bit_count = pn;
+ if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
+ panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
max_backlight = (1 << pn) - 1;
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 2/9] drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
2021-05-14 18:14 ` Lyude Paul
(?)
(?)
@ 2021-05-14 18:14 ` Lyude Paul
-1 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Rodrigo Vivi, Jani Nikula,
Joonas Lahtinen, David Airlie, Daniel Vetter,
Ville Syrjälä,
Sean Paul, open list
This is kind of an annoying aspect of DRM's DP helpers:
drm_dp_dpcd_readb/writeb() return the size of bytes read/written on
success, thus we want to check against that instead of checking if the
return value is less than 0.
I'll probably be fixing this in the near future once I start doing DP work
again, also because I'd rather not mix a tree-wide refactor like that in
with a patch series intended to be around introducing DP backlight helpers.
So, for now let's just handle the return values from each function
correctly.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 41 +++++++++----------
1 file changed, 19 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 68bfe50ada59..1dbe38282ebe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -107,7 +107,7 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
u8 tcon_cap[4];
ret = drm_dp_dpcd_read(aux, INTEL_EDP_HDR_TCON_CAP0, tcon_cap, sizeof(tcon_cap));
- if (ret < 0)
+ if (ret != sizeof(tcon_cap))
return false;
if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP))
@@ -137,7 +137,7 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe
u8 tmp;
u8 buf[2] = { 0 };
- if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) < 0) {
+ if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) {
drm_err(&i915->drm, "Failed to read current backlight mode from DPCD\n");
return 0;
}
@@ -153,7 +153,8 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe
return panel->backlight.max;
}
- if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf, sizeof(buf)) < 0) {
+ if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,
+ sizeof(buf)) != sizeof(buf)) {
drm_err(&i915->drm, "Failed to read brightness from DPCD\n");
return 0;
}
@@ -172,7 +173,8 @@ intel_dp_aux_hdr_set_aux_backlight(const struct drm_connector_state *conn_state,
buf[0] = level & 0xFF;
buf[1] = (level & 0xFF00) >> 8;
- if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf, 4) < 0)
+ if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,
+ sizeof(buf)) != sizeof(buf))
drm_err(dev, "Failed to write brightness level to DPCD\n");
}
@@ -203,7 +205,7 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
u8 old_ctrl, ctrl;
ret = drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl);
- if (ret < 0) {
+ if (ret != 1) {
drm_err(&i915->drm, "Failed to read current backlight control mode: %d\n", ret);
return;
}
@@ -221,7 +223,7 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
}
if (ctrl != old_ctrl)
- if (drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) < 0)
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1)
drm_err(&i915->drm, "Failed to configure DPCD brightness controls\n");
}
@@ -277,8 +279,7 @@ static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
return;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- ®_val) < 0) {
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
DP_EDP_DISPLAY_CONTROL_REGISTER);
return;
@@ -332,8 +333,8 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
return connector->panel.backlight.max;
- if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
- &read_val, sizeof(read_val)) < 0) {
+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
+ sizeof(read_val)) != sizeof(read_val)) {
drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
return 0;
@@ -365,8 +366,8 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
vals[0] = (level & 0xFF00) >> 8;
vals[1] = (level & 0xFF);
}
- if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
- vals, sizeof(vals)) < 0) {
+ if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
+ sizeof(vals)) != sizeof(vals)) {
drm_dbg_kms(&i915->drm,
"Failed to write aux backlight level\n");
return;
@@ -401,9 +402,8 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT,
- pwmgen_bit_count) < 0)
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT,
+ pwmgen_bit_count) != 1)
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
@@ -424,11 +424,9 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
if (new_dpcd_buf != dpcd_buf) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux backlight mode\n");
- }
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+ new_dpcd_buf) != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode\n");
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
@@ -519,8 +517,7 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
}
drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) {
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn) != 1) {
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
return max_backlight;
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Nouveau] [PATCH v6 2/9] drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Joonas Lahtinen, open list,
Jani Nikula, David Airlie, Sean Paul, Daniel Vetter,
Rodrigo Vivi, Ville Syrjälä
This is kind of an annoying aspect of DRM's DP helpers:
drm_dp_dpcd_readb/writeb() return the size of bytes read/written on
success, thus we want to check against that instead of checking if the
return value is less than 0.
I'll probably be fixing this in the near future once I start doing DP work
again, also because I'd rather not mix a tree-wide refactor like that in
with a patch series intended to be around introducing DP backlight helpers.
So, for now let's just handle the return values from each function
correctly.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 41 +++++++++----------
1 file changed, 19 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 68bfe50ada59..1dbe38282ebe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -107,7 +107,7 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
u8 tcon_cap[4];
ret = drm_dp_dpcd_read(aux, INTEL_EDP_HDR_TCON_CAP0, tcon_cap, sizeof(tcon_cap));
- if (ret < 0)
+ if (ret != sizeof(tcon_cap))
return false;
if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP))
@@ -137,7 +137,7 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe
u8 tmp;
u8 buf[2] = { 0 };
- if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) < 0) {
+ if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) {
drm_err(&i915->drm, "Failed to read current backlight mode from DPCD\n");
return 0;
}
@@ -153,7 +153,8 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe
return panel->backlight.max;
}
- if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf, sizeof(buf)) < 0) {
+ if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,
+ sizeof(buf)) != sizeof(buf)) {
drm_err(&i915->drm, "Failed to read brightness from DPCD\n");
return 0;
}
@@ -172,7 +173,8 @@ intel_dp_aux_hdr_set_aux_backlight(const struct drm_connector_state *conn_state,
buf[0] = level & 0xFF;
buf[1] = (level & 0xFF00) >> 8;
- if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf, 4) < 0)
+ if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,
+ sizeof(buf)) != sizeof(buf))
drm_err(dev, "Failed to write brightness level to DPCD\n");
}
@@ -203,7 +205,7 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
u8 old_ctrl, ctrl;
ret = drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl);
- if (ret < 0) {
+ if (ret != 1) {
drm_err(&i915->drm, "Failed to read current backlight control mode: %d\n", ret);
return;
}
@@ -221,7 +223,7 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
}
if (ctrl != old_ctrl)
- if (drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) < 0)
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1)
drm_err(&i915->drm, "Failed to configure DPCD brightness controls\n");
}
@@ -277,8 +279,7 @@ static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
return;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- ®_val) < 0) {
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
DP_EDP_DISPLAY_CONTROL_REGISTER);
return;
@@ -332,8 +333,8 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
return connector->panel.backlight.max;
- if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
- &read_val, sizeof(read_val)) < 0) {
+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
+ sizeof(read_val)) != sizeof(read_val)) {
drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
return 0;
@@ -365,8 +366,8 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
vals[0] = (level & 0xFF00) >> 8;
vals[1] = (level & 0xFF);
}
- if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
- vals, sizeof(vals)) < 0) {
+ if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
+ sizeof(vals)) != sizeof(vals)) {
drm_dbg_kms(&i915->drm,
"Failed to write aux backlight level\n");
return;
@@ -401,9 +402,8 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT,
- pwmgen_bit_count) < 0)
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT,
+ pwmgen_bit_count) != 1)
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
@@ -424,11 +424,9 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
if (new_dpcd_buf != dpcd_buf) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux backlight mode\n");
- }
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+ new_dpcd_buf) != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode\n");
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
@@ -519,8 +517,7 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
}
drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) {
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn) != 1) {
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
return max_backlight;
--
2.31.1
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 2/9] drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, open list, David Airlie, Sean Paul,
Rodrigo Vivi
This is kind of an annoying aspect of DRM's DP helpers:
drm_dp_dpcd_readb/writeb() return the size of bytes read/written on
success, thus we want to check against that instead of checking if the
return value is less than 0.
I'll probably be fixing this in the near future once I start doing DP work
again, also because I'd rather not mix a tree-wide refactor like that in
with a patch series intended to be around introducing DP backlight helpers.
So, for now let's just handle the return values from each function
correctly.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 41 +++++++++----------
1 file changed, 19 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 68bfe50ada59..1dbe38282ebe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -107,7 +107,7 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
u8 tcon_cap[4];
ret = drm_dp_dpcd_read(aux, INTEL_EDP_HDR_TCON_CAP0, tcon_cap, sizeof(tcon_cap));
- if (ret < 0)
+ if (ret != sizeof(tcon_cap))
return false;
if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP))
@@ -137,7 +137,7 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe
u8 tmp;
u8 buf[2] = { 0 };
- if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) < 0) {
+ if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) {
drm_err(&i915->drm, "Failed to read current backlight mode from DPCD\n");
return 0;
}
@@ -153,7 +153,8 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe
return panel->backlight.max;
}
- if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf, sizeof(buf)) < 0) {
+ if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,
+ sizeof(buf)) != sizeof(buf)) {
drm_err(&i915->drm, "Failed to read brightness from DPCD\n");
return 0;
}
@@ -172,7 +173,8 @@ intel_dp_aux_hdr_set_aux_backlight(const struct drm_connector_state *conn_state,
buf[0] = level & 0xFF;
buf[1] = (level & 0xFF00) >> 8;
- if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf, 4) < 0)
+ if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,
+ sizeof(buf)) != sizeof(buf))
drm_err(dev, "Failed to write brightness level to DPCD\n");
}
@@ -203,7 +205,7 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
u8 old_ctrl, ctrl;
ret = drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl);
- if (ret < 0) {
+ if (ret != 1) {
drm_err(&i915->drm, "Failed to read current backlight control mode: %d\n", ret);
return;
}
@@ -221,7 +223,7 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
}
if (ctrl != old_ctrl)
- if (drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) < 0)
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1)
drm_err(&i915->drm, "Failed to configure DPCD brightness controls\n");
}
@@ -277,8 +279,7 @@ static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
return;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- ®_val) < 0) {
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
DP_EDP_DISPLAY_CONTROL_REGISTER);
return;
@@ -332,8 +333,8 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
return connector->panel.backlight.max;
- if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
- &read_val, sizeof(read_val)) < 0) {
+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
+ sizeof(read_val)) != sizeof(read_val)) {
drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
return 0;
@@ -365,8 +366,8 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
vals[0] = (level & 0xFF00) >> 8;
vals[1] = (level & 0xFF);
}
- if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
- vals, sizeof(vals)) < 0) {
+ if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
+ sizeof(vals)) != sizeof(vals)) {
drm_dbg_kms(&i915->drm,
"Failed to write aux backlight level\n");
return;
@@ -401,9 +402,8 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT,
- pwmgen_bit_count) < 0)
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT,
+ pwmgen_bit_count) != 1)
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
@@ -424,11 +424,9 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
if (new_dpcd_buf != dpcd_buf) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux backlight mode\n");
- }
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+ new_dpcd_buf) != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode\n");
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
@@ -519,8 +517,7 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
}
drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) {
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn) != 1) {
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
return max_backlight;
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v6 2/9] drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, open list, David Airlie, Sean Paul
This is kind of an annoying aspect of DRM's DP helpers:
drm_dp_dpcd_readb/writeb() return the size of bytes read/written on
success, thus we want to check against that instead of checking if the
return value is less than 0.
I'll probably be fixing this in the near future once I start doing DP work
again, also because I'd rather not mix a tree-wide refactor like that in
with a patch series intended to be around introducing DP backlight helpers.
So, for now let's just handle the return values from each function
correctly.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 41 +++++++++----------
1 file changed, 19 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 68bfe50ada59..1dbe38282ebe 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -107,7 +107,7 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
u8 tcon_cap[4];
ret = drm_dp_dpcd_read(aux, INTEL_EDP_HDR_TCON_CAP0, tcon_cap, sizeof(tcon_cap));
- if (ret < 0)
+ if (ret != sizeof(tcon_cap))
return false;
if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP))
@@ -137,7 +137,7 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe
u8 tmp;
u8 buf[2] = { 0 };
- if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) < 0) {
+ if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) {
drm_err(&i915->drm, "Failed to read current backlight mode from DPCD\n");
return 0;
}
@@ -153,7 +153,8 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe
return panel->backlight.max;
}
- if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf, sizeof(buf)) < 0) {
+ if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,
+ sizeof(buf)) != sizeof(buf)) {
drm_err(&i915->drm, "Failed to read brightness from DPCD\n");
return 0;
}
@@ -172,7 +173,8 @@ intel_dp_aux_hdr_set_aux_backlight(const struct drm_connector_state *conn_state,
buf[0] = level & 0xFF;
buf[1] = (level & 0xFF00) >> 8;
- if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf, 4) < 0)
+ if (drm_dp_dpcd_write(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf,
+ sizeof(buf)) != sizeof(buf))
drm_err(dev, "Failed to write brightness level to DPCD\n");
}
@@ -203,7 +205,7 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
u8 old_ctrl, ctrl;
ret = drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl);
- if (ret < 0) {
+ if (ret != 1) {
drm_err(&i915->drm, "Failed to read current backlight control mode: %d\n", ret);
return;
}
@@ -221,7 +223,7 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
}
if (ctrl != old_ctrl)
- if (drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) < 0)
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1)
drm_err(&i915->drm, "Failed to configure DPCD brightness controls\n");
}
@@ -277,8 +279,7 @@ static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
return;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- ®_val) < 0) {
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
DP_EDP_DISPLAY_CONTROL_REGISTER);
return;
@@ -332,8 +333,8 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
return connector->panel.backlight.max;
- if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
- &read_val, sizeof(read_val)) < 0) {
+ if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
+ sizeof(read_val)) != sizeof(read_val)) {
drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
return 0;
@@ -365,8 +366,8 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
vals[0] = (level & 0xFF00) >> 8;
vals[1] = (level & 0xFF);
}
- if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB,
- vals, sizeof(vals)) < 0) {
+ if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
+ sizeof(vals)) != sizeof(vals)) {
drm_dbg_kms(&i915->drm,
"Failed to write aux backlight level\n");
return;
@@ -401,9 +402,8 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT,
- pwmgen_bit_count) < 0)
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT,
+ pwmgen_bit_count) != 1)
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
@@ -424,11 +424,9 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
if (new_dpcd_buf != dpcd_buf) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf) < 0) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux backlight mode\n");
- }
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+ new_dpcd_buf) != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode\n");
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
@@ -519,8 +517,7 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
}
drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- if (drm_dp_dpcd_writeb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT, pn) < 0) {
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn) != 1) {
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
return max_backlight;
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 3/9] drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
2021-05-14 18:14 ` Lyude Paul
(?)
(?)
@ 2021-05-14 18:14 ` Lyude Paul
-1 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Rodrigo Vivi, Jani Nikula,
Joonas Lahtinen, David Airlie, Daniel Vetter,
Ville Syrjälä,
Sean Paul, open list
Get rid of the extraneous switch case in here, and just open code
edp_backlight_mode as we only ever use it once.
v4:
* Check that backlight mode is DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD, not
DP_EDP_BACKLIGHT_CONTROL_MODE_MASK - imirkin
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../gpu/drm/i915/display/intel_dp_aux_backlight.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1dbe38282ebe..1ab82933afb5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -382,7 +382,7 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
- u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode;
+ u8 dpcd_buf, new_dpcd_buf;
u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
if (drm_dp_dpcd_readb(&intel_dp->aux,
@@ -393,12 +393,8 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
new_dpcd_buf = dpcd_buf;
- edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
- switch (edp_backlight_mode) {
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM:
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET:
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT:
+ if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
@@ -406,13 +402,6 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
pwmgen_bit_count) != 1)
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
-
- break;
-
- /* Do nothing when it is already DPCD mode */
- case DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD:
- default:
- break;
}
if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Nouveau] [PATCH v6 3/9] drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Joonas Lahtinen, open list,
Jani Nikula, David Airlie, Sean Paul, Daniel Vetter,
Rodrigo Vivi, Ville Syrjälä
Get rid of the extraneous switch case in here, and just open code
edp_backlight_mode as we only ever use it once.
v4:
* Check that backlight mode is DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD, not
DP_EDP_BACKLIGHT_CONTROL_MODE_MASK - imirkin
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../gpu/drm/i915/display/intel_dp_aux_backlight.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1dbe38282ebe..1ab82933afb5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -382,7 +382,7 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
- u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode;
+ u8 dpcd_buf, new_dpcd_buf;
u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
if (drm_dp_dpcd_readb(&intel_dp->aux,
@@ -393,12 +393,8 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
new_dpcd_buf = dpcd_buf;
- edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
- switch (edp_backlight_mode) {
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM:
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET:
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT:
+ if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
@@ -406,13 +402,6 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
pwmgen_bit_count) != 1)
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
-
- break;
-
- /* Do nothing when it is already DPCD mode */
- case DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD:
- default:
- break;
}
if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
--
2.31.1
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 3/9] drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, open list, David Airlie, Sean Paul,
Rodrigo Vivi
Get rid of the extraneous switch case in here, and just open code
edp_backlight_mode as we only ever use it once.
v4:
* Check that backlight mode is DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD, not
DP_EDP_BACKLIGHT_CONTROL_MODE_MASK - imirkin
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../gpu/drm/i915/display/intel_dp_aux_backlight.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1dbe38282ebe..1ab82933afb5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -382,7 +382,7 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
- u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode;
+ u8 dpcd_buf, new_dpcd_buf;
u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
if (drm_dp_dpcd_readb(&intel_dp->aux,
@@ -393,12 +393,8 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
new_dpcd_buf = dpcd_buf;
- edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
- switch (edp_backlight_mode) {
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM:
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET:
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT:
+ if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
@@ -406,13 +402,6 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
pwmgen_bit_count) != 1)
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
-
- break;
-
- /* Do nothing when it is already DPCD mode */
- case DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD:
- default:
- break;
}
if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v6 3/9] drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, open list, David Airlie, Sean Paul
Get rid of the extraneous switch case in here, and just open code
edp_backlight_mode as we only ever use it once.
v4:
* Check that backlight mode is DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD, not
DP_EDP_BACKLIGHT_CONTROL_MODE_MASK - imirkin
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../gpu/drm/i915/display/intel_dp_aux_backlight.c | 15 ++-------------
1 file changed, 2 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1dbe38282ebe..1ab82933afb5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -382,7 +382,7 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
- u8 dpcd_buf, new_dpcd_buf, edp_backlight_mode;
+ u8 dpcd_buf, new_dpcd_buf;
u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
if (drm_dp_dpcd_readb(&intel_dp->aux,
@@ -393,12 +393,8 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
new_dpcd_buf = dpcd_buf;
- edp_backlight_mode = dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
- switch (edp_backlight_mode) {
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PWM:
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PRESET:
- case DP_EDP_BACKLIGHT_CONTROL_MODE_PRODUCT:
+ if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
@@ -406,13 +402,6 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
pwmgen_bit_count) != 1)
drm_dbg_kms(&i915->drm,
"Failed to write aux pwmgen bit count\n");
-
- break;
-
- /* Do nothing when it is already DPCD mode */
- case DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD:
- default:
- break;
}
if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 4/9] drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight
2021-05-14 18:14 ` Lyude Paul
(?)
(?)
@ 2021-05-14 18:14 ` Lyude Paul
-1 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Rodrigo Vivi, Jani Nikula,
Joonas Lahtinen, David Airlie, Daniel Vetter,
Ville Syrjälä,
Imre Deak, Uma Shankar, Ramalingam C, Anshuman Gupta,
Dave Airlie, Gwan-gyeong Mun, Lucas De Marchi, Sean Paul,
open list
Since we're about to be moving this code into shared DRM helpers, we might
as well start to cache certain backlight capabilities that can be
determined from the EDP DPCD, and are likely to be relevant to the majority
of drivers using said helpers. The main purpose of this is just to prevent
every driver from having to check everything against the eDP DPCD using DP
macros, which makes the code slightly easier to read (especially since the
names of some of the eDP capabilities don't exactly match up with what we
actually need to use them for, like DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT
for instance).
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 ++
.../drm/i915/display/intel_dp_aux_backlight.c | 29 ++++++++++++-------
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7054a37363fb..d4a57bce71b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -312,6 +312,8 @@ struct intel_panel {
struct {
u8 pwmgen_bit_count;
u8 pwm_freq_pre_divider;
+ bool lsb_reg_used;
+ bool aux_enable;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1ab82933afb5..1d31c33f4867 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,13 +270,14 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
+static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 reg_val = 0;
/* Early return when display use other mechanism to enable backlight. */
- if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
+ if (!connector->panel.backlight.edp.vesa.aux_enable)
return;
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
@@ -339,9 +340,11 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
return 0;
}
- level = read_val[0];
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+
+ if (connector->panel.backlight.edp.vesa.lsb_reg_used)
level = (read_val[0] << 8 | read_val[1]);
+ else
+ level = read_val[0];
return level;
}
@@ -359,13 +362,14 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 vals[2] = { 0x0 };
- vals[0] = level;
-
/* Write the MSB and/or LSB */
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
+ if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
vals[0] = (level & 0xFF00) >> 8;
vals[1] = (level & 0xFF);
+ } else {
+ vals[0] = level;
}
+
if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
sizeof(vals)) != sizeof(vals)) {
drm_dbg_kms(&i915->drm,
@@ -419,14 +423,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
- set_vesa_backlight_enable(intel_dp, true);
+ set_vesa_backlight_enable(connector, true);
}
static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
u32 level)
{
- set_vesa_backlight_enable(enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)),
- false);
+ set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
}
/*
@@ -524,8 +527,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
enum pipe pipe)
{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
+ if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
+ panel->backlight.edp.vesa.aux_enable = true;
+ if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+ panel->backlight.edp.vesa.lsb_reg_used = true;
+
panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
if (!panel->backlight.max)
return -ENODEV;
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Nouveau] [PATCH v6 4/9] drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Ramalingam C, Imre Deak,
Joonas Lahtinen, Lucas De Marchi, open list, Jani Nikula,
Anshuman Gupta, David Airlie, Uma Shankar, Sean Paul,
Daniel Vetter, Rodrigo Vivi, Dave Airlie, Gwan-gyeong Mun,
Ville Syrjälä
Since we're about to be moving this code into shared DRM helpers, we might
as well start to cache certain backlight capabilities that can be
determined from the EDP DPCD, and are likely to be relevant to the majority
of drivers using said helpers. The main purpose of this is just to prevent
every driver from having to check everything against the eDP DPCD using DP
macros, which makes the code slightly easier to read (especially since the
names of some of the eDP capabilities don't exactly match up with what we
actually need to use them for, like DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT
for instance).
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 ++
.../drm/i915/display/intel_dp_aux_backlight.c | 29 ++++++++++++-------
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7054a37363fb..d4a57bce71b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -312,6 +312,8 @@ struct intel_panel {
struct {
u8 pwmgen_bit_count;
u8 pwm_freq_pre_divider;
+ bool lsb_reg_used;
+ bool aux_enable;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1ab82933afb5..1d31c33f4867 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,13 +270,14 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
+static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 reg_val = 0;
/* Early return when display use other mechanism to enable backlight. */
- if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
+ if (!connector->panel.backlight.edp.vesa.aux_enable)
return;
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
@@ -339,9 +340,11 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
return 0;
}
- level = read_val[0];
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+
+ if (connector->panel.backlight.edp.vesa.lsb_reg_used)
level = (read_val[0] << 8 | read_val[1]);
+ else
+ level = read_val[0];
return level;
}
@@ -359,13 +362,14 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 vals[2] = { 0x0 };
- vals[0] = level;
-
/* Write the MSB and/or LSB */
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
+ if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
vals[0] = (level & 0xFF00) >> 8;
vals[1] = (level & 0xFF);
+ } else {
+ vals[0] = level;
}
+
if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
sizeof(vals)) != sizeof(vals)) {
drm_dbg_kms(&i915->drm,
@@ -419,14 +423,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
- set_vesa_backlight_enable(intel_dp, true);
+ set_vesa_backlight_enable(connector, true);
}
static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
u32 level)
{
- set_vesa_backlight_enable(enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)),
- false);
+ set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
}
/*
@@ -524,8 +527,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
enum pipe pipe)
{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
+ if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
+ panel->backlight.edp.vesa.aux_enable = true;
+ if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+ panel->backlight.edp.vesa.lsb_reg_used = true;
+
panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
if (!panel->backlight.max)
return -ENODEV;
--
2.31.1
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 4/9] drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Lucas De Marchi, open list,
Anshuman Gupta, David Airlie, Uma Shankar, Sean Paul,
Rodrigo Vivi, Dave Airlie, Gwan-gyeong Mun
Since we're about to be moving this code into shared DRM helpers, we might
as well start to cache certain backlight capabilities that can be
determined from the EDP DPCD, and are likely to be relevant to the majority
of drivers using said helpers. The main purpose of this is just to prevent
every driver from having to check everything against the eDP DPCD using DP
macros, which makes the code slightly easier to read (especially since the
names of some of the eDP capabilities don't exactly match up with what we
actually need to use them for, like DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT
for instance).
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 ++
.../drm/i915/display/intel_dp_aux_backlight.c | 29 ++++++++++++-------
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7054a37363fb..d4a57bce71b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -312,6 +312,8 @@ struct intel_panel {
struct {
u8 pwmgen_bit_count;
u8 pwm_freq_pre_divider;
+ bool lsb_reg_used;
+ bool aux_enable;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1ab82933afb5..1d31c33f4867 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,13 +270,14 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
+static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 reg_val = 0;
/* Early return when display use other mechanism to enable backlight. */
- if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
+ if (!connector->panel.backlight.edp.vesa.aux_enable)
return;
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
@@ -339,9 +340,11 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
return 0;
}
- level = read_val[0];
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+
+ if (connector->panel.backlight.edp.vesa.lsb_reg_used)
level = (read_val[0] << 8 | read_val[1]);
+ else
+ level = read_val[0];
return level;
}
@@ -359,13 +362,14 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 vals[2] = { 0x0 };
- vals[0] = level;
-
/* Write the MSB and/or LSB */
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
+ if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
vals[0] = (level & 0xFF00) >> 8;
vals[1] = (level & 0xFF);
+ } else {
+ vals[0] = level;
}
+
if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
sizeof(vals)) != sizeof(vals)) {
drm_dbg_kms(&i915->drm,
@@ -419,14 +423,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
- set_vesa_backlight_enable(intel_dp, true);
+ set_vesa_backlight_enable(connector, true);
}
static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
u32 level)
{
- set_vesa_backlight_enable(enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)),
- false);
+ set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
}
/*
@@ -524,8 +527,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
enum pipe pipe)
{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
+ if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
+ panel->backlight.edp.vesa.aux_enable = true;
+ if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+ panel->backlight.edp.vesa.lsb_reg_used = true;
+
panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
if (!panel->backlight.max)
return -ENODEV;
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v6 4/9] drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Lucas De Marchi, open list,
David Airlie, Sean Paul, Dave Airlie
Since we're about to be moving this code into shared DRM helpers, we might
as well start to cache certain backlight capabilities that can be
determined from the EDP DPCD, and are likely to be relevant to the majority
of drivers using said helpers. The main purpose of this is just to prevent
every driver from having to check everything against the eDP DPCD using DP
macros, which makes the code slightly easier to read (especially since the
names of some of the eDP capabilities don't exactly match up with what we
actually need to use them for, like DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT
for instance).
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_display_types.h | 2 ++
.../drm/i915/display/intel_dp_aux_backlight.c | 29 ++++++++++++-------
2 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7054a37363fb..d4a57bce71b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -312,6 +312,8 @@ struct intel_panel {
struct {
u8 pwmgen_bit_count;
u8 pwm_freq_pre_divider;
+ bool lsb_reg_used;
+ bool aux_enable;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1ab82933afb5..1d31c33f4867 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,13 +270,14 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static void set_vesa_backlight_enable(struct intel_dp *intel_dp, bool enable)
+static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 reg_val = 0;
/* Early return when display use other mechanism to enable backlight. */
- if (!(intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP))
+ if (!connector->panel.backlight.edp.vesa.aux_enable)
return;
if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
@@ -339,9 +340,11 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
return 0;
}
- level = read_val[0];
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+
+ if (connector->panel.backlight.edp.vesa.lsb_reg_used)
level = (read_val[0] << 8 | read_val[1]);
+ else
+ level = read_val[0];
return level;
}
@@ -359,13 +362,14 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
u8 vals[2] = { 0x0 };
- vals[0] = level;
-
/* Write the MSB and/or LSB */
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) {
+ if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
vals[0] = (level & 0xFF00) >> 8;
vals[1] = (level & 0xFF);
+ } else {
+ vals[0] = level;
}
+
if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
sizeof(vals)) != sizeof(vals)) {
drm_dbg_kms(&i915->drm,
@@ -419,14 +423,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
- set_vesa_backlight_enable(intel_dp, true);
+ set_vesa_backlight_enable(connector, true);
}
static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
u32 level)
{
- set_vesa_backlight_enable(enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)),
- false);
+ set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
}
/*
@@ -524,8 +527,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
enum pipe pipe)
{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
+ if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
+ panel->backlight.edp.vesa.aux_enable = true;
+ if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+ panel->backlight.edp.vesa.lsb_reg_used = true;
+
panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
if (!panel->backlight.max)
return -ENODEV;
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 5/9] drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
2021-05-14 18:14 ` Lyude Paul
(?)
(?)
@ 2021-05-14 18:14 ` Lyude Paul
-1 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Rodrigo Vivi, Jani Nikula,
Joonas Lahtinen, David Airlie, Daniel Vetter,
Ville Syrjälä,
Sean Paul, open list
No functional changes, just move set_vesa_backlight_enable() closer to it's
only caller: intel_dp_aux_vesa_enable_backlight().
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 54 +++++++++----------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1d31c33f4867..781c7cd98d75 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,33 +270,6 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- u8 reg_val = 0;
-
- /* Early return when display use other mechanism to enable backlight. */
- if (!connector->panel.backlight.edp.vesa.aux_enable)
- return;
-
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_DISPLAY_CONTROL_REGISTER);
- return;
- }
- if (enable)
- reg_val |= DP_EDP_BACKLIGHT_ENABLE;
- else
- reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
-
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- reg_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
- enabledisable(enable));
- }
-}
-
static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -378,6 +351,33 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
}
}
+static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
+{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u8 reg_val = 0;
+
+ /* Early return when display use other mechanism to enable backlight. */
+ if (!connector->panel.backlight.edp.vesa.aux_enable)
+ return;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
+ DP_EDP_DISPLAY_CONTROL_REGISTER);
+ return;
+ }
+ if (enable)
+ reg_val |= DP_EDP_BACKLIGHT_ENABLE;
+ else
+ reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+ reg_val) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
+ enabledisable(enable));
+ }
+}
+
static void
intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Nouveau] [PATCH v6 5/9] drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Joonas Lahtinen, open list,
Jani Nikula, David Airlie, Sean Paul, Daniel Vetter,
Rodrigo Vivi, Ville Syrjälä
No functional changes, just move set_vesa_backlight_enable() closer to it's
only caller: intel_dp_aux_vesa_enable_backlight().
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 54 +++++++++----------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1d31c33f4867..781c7cd98d75 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,33 +270,6 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- u8 reg_val = 0;
-
- /* Early return when display use other mechanism to enable backlight. */
- if (!connector->panel.backlight.edp.vesa.aux_enable)
- return;
-
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_DISPLAY_CONTROL_REGISTER);
- return;
- }
- if (enable)
- reg_val |= DP_EDP_BACKLIGHT_ENABLE;
- else
- reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
-
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- reg_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
- enabledisable(enable));
- }
-}
-
static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -378,6 +351,33 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
}
}
+static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
+{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u8 reg_val = 0;
+
+ /* Early return when display use other mechanism to enable backlight. */
+ if (!connector->panel.backlight.edp.vesa.aux_enable)
+ return;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
+ DP_EDP_DISPLAY_CONTROL_REGISTER);
+ return;
+ }
+ if (enable)
+ reg_val |= DP_EDP_BACKLIGHT_ENABLE;
+ else
+ reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+ reg_val) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
+ enabledisable(enable));
+ }
+}
+
static void
intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
--
2.31.1
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 5/9] drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, open list, David Airlie, Sean Paul,
Rodrigo Vivi
No functional changes, just move set_vesa_backlight_enable() closer to it's
only caller: intel_dp_aux_vesa_enable_backlight().
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 54 +++++++++----------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1d31c33f4867..781c7cd98d75 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,33 +270,6 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- u8 reg_val = 0;
-
- /* Early return when display use other mechanism to enable backlight. */
- if (!connector->panel.backlight.edp.vesa.aux_enable)
- return;
-
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_DISPLAY_CONTROL_REGISTER);
- return;
- }
- if (enable)
- reg_val |= DP_EDP_BACKLIGHT_ENABLE;
- else
- reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
-
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- reg_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
- enabledisable(enable));
- }
-}
-
static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -378,6 +351,33 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
}
}
+static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
+{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u8 reg_val = 0;
+
+ /* Early return when display use other mechanism to enable backlight. */
+ if (!connector->panel.backlight.edp.vesa.aux_enable)
+ return;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
+ DP_EDP_DISPLAY_CONTROL_REGISTER);
+ return;
+ }
+ if (enable)
+ reg_val |= DP_EDP_BACKLIGHT_ENABLE;
+ else
+ reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+ reg_val) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
+ enabledisable(enable));
+ }
+}
+
static void
intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v6 5/9] drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
@ 2021-05-14 18:14 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:14 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, open list, David Airlie, Sean Paul
No functional changes, just move set_vesa_backlight_enable() closer to it's
only caller: intel_dp_aux_vesa_enable_backlight().
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 54 +++++++++----------
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 1d31c33f4867..781c7cd98d75 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,33 +270,6 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- u8 reg_val = 0;
-
- /* Early return when display use other mechanism to enable backlight. */
- if (!connector->panel.backlight.edp.vesa.aux_enable)
- return;
-
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_DISPLAY_CONTROL_REGISTER);
- return;
- }
- if (enable)
- reg_val |= DP_EDP_BACKLIGHT_ENABLE;
- else
- reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
-
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- reg_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
- enabledisable(enable));
- }
-}
-
static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
@@ -378,6 +351,33 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
}
}
+static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
+{
+ struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u8 reg_val = 0;
+
+ /* Early return when display use other mechanism to enable backlight. */
+ if (!connector->panel.backlight.edp.vesa.aux_enable)
+ return;
+
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
+ DP_EDP_DISPLAY_CONTROL_REGISTER);
+ return;
+ }
+ if (enable)
+ reg_val |= DP_EDP_BACKLIGHT_ENABLE;
+ else
+ reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+
+ if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
+ reg_val) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
+ enabledisable(enable));
+ }
+}
+
static void
intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 6/9] drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT
2021-05-14 18:14 ` Lyude Paul
(?)
(?)
@ 2021-05-14 18:15 ` Lyude Paul
-1 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Rodrigo Vivi, Jani Nikula,
Joonas Lahtinen, David Airlie, Daniel Vetter,
Ville Syrjälä,
Sean Paul, open list
If we can't read DP_EDP_PWMGEN_BIT_COUNT in
intel_dp_aux_vesa_calc_max_backlight() but do have a valid PWM frequency
defined in the VBT, we'll keep going in the function until we inevitably
fail on reading DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN. There's not much point in
doing this, so just return early.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 781c7cd98d75..bf8e4ed56847 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -449,11 +449,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
u8 pn, pn_min, pn_max;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) == 1) {
- pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- max_backlight = (1 << pn) - 1;
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap\n");
+ return 0;
}
+ pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ max_backlight = (1 << pn) - 1;
+
/* Find desired value of (F x P)
* Note that, if F x P is out of supported range, the maximum value or
* minimum value will applied automatically. So no need to check that.
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Nouveau] [PATCH v6 6/9] drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Joonas Lahtinen, open list,
Jani Nikula, David Airlie, Sean Paul, Daniel Vetter,
Rodrigo Vivi, Ville Syrjälä
If we can't read DP_EDP_PWMGEN_BIT_COUNT in
intel_dp_aux_vesa_calc_max_backlight() but do have a valid PWM frequency
defined in the VBT, we'll keep going in the function until we inevitably
fail on reading DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN. There's not much point in
doing this, so just return early.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 781c7cd98d75..bf8e4ed56847 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -449,11 +449,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
u8 pn, pn_min, pn_max;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) == 1) {
- pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- max_backlight = (1 << pn) - 1;
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap\n");
+ return 0;
}
+ pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ max_backlight = (1 << pn) - 1;
+
/* Find desired value of (F x P)
* Note that, if F x P is out of supported range, the maximum value or
* minimum value will applied automatically. So no need to check that.
--
2.31.1
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 6/9] drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, open list, David Airlie, Sean Paul,
Rodrigo Vivi
If we can't read DP_EDP_PWMGEN_BIT_COUNT in
intel_dp_aux_vesa_calc_max_backlight() but do have a valid PWM frequency
defined in the VBT, we'll keep going in the function until we inevitably
fail on reading DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN. There's not much point in
doing this, so just return early.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 781c7cd98d75..bf8e4ed56847 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -449,11 +449,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
u8 pn, pn_min, pn_max;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) == 1) {
- pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- max_backlight = (1 << pn) - 1;
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap\n");
+ return 0;
}
+ pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ max_backlight = (1 << pn) - 1;
+
/* Find desired value of (F x P)
* Note that, if F x P is out of supported range, the maximum value or
* minimum value will applied automatically. So no need to check that.
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v6 6/9] drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, open list, David Airlie, Sean Paul
If we can't read DP_EDP_PWMGEN_BIT_COUNT in
intel_dp_aux_vesa_calc_max_backlight() but do have a valid PWM frequency
defined in the VBT, we'll keep going in the function until we inevitably
fail on reading DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN. There's not much point in
doing this, so just return early.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 781c7cd98d75..bf8e4ed56847 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -449,11 +449,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
u8 pn, pn_min, pn_max;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) == 1) {
- pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- max_backlight = (1 << pn) - 1;
+ if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap\n");
+ return 0;
}
+ pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ max_backlight = (1 << pn) - 1;
+
/* Find desired value of (F x P)
* Note that, if F x P is out of supported range, the maximum value or
* minimum value will applied automatically. So no need to check that.
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 7/9] drm/i915/dpcd_bl: Print return codes for VESA backlight failures
2021-05-14 18:14 ` Lyude Paul
(?)
(?)
@ 2021-05-14 18:15 ` Lyude Paul
-1 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Rodrigo Vivi, Jani Nikula,
Joonas Lahtinen, David Airlie, Daniel Vetter,
Ville Syrjälä,
Sean Paul, open list
Also, stop printing the DPCD register that failed, and just describe it
instead. Saves us from having to look up each register offset when reading
through kernel logs (plus, DPCD dumping with drm.debug |= 0x100 will give
us that anyway).
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 101 +++++++++---------
1 file changed, 52 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index bf8e4ed56847..95f2df631052 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -274,14 +274,12 @@ static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connec
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 mode_reg;
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- &mode_reg) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read the DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
return false;
}
@@ -297,6 +295,7 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 read_val[2] = { 0x0 };
u16 level = 0;
@@ -307,10 +306,10 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
return connector->panel.backlight.max;
- if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
- sizeof(read_val)) != sizeof(read_val)) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
+ ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
+ sizeof(read_val));
+ if (ret != sizeof(read_val)) {
+ drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
return 0;
}
@@ -333,6 +332,7 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
struct intel_connector *connector = to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 vals[2] = { 0x0 };
/* Write the MSB and/or LSB */
@@ -343,10 +343,10 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
vals[0] = level;
}
- if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
- sizeof(vals)) != sizeof(vals)) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux backlight level\n");
+ ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
+ sizeof(vals));
+ if (ret != sizeof(vals)) {
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
return;
}
}
@@ -355,26 +355,28 @@ static void set_vesa_backlight_enable(struct intel_connector *connector, bool en
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 reg_val = 0;
/* Early return when display use other mechanism to enable backlight. */
if (!connector->panel.backlight.edp.vesa.aux_enable)
return;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_DISPLAY_CONTROL_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
return;
}
+
if (enable)
reg_val |= DP_EDP_BACKLIGHT_ENABLE;
else
reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- reg_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
- enabledisable(enable));
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
+ enabledisable(enable), ret);
}
}
@@ -386,13 +388,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
+ int ret;
u8 dpcd_buf, new_dpcd_buf;
u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
return;
}
@@ -402,24 +404,26 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT,
- pwmgen_bit_count) != 1)
- drm_dbg_kms(&i915->drm,
- "Failed to write aux pwmgen bit count\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
+ if (ret != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
}
if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
- panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
+ panel->backlight.edp.vesa.pwm_freq_pre_divider);
+ if (ret == 1)
new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
else
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
+ ret);
}
if (new_dpcd_buf != dpcd_buf) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- new_dpcd_buf) != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+ new_dpcd_buf);
+ if (ret != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
@@ -446,11 +450,12 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
u32 max_backlight = 0;
- int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
+ int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
u8 pn, pn_min, pn_max;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
return 0;
}
@@ -479,16 +484,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
* - FxP is within 25% of desired value.
* Note: 25% is arbitrary value and may need some tweak.
*/
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read pwmgen bit count cap min\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
return max_backlight;
}
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read pwmgen bit count cap max\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
return max_backlight;
}
pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
@@ -512,9 +515,9 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
}
drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux pwmgen bit count\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
return max_backlight;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Nouveau] [PATCH v6 7/9] drm/i915/dpcd_bl: Print return codes for VESA backlight failures
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Joonas Lahtinen, open list,
Jani Nikula, David Airlie, Sean Paul, Daniel Vetter,
Rodrigo Vivi, Ville Syrjälä
Also, stop printing the DPCD register that failed, and just describe it
instead. Saves us from having to look up each register offset when reading
through kernel logs (plus, DPCD dumping with drm.debug |= 0x100 will give
us that anyway).
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 101 +++++++++---------
1 file changed, 52 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index bf8e4ed56847..95f2df631052 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -274,14 +274,12 @@ static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connec
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 mode_reg;
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- &mode_reg) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read the DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
return false;
}
@@ -297,6 +295,7 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 read_val[2] = { 0x0 };
u16 level = 0;
@@ -307,10 +306,10 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
return connector->panel.backlight.max;
- if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
- sizeof(read_val)) != sizeof(read_val)) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
+ ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
+ sizeof(read_val));
+ if (ret != sizeof(read_val)) {
+ drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
return 0;
}
@@ -333,6 +332,7 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
struct intel_connector *connector = to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 vals[2] = { 0x0 };
/* Write the MSB and/or LSB */
@@ -343,10 +343,10 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
vals[0] = level;
}
- if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
- sizeof(vals)) != sizeof(vals)) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux backlight level\n");
+ ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
+ sizeof(vals));
+ if (ret != sizeof(vals)) {
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
return;
}
}
@@ -355,26 +355,28 @@ static void set_vesa_backlight_enable(struct intel_connector *connector, bool en
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 reg_val = 0;
/* Early return when display use other mechanism to enable backlight. */
if (!connector->panel.backlight.edp.vesa.aux_enable)
return;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_DISPLAY_CONTROL_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
return;
}
+
if (enable)
reg_val |= DP_EDP_BACKLIGHT_ENABLE;
else
reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- reg_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
- enabledisable(enable));
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
+ enabledisable(enable), ret);
}
}
@@ -386,13 +388,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
+ int ret;
u8 dpcd_buf, new_dpcd_buf;
u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
return;
}
@@ -402,24 +404,26 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT,
- pwmgen_bit_count) != 1)
- drm_dbg_kms(&i915->drm,
- "Failed to write aux pwmgen bit count\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
+ if (ret != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
}
if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
- panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
+ panel->backlight.edp.vesa.pwm_freq_pre_divider);
+ if (ret == 1)
new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
else
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
+ ret);
}
if (new_dpcd_buf != dpcd_buf) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- new_dpcd_buf) != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+ new_dpcd_buf);
+ if (ret != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
@@ -446,11 +450,12 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
u32 max_backlight = 0;
- int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
+ int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
u8 pn, pn_min, pn_max;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
return 0;
}
@@ -479,16 +484,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
* - FxP is within 25% of desired value.
* Note: 25% is arbitrary value and may need some tweak.
*/
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read pwmgen bit count cap min\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
return max_backlight;
}
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read pwmgen bit count cap max\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
return max_backlight;
}
pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
@@ -512,9 +515,9 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
}
drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux pwmgen bit count\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
return max_backlight;
}
--
2.31.1
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 7/9] drm/i915/dpcd_bl: Print return codes for VESA backlight failures
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, open list, David Airlie, Sean Paul,
Rodrigo Vivi
Also, stop printing the DPCD register that failed, and just describe it
instead. Saves us from having to look up each register offset when reading
through kernel logs (plus, DPCD dumping with drm.debug |= 0x100 will give
us that anyway).
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 101 +++++++++---------
1 file changed, 52 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index bf8e4ed56847..95f2df631052 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -274,14 +274,12 @@ static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connec
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 mode_reg;
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- &mode_reg) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read the DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
return false;
}
@@ -297,6 +295,7 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 read_val[2] = { 0x0 };
u16 level = 0;
@@ -307,10 +306,10 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
return connector->panel.backlight.max;
- if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
- sizeof(read_val)) != sizeof(read_val)) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
+ ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
+ sizeof(read_val));
+ if (ret != sizeof(read_val)) {
+ drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
return 0;
}
@@ -333,6 +332,7 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
struct intel_connector *connector = to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 vals[2] = { 0x0 };
/* Write the MSB and/or LSB */
@@ -343,10 +343,10 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
vals[0] = level;
}
- if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
- sizeof(vals)) != sizeof(vals)) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux backlight level\n");
+ ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
+ sizeof(vals));
+ if (ret != sizeof(vals)) {
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
return;
}
}
@@ -355,26 +355,28 @@ static void set_vesa_backlight_enable(struct intel_connector *connector, bool en
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 reg_val = 0;
/* Early return when display use other mechanism to enable backlight. */
if (!connector->panel.backlight.edp.vesa.aux_enable)
return;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_DISPLAY_CONTROL_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
return;
}
+
if (enable)
reg_val |= DP_EDP_BACKLIGHT_ENABLE;
else
reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- reg_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
- enabledisable(enable));
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
+ enabledisable(enable), ret);
}
}
@@ -386,13 +388,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
+ int ret;
u8 dpcd_buf, new_dpcd_buf;
u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
return;
}
@@ -402,24 +404,26 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT,
- pwmgen_bit_count) != 1)
- drm_dbg_kms(&i915->drm,
- "Failed to write aux pwmgen bit count\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
+ if (ret != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
}
if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
- panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
+ panel->backlight.edp.vesa.pwm_freq_pre_divider);
+ if (ret == 1)
new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
else
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
+ ret);
}
if (new_dpcd_buf != dpcd_buf) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- new_dpcd_buf) != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+ new_dpcd_buf);
+ if (ret != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
@@ -446,11 +450,12 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
u32 max_backlight = 0;
- int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
+ int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
u8 pn, pn_min, pn_max;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
return 0;
}
@@ -479,16 +484,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
* - FxP is within 25% of desired value.
* Note: 25% is arbitrary value and may need some tweak.
*/
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read pwmgen bit count cap min\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
return max_backlight;
}
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read pwmgen bit count cap max\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
return max_backlight;
}
pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
@@ -512,9 +515,9 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
}
drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux pwmgen bit count\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
return max_backlight;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v6 7/9] drm/i915/dpcd_bl: Print return codes for VESA backlight failures
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, open list, David Airlie, Sean Paul
Also, stop printing the DPCD register that failed, and just describe it
instead. Saves us from having to look up each register offset when reading
through kernel logs (plus, DPCD dumping with drm.debug |= 0x100 will give
us that anyway).
Signed-off-by: Lyude Paul <lyude@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
---
.../drm/i915/display/intel_dp_aux_backlight.c | 101 +++++++++---------
1 file changed, 52 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index bf8e4ed56847..95f2df631052 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -274,14 +274,12 @@ static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connec
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 mode_reg;
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- &mode_reg) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read the DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
return false;
}
@@ -297,6 +295,7 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 read_val[2] = { 0x0 };
u16 level = 0;
@@ -307,10 +306,10 @@ static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, en
if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
return connector->panel.backlight.max;
- if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
- sizeof(read_val)) != sizeof(read_val)) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_BRIGHTNESS_MSB);
+ ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
+ sizeof(read_val));
+ if (ret != sizeof(read_val)) {
+ drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
return 0;
}
@@ -333,6 +332,7 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
struct intel_connector *connector = to_intel_connector(conn_state->connector);
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 vals[2] = { 0x0 };
/* Write the MSB and/or LSB */
@@ -343,10 +343,10 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
vals[0] = level;
}
- if (drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
- sizeof(vals)) != sizeof(vals)) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux backlight level\n");
+ ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
+ sizeof(vals));
+ if (ret != sizeof(vals)) {
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
return;
}
}
@@ -355,26 +355,28 @@ static void set_vesa_backlight_enable(struct intel_connector *connector, bool en
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ int ret;
u8 reg_val = 0;
/* Early return when display use other mechanism to enable backlight. */
if (!connector->panel.backlight.edp.vesa.aux_enable)
return;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_DISPLAY_CONTROL_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
return;
}
+
if (enable)
reg_val |= DP_EDP_BACKLIGHT_ENABLE;
else
reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER,
- reg_val) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight\n",
- enabledisable(enable));
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
+ enabledisable(enable), ret);
}
}
@@ -386,13 +388,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
+ int ret;
u8 dpcd_buf, new_dpcd_buf;
u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read DPCD register 0x%x\n",
- DP_EDP_BACKLIGHT_MODE_SET_REGISTER);
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
return;
}
@@ -402,24 +404,26 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT,
- pwmgen_bit_count) != 1)
- drm_dbg_kms(&i915->drm,
- "Failed to write aux pwmgen bit count\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
+ if (ret != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
}
if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
- panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
+ panel->backlight.edp.vesa.pwm_freq_pre_divider);
+ if (ret == 1)
new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
else
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
+ ret);
}
if (new_dpcd_buf != dpcd_buf) {
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- new_dpcd_buf) != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
+ new_dpcd_buf);
+ if (ret != 1)
+ drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
}
intel_dp_aux_vesa_set_backlight(conn_state, level);
@@ -446,11 +450,12 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
u32 max_backlight = 0;
- int freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
+ int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
u8 pn, pn_min, pn_max;
- if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn) != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
return 0;
}
@@ -479,16 +484,14 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
* - FxP is within 25% of desired value.
* Note: 25% is arbitrary value and may need some tweak.
*/
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read pwmgen bit count cap min\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
return max_backlight;
}
- if (drm_dp_dpcd_readb(&intel_dp->aux,
- DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to read pwmgen bit count cap max\n");
+ ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
return max_backlight;
}
pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
@@ -512,9 +515,9 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
}
drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn) != 1) {
- drm_dbg_kms(&i915->drm,
- "Failed to write aux pwmgen bit count\n");
+ ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
+ if (ret != 1) {
+ drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
return max_backlight;
}
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 8/9] drm/dp: Extract i915's eDP backlight code into DRM helpers
2021-05-14 18:14 ` Lyude Paul
(?)
(?)
@ 2021-05-14 18:15 ` Lyude Paul
-1 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Jani Nikula, Dave Airlie,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
David Airlie, Daniel Vetter, Jani Nikula, Joonas Lahtinen,
Rodrigo Vivi, Ville Syrjälä,
Imre Deak, Uma Shankar, Ramalingam C, Dave Airlie,
Anshuman Gupta, Gwan-gyeong Mun, Lucas De Marchi, Sean Paul,
open list
Since we're about to implement eDP backlight support in nouveau using the
standard protocol from VESA, we might as well just take the code that's
already written for this and move it into a set of shared DRM helpers.
Note that these helpers are intended to handle DPCD related backlight
control bits such as setting the brightness level over AUX, probing the
backlight's TCON, enabling/disabling the backlight over AUX if supported,
etc. Any PWM-related portions of backlight control are explicitly left up
to the driver, as these will vary from platform to platform.
The only exception to this is the calculation of the PWM frequency
pre-divider value. This is because the only platform-specific information
required for this is the PWM frequency of the panel, which the driver is
expected to provide if available. The actual algorithm for calculating this
value is standard and is defined in the eDP specification from VESA.
Note that these helpers do not yet implement the full range of features
the VESA backlight interface provides, and only provide the following
functionality (all of which was already present in i915's DPCD backlight
support):
* Basic control of brightness levels
* Basic probing of backlight capabilities
* Helpers for enabling and disabling the backlight
v3:
* Split out changes to i915's backlight code to separate patches to make it
easier to review
v4:
* Style/spelling changes from Thomas Zimmermann
v5:
* Start using new drm_dbg_*() functions
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
drivers/gpu/drm/drm_dp_helper.c | 347 ++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 5 +-
.../drm/i915/display/intel_dp_aux_backlight.c | 285 ++------------
include/drm/drm_dp_helper.h | 48 +++
4 files changed, 427 insertions(+), 258 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 55b53df6ce34..24bbc710c825 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -3115,3 +3115,350 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
return 0;
}
EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
+
+/**
+ * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ * @level: The brightness level to set
+ *
+ * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
+ * already have been enabled by the driver by calling drm_edp_backlight_enable().
+ *
+ * Returns: %0 on success, negative error code on failure
+ */
+int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level)
+{
+ int ret;
+ u8 buf[2] = { 0 };
+
+ if (bl->lsb_reg_used) {
+ buf[0] = (level & 0xff00) >> 8;
+ buf[1] = (level & 0x00ff);
+ } else {
+ buf[0] = level;
+ }
+
+ ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
+ if (ret != sizeof(buf)) {
+ drm_err(aux->drm_dev,
+ "%s: Failed to write aux backlight level: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_set_level);
+
+static int
+drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ bool enable)
+{
+ int ret;
+ u8 buf;
+
+ /* The panel uses something other then DPCD for enabling its backlight */
+ if (!bl->aux_enable)
+ return 0;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
+ if (ret != 1) {
+ drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+ if (enable)
+ buf |= DP_EDP_BACKLIGHT_ENABLE;
+ else
+ buf &= ~DP_EDP_BACKLIGHT_ENABLE;
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
+ if (ret != 1) {
+ drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ return 0;
+}
+
+/**
+ * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ * @level: The initial backlight level to set via AUX, if there is one
+ *
+ * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
+ * restoring any important backlight state such as the given backlight level, the brightness byte
+ * count, backlight frequency, etc.
+ *
+ * Note that certain panels, while supporting brightness level controls over DPCD, may not support
+ * having their backlights enabled via the standard %DP_EDP_DISPLAY_CONTROL_REGISTER. On such panels
+ * &drm_edp_backlight_info.aux_enable will be set to %false, this function will skip the step of
+ * programming the %DP_EDP_DISPLAY_CONTROL_REGISTER, and the driver must perform the required
+ * implementation specific step for enabling the backlight after calling this function.
+ *
+ * Returns: %0 on success, negative error code on failure.
+ */
+int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ const u16 level)
+{
+ int ret;
+ u8 dpcd_buf, new_dpcd_buf;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Failed to read backlight mode: %d\n", aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ new_dpcd_buf = dpcd_buf;
+
+ if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
+ new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
+ if (ret != 1)
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
+ aux->name, ret);
+ }
+
+ if (bl->pwm_freq_pre_divider) {
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
+ if (ret != 1)
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Failed to write aux backlight frequency: %d\n",
+ aux->name, ret);
+ else
+ new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
+ }
+
+ if (new_dpcd_buf != dpcd_buf) {
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+ }
+
+ ret = drm_edp_backlight_set_level(aux, bl, level);
+ if (ret < 0)
+ return ret;
+ ret = drm_edp_backlight_set_enable(aux, bl, true);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_enable);
+
+/**
+ * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ *
+ * This function handles disabling DPCD backlight controls on a panel over AUX. Note that some
+ * panels have backlights that are enabled/disabled by other means, despite having their brightness
+ * values controlled through DPCD. On such panels &drm_edp_backlight_info.aux_enable will be set to
+ * %false, this function will become a no-op (and we will skip updating
+ * %DP_EDP_DISPLAY_CONTROL_REGISTER), and the driver must take care to perform it's own
+ * implementation specific step for disabling the backlight.
+ *
+ * Returns: %0 on success or no-op, negative error code on failure.
+ */
+int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
+{
+ int ret;
+
+ ret = drm_edp_backlight_set_enable(aux, bl, false);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_disable);
+
+static inline int
+drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
+{
+ int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
+ int ret;
+ u8 pn, pn_min, pn_max;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
+ aux->name, ret);
+ return -ENODEV;
+ }
+
+ pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ bl->max = (1 << pn) - 1;
+ if (!driver_pwm_freq_hz)
+ return 0;
+
+ /*
+ * Set PWM Frequency divider to match desired frequency provided by the driver.
+ * The PWM Frequency is calculated as 27Mhz / (F x P).
+ * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
+ * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
+ * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
+ * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
+ */
+
+ /* Find desired value of (F x P)
+ * Note that, if F x P is out of supported range, the maximum value or minimum value will
+ * applied automatically. So no need to check that.
+ */
+ fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
+
+ /* Use highest possible value of Pn for more granularity of brightness adjustment while
+ * satifying the conditions below.
+ * - Pn is in the range of Pn_min and Pn_max
+ * - F is in the range of 1 and 255
+ * - FxP is within 25% of desired value.
+ * Note: 25% is arbitrary value and may need some tweak.
+ */
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+
+ /* Ensure frequency is within 25% of desired value */
+ fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
+ fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
+ if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Driver defined backlight frequency (%d) out of range\n",
+ aux->name, driver_pwm_freq_hz);
+ return 0;
+ }
+
+ for (pn = pn_max; pn >= pn_min; pn--) {
+ f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
+ fxp_actual = f << pn;
+ if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
+ break;
+ }
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ bl->pwmgen_bit_count = pn;
+ bl->max = (1 << pn) - 1;
+
+ if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
+ bl->pwm_freq_pre_divider = f;
+ drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
+ aux->name, driver_pwm_freq_hz);
+ }
+
+ return 0;
+}
+
+static inline int
+drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u8 *current_mode)
+{
+ int ret;
+ u8 buf[2];
+ u8 mode_reg;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
+ if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ int size = 1 + bl->lsb_reg_used;
+
+ ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
+ if (ret != size) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ if (bl->lsb_reg_used)
+ return (buf[0] << 8) | buf[1];
+ else
+ return buf[0];
+ }
+
+ /*
+ * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
+ * the driver should assume max brightness
+ */
+ return bl->max;
+}
+
+/**
+ * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
+ * interface.
+ * @aux: The DP aux device to use for probing
+ * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
+ * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
+ * @edp_dpcd: A cached copy of the eDP DPCD
+ * @current_level: Where to store the probed brightness level
+ * @current_mode: Where to store the currently set backlight control mode
+ *
+ * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
+ * along with also probing the current and maximum supported brightness levels.
+ *
+ * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
+ * default frequency from the panel is used.
+ *
+ * Returns: %0 on success, negative error code on failure.
+ */
+int
+drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
+ u16 *current_level, u8 *current_mode)
+{
+ int ret;
+
+ if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
+ bl->aux_enable = true;
+ if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+ bl->lsb_reg_used = true;
+
+ ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
+ if (ret < 0)
+ return ret;
+
+ ret = drm_edp_backlight_probe_level(aux, bl, current_mode);
+ if (ret < 0)
+ return ret;
+ *current_level = ret;
+
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Found backlight level=%d/%d pwm_freq_pre_divider=%d mode=%x\n",
+ aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, *current_mode);
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Backlight caps: pwmgen_bit_count=%d lsb_reg_used=%d aux_enable=%d\n",
+ aux->name, bl->pwmgen_bit_count, bl->lsb_reg_used, bl->aux_enable);
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_init);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d4a57bce71b1..8696b39da2fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -310,10 +310,7 @@ struct intel_panel {
/* DPCD backlight */
union {
struct {
- u8 pwmgen_bit_count;
- u8 pwm_freq_pre_divider;
- bool lsb_reg_used;
- bool aux_enable;
+ struct drm_edp_backlight_info info;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 95f2df631052..6ac568617ef3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,114 +270,19 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 mode_reg;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
- return false;
- }
-
- return (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
- DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
-}
-
-/*
- * Read the current backlight value from DPCD register(s) based
- * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
- */
static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, enum pipe unused)
{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 read_val[2] = { 0x0 };
- u16 level = 0;
-
- /*
- * If we're not in DPCD control mode yet, the programmed brightness
- * value is meaningless and we should assume max brightness
- */
- if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
- return connector->panel.backlight.max;
-
- ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
- sizeof(read_val));
- if (ret != sizeof(read_val)) {
- drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
- return 0;
- }
-
- if (connector->panel.backlight.edp.vesa.lsb_reg_used)
- level = (read_val[0] << 8 | read_val[1]);
- else
- level = read_val[0];
-
- return level;
+ return connector->panel.backlight.level;
}
-/*
- * Sends the current backlight level over the aux channel, checking if its using
- * 8-bit or 16 bit value (MSB and LSB)
- */
static void
-intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
- u32 level)
+intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, u32 level)
{
struct intel_connector *connector = to_intel_connector(conn_state->connector);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 vals[2] = { 0x0 };
-
- /* Write the MSB and/or LSB */
- if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
- vals[0] = (level & 0xFF00) >> 8;
- vals[1] = (level & 0xFF);
- } else {
- vals[0] = level;
- }
-
- ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
- sizeof(vals));
- if (ret != sizeof(vals)) {
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
- return;
- }
-}
-
-static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 reg_val = 0;
-
- /* Early return when display use other mechanism to enable backlight. */
- if (!connector->panel.backlight.edp.vesa.aux_enable)
- return;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
- return;
- }
-
- if (enable)
- reg_val |= DP_EDP_BACKLIGHT_ENABLE;
- else
- reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+ struct intel_panel *panel = &connector->panel;
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
- enabledisable(enable), ret);
- }
+ drm_edp_backlight_set_level(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
}
static void
@@ -385,170 +290,46 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
{
struct intel_connector *connector = to_intel_connector(conn_state->connector);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
- int ret;
- u8 dpcd_buf, new_dpcd_buf;
- u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
- return;
- }
-
- new_dpcd_buf = dpcd_buf;
-
- if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
- new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
- new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
-
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
- if (ret != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
- }
-
- if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
- panel->backlight.edp.vesa.pwm_freq_pre_divider);
- if (ret == 1)
- new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
- else
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
- ret);
- }
-
- if (new_dpcd_buf != dpcd_buf) {
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- new_dpcd_buf);
- if (ret != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
- }
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- intel_dp_aux_vesa_set_backlight(conn_state, level);
- set_vesa_backlight_enable(connector, true);
+ drm_edp_backlight_enable(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
}
static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
u32 level)
{
- set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
-}
-
-/*
- * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
- * The PWM Frequency is calculated as 27Mhz / (F x P).
- * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
- * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
- * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
- * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
- */
-static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
-{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
struct intel_panel *panel = &connector->panel;
- u32 max_backlight = 0;
- int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
- u8 pn, pn_min, pn_max;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
- return 0;
- }
-
- pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- max_backlight = (1 << pn) - 1;
-
- /* Find desired value of (F x P)
- * Note that, if F x P is out of supported range, the maximum value or
- * minimum value will applied automatically. So no need to check that.
- */
- freq = i915->vbt.backlight.pwm_freq_hz;
- drm_dbg_kms(&i915->drm, "VBT defined backlight frequency %u Hz\n",
- freq);
- if (!freq) {
- drm_dbg_kms(&i915->drm,
- "Use panel default backlight frequency\n");
- return max_backlight;
- }
-
- fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
-
- /* Use highest possible value of Pn for more granularity of brightness
- * adjustment while satifying the conditions below.
- * - Pn is in the range of Pn_min and Pn_max
- * - F is in the range of 1 and 255
- * - FxP is within 25% of desired value.
- * Note: 25% is arbitrary value and may need some tweak.
- */
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
- return max_backlight;
- }
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
- return max_backlight;
- }
- pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
-
- /* Ensure frequency is within 25% of desired value */
- fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
- fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
-
- if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
- drm_dbg_kms(&i915->drm,
- "VBT defined backlight frequency out of range\n");
- return max_backlight;
- }
-
- for (pn = pn_max; pn >= pn_min; pn--) {
- f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
- fxp_actual = f << pn;
- if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
- break;
- }
-
- drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
- return max_backlight;
- }
-
- panel->backlight.edp.vesa.pwmgen_bit_count = pn;
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
- panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
-
- max_backlight = (1 << pn) - 1;
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- return max_backlight;
+ drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info);
}
-static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
- enum pipe pipe)
+static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 current_level;
+ u8 current_mode;
+ int ret;
- if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
- panel->backlight.edp.vesa.aux_enable = true;
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
- panel->backlight.edp.vesa.lsb_reg_used = true;
-
- panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
- if (!panel->backlight.max)
- return -ENODEV;
+ ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,
+ i915->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
+ ¤t_level, ¤t_mode);
+ if (ret < 0)
+ return ret;
+ panel->backlight.max = panel->backlight.edp.vesa.info.max;
panel->backlight.min = 0;
- panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector, pipe);
- panel->backlight.enabled = intel_dp_aux_vesa_backlight_dpcd_mode(connector) &&
- panel->backlight.level != 0;
+ if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ panel->backlight.level = current_level;
+ panel->backlight.enabled = panel->backlight.level != 0;
+ } else {
+ panel->backlight.level = panel->backlight.max;
+ panel->backlight.enabled = false;
+ }
return 0;
}
@@ -559,16 +340,12 @@ intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector)
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- /* Check the eDP Display control capabilities registers to determine if
- * the panel can support backlight control over the aux channel.
- *
- * TODO: We currently only support AUX only backlight configurations, not backlights which
+ /* TODO: We currently only support AUX only backlight configurations, not backlights which
* require a mix of PWM and AUX controls to work. In the mean time, these machines typically
* work just fine using normal PWM controls anyway.
*/
- if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
- (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
- (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
+ if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
+ drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
drm_dbg_kms(&i915->drm, "AUX Backlight Control Supported!\n");
return true;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 06681bf46d81..0bd6396648b4 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1801,6 +1801,24 @@ drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_MSA_TIMING_PAR_IGNORED;
}
+/**
+ * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
+ * @edp_dpcd: The DPCD to check
+ *
+ * Note that currently this function will return %false for panels which support various DPCD
+ * backlight features but which require the brightness be set through PWM, and don't support setting
+ * the brightness level via the DPCD. This is a TODO.
+ *
+ * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
+ * otherwise
+ */
+static inline bool
+drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
+{
+ return (edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
+ (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP);
+}
+
/*
* DisplayPort AUX channel
*/
@@ -2107,6 +2125,36 @@ drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
return desc->quirks & BIT(quirk);
}
+/**
+ * struct drm_edp_backlight_info - Probed eDP backlight info struct
+ * @pwmgen_bit_count: The pwmgen bit count
+ * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
+ * @max: The maximum backlight level that may be set
+ * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
+ * @aux_enable: Does the panel support the AUX enable cap?
+ *
+ * This structure contains various data about an eDP backlight, which can be populated by using
+ * drm_edp_backlight_init().
+ */
+struct drm_edp_backlight_info {
+ u8 pwmgen_bit_count;
+ u8 pwm_freq_pre_divider;
+ u16 max;
+
+ bool lsb_reg_used : 1;
+ bool aux_enable : 1;
+};
+
+int
+drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
+ u16 *current_level, u8 *current_mode);
+int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level);
+int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level);
+int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
+
#ifdef CONFIG_DRM_DP_CEC
void drm_dp_cec_irq(struct drm_dp_aux *aux);
void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Nouveau] [PATCH v6 8/9] drm/dp: Extract i915's eDP backlight code into DRM helpers
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: David Airlie, Ramalingam C, Imre Deak, Joonas Lahtinen,
Ville Syrjälä,
Jani Nikula, Uma Shankar, Anshuman Gupta, Dave Airlie,
greg.depoire, Maarten Lankhorst, Lucas De Marchi, Maxime Ripard,
Gwan-gyeong Mun, Sean Paul, Jani Nikula, Rodrigo Vivi,
Rajeev Nandan, open list, Daniel Vetter
Since we're about to implement eDP backlight support in nouveau using the
standard protocol from VESA, we might as well just take the code that's
already written for this and move it into a set of shared DRM helpers.
Note that these helpers are intended to handle DPCD related backlight
control bits such as setting the brightness level over AUX, probing the
backlight's TCON, enabling/disabling the backlight over AUX if supported,
etc. Any PWM-related portions of backlight control are explicitly left up
to the driver, as these will vary from platform to platform.
The only exception to this is the calculation of the PWM frequency
pre-divider value. This is because the only platform-specific information
required for this is the PWM frequency of the panel, which the driver is
expected to provide if available. The actual algorithm for calculating this
value is standard and is defined in the eDP specification from VESA.
Note that these helpers do not yet implement the full range of features
the VESA backlight interface provides, and only provide the following
functionality (all of which was already present in i915's DPCD backlight
support):
* Basic control of brightness levels
* Basic probing of backlight capabilities
* Helpers for enabling and disabling the backlight
v3:
* Split out changes to i915's backlight code to separate patches to make it
easier to review
v4:
* Style/spelling changes from Thomas Zimmermann
v5:
* Start using new drm_dbg_*() functions
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
drivers/gpu/drm/drm_dp_helper.c | 347 ++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 5 +-
.../drm/i915/display/intel_dp_aux_backlight.c | 285 ++------------
include/drm/drm_dp_helper.h | 48 +++
4 files changed, 427 insertions(+), 258 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 55b53df6ce34..24bbc710c825 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -3115,3 +3115,350 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
return 0;
}
EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
+
+/**
+ * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ * @level: The brightness level to set
+ *
+ * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
+ * already have been enabled by the driver by calling drm_edp_backlight_enable().
+ *
+ * Returns: %0 on success, negative error code on failure
+ */
+int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level)
+{
+ int ret;
+ u8 buf[2] = { 0 };
+
+ if (bl->lsb_reg_used) {
+ buf[0] = (level & 0xff00) >> 8;
+ buf[1] = (level & 0x00ff);
+ } else {
+ buf[0] = level;
+ }
+
+ ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
+ if (ret != sizeof(buf)) {
+ drm_err(aux->drm_dev,
+ "%s: Failed to write aux backlight level: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_set_level);
+
+static int
+drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ bool enable)
+{
+ int ret;
+ u8 buf;
+
+ /* The panel uses something other then DPCD for enabling its backlight */
+ if (!bl->aux_enable)
+ return 0;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
+ if (ret != 1) {
+ drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+ if (enable)
+ buf |= DP_EDP_BACKLIGHT_ENABLE;
+ else
+ buf &= ~DP_EDP_BACKLIGHT_ENABLE;
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
+ if (ret != 1) {
+ drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ return 0;
+}
+
+/**
+ * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ * @level: The initial backlight level to set via AUX, if there is one
+ *
+ * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
+ * restoring any important backlight state such as the given backlight level, the brightness byte
+ * count, backlight frequency, etc.
+ *
+ * Note that certain panels, while supporting brightness level controls over DPCD, may not support
+ * having their backlights enabled via the standard %DP_EDP_DISPLAY_CONTROL_REGISTER. On such panels
+ * &drm_edp_backlight_info.aux_enable will be set to %false, this function will skip the step of
+ * programming the %DP_EDP_DISPLAY_CONTROL_REGISTER, and the driver must perform the required
+ * implementation specific step for enabling the backlight after calling this function.
+ *
+ * Returns: %0 on success, negative error code on failure.
+ */
+int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ const u16 level)
+{
+ int ret;
+ u8 dpcd_buf, new_dpcd_buf;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Failed to read backlight mode: %d\n", aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ new_dpcd_buf = dpcd_buf;
+
+ if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
+ new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
+ if (ret != 1)
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
+ aux->name, ret);
+ }
+
+ if (bl->pwm_freq_pre_divider) {
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
+ if (ret != 1)
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Failed to write aux backlight frequency: %d\n",
+ aux->name, ret);
+ else
+ new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
+ }
+
+ if (new_dpcd_buf != dpcd_buf) {
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+ }
+
+ ret = drm_edp_backlight_set_level(aux, bl, level);
+ if (ret < 0)
+ return ret;
+ ret = drm_edp_backlight_set_enable(aux, bl, true);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_enable);
+
+/**
+ * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ *
+ * This function handles disabling DPCD backlight controls on a panel over AUX. Note that some
+ * panels have backlights that are enabled/disabled by other means, despite having their brightness
+ * values controlled through DPCD. On such panels &drm_edp_backlight_info.aux_enable will be set to
+ * %false, this function will become a no-op (and we will skip updating
+ * %DP_EDP_DISPLAY_CONTROL_REGISTER), and the driver must take care to perform it's own
+ * implementation specific step for disabling the backlight.
+ *
+ * Returns: %0 on success or no-op, negative error code on failure.
+ */
+int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
+{
+ int ret;
+
+ ret = drm_edp_backlight_set_enable(aux, bl, false);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_disable);
+
+static inline int
+drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
+{
+ int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
+ int ret;
+ u8 pn, pn_min, pn_max;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
+ aux->name, ret);
+ return -ENODEV;
+ }
+
+ pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ bl->max = (1 << pn) - 1;
+ if (!driver_pwm_freq_hz)
+ return 0;
+
+ /*
+ * Set PWM Frequency divider to match desired frequency provided by the driver.
+ * The PWM Frequency is calculated as 27Mhz / (F x P).
+ * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
+ * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
+ * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
+ * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
+ */
+
+ /* Find desired value of (F x P)
+ * Note that, if F x P is out of supported range, the maximum value or minimum value will
+ * applied automatically. So no need to check that.
+ */
+ fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
+
+ /* Use highest possible value of Pn for more granularity of brightness adjustment while
+ * satifying the conditions below.
+ * - Pn is in the range of Pn_min and Pn_max
+ * - F is in the range of 1 and 255
+ * - FxP is within 25% of desired value.
+ * Note: 25% is arbitrary value and may need some tweak.
+ */
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+
+ /* Ensure frequency is within 25% of desired value */
+ fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
+ fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
+ if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Driver defined backlight frequency (%d) out of range\n",
+ aux->name, driver_pwm_freq_hz);
+ return 0;
+ }
+
+ for (pn = pn_max; pn >= pn_min; pn--) {
+ f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
+ fxp_actual = f << pn;
+ if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
+ break;
+ }
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ bl->pwmgen_bit_count = pn;
+ bl->max = (1 << pn) - 1;
+
+ if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
+ bl->pwm_freq_pre_divider = f;
+ drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
+ aux->name, driver_pwm_freq_hz);
+ }
+
+ return 0;
+}
+
+static inline int
+drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u8 *current_mode)
+{
+ int ret;
+ u8 buf[2];
+ u8 mode_reg;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
+ if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ int size = 1 + bl->lsb_reg_used;
+
+ ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
+ if (ret != size) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ if (bl->lsb_reg_used)
+ return (buf[0] << 8) | buf[1];
+ else
+ return buf[0];
+ }
+
+ /*
+ * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
+ * the driver should assume max brightness
+ */
+ return bl->max;
+}
+
+/**
+ * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
+ * interface.
+ * @aux: The DP aux device to use for probing
+ * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
+ * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
+ * @edp_dpcd: A cached copy of the eDP DPCD
+ * @current_level: Where to store the probed brightness level
+ * @current_mode: Where to store the currently set backlight control mode
+ *
+ * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
+ * along with also probing the current and maximum supported brightness levels.
+ *
+ * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
+ * default frequency from the panel is used.
+ *
+ * Returns: %0 on success, negative error code on failure.
+ */
+int
+drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
+ u16 *current_level, u8 *current_mode)
+{
+ int ret;
+
+ if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
+ bl->aux_enable = true;
+ if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+ bl->lsb_reg_used = true;
+
+ ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
+ if (ret < 0)
+ return ret;
+
+ ret = drm_edp_backlight_probe_level(aux, bl, current_mode);
+ if (ret < 0)
+ return ret;
+ *current_level = ret;
+
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Found backlight level=%d/%d pwm_freq_pre_divider=%d mode=%x\n",
+ aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, *current_mode);
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Backlight caps: pwmgen_bit_count=%d lsb_reg_used=%d aux_enable=%d\n",
+ aux->name, bl->pwmgen_bit_count, bl->lsb_reg_used, bl->aux_enable);
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_init);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d4a57bce71b1..8696b39da2fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -310,10 +310,7 @@ struct intel_panel {
/* DPCD backlight */
union {
struct {
- u8 pwmgen_bit_count;
- u8 pwm_freq_pre_divider;
- bool lsb_reg_used;
- bool aux_enable;
+ struct drm_edp_backlight_info info;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 95f2df631052..6ac568617ef3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,114 +270,19 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 mode_reg;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
- return false;
- }
-
- return (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
- DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
-}
-
-/*
- * Read the current backlight value from DPCD register(s) based
- * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
- */
static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, enum pipe unused)
{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 read_val[2] = { 0x0 };
- u16 level = 0;
-
- /*
- * If we're not in DPCD control mode yet, the programmed brightness
- * value is meaningless and we should assume max brightness
- */
- if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
- return connector->panel.backlight.max;
-
- ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
- sizeof(read_val));
- if (ret != sizeof(read_val)) {
- drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
- return 0;
- }
-
- if (connector->panel.backlight.edp.vesa.lsb_reg_used)
- level = (read_val[0] << 8 | read_val[1]);
- else
- level = read_val[0];
-
- return level;
+ return connector->panel.backlight.level;
}
-/*
- * Sends the current backlight level over the aux channel, checking if its using
- * 8-bit or 16 bit value (MSB and LSB)
- */
static void
-intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
- u32 level)
+intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, u32 level)
{
struct intel_connector *connector = to_intel_connector(conn_state->connector);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 vals[2] = { 0x0 };
-
- /* Write the MSB and/or LSB */
- if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
- vals[0] = (level & 0xFF00) >> 8;
- vals[1] = (level & 0xFF);
- } else {
- vals[0] = level;
- }
-
- ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
- sizeof(vals));
- if (ret != sizeof(vals)) {
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
- return;
- }
-}
-
-static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 reg_val = 0;
-
- /* Early return when display use other mechanism to enable backlight. */
- if (!connector->panel.backlight.edp.vesa.aux_enable)
- return;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
- return;
- }
-
- if (enable)
- reg_val |= DP_EDP_BACKLIGHT_ENABLE;
- else
- reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+ struct intel_panel *panel = &connector->panel;
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
- enabledisable(enable), ret);
- }
+ drm_edp_backlight_set_level(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
}
static void
@@ -385,170 +290,46 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
{
struct intel_connector *connector = to_intel_connector(conn_state->connector);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
- int ret;
- u8 dpcd_buf, new_dpcd_buf;
- u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
- return;
- }
-
- new_dpcd_buf = dpcd_buf;
-
- if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
- new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
- new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
-
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
- if (ret != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
- }
-
- if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
- panel->backlight.edp.vesa.pwm_freq_pre_divider);
- if (ret == 1)
- new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
- else
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
- ret);
- }
-
- if (new_dpcd_buf != dpcd_buf) {
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- new_dpcd_buf);
- if (ret != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
- }
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- intel_dp_aux_vesa_set_backlight(conn_state, level);
- set_vesa_backlight_enable(connector, true);
+ drm_edp_backlight_enable(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
}
static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
u32 level)
{
- set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
-}
-
-/*
- * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
- * The PWM Frequency is calculated as 27Mhz / (F x P).
- * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
- * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
- * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
- * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
- */
-static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
-{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
struct intel_panel *panel = &connector->panel;
- u32 max_backlight = 0;
- int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
- u8 pn, pn_min, pn_max;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
- return 0;
- }
-
- pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- max_backlight = (1 << pn) - 1;
-
- /* Find desired value of (F x P)
- * Note that, if F x P is out of supported range, the maximum value or
- * minimum value will applied automatically. So no need to check that.
- */
- freq = i915->vbt.backlight.pwm_freq_hz;
- drm_dbg_kms(&i915->drm, "VBT defined backlight frequency %u Hz\n",
- freq);
- if (!freq) {
- drm_dbg_kms(&i915->drm,
- "Use panel default backlight frequency\n");
- return max_backlight;
- }
-
- fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
-
- /* Use highest possible value of Pn for more granularity of brightness
- * adjustment while satifying the conditions below.
- * - Pn is in the range of Pn_min and Pn_max
- * - F is in the range of 1 and 255
- * - FxP is within 25% of desired value.
- * Note: 25% is arbitrary value and may need some tweak.
- */
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
- return max_backlight;
- }
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
- return max_backlight;
- }
- pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
-
- /* Ensure frequency is within 25% of desired value */
- fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
- fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
-
- if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
- drm_dbg_kms(&i915->drm,
- "VBT defined backlight frequency out of range\n");
- return max_backlight;
- }
-
- for (pn = pn_max; pn >= pn_min; pn--) {
- f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
- fxp_actual = f << pn;
- if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
- break;
- }
-
- drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
- return max_backlight;
- }
-
- panel->backlight.edp.vesa.pwmgen_bit_count = pn;
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
- panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
-
- max_backlight = (1 << pn) - 1;
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- return max_backlight;
+ drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info);
}
-static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
- enum pipe pipe)
+static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 current_level;
+ u8 current_mode;
+ int ret;
- if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
- panel->backlight.edp.vesa.aux_enable = true;
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
- panel->backlight.edp.vesa.lsb_reg_used = true;
-
- panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
- if (!panel->backlight.max)
- return -ENODEV;
+ ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,
+ i915->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
+ ¤t_level, ¤t_mode);
+ if (ret < 0)
+ return ret;
+ panel->backlight.max = panel->backlight.edp.vesa.info.max;
panel->backlight.min = 0;
- panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector, pipe);
- panel->backlight.enabled = intel_dp_aux_vesa_backlight_dpcd_mode(connector) &&
- panel->backlight.level != 0;
+ if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ panel->backlight.level = current_level;
+ panel->backlight.enabled = panel->backlight.level != 0;
+ } else {
+ panel->backlight.level = panel->backlight.max;
+ panel->backlight.enabled = false;
+ }
return 0;
}
@@ -559,16 +340,12 @@ intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector)
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- /* Check the eDP Display control capabilities registers to determine if
- * the panel can support backlight control over the aux channel.
- *
- * TODO: We currently only support AUX only backlight configurations, not backlights which
+ /* TODO: We currently only support AUX only backlight configurations, not backlights which
* require a mix of PWM and AUX controls to work. In the mean time, these machines typically
* work just fine using normal PWM controls anyway.
*/
- if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
- (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
- (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
+ if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
+ drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
drm_dbg_kms(&i915->drm, "AUX Backlight Control Supported!\n");
return true;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 06681bf46d81..0bd6396648b4 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1801,6 +1801,24 @@ drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_MSA_TIMING_PAR_IGNORED;
}
+/**
+ * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
+ * @edp_dpcd: The DPCD to check
+ *
+ * Note that currently this function will return %false for panels which support various DPCD
+ * backlight features but which require the brightness be set through PWM, and don't support setting
+ * the brightness level via the DPCD. This is a TODO.
+ *
+ * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
+ * otherwise
+ */
+static inline bool
+drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
+{
+ return (edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
+ (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP);
+}
+
/*
* DisplayPort AUX channel
*/
@@ -2107,6 +2125,36 @@ drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
return desc->quirks & BIT(quirk);
}
+/**
+ * struct drm_edp_backlight_info - Probed eDP backlight info struct
+ * @pwmgen_bit_count: The pwmgen bit count
+ * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
+ * @max: The maximum backlight level that may be set
+ * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
+ * @aux_enable: Does the panel support the AUX enable cap?
+ *
+ * This structure contains various data about an eDP backlight, which can be populated by using
+ * drm_edp_backlight_init().
+ */
+struct drm_edp_backlight_info {
+ u8 pwmgen_bit_count;
+ u8 pwm_freq_pre_divider;
+ u16 max;
+
+ bool lsb_reg_used : 1;
+ bool aux_enable : 1;
+};
+
+int
+drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
+ u16 *current_level, u8 *current_mode);
+int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level);
+int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level);
+int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
+
#ifdef CONFIG_DRM_DP_CEC
void drm_dp_cec_irq(struct drm_dp_aux *aux);
void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
--
2.31.1
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 8/9] drm/dp: Extract i915's eDP backlight code into DRM helpers
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: David Airlie, Jani Nikula, Uma Shankar, Anshuman Gupta,
Dave Airlie, Thomas Zimmermann, greg.depoire, Lucas De Marchi,
Gwan-gyeong Mun, Sean Paul, Rodrigo Vivi, Rajeev Nandan,
open list
Since we're about to implement eDP backlight support in nouveau using the
standard protocol from VESA, we might as well just take the code that's
already written for this and move it into a set of shared DRM helpers.
Note that these helpers are intended to handle DPCD related backlight
control bits such as setting the brightness level over AUX, probing the
backlight's TCON, enabling/disabling the backlight over AUX if supported,
etc. Any PWM-related portions of backlight control are explicitly left up
to the driver, as these will vary from platform to platform.
The only exception to this is the calculation of the PWM frequency
pre-divider value. This is because the only platform-specific information
required for this is the PWM frequency of the panel, which the driver is
expected to provide if available. The actual algorithm for calculating this
value is standard and is defined in the eDP specification from VESA.
Note that these helpers do not yet implement the full range of features
the VESA backlight interface provides, and only provide the following
functionality (all of which was already present in i915's DPCD backlight
support):
* Basic control of brightness levels
* Basic probing of backlight capabilities
* Helpers for enabling and disabling the backlight
v3:
* Split out changes to i915's backlight code to separate patches to make it
easier to review
v4:
* Style/spelling changes from Thomas Zimmermann
v5:
* Start using new drm_dbg_*() functions
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
drivers/gpu/drm/drm_dp_helper.c | 347 ++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 5 +-
.../drm/i915/display/intel_dp_aux_backlight.c | 285 ++------------
include/drm/drm_dp_helper.h | 48 +++
4 files changed, 427 insertions(+), 258 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 55b53df6ce34..24bbc710c825 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -3115,3 +3115,350 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
return 0;
}
EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
+
+/**
+ * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ * @level: The brightness level to set
+ *
+ * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
+ * already have been enabled by the driver by calling drm_edp_backlight_enable().
+ *
+ * Returns: %0 on success, negative error code on failure
+ */
+int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level)
+{
+ int ret;
+ u8 buf[2] = { 0 };
+
+ if (bl->lsb_reg_used) {
+ buf[0] = (level & 0xff00) >> 8;
+ buf[1] = (level & 0x00ff);
+ } else {
+ buf[0] = level;
+ }
+
+ ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
+ if (ret != sizeof(buf)) {
+ drm_err(aux->drm_dev,
+ "%s: Failed to write aux backlight level: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_set_level);
+
+static int
+drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ bool enable)
+{
+ int ret;
+ u8 buf;
+
+ /* The panel uses something other then DPCD for enabling its backlight */
+ if (!bl->aux_enable)
+ return 0;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
+ if (ret != 1) {
+ drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+ if (enable)
+ buf |= DP_EDP_BACKLIGHT_ENABLE;
+ else
+ buf &= ~DP_EDP_BACKLIGHT_ENABLE;
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
+ if (ret != 1) {
+ drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ return 0;
+}
+
+/**
+ * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ * @level: The initial backlight level to set via AUX, if there is one
+ *
+ * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
+ * restoring any important backlight state such as the given backlight level, the brightness byte
+ * count, backlight frequency, etc.
+ *
+ * Note that certain panels, while supporting brightness level controls over DPCD, may not support
+ * having their backlights enabled via the standard %DP_EDP_DISPLAY_CONTROL_REGISTER. On such panels
+ * &drm_edp_backlight_info.aux_enable will be set to %false, this function will skip the step of
+ * programming the %DP_EDP_DISPLAY_CONTROL_REGISTER, and the driver must perform the required
+ * implementation specific step for enabling the backlight after calling this function.
+ *
+ * Returns: %0 on success, negative error code on failure.
+ */
+int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ const u16 level)
+{
+ int ret;
+ u8 dpcd_buf, new_dpcd_buf;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Failed to read backlight mode: %d\n", aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ new_dpcd_buf = dpcd_buf;
+
+ if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
+ new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
+ if (ret != 1)
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
+ aux->name, ret);
+ }
+
+ if (bl->pwm_freq_pre_divider) {
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
+ if (ret != 1)
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Failed to write aux backlight frequency: %d\n",
+ aux->name, ret);
+ else
+ new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
+ }
+
+ if (new_dpcd_buf != dpcd_buf) {
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+ }
+
+ ret = drm_edp_backlight_set_level(aux, bl, level);
+ if (ret < 0)
+ return ret;
+ ret = drm_edp_backlight_set_enable(aux, bl, true);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_enable);
+
+/**
+ * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ *
+ * This function handles disabling DPCD backlight controls on a panel over AUX. Note that some
+ * panels have backlights that are enabled/disabled by other means, despite having their brightness
+ * values controlled through DPCD. On such panels &drm_edp_backlight_info.aux_enable will be set to
+ * %false, this function will become a no-op (and we will skip updating
+ * %DP_EDP_DISPLAY_CONTROL_REGISTER), and the driver must take care to perform it's own
+ * implementation specific step for disabling the backlight.
+ *
+ * Returns: %0 on success or no-op, negative error code on failure.
+ */
+int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
+{
+ int ret;
+
+ ret = drm_edp_backlight_set_enable(aux, bl, false);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_disable);
+
+static inline int
+drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
+{
+ int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
+ int ret;
+ u8 pn, pn_min, pn_max;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
+ aux->name, ret);
+ return -ENODEV;
+ }
+
+ pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ bl->max = (1 << pn) - 1;
+ if (!driver_pwm_freq_hz)
+ return 0;
+
+ /*
+ * Set PWM Frequency divider to match desired frequency provided by the driver.
+ * The PWM Frequency is calculated as 27Mhz / (F x P).
+ * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
+ * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
+ * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
+ * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
+ */
+
+ /* Find desired value of (F x P)
+ * Note that, if F x P is out of supported range, the maximum value or minimum value will
+ * applied automatically. So no need to check that.
+ */
+ fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
+
+ /* Use highest possible value of Pn for more granularity of brightness adjustment while
+ * satifying the conditions below.
+ * - Pn is in the range of Pn_min and Pn_max
+ * - F is in the range of 1 and 255
+ * - FxP is within 25% of desired value.
+ * Note: 25% is arbitrary value and may need some tweak.
+ */
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+
+ /* Ensure frequency is within 25% of desired value */
+ fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
+ fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
+ if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Driver defined backlight frequency (%d) out of range\n",
+ aux->name, driver_pwm_freq_hz);
+ return 0;
+ }
+
+ for (pn = pn_max; pn >= pn_min; pn--) {
+ f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
+ fxp_actual = f << pn;
+ if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
+ break;
+ }
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ bl->pwmgen_bit_count = pn;
+ bl->max = (1 << pn) - 1;
+
+ if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
+ bl->pwm_freq_pre_divider = f;
+ drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
+ aux->name, driver_pwm_freq_hz);
+ }
+
+ return 0;
+}
+
+static inline int
+drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u8 *current_mode)
+{
+ int ret;
+ u8 buf[2];
+ u8 mode_reg;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
+ if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ int size = 1 + bl->lsb_reg_used;
+
+ ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
+ if (ret != size) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ if (bl->lsb_reg_used)
+ return (buf[0] << 8) | buf[1];
+ else
+ return buf[0];
+ }
+
+ /*
+ * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
+ * the driver should assume max brightness
+ */
+ return bl->max;
+}
+
+/**
+ * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
+ * interface.
+ * @aux: The DP aux device to use for probing
+ * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
+ * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
+ * @edp_dpcd: A cached copy of the eDP DPCD
+ * @current_level: Where to store the probed brightness level
+ * @current_mode: Where to store the currently set backlight control mode
+ *
+ * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
+ * along with also probing the current and maximum supported brightness levels.
+ *
+ * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
+ * default frequency from the panel is used.
+ *
+ * Returns: %0 on success, negative error code on failure.
+ */
+int
+drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
+ u16 *current_level, u8 *current_mode)
+{
+ int ret;
+
+ if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
+ bl->aux_enable = true;
+ if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+ bl->lsb_reg_used = true;
+
+ ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
+ if (ret < 0)
+ return ret;
+
+ ret = drm_edp_backlight_probe_level(aux, bl, current_mode);
+ if (ret < 0)
+ return ret;
+ *current_level = ret;
+
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Found backlight level=%d/%d pwm_freq_pre_divider=%d mode=%x\n",
+ aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, *current_mode);
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Backlight caps: pwmgen_bit_count=%d lsb_reg_used=%d aux_enable=%d\n",
+ aux->name, bl->pwmgen_bit_count, bl->lsb_reg_used, bl->aux_enable);
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_init);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d4a57bce71b1..8696b39da2fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -310,10 +310,7 @@ struct intel_panel {
/* DPCD backlight */
union {
struct {
- u8 pwmgen_bit_count;
- u8 pwm_freq_pre_divider;
- bool lsb_reg_used;
- bool aux_enable;
+ struct drm_edp_backlight_info info;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 95f2df631052..6ac568617ef3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,114 +270,19 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 mode_reg;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
- return false;
- }
-
- return (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
- DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
-}
-
-/*
- * Read the current backlight value from DPCD register(s) based
- * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
- */
static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, enum pipe unused)
{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 read_val[2] = { 0x0 };
- u16 level = 0;
-
- /*
- * If we're not in DPCD control mode yet, the programmed brightness
- * value is meaningless and we should assume max brightness
- */
- if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
- return connector->panel.backlight.max;
-
- ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
- sizeof(read_val));
- if (ret != sizeof(read_val)) {
- drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
- return 0;
- }
-
- if (connector->panel.backlight.edp.vesa.lsb_reg_used)
- level = (read_val[0] << 8 | read_val[1]);
- else
- level = read_val[0];
-
- return level;
+ return connector->panel.backlight.level;
}
-/*
- * Sends the current backlight level over the aux channel, checking if its using
- * 8-bit or 16 bit value (MSB and LSB)
- */
static void
-intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
- u32 level)
+intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, u32 level)
{
struct intel_connector *connector = to_intel_connector(conn_state->connector);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 vals[2] = { 0x0 };
-
- /* Write the MSB and/or LSB */
- if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
- vals[0] = (level & 0xFF00) >> 8;
- vals[1] = (level & 0xFF);
- } else {
- vals[0] = level;
- }
-
- ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
- sizeof(vals));
- if (ret != sizeof(vals)) {
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
- return;
- }
-}
-
-static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 reg_val = 0;
-
- /* Early return when display use other mechanism to enable backlight. */
- if (!connector->panel.backlight.edp.vesa.aux_enable)
- return;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
- return;
- }
-
- if (enable)
- reg_val |= DP_EDP_BACKLIGHT_ENABLE;
- else
- reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+ struct intel_panel *panel = &connector->panel;
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
- enabledisable(enable), ret);
- }
+ drm_edp_backlight_set_level(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
}
static void
@@ -385,170 +290,46 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
{
struct intel_connector *connector = to_intel_connector(conn_state->connector);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
- int ret;
- u8 dpcd_buf, new_dpcd_buf;
- u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
- return;
- }
-
- new_dpcd_buf = dpcd_buf;
-
- if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
- new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
- new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
-
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
- if (ret != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
- }
-
- if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
- panel->backlight.edp.vesa.pwm_freq_pre_divider);
- if (ret == 1)
- new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
- else
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
- ret);
- }
-
- if (new_dpcd_buf != dpcd_buf) {
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- new_dpcd_buf);
- if (ret != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
- }
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- intel_dp_aux_vesa_set_backlight(conn_state, level);
- set_vesa_backlight_enable(connector, true);
+ drm_edp_backlight_enable(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
}
static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
u32 level)
{
- set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
-}
-
-/*
- * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
- * The PWM Frequency is calculated as 27Mhz / (F x P).
- * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
- * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
- * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
- * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
- */
-static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
-{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
struct intel_panel *panel = &connector->panel;
- u32 max_backlight = 0;
- int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
- u8 pn, pn_min, pn_max;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
- return 0;
- }
-
- pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- max_backlight = (1 << pn) - 1;
-
- /* Find desired value of (F x P)
- * Note that, if F x P is out of supported range, the maximum value or
- * minimum value will applied automatically. So no need to check that.
- */
- freq = i915->vbt.backlight.pwm_freq_hz;
- drm_dbg_kms(&i915->drm, "VBT defined backlight frequency %u Hz\n",
- freq);
- if (!freq) {
- drm_dbg_kms(&i915->drm,
- "Use panel default backlight frequency\n");
- return max_backlight;
- }
-
- fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
-
- /* Use highest possible value of Pn for more granularity of brightness
- * adjustment while satifying the conditions below.
- * - Pn is in the range of Pn_min and Pn_max
- * - F is in the range of 1 and 255
- * - FxP is within 25% of desired value.
- * Note: 25% is arbitrary value and may need some tweak.
- */
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
- return max_backlight;
- }
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
- return max_backlight;
- }
- pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
-
- /* Ensure frequency is within 25% of desired value */
- fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
- fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
-
- if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
- drm_dbg_kms(&i915->drm,
- "VBT defined backlight frequency out of range\n");
- return max_backlight;
- }
-
- for (pn = pn_max; pn >= pn_min; pn--) {
- f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
- fxp_actual = f << pn;
- if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
- break;
- }
-
- drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
- return max_backlight;
- }
-
- panel->backlight.edp.vesa.pwmgen_bit_count = pn;
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
- panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
-
- max_backlight = (1 << pn) - 1;
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- return max_backlight;
+ drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info);
}
-static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
- enum pipe pipe)
+static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 current_level;
+ u8 current_mode;
+ int ret;
- if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
- panel->backlight.edp.vesa.aux_enable = true;
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
- panel->backlight.edp.vesa.lsb_reg_used = true;
-
- panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
- if (!panel->backlight.max)
- return -ENODEV;
+ ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,
+ i915->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
+ ¤t_level, ¤t_mode);
+ if (ret < 0)
+ return ret;
+ panel->backlight.max = panel->backlight.edp.vesa.info.max;
panel->backlight.min = 0;
- panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector, pipe);
- panel->backlight.enabled = intel_dp_aux_vesa_backlight_dpcd_mode(connector) &&
- panel->backlight.level != 0;
+ if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ panel->backlight.level = current_level;
+ panel->backlight.enabled = panel->backlight.level != 0;
+ } else {
+ panel->backlight.level = panel->backlight.max;
+ panel->backlight.enabled = false;
+ }
return 0;
}
@@ -559,16 +340,12 @@ intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector)
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- /* Check the eDP Display control capabilities registers to determine if
- * the panel can support backlight control over the aux channel.
- *
- * TODO: We currently only support AUX only backlight configurations, not backlights which
+ /* TODO: We currently only support AUX only backlight configurations, not backlights which
* require a mix of PWM and AUX controls to work. In the mean time, these machines typically
* work just fine using normal PWM controls anyway.
*/
- if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
- (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
- (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
+ if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
+ drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
drm_dbg_kms(&i915->drm, "AUX Backlight Control Supported!\n");
return true;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 06681bf46d81..0bd6396648b4 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1801,6 +1801,24 @@ drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_MSA_TIMING_PAR_IGNORED;
}
+/**
+ * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
+ * @edp_dpcd: The DPCD to check
+ *
+ * Note that currently this function will return %false for panels which support various DPCD
+ * backlight features but which require the brightness be set through PWM, and don't support setting
+ * the brightness level via the DPCD. This is a TODO.
+ *
+ * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
+ * otherwise
+ */
+static inline bool
+drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
+{
+ return (edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
+ (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP);
+}
+
/*
* DisplayPort AUX channel
*/
@@ -2107,6 +2125,36 @@ drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
return desc->quirks & BIT(quirk);
}
+/**
+ * struct drm_edp_backlight_info - Probed eDP backlight info struct
+ * @pwmgen_bit_count: The pwmgen bit count
+ * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
+ * @max: The maximum backlight level that may be set
+ * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
+ * @aux_enable: Does the panel support the AUX enable cap?
+ *
+ * This structure contains various data about an eDP backlight, which can be populated by using
+ * drm_edp_backlight_init().
+ */
+struct drm_edp_backlight_info {
+ u8 pwmgen_bit_count;
+ u8 pwm_freq_pre_divider;
+ u16 max;
+
+ bool lsb_reg_used : 1;
+ bool aux_enable : 1;
+};
+
+int
+drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
+ u16 *current_level, u8 *current_mode);
+int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level);
+int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level);
+int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
+
#ifdef CONFIG_DRM_DP_CEC
void drm_dp_cec_irq(struct drm_dp_aux *aux);
void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v6 8/9] drm/dp: Extract i915's eDP backlight code into DRM helpers
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: David Airlie, Jani Nikula, Dave Airlie, Thomas Zimmermann,
greg.depoire, Lucas De Marchi, Maxime Ripard, Sean Paul,
Rajeev Nandan, open list
Since we're about to implement eDP backlight support in nouveau using the
standard protocol from VESA, we might as well just take the code that's
already written for this and move it into a set of shared DRM helpers.
Note that these helpers are intended to handle DPCD related backlight
control bits such as setting the brightness level over AUX, probing the
backlight's TCON, enabling/disabling the backlight over AUX if supported,
etc. Any PWM-related portions of backlight control are explicitly left up
to the driver, as these will vary from platform to platform.
The only exception to this is the calculation of the PWM frequency
pre-divider value. This is because the only platform-specific information
required for this is the PWM frequency of the panel, which the driver is
expected to provide if available. The actual algorithm for calculating this
value is standard and is defined in the eDP specification from VESA.
Note that these helpers do not yet implement the full range of features
the VESA backlight interface provides, and only provide the following
functionality (all of which was already present in i915's DPCD backlight
support):
* Basic control of brightness levels
* Basic probing of backlight capabilities
* Helpers for enabling and disabling the backlight
v3:
* Split out changes to i915's backlight code to separate patches to make it
easier to review
v4:
* Style/spelling changes from Thomas Zimmermann
v5:
* Start using new drm_dbg_*() functions
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
drivers/gpu/drm/drm_dp_helper.c | 347 ++++++++++++++++++
.../drm/i915/display/intel_display_types.h | 5 +-
.../drm/i915/display/intel_dp_aux_backlight.c | 285 ++------------
include/drm/drm_dp_helper.h | 48 +++
4 files changed, 427 insertions(+), 258 deletions(-)
diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
index 55b53df6ce34..24bbc710c825 100644
--- a/drivers/gpu/drm/drm_dp_helper.c
+++ b/drivers/gpu/drm/drm_dp_helper.c
@@ -3115,3 +3115,350 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
return 0;
}
EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
+
+/**
+ * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ * @level: The brightness level to set
+ *
+ * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
+ * already have been enabled by the driver by calling drm_edp_backlight_enable().
+ *
+ * Returns: %0 on success, negative error code on failure
+ */
+int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level)
+{
+ int ret;
+ u8 buf[2] = { 0 };
+
+ if (bl->lsb_reg_used) {
+ buf[0] = (level & 0xff00) >> 8;
+ buf[1] = (level & 0x00ff);
+ } else {
+ buf[0] = level;
+ }
+
+ ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
+ if (ret != sizeof(buf)) {
+ drm_err(aux->drm_dev,
+ "%s: Failed to write aux backlight level: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_set_level);
+
+static int
+drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ bool enable)
+{
+ int ret;
+ u8 buf;
+
+ /* The panel uses something other then DPCD for enabling its backlight */
+ if (!bl->aux_enable)
+ return 0;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
+ if (ret != 1) {
+ drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+ if (enable)
+ buf |= DP_EDP_BACKLIGHT_ENABLE;
+ else
+ buf &= ~DP_EDP_BACKLIGHT_ENABLE;
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
+ if (ret != 1) {
+ drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ return 0;
+}
+
+/**
+ * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ * @level: The initial backlight level to set via AUX, if there is one
+ *
+ * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
+ * restoring any important backlight state such as the given backlight level, the brightness byte
+ * count, backlight frequency, etc.
+ *
+ * Note that certain panels, while supporting brightness level controls over DPCD, may not support
+ * having their backlights enabled via the standard %DP_EDP_DISPLAY_CONTROL_REGISTER. On such panels
+ * &drm_edp_backlight_info.aux_enable will be set to %false, this function will skip the step of
+ * programming the %DP_EDP_DISPLAY_CONTROL_REGISTER, and the driver must perform the required
+ * implementation specific step for enabling the backlight after calling this function.
+ *
+ * Returns: %0 on success, negative error code on failure.
+ */
+int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ const u16 level)
+{
+ int ret;
+ u8 dpcd_buf, new_dpcd_buf;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Failed to read backlight mode: %d\n", aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ new_dpcd_buf = dpcd_buf;
+
+ if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
+ new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
+ if (ret != 1)
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
+ aux->name, ret);
+ }
+
+ if (bl->pwm_freq_pre_divider) {
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
+ if (ret != 1)
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Failed to write aux backlight frequency: %d\n",
+ aux->name, ret);
+ else
+ new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
+ }
+
+ if (new_dpcd_buf != dpcd_buf) {
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+ }
+
+ ret = drm_edp_backlight_set_level(aux, bl, level);
+ if (ret < 0)
+ return ret;
+ ret = drm_edp_backlight_set_enable(aux, bl, true);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_enable);
+
+/**
+ * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
+ * @aux: The DP AUX channel to use
+ * @bl: Backlight capability info from drm_edp_backlight_init()
+ *
+ * This function handles disabling DPCD backlight controls on a panel over AUX. Note that some
+ * panels have backlights that are enabled/disabled by other means, despite having their brightness
+ * values controlled through DPCD. On such panels &drm_edp_backlight_info.aux_enable will be set to
+ * %false, this function will become a no-op (and we will skip updating
+ * %DP_EDP_DISPLAY_CONTROL_REGISTER), and the driver must take care to perform it's own
+ * implementation specific step for disabling the backlight.
+ *
+ * Returns: %0 on success or no-op, negative error code on failure.
+ */
+int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
+{
+ int ret;
+
+ ret = drm_edp_backlight_set_enable(aux, bl, false);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_disable);
+
+static inline int
+drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
+{
+ int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
+ int ret;
+ u8 pn, pn_min, pn_max;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
+ aux->name, ret);
+ return -ENODEV;
+ }
+
+ pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ bl->max = (1 << pn) - 1;
+ if (!driver_pwm_freq_hz)
+ return 0;
+
+ /*
+ * Set PWM Frequency divider to match desired frequency provided by the driver.
+ * The PWM Frequency is calculated as 27Mhz / (F x P).
+ * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
+ * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
+ * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
+ * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
+ */
+
+ /* Find desired value of (F x P)
+ * Note that, if F x P is out of supported range, the maximum value or minimum value will
+ * applied automatically. So no need to check that.
+ */
+ fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
+
+ /* Use highest possible value of Pn for more granularity of brightness adjustment while
+ * satifying the conditions below.
+ * - Pn is in the range of Pn_min and Pn_max
+ * - F is in the range of 1 and 255
+ * - FxP is within 25% of desired value.
+ * Note: 25% is arbitrary value and may need some tweak.
+ */
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+ pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
+
+ /* Ensure frequency is within 25% of desired value */
+ fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
+ fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
+ if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Driver defined backlight frequency (%d) out of range\n",
+ aux->name, driver_pwm_freq_hz);
+ return 0;
+ }
+
+ for (pn = pn_max; pn >= pn_min; pn--) {
+ f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
+ fxp_actual = f << pn;
+ if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
+ break;
+ }
+
+ ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
+ aux->name, ret);
+ return 0;
+ }
+ bl->pwmgen_bit_count = pn;
+ bl->max = (1 << pn) - 1;
+
+ if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
+ bl->pwm_freq_pre_divider = f;
+ drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
+ aux->name, driver_pwm_freq_hz);
+ }
+
+ return 0;
+}
+
+static inline int
+drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u8 *current_mode)
+{
+ int ret;
+ u8 buf[2];
+ u8 mode_reg;
+
+ ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
+ if (ret != 1) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
+ if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ int size = 1 + bl->lsb_reg_used;
+
+ ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
+ if (ret != size) {
+ drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
+ aux->name, ret);
+ return ret < 0 ? ret : -EIO;
+ }
+
+ if (bl->lsb_reg_used)
+ return (buf[0] << 8) | buf[1];
+ else
+ return buf[0];
+ }
+
+ /*
+ * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
+ * the driver should assume max brightness
+ */
+ return bl->max;
+}
+
+/**
+ * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
+ * interface.
+ * @aux: The DP aux device to use for probing
+ * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
+ * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
+ * @edp_dpcd: A cached copy of the eDP DPCD
+ * @current_level: Where to store the probed brightness level
+ * @current_mode: Where to store the currently set backlight control mode
+ *
+ * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
+ * along with also probing the current and maximum supported brightness levels.
+ *
+ * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
+ * default frequency from the panel is used.
+ *
+ * Returns: %0 on success, negative error code on failure.
+ */
+int
+drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
+ u16 *current_level, u8 *current_mode)
+{
+ int ret;
+
+ if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
+ bl->aux_enable = true;
+ if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
+ bl->lsb_reg_used = true;
+
+ ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
+ if (ret < 0)
+ return ret;
+
+ ret = drm_edp_backlight_probe_level(aux, bl, current_mode);
+ if (ret < 0)
+ return ret;
+ *current_level = ret;
+
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Found backlight level=%d/%d pwm_freq_pre_divider=%d mode=%x\n",
+ aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, *current_mode);
+ drm_dbg_kms(aux->drm_dev,
+ "%s: Backlight caps: pwmgen_bit_count=%d lsb_reg_used=%d aux_enable=%d\n",
+ aux->name, bl->pwmgen_bit_count, bl->lsb_reg_used, bl->aux_enable);
+ return 0;
+}
+EXPORT_SYMBOL(drm_edp_backlight_init);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index d4a57bce71b1..8696b39da2fe 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -310,10 +310,7 @@ struct intel_panel {
/* DPCD backlight */
union {
struct {
- u8 pwmgen_bit_count;
- u8 pwm_freq_pre_divider;
- bool lsb_reg_used;
- bool aux_enable;
+ struct drm_edp_backlight_info info;
} vesa;
struct {
bool sdr_uses_aux;
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
index 95f2df631052..6ac568617ef3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
@@ -270,114 +270,19 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
}
/* VESA backlight callbacks */
-static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 mode_reg;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
- return false;
- }
-
- return (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
- DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
-}
-
-/*
- * Read the current backlight value from DPCD register(s) based
- * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
- */
static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, enum pipe unused)
{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 read_val[2] = { 0x0 };
- u16 level = 0;
-
- /*
- * If we're not in DPCD control mode yet, the programmed brightness
- * value is meaningless and we should assume max brightness
- */
- if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
- return connector->panel.backlight.max;
-
- ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
- sizeof(read_val));
- if (ret != sizeof(read_val)) {
- drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
- return 0;
- }
-
- if (connector->panel.backlight.edp.vesa.lsb_reg_used)
- level = (read_val[0] << 8 | read_val[1]);
- else
- level = read_val[0];
-
- return level;
+ return connector->panel.backlight.level;
}
-/*
- * Sends the current backlight level over the aux channel, checking if its using
- * 8-bit or 16 bit value (MSB and LSB)
- */
static void
-intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
- u32 level)
+intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, u32 level)
{
struct intel_connector *connector = to_intel_connector(conn_state->connector);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 vals[2] = { 0x0 };
-
- /* Write the MSB and/or LSB */
- if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
- vals[0] = (level & 0xFF00) >> 8;
- vals[1] = (level & 0xFF);
- } else {
- vals[0] = level;
- }
-
- ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
- sizeof(vals));
- if (ret != sizeof(vals)) {
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
- return;
- }
-}
-
-static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
-{
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- int ret;
- u8 reg_val = 0;
-
- /* Early return when display use other mechanism to enable backlight. */
- if (!connector->panel.backlight.edp.vesa.aux_enable)
- return;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
- return;
- }
-
- if (enable)
- reg_val |= DP_EDP_BACKLIGHT_ENABLE;
- else
- reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
+ struct intel_panel *panel = &connector->panel;
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
- enabledisable(enable), ret);
- }
+ drm_edp_backlight_set_level(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
}
static void
@@ -385,170 +290,46 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state, u32 level)
{
struct intel_connector *connector = to_intel_connector(conn_state->connector);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
struct intel_panel *panel = &connector->panel;
- int ret;
- u8 dpcd_buf, new_dpcd_buf;
- u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
- return;
- }
-
- new_dpcd_buf = dpcd_buf;
-
- if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
- new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
- new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
-
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
- if (ret != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
- }
-
- if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
- panel->backlight.edp.vesa.pwm_freq_pre_divider);
- if (ret == 1)
- new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
- else
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
- ret);
- }
-
- if (new_dpcd_buf != dpcd_buf) {
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
- new_dpcd_buf);
- if (ret != 1)
- drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
- }
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- intel_dp_aux_vesa_set_backlight(conn_state, level);
- set_vesa_backlight_enable(connector, true);
+ drm_edp_backlight_enable(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
}
static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
u32 level)
{
- set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
-}
-
-/*
- * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
- * The PWM Frequency is calculated as 27Mhz / (F x P).
- * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
- * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
- * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
- * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
- */
-static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
-{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
- struct intel_dp *intel_dp = intel_attached_dp(connector);
+ struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
struct intel_panel *panel = &connector->panel;
- u32 max_backlight = 0;
- int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
- u8 pn, pn_min, pn_max;
-
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
- return 0;
- }
-
- pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- max_backlight = (1 << pn) - 1;
-
- /* Find desired value of (F x P)
- * Note that, if F x P is out of supported range, the maximum value or
- * minimum value will applied automatically. So no need to check that.
- */
- freq = i915->vbt.backlight.pwm_freq_hz;
- drm_dbg_kms(&i915->drm, "VBT defined backlight frequency %u Hz\n",
- freq);
- if (!freq) {
- drm_dbg_kms(&i915->drm,
- "Use panel default backlight frequency\n");
- return max_backlight;
- }
-
- fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
-
- /* Use highest possible value of Pn for more granularity of brightness
- * adjustment while satifying the conditions below.
- * - Pn is in the range of Pn_min and Pn_max
- * - F is in the range of 1 and 255
- * - FxP is within 25% of desired value.
- * Note: 25% is arbitrary value and may need some tweak.
- */
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
- return max_backlight;
- }
- ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
- return max_backlight;
- }
- pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
- pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
-
- /* Ensure frequency is within 25% of desired value */
- fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
- fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
-
- if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
- drm_dbg_kms(&i915->drm,
- "VBT defined backlight frequency out of range\n");
- return max_backlight;
- }
-
- for (pn = pn_max; pn >= pn_min; pn--) {
- f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
- fxp_actual = f << pn;
- if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
- break;
- }
-
- drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
- ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
- if (ret != 1) {
- drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
- return max_backlight;
- }
-
- panel->backlight.edp.vesa.pwmgen_bit_count = pn;
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
- panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
-
- max_backlight = (1 << pn) - 1;
+ struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
- return max_backlight;
+ drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info);
}
-static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
- enum pipe pipe)
+static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe)
{
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct intel_panel *panel = &connector->panel;
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ u16 current_level;
+ u8 current_mode;
+ int ret;
- if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
- panel->backlight.edp.vesa.aux_enable = true;
- if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
- panel->backlight.edp.vesa.lsb_reg_used = true;
-
- panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
- if (!panel->backlight.max)
- return -ENODEV;
+ ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,
+ i915->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
+ ¤t_level, ¤t_mode);
+ if (ret < 0)
+ return ret;
+ panel->backlight.max = panel->backlight.edp.vesa.info.max;
panel->backlight.min = 0;
- panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector, pipe);
- panel->backlight.enabled = intel_dp_aux_vesa_backlight_dpcd_mode(connector) &&
- panel->backlight.level != 0;
+ if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
+ panel->backlight.level = current_level;
+ panel->backlight.enabled = panel->backlight.level != 0;
+ } else {
+ panel->backlight.level = panel->backlight.max;
+ panel->backlight.enabled = false;
+ }
return 0;
}
@@ -559,16 +340,12 @@ intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector)
struct intel_dp *intel_dp = intel_attached_dp(connector);
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- /* Check the eDP Display control capabilities registers to determine if
- * the panel can support backlight control over the aux channel.
- *
- * TODO: We currently only support AUX only backlight configurations, not backlights which
+ /* TODO: We currently only support AUX only backlight configurations, not backlights which
* require a mix of PWM and AUX controls to work. In the mean time, these machines typically
* work just fine using normal PWM controls anyway.
*/
- if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
- (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
- (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
+ if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
+ drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
drm_dbg_kms(&i915->drm, "AUX Backlight Control Supported!\n");
return true;
}
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 06681bf46d81..0bd6396648b4 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1801,6 +1801,24 @@ drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_MSA_TIMING_PAR_IGNORED;
}
+/**
+ * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
+ * @edp_dpcd: The DPCD to check
+ *
+ * Note that currently this function will return %false for panels which support various DPCD
+ * backlight features but which require the brightness be set through PWM, and don't support setting
+ * the brightness level via the DPCD. This is a TODO.
+ *
+ * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
+ * otherwise
+ */
+static inline bool
+drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
+{
+ return (edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
+ (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP);
+}
+
/*
* DisplayPort AUX channel
*/
@@ -2107,6 +2125,36 @@ drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
return desc->quirks & BIT(quirk);
}
+/**
+ * struct drm_edp_backlight_info - Probed eDP backlight info struct
+ * @pwmgen_bit_count: The pwmgen bit count
+ * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
+ * @max: The maximum backlight level that may be set
+ * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
+ * @aux_enable: Does the panel support the AUX enable cap?
+ *
+ * This structure contains various data about an eDP backlight, which can be populated by using
+ * drm_edp_backlight_init().
+ */
+struct drm_edp_backlight_info {
+ u8 pwmgen_bit_count;
+ u8 pwm_freq_pre_divider;
+ u16 max;
+
+ bool lsb_reg_used : 1;
+ bool aux_enable : 1;
+};
+
+int
+drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
+ u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
+ u16 *current_level, u8 *current_mode);
+int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level);
+int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
+ u16 level);
+int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
+
#ifdef CONFIG_DRM_DP_CEC
void drm_dp_cec_irq(struct drm_dp_aux *aux);
void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 9/9] drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
2021-05-14 18:14 ` Lyude Paul
(?)
(?)
@ 2021-05-14 18:15 ` Lyude Paul
-1 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, Jani Nikula, Dave Airlie,
Ben Skeggs, David Airlie, Daniel Vetter, Dave Airlie,
James Jones, open list
This adds support for controlling panel backlights over eDP using VESA's
standard backlight control interface. Luckily, Nvidia was cool enough to
never come up with their own proprietary backlight control interface (at
least, not any that I or the laptop manufacturers I've talked to are aware
of), so this should work for any laptop panels which support the VESA
backlight control interface.
Note that we don't yet provide the panel backlight frequency to the DRM DP
backlight helpers. This should be fine for the time being, since it's not
required to get basic backlight controls working.
For reference: there's some mentions of PWM backlight values in
nouveau_reg.h, but I'm not sure these are the values we would want to use.
If we figure out how to get this information in the future, we'll have the
benefit of more granular backlight control.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 28 ++++
drivers/gpu/drm/nouveau/nouveau_backlight.c | 166 ++++++++++++++++++--
drivers/gpu/drm/nouveau/nouveau_connector.h | 9 +-
drivers/gpu/drm/nouveau/nouveau_encoder.h | 1 +
4 files changed, 186 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index c46d0374b6e6..80ad2d6b7e4b 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -31,6 +31,7 @@
#include <linux/dma-mapping.h>
#include <linux/hdmi.h>
#include <linux/component.h>
+#include <linux/iopoll.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -1648,15 +1649,30 @@ nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
}
+/* TODO: Should we extend this to PWM-only backlights?
+ * As well, should we add a DRM helper for waiting for the backlight to acknowledge
+ * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a
+ * fixed time delay from the vbios…
+ */
static void
nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+ struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder);
+ struct nouveau_backlight *backlight = nv_connector->backlight;
struct drm_dp_aux *aux = &nv_connector->aux;
+ int ret;
u8 pwr;
+ if (backlight && backlight->uses_dpcd) {
+ ret = drm_edp_backlight_disable(aux, &backlight->edp_info);
+ if (ret < 0)
+ NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n",
+ nv_connector->base.base.id, nv_connector->base.name, ret);
+ }
+
if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
@@ -1695,6 +1711,9 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *sta
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_connector *nv_connector;
+#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
+ struct nouveau_backlight *backlight;
+#endif
struct nvbios *bios = &drm->vbios;
bool hda = false;
u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
@@ -1769,6 +1788,14 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *sta
proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
+
+#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
+ backlight = nv_connector->backlight;
+ if (backlight && backlight->uses_dpcd)
+ drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info,
+ (u16)backlight->dev->props.brightness);
+#endif
+
break;
default:
BUG();
@@ -2294,6 +2321,7 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
nv50_crc_atomic_start_reporting(state);
if (!flushed)
nv50_crc_atomic_release_notifier_contexts(state);
+
drm_atomic_helper_commit_hw_done(state);
drm_atomic_helper_cleanup_planes(dev, state);
drm_atomic_helper_commit_cleanup_done(state);
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index 72f35a2babcb..1cbd71abc80a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -42,11 +42,6 @@
static struct ida bl_ida;
#define BL_NAME_SIZE 15 // 12 for name + 2 for digits + 1 for '\0'
-struct nouveau_backlight {
- struct backlight_device *dev;
- int id;
-};
-
static bool
nouveau_get_backlight_name(char backlight_name[BL_NAME_SIZE],
struct nouveau_backlight *bl)
@@ -148,6 +143,98 @@ static const struct backlight_ops nv50_bl_ops = {
.update_status = nv50_set_intensity,
};
+/*
+ * eDP brightness callbacks need to happen under lock, since we need to
+ * enable/disable the backlight ourselves for modesets
+ */
+static int
+nv50_edp_get_brightness(struct backlight_device *bd)
+{
+ struct drm_connector *connector = dev_get_drvdata(bd->dev.parent);
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret = 0;
+
+ drm_modeset_acquire_init(&ctx, 0);
+
+retry:
+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ crtc = connector->state->crtc;
+ if (!crtc)
+ goto out;
+
+ ret = drm_modeset_lock(&crtc->mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ if (!crtc->state->active)
+ goto out;
+
+ ret = bd->props.brightness;
+out:
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+ return ret;
+deadlock:
+ drm_modeset_backoff(&ctx);
+ goto retry;
+}
+
+static int
+nv50_edp_set_brightness(struct backlight_device *bd)
+{
+ struct drm_connector *connector = dev_get_drvdata(bd->dev.parent);
+ struct nouveau_connector *nv_connector = nouveau_connector(connector);
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct drm_dp_aux *aux = &nv_connector->aux;
+ struct nouveau_backlight *nv_bl = nv_connector->backlight;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret = 0;
+
+ drm_modeset_acquire_init(&ctx, 0);
+retry:
+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ crtc = connector->state->crtc;
+ if (!crtc)
+ goto out;
+
+ ret = drm_modeset_lock(&crtc->mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ if (crtc->state->active)
+ ret = drm_edp_backlight_set_level(aux, &nv_bl->edp_info, bd->props.brightness);
+
+out:
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+ return ret;
+deadlock:
+ drm_modeset_backoff(&ctx);
+ goto retry;
+}
+
+static const struct backlight_ops nv50_edp_bl_ops = {
+ .get_brightness = nv50_edp_get_brightness,
+ .update_status = nv50_edp_set_brightness,
+};
+
static int
nva3_get_intensity(struct backlight_device *bd)
{
@@ -194,8 +281,13 @@ static const struct backlight_ops nva3_bl_ops = {
.update_status = nva3_set_intensity,
};
+/* FIXME: perform backlight probing for eDP _before_ this, this only gets called after connector
+ * registration which happens after the initial modeset
+ */
static int
-nv50_backlight_init(struct nouveau_encoder *nv_encoder,
+nv50_backlight_init(struct nouveau_backlight *bl,
+ struct nouveau_connector *nv_conn,
+ struct nouveau_encoder *nv_encoder,
struct backlight_properties *props,
const struct backlight_ops **ops)
{
@@ -205,6 +297,41 @@ nv50_backlight_init(struct nouveau_encoder *nv_encoder,
if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(ffs(nv_encoder->dcb->or) - 1)))
return -ENODEV;
+ if (nv_conn->type == DCB_CONNECTOR_eDP) {
+ int ret;
+ u16 current_level;
+ u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+ u8 current_mode;
+
+ ret = drm_dp_dpcd_read(&nv_conn->aux, DP_EDP_DPCD_REV, edp_dpcd,
+ EDP_DISPLAY_CTL_CAP_SIZE);
+ if (ret < 0)
+ return ret;
+
+ if (drm_edp_backlight_supported(edp_dpcd)) {
+ NV_DEBUG(drm, "DPCD backlight controls supported on %s\n",
+ nv_conn->base.name);
+
+ ret = drm_edp_backlight_init(&nv_conn->aux, &bl->edp_info, 0, edp_dpcd,
+ ¤t_level, ¤t_mode);
+ if (ret < 0)
+ return ret;
+
+ ret = drm_edp_backlight_enable(&nv_conn->aux, &bl->edp_info, current_level);
+ if (ret < 0) {
+ NV_ERROR(drm, "Failed to enable backlight on %s: %d\n",
+ nv_conn->base.name, ret);
+ return ret;
+ }
+
+ *ops = &nv50_edp_bl_ops;
+ props->brightness = current_level;
+ props->max_brightness = bl->edp_info.max;
+ bl->uses_dpcd = true;
+ return 0;
+ }
+ }
+
if (drm->client.device.info.chipset <= 0xa0 ||
drm->client.device.info.chipset == 0xaa ||
drm->client.device.info.chipset == 0xac)
@@ -245,6 +372,10 @@ nouveau_backlight_init(struct drm_connector *connector)
if (!nv_encoder)
return 0;
+ bl = kzalloc(sizeof(*bl), GFP_KERNEL);
+ if (!bl)
+ return -ENOMEM;
+
switch (device->info.family) {
case NV_DEVICE_INFO_V0_CURIE:
ret = nv40_backlight_init(nv_encoder, &props, &ops);
@@ -257,20 +388,19 @@ nouveau_backlight_init(struct drm_connector *connector)
case NV_DEVICE_INFO_V0_VOLTA:
case NV_DEVICE_INFO_V0_TURING:
case NV_DEVICE_INFO_V0_AMPERE: //XXX: not confirmed
- ret = nv50_backlight_init(nv_encoder, &props, &ops);
+ ret = nv50_backlight_init(bl, nouveau_connector(connector),
+ nv_encoder, &props, &ops);
break;
default:
- return 0;
+ ret = 0;
+ goto fail_alloc;
}
- if (ret == -ENODEV)
- return 0;
- else if (ret)
- return ret;
-
- bl = kzalloc(sizeof(*bl), GFP_KERNEL);
- if (!bl)
- return -ENOMEM;
+ if (ret) {
+ if (ret == -ENODEV)
+ ret = 0;
+ goto fail_alloc;
+ }
if (!nouveau_get_backlight_name(backlight_name, bl)) {
NV_ERROR(drm, "Failed to retrieve a unique name for the backlight interface\n");
@@ -287,7 +417,9 @@ nouveau_backlight_init(struct drm_connector *connector)
}
nouveau_connector(connector)->backlight = bl;
- bl->dev->props.brightness = bl->dev->ops->get_brightness(bl->dev);
+ if (!bl->dev->props.brightness)
+ bl->dev->props.brightness =
+ bl->dev->ops->get_brightness(bl->dev);
backlight_update_status(bl->dev);
return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h
index d0b859c4a80e..40f90e353540 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
@@ -46,7 +46,14 @@ struct nvkm_i2c_port;
struct dcb_output;
#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
-struct nouveau_backlight;
+struct nouveau_backlight {
+ struct backlight_device *dev;
+
+ struct drm_edp_backlight_info edp_info;
+ bool uses_dpcd : 1;
+
+ int id;
+};
#endif
#define nouveau_conn_atom(p) \
diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index 1ffcc0a491fd..77c2fed76e8b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -30,6 +30,7 @@
#include <subdev/bios/dcb.h>
#include <drm/drm_encoder_slave.h>
+#include <drm/drm_dp_helper.h>
#include <drm/drm_dp_mst_helper.h>
#include "dispnv04/disp.h"
struct nv50_head_atom;
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Nouveau] [PATCH v6 9/9] drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, David Airlie, open list,
Jani Nikula, Ben Skeggs, Daniel Vetter, Dave Airlie
This adds support for controlling panel backlights over eDP using VESA's
standard backlight control interface. Luckily, Nvidia was cool enough to
never come up with their own proprietary backlight control interface (at
least, not any that I or the laptop manufacturers I've talked to are aware
of), so this should work for any laptop panels which support the VESA
backlight control interface.
Note that we don't yet provide the panel backlight frequency to the DRM DP
backlight helpers. This should be fine for the time being, since it's not
required to get basic backlight controls working.
For reference: there's some mentions of PWM backlight values in
nouveau_reg.h, but I'm not sure these are the values we would want to use.
If we figure out how to get this information in the future, we'll have the
benefit of more granular backlight control.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 28 ++++
drivers/gpu/drm/nouveau/nouveau_backlight.c | 166 ++++++++++++++++++--
drivers/gpu/drm/nouveau/nouveau_connector.h | 9 +-
drivers/gpu/drm/nouveau/nouveau_encoder.h | 1 +
4 files changed, 186 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index c46d0374b6e6..80ad2d6b7e4b 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -31,6 +31,7 @@
#include <linux/dma-mapping.h>
#include <linux/hdmi.h>
#include <linux/component.h>
+#include <linux/iopoll.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -1648,15 +1649,30 @@ nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
}
+/* TODO: Should we extend this to PWM-only backlights?
+ * As well, should we add a DRM helper for waiting for the backlight to acknowledge
+ * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a
+ * fixed time delay from the vbios…
+ */
static void
nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+ struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder);
+ struct nouveau_backlight *backlight = nv_connector->backlight;
struct drm_dp_aux *aux = &nv_connector->aux;
+ int ret;
u8 pwr;
+ if (backlight && backlight->uses_dpcd) {
+ ret = drm_edp_backlight_disable(aux, &backlight->edp_info);
+ if (ret < 0)
+ NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n",
+ nv_connector->base.base.id, nv_connector->base.name, ret);
+ }
+
if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
@@ -1695,6 +1711,9 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *sta
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_connector *nv_connector;
+#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
+ struct nouveau_backlight *backlight;
+#endif
struct nvbios *bios = &drm->vbios;
bool hda = false;
u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
@@ -1769,6 +1788,14 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *sta
proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
+
+#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
+ backlight = nv_connector->backlight;
+ if (backlight && backlight->uses_dpcd)
+ drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info,
+ (u16)backlight->dev->props.brightness);
+#endif
+
break;
default:
BUG();
@@ -2294,6 +2321,7 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
nv50_crc_atomic_start_reporting(state);
if (!flushed)
nv50_crc_atomic_release_notifier_contexts(state);
+
drm_atomic_helper_commit_hw_done(state);
drm_atomic_helper_cleanup_planes(dev, state);
drm_atomic_helper_commit_cleanup_done(state);
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index 72f35a2babcb..1cbd71abc80a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -42,11 +42,6 @@
static struct ida bl_ida;
#define BL_NAME_SIZE 15 // 12 for name + 2 for digits + 1 for '\0'
-struct nouveau_backlight {
- struct backlight_device *dev;
- int id;
-};
-
static bool
nouveau_get_backlight_name(char backlight_name[BL_NAME_SIZE],
struct nouveau_backlight *bl)
@@ -148,6 +143,98 @@ static const struct backlight_ops nv50_bl_ops = {
.update_status = nv50_set_intensity,
};
+/*
+ * eDP brightness callbacks need to happen under lock, since we need to
+ * enable/disable the backlight ourselves for modesets
+ */
+static int
+nv50_edp_get_brightness(struct backlight_device *bd)
+{
+ struct drm_connector *connector = dev_get_drvdata(bd->dev.parent);
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret = 0;
+
+ drm_modeset_acquire_init(&ctx, 0);
+
+retry:
+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ crtc = connector->state->crtc;
+ if (!crtc)
+ goto out;
+
+ ret = drm_modeset_lock(&crtc->mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ if (!crtc->state->active)
+ goto out;
+
+ ret = bd->props.brightness;
+out:
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+ return ret;
+deadlock:
+ drm_modeset_backoff(&ctx);
+ goto retry;
+}
+
+static int
+nv50_edp_set_brightness(struct backlight_device *bd)
+{
+ struct drm_connector *connector = dev_get_drvdata(bd->dev.parent);
+ struct nouveau_connector *nv_connector = nouveau_connector(connector);
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct drm_dp_aux *aux = &nv_connector->aux;
+ struct nouveau_backlight *nv_bl = nv_connector->backlight;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret = 0;
+
+ drm_modeset_acquire_init(&ctx, 0);
+retry:
+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ crtc = connector->state->crtc;
+ if (!crtc)
+ goto out;
+
+ ret = drm_modeset_lock(&crtc->mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ if (crtc->state->active)
+ ret = drm_edp_backlight_set_level(aux, &nv_bl->edp_info, bd->props.brightness);
+
+out:
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+ return ret;
+deadlock:
+ drm_modeset_backoff(&ctx);
+ goto retry;
+}
+
+static const struct backlight_ops nv50_edp_bl_ops = {
+ .get_brightness = nv50_edp_get_brightness,
+ .update_status = nv50_edp_set_brightness,
+};
+
static int
nva3_get_intensity(struct backlight_device *bd)
{
@@ -194,8 +281,13 @@ static const struct backlight_ops nva3_bl_ops = {
.update_status = nva3_set_intensity,
};
+/* FIXME: perform backlight probing for eDP _before_ this, this only gets called after connector
+ * registration which happens after the initial modeset
+ */
static int
-nv50_backlight_init(struct nouveau_encoder *nv_encoder,
+nv50_backlight_init(struct nouveau_backlight *bl,
+ struct nouveau_connector *nv_conn,
+ struct nouveau_encoder *nv_encoder,
struct backlight_properties *props,
const struct backlight_ops **ops)
{
@@ -205,6 +297,41 @@ nv50_backlight_init(struct nouveau_encoder *nv_encoder,
if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(ffs(nv_encoder->dcb->or) - 1)))
return -ENODEV;
+ if (nv_conn->type == DCB_CONNECTOR_eDP) {
+ int ret;
+ u16 current_level;
+ u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+ u8 current_mode;
+
+ ret = drm_dp_dpcd_read(&nv_conn->aux, DP_EDP_DPCD_REV, edp_dpcd,
+ EDP_DISPLAY_CTL_CAP_SIZE);
+ if (ret < 0)
+ return ret;
+
+ if (drm_edp_backlight_supported(edp_dpcd)) {
+ NV_DEBUG(drm, "DPCD backlight controls supported on %s\n",
+ nv_conn->base.name);
+
+ ret = drm_edp_backlight_init(&nv_conn->aux, &bl->edp_info, 0, edp_dpcd,
+ ¤t_level, ¤t_mode);
+ if (ret < 0)
+ return ret;
+
+ ret = drm_edp_backlight_enable(&nv_conn->aux, &bl->edp_info, current_level);
+ if (ret < 0) {
+ NV_ERROR(drm, "Failed to enable backlight on %s: %d\n",
+ nv_conn->base.name, ret);
+ return ret;
+ }
+
+ *ops = &nv50_edp_bl_ops;
+ props->brightness = current_level;
+ props->max_brightness = bl->edp_info.max;
+ bl->uses_dpcd = true;
+ return 0;
+ }
+ }
+
if (drm->client.device.info.chipset <= 0xa0 ||
drm->client.device.info.chipset == 0xaa ||
drm->client.device.info.chipset == 0xac)
@@ -245,6 +372,10 @@ nouveau_backlight_init(struct drm_connector *connector)
if (!nv_encoder)
return 0;
+ bl = kzalloc(sizeof(*bl), GFP_KERNEL);
+ if (!bl)
+ return -ENOMEM;
+
switch (device->info.family) {
case NV_DEVICE_INFO_V0_CURIE:
ret = nv40_backlight_init(nv_encoder, &props, &ops);
@@ -257,20 +388,19 @@ nouveau_backlight_init(struct drm_connector *connector)
case NV_DEVICE_INFO_V0_VOLTA:
case NV_DEVICE_INFO_V0_TURING:
case NV_DEVICE_INFO_V0_AMPERE: //XXX: not confirmed
- ret = nv50_backlight_init(nv_encoder, &props, &ops);
+ ret = nv50_backlight_init(bl, nouveau_connector(connector),
+ nv_encoder, &props, &ops);
break;
default:
- return 0;
+ ret = 0;
+ goto fail_alloc;
}
- if (ret == -ENODEV)
- return 0;
- else if (ret)
- return ret;
-
- bl = kzalloc(sizeof(*bl), GFP_KERNEL);
- if (!bl)
- return -ENOMEM;
+ if (ret) {
+ if (ret == -ENODEV)
+ ret = 0;
+ goto fail_alloc;
+ }
if (!nouveau_get_backlight_name(backlight_name, bl)) {
NV_ERROR(drm, "Failed to retrieve a unique name for the backlight interface\n");
@@ -287,7 +417,9 @@ nouveau_backlight_init(struct drm_connector *connector)
}
nouveau_connector(connector)->backlight = bl;
- bl->dev->props.brightness = bl->dev->ops->get_brightness(bl->dev);
+ if (!bl->dev->props.brightness)
+ bl->dev->props.brightness =
+ bl->dev->ops->get_brightness(bl->dev);
backlight_update_status(bl->dev);
return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h
index d0b859c4a80e..40f90e353540 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
@@ -46,7 +46,14 @@ struct nvkm_i2c_port;
struct dcb_output;
#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
-struct nouveau_backlight;
+struct nouveau_backlight {
+ struct backlight_device *dev;
+
+ struct drm_edp_backlight_info edp_info;
+ bool uses_dpcd : 1;
+
+ int id;
+};
#endif
#define nouveau_conn_atom(p) \
diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index 1ffcc0a491fd..77c2fed76e8b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -30,6 +30,7 @@
#include <subdev/bios/dcb.h>
#include <drm/drm_encoder_slave.h>
+#include <drm/drm_dp_helper.h>
#include <drm/drm_dp_mst_helper.h>
#include "dispnv04/disp.h"
struct nv50_head_atom;
--
2.31.1
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v6 9/9] drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, David Airlie, open list,
Jani Nikula, Ben Skeggs, Dave Airlie, James Jones
This adds support for controlling panel backlights over eDP using VESA's
standard backlight control interface. Luckily, Nvidia was cool enough to
never come up with their own proprietary backlight control interface (at
least, not any that I or the laptop manufacturers I've talked to are aware
of), so this should work for any laptop panels which support the VESA
backlight control interface.
Note that we don't yet provide the panel backlight frequency to the DRM DP
backlight helpers. This should be fine for the time being, since it's not
required to get basic backlight controls working.
For reference: there's some mentions of PWM backlight values in
nouveau_reg.h, but I'm not sure these are the values we would want to use.
If we figure out how to get this information in the future, we'll have the
benefit of more granular backlight control.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 28 ++++
drivers/gpu/drm/nouveau/nouveau_backlight.c | 166 ++++++++++++++++++--
drivers/gpu/drm/nouveau/nouveau_connector.h | 9 +-
drivers/gpu/drm/nouveau/nouveau_encoder.h | 1 +
4 files changed, 186 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index c46d0374b6e6..80ad2d6b7e4b 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -31,6 +31,7 @@
#include <linux/dma-mapping.h>
#include <linux/hdmi.h>
#include <linux/component.h>
+#include <linux/iopoll.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -1648,15 +1649,30 @@ nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
}
+/* TODO: Should we extend this to PWM-only backlights?
+ * As well, should we add a DRM helper for waiting for the backlight to acknowledge
+ * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a
+ * fixed time delay from the vbios…
+ */
static void
nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+ struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder);
+ struct nouveau_backlight *backlight = nv_connector->backlight;
struct drm_dp_aux *aux = &nv_connector->aux;
+ int ret;
u8 pwr;
+ if (backlight && backlight->uses_dpcd) {
+ ret = drm_edp_backlight_disable(aux, &backlight->edp_info);
+ if (ret < 0)
+ NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n",
+ nv_connector->base.base.id, nv_connector->base.name, ret);
+ }
+
if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
@@ -1695,6 +1711,9 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *sta
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_connector *nv_connector;
+#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
+ struct nouveau_backlight *backlight;
+#endif
struct nvbios *bios = &drm->vbios;
bool hda = false;
u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
@@ -1769,6 +1788,14 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *sta
proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
+
+#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
+ backlight = nv_connector->backlight;
+ if (backlight && backlight->uses_dpcd)
+ drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info,
+ (u16)backlight->dev->props.brightness);
+#endif
+
break;
default:
BUG();
@@ -2294,6 +2321,7 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
nv50_crc_atomic_start_reporting(state);
if (!flushed)
nv50_crc_atomic_release_notifier_contexts(state);
+
drm_atomic_helper_commit_hw_done(state);
drm_atomic_helper_cleanup_planes(dev, state);
drm_atomic_helper_commit_cleanup_done(state);
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index 72f35a2babcb..1cbd71abc80a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -42,11 +42,6 @@
static struct ida bl_ida;
#define BL_NAME_SIZE 15 // 12 for name + 2 for digits + 1 for '\0'
-struct nouveau_backlight {
- struct backlight_device *dev;
- int id;
-};
-
static bool
nouveau_get_backlight_name(char backlight_name[BL_NAME_SIZE],
struct nouveau_backlight *bl)
@@ -148,6 +143,98 @@ static const struct backlight_ops nv50_bl_ops = {
.update_status = nv50_set_intensity,
};
+/*
+ * eDP brightness callbacks need to happen under lock, since we need to
+ * enable/disable the backlight ourselves for modesets
+ */
+static int
+nv50_edp_get_brightness(struct backlight_device *bd)
+{
+ struct drm_connector *connector = dev_get_drvdata(bd->dev.parent);
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret = 0;
+
+ drm_modeset_acquire_init(&ctx, 0);
+
+retry:
+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ crtc = connector->state->crtc;
+ if (!crtc)
+ goto out;
+
+ ret = drm_modeset_lock(&crtc->mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ if (!crtc->state->active)
+ goto out;
+
+ ret = bd->props.brightness;
+out:
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+ return ret;
+deadlock:
+ drm_modeset_backoff(&ctx);
+ goto retry;
+}
+
+static int
+nv50_edp_set_brightness(struct backlight_device *bd)
+{
+ struct drm_connector *connector = dev_get_drvdata(bd->dev.parent);
+ struct nouveau_connector *nv_connector = nouveau_connector(connector);
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct drm_dp_aux *aux = &nv_connector->aux;
+ struct nouveau_backlight *nv_bl = nv_connector->backlight;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret = 0;
+
+ drm_modeset_acquire_init(&ctx, 0);
+retry:
+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ crtc = connector->state->crtc;
+ if (!crtc)
+ goto out;
+
+ ret = drm_modeset_lock(&crtc->mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ if (crtc->state->active)
+ ret = drm_edp_backlight_set_level(aux, &nv_bl->edp_info, bd->props.brightness);
+
+out:
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+ return ret;
+deadlock:
+ drm_modeset_backoff(&ctx);
+ goto retry;
+}
+
+static const struct backlight_ops nv50_edp_bl_ops = {
+ .get_brightness = nv50_edp_get_brightness,
+ .update_status = nv50_edp_set_brightness,
+};
+
static int
nva3_get_intensity(struct backlight_device *bd)
{
@@ -194,8 +281,13 @@ static const struct backlight_ops nva3_bl_ops = {
.update_status = nva3_set_intensity,
};
+/* FIXME: perform backlight probing for eDP _before_ this, this only gets called after connector
+ * registration which happens after the initial modeset
+ */
static int
-nv50_backlight_init(struct nouveau_encoder *nv_encoder,
+nv50_backlight_init(struct nouveau_backlight *bl,
+ struct nouveau_connector *nv_conn,
+ struct nouveau_encoder *nv_encoder,
struct backlight_properties *props,
const struct backlight_ops **ops)
{
@@ -205,6 +297,41 @@ nv50_backlight_init(struct nouveau_encoder *nv_encoder,
if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(ffs(nv_encoder->dcb->or) - 1)))
return -ENODEV;
+ if (nv_conn->type == DCB_CONNECTOR_eDP) {
+ int ret;
+ u16 current_level;
+ u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+ u8 current_mode;
+
+ ret = drm_dp_dpcd_read(&nv_conn->aux, DP_EDP_DPCD_REV, edp_dpcd,
+ EDP_DISPLAY_CTL_CAP_SIZE);
+ if (ret < 0)
+ return ret;
+
+ if (drm_edp_backlight_supported(edp_dpcd)) {
+ NV_DEBUG(drm, "DPCD backlight controls supported on %s\n",
+ nv_conn->base.name);
+
+ ret = drm_edp_backlight_init(&nv_conn->aux, &bl->edp_info, 0, edp_dpcd,
+ ¤t_level, ¤t_mode);
+ if (ret < 0)
+ return ret;
+
+ ret = drm_edp_backlight_enable(&nv_conn->aux, &bl->edp_info, current_level);
+ if (ret < 0) {
+ NV_ERROR(drm, "Failed to enable backlight on %s: %d\n",
+ nv_conn->base.name, ret);
+ return ret;
+ }
+
+ *ops = &nv50_edp_bl_ops;
+ props->brightness = current_level;
+ props->max_brightness = bl->edp_info.max;
+ bl->uses_dpcd = true;
+ return 0;
+ }
+ }
+
if (drm->client.device.info.chipset <= 0xa0 ||
drm->client.device.info.chipset == 0xaa ||
drm->client.device.info.chipset == 0xac)
@@ -245,6 +372,10 @@ nouveau_backlight_init(struct drm_connector *connector)
if (!nv_encoder)
return 0;
+ bl = kzalloc(sizeof(*bl), GFP_KERNEL);
+ if (!bl)
+ return -ENOMEM;
+
switch (device->info.family) {
case NV_DEVICE_INFO_V0_CURIE:
ret = nv40_backlight_init(nv_encoder, &props, &ops);
@@ -257,20 +388,19 @@ nouveau_backlight_init(struct drm_connector *connector)
case NV_DEVICE_INFO_V0_VOLTA:
case NV_DEVICE_INFO_V0_TURING:
case NV_DEVICE_INFO_V0_AMPERE: //XXX: not confirmed
- ret = nv50_backlight_init(nv_encoder, &props, &ops);
+ ret = nv50_backlight_init(bl, nouveau_connector(connector),
+ nv_encoder, &props, &ops);
break;
default:
- return 0;
+ ret = 0;
+ goto fail_alloc;
}
- if (ret == -ENODEV)
- return 0;
- else if (ret)
- return ret;
-
- bl = kzalloc(sizeof(*bl), GFP_KERNEL);
- if (!bl)
- return -ENOMEM;
+ if (ret) {
+ if (ret == -ENODEV)
+ ret = 0;
+ goto fail_alloc;
+ }
if (!nouveau_get_backlight_name(backlight_name, bl)) {
NV_ERROR(drm, "Failed to retrieve a unique name for the backlight interface\n");
@@ -287,7 +417,9 @@ nouveau_backlight_init(struct drm_connector *connector)
}
nouveau_connector(connector)->backlight = bl;
- bl->dev->props.brightness = bl->dev->ops->get_brightness(bl->dev);
+ if (!bl->dev->props.brightness)
+ bl->dev->props.brightness =
+ bl->dev->ops->get_brightness(bl->dev);
backlight_update_status(bl->dev);
return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h
index d0b859c4a80e..40f90e353540 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
@@ -46,7 +46,14 @@ struct nvkm_i2c_port;
struct dcb_output;
#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
-struct nouveau_backlight;
+struct nouveau_backlight {
+ struct backlight_device *dev;
+
+ struct drm_edp_backlight_info edp_info;
+ bool uses_dpcd : 1;
+
+ int id;
+};
#endif
#define nouveau_conn_atom(p) \
diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index 1ffcc0a491fd..77c2fed76e8b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -30,6 +30,7 @@
#include <subdev/bios/dcb.h>
#include <drm/drm_encoder_slave.h>
+#include <drm/drm_dp_helper.h>
#include <drm/drm_dp_mst_helper.h>
#include "dispnv04/disp.h"
struct nv50_head_atom;
--
2.31.1
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Intel-gfx] [PATCH v6 9/9] drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
@ 2021-05-14 18:15 ` Lyude Paul
0 siblings, 0 replies; 62+ messages in thread
From: Lyude Paul @ 2021-05-14 18:15 UTC (permalink / raw)
To: intel-gfx, dri-devel, nouveau
Cc: Rajeev Nandan, greg.depoire, David Airlie, open list,
Jani Nikula, Ben Skeggs, Dave Airlie, James Jones
This adds support for controlling panel backlights over eDP using VESA's
standard backlight control interface. Luckily, Nvidia was cool enough to
never come up with their own proprietary backlight control interface (at
least, not any that I or the laptop manufacturers I've talked to are aware
of), so this should work for any laptop panels which support the VESA
backlight control interface.
Note that we don't yet provide the panel backlight frequency to the DRM DP
backlight helpers. This should be fine for the time being, since it's not
required to get basic backlight controls working.
For reference: there's some mentions of PWM backlight values in
nouveau_reg.h, but I'm not sure these are the values we would want to use.
If we figure out how to get this information in the future, we'll have the
benefit of more granular backlight control.
Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Dave Airlie <airlied@gmail.com>
Cc: greg.depoire@gmail.com
---
drivers/gpu/drm/nouveau/dispnv50/disp.c | 28 ++++
drivers/gpu/drm/nouveau/nouveau_backlight.c | 166 ++++++++++++++++++--
drivers/gpu/drm/nouveau/nouveau_connector.h | 9 +-
drivers/gpu/drm/nouveau/nouveau_encoder.h | 1 +
4 files changed, 186 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index c46d0374b6e6..80ad2d6b7e4b 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -31,6 +31,7 @@
#include <linux/dma-mapping.h>
#include <linux/hdmi.h>
#include <linux/component.h>
+#include <linux/iopoll.h>
#include <drm/drm_atomic.h>
#include <drm/drm_atomic_helper.h>
@@ -1648,15 +1649,30 @@ nv50_sor_update(struct nouveau_encoder *nv_encoder, u8 head,
core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);
}
+/* TODO: Should we extend this to PWM-only backlights?
+ * As well, should we add a DRM helper for waiting for the backlight to acknowledge
+ * the panel backlight has been shut off? Intel doesn't seem to do this, and uses a
+ * fixed time delay from the vbios…
+ */
static void
nv50_sor_atomic_disable(struct drm_encoder *encoder, struct drm_atomic_state *state)
{
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
+ struct nouveau_drm *drm = nouveau_drm(nv_encoder->base.base.dev);
struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
struct nouveau_connector *nv_connector = nv50_outp_get_old_connector(state, nv_encoder);
+ struct nouveau_backlight *backlight = nv_connector->backlight;
struct drm_dp_aux *aux = &nv_connector->aux;
+ int ret;
u8 pwr;
+ if (backlight && backlight->uses_dpcd) {
+ ret = drm_edp_backlight_disable(aux, &backlight->edp_info);
+ if (ret < 0)
+ NV_ERROR(drm, "Failed to disable backlight on [CONNECTOR:%d:%s]: %d\n",
+ nv_connector->base.base.id, nv_connector->base.name, ret);
+ }
+
if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
int ret = drm_dp_dpcd_readb(aux, DP_SET_POWER, &pwr);
@@ -1695,6 +1711,9 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *sta
struct drm_device *dev = encoder->dev;
struct nouveau_drm *drm = nouveau_drm(dev);
struct nouveau_connector *nv_connector;
+#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
+ struct nouveau_backlight *backlight;
+#endif
struct nvbios *bios = &drm->vbios;
bool hda = false;
u8 proto = NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM;
@@ -1769,6 +1788,14 @@ nv50_sor_atomic_enable(struct drm_encoder *encoder, struct drm_atomic_state *sta
proto = NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B;
nv50_audio_enable(encoder, nv_crtc, nv_connector, state, mode);
+
+#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
+ backlight = nv_connector->backlight;
+ if (backlight && backlight->uses_dpcd)
+ drm_edp_backlight_enable(&nv_connector->aux, &backlight->edp_info,
+ (u16)backlight->dev->props.brightness);
+#endif
+
break;
default:
BUG();
@@ -2294,6 +2321,7 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state)
nv50_crc_atomic_start_reporting(state);
if (!flushed)
nv50_crc_atomic_release_notifier_contexts(state);
+
drm_atomic_helper_commit_hw_done(state);
drm_atomic_helper_cleanup_planes(dev, state);
drm_atomic_helper_commit_cleanup_done(state);
diff --git a/drivers/gpu/drm/nouveau/nouveau_backlight.c b/drivers/gpu/drm/nouveau/nouveau_backlight.c
index 72f35a2babcb..1cbd71abc80a 100644
--- a/drivers/gpu/drm/nouveau/nouveau_backlight.c
+++ b/drivers/gpu/drm/nouveau/nouveau_backlight.c
@@ -42,11 +42,6 @@
static struct ida bl_ida;
#define BL_NAME_SIZE 15 // 12 for name + 2 for digits + 1 for '\0'
-struct nouveau_backlight {
- struct backlight_device *dev;
- int id;
-};
-
static bool
nouveau_get_backlight_name(char backlight_name[BL_NAME_SIZE],
struct nouveau_backlight *bl)
@@ -148,6 +143,98 @@ static const struct backlight_ops nv50_bl_ops = {
.update_status = nv50_set_intensity,
};
+/*
+ * eDP brightness callbacks need to happen under lock, since we need to
+ * enable/disable the backlight ourselves for modesets
+ */
+static int
+nv50_edp_get_brightness(struct backlight_device *bd)
+{
+ struct drm_connector *connector = dev_get_drvdata(bd->dev.parent);
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret = 0;
+
+ drm_modeset_acquire_init(&ctx, 0);
+
+retry:
+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ crtc = connector->state->crtc;
+ if (!crtc)
+ goto out;
+
+ ret = drm_modeset_lock(&crtc->mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ if (!crtc->state->active)
+ goto out;
+
+ ret = bd->props.brightness;
+out:
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+ return ret;
+deadlock:
+ drm_modeset_backoff(&ctx);
+ goto retry;
+}
+
+static int
+nv50_edp_set_brightness(struct backlight_device *bd)
+{
+ struct drm_connector *connector = dev_get_drvdata(bd->dev.parent);
+ struct nouveau_connector *nv_connector = nouveau_connector(connector);
+ struct drm_device *dev = connector->dev;
+ struct drm_crtc *crtc;
+ struct drm_dp_aux *aux = &nv_connector->aux;
+ struct nouveau_backlight *nv_bl = nv_connector->backlight;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret = 0;
+
+ drm_modeset_acquire_init(&ctx, 0);
+retry:
+ ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ crtc = connector->state->crtc;
+ if (!crtc)
+ goto out;
+
+ ret = drm_modeset_lock(&crtc->mutex, &ctx);
+ if (ret == -EDEADLK)
+ goto deadlock;
+ else if (ret < 0)
+ goto out;
+
+ if (crtc->state->active)
+ ret = drm_edp_backlight_set_level(aux, &nv_bl->edp_info, bd->props.brightness);
+
+out:
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+ return ret;
+deadlock:
+ drm_modeset_backoff(&ctx);
+ goto retry;
+}
+
+static const struct backlight_ops nv50_edp_bl_ops = {
+ .get_brightness = nv50_edp_get_brightness,
+ .update_status = nv50_edp_set_brightness,
+};
+
static int
nva3_get_intensity(struct backlight_device *bd)
{
@@ -194,8 +281,13 @@ static const struct backlight_ops nva3_bl_ops = {
.update_status = nva3_set_intensity,
};
+/* FIXME: perform backlight probing for eDP _before_ this, this only gets called after connector
+ * registration which happens after the initial modeset
+ */
static int
-nv50_backlight_init(struct nouveau_encoder *nv_encoder,
+nv50_backlight_init(struct nouveau_backlight *bl,
+ struct nouveau_connector *nv_conn,
+ struct nouveau_encoder *nv_encoder,
struct backlight_properties *props,
const struct backlight_ops **ops)
{
@@ -205,6 +297,41 @@ nv50_backlight_init(struct nouveau_encoder *nv_encoder,
if (!nvif_rd32(device, NV50_PDISP_SOR_PWM_CTL(ffs(nv_encoder->dcb->or) - 1)))
return -ENODEV;
+ if (nv_conn->type == DCB_CONNECTOR_eDP) {
+ int ret;
+ u16 current_level;
+ u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
+ u8 current_mode;
+
+ ret = drm_dp_dpcd_read(&nv_conn->aux, DP_EDP_DPCD_REV, edp_dpcd,
+ EDP_DISPLAY_CTL_CAP_SIZE);
+ if (ret < 0)
+ return ret;
+
+ if (drm_edp_backlight_supported(edp_dpcd)) {
+ NV_DEBUG(drm, "DPCD backlight controls supported on %s\n",
+ nv_conn->base.name);
+
+ ret = drm_edp_backlight_init(&nv_conn->aux, &bl->edp_info, 0, edp_dpcd,
+ ¤t_level, ¤t_mode);
+ if (ret < 0)
+ return ret;
+
+ ret = drm_edp_backlight_enable(&nv_conn->aux, &bl->edp_info, current_level);
+ if (ret < 0) {
+ NV_ERROR(drm, "Failed to enable backlight on %s: %d\n",
+ nv_conn->base.name, ret);
+ return ret;
+ }
+
+ *ops = &nv50_edp_bl_ops;
+ props->brightness = current_level;
+ props->max_brightness = bl->edp_info.max;
+ bl->uses_dpcd = true;
+ return 0;
+ }
+ }
+
if (drm->client.device.info.chipset <= 0xa0 ||
drm->client.device.info.chipset == 0xaa ||
drm->client.device.info.chipset == 0xac)
@@ -245,6 +372,10 @@ nouveau_backlight_init(struct drm_connector *connector)
if (!nv_encoder)
return 0;
+ bl = kzalloc(sizeof(*bl), GFP_KERNEL);
+ if (!bl)
+ return -ENOMEM;
+
switch (device->info.family) {
case NV_DEVICE_INFO_V0_CURIE:
ret = nv40_backlight_init(nv_encoder, &props, &ops);
@@ -257,20 +388,19 @@ nouveau_backlight_init(struct drm_connector *connector)
case NV_DEVICE_INFO_V0_VOLTA:
case NV_DEVICE_INFO_V0_TURING:
case NV_DEVICE_INFO_V0_AMPERE: //XXX: not confirmed
- ret = nv50_backlight_init(nv_encoder, &props, &ops);
+ ret = nv50_backlight_init(bl, nouveau_connector(connector),
+ nv_encoder, &props, &ops);
break;
default:
- return 0;
+ ret = 0;
+ goto fail_alloc;
}
- if (ret == -ENODEV)
- return 0;
- else if (ret)
- return ret;
-
- bl = kzalloc(sizeof(*bl), GFP_KERNEL);
- if (!bl)
- return -ENOMEM;
+ if (ret) {
+ if (ret == -ENODEV)
+ ret = 0;
+ goto fail_alloc;
+ }
if (!nouveau_get_backlight_name(backlight_name, bl)) {
NV_ERROR(drm, "Failed to retrieve a unique name for the backlight interface\n");
@@ -287,7 +417,9 @@ nouveau_backlight_init(struct drm_connector *connector)
}
nouveau_connector(connector)->backlight = bl;
- bl->dev->props.brightness = bl->dev->ops->get_brightness(bl->dev);
+ if (!bl->dev->props.brightness)
+ bl->dev->props.brightness =
+ bl->dev->ops->get_brightness(bl->dev);
backlight_update_status(bl->dev);
return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h
index d0b859c4a80e..40f90e353540 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.h
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.h
@@ -46,7 +46,14 @@ struct nvkm_i2c_port;
struct dcb_output;
#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
-struct nouveau_backlight;
+struct nouveau_backlight {
+ struct backlight_device *dev;
+
+ struct drm_edp_backlight_info edp_info;
+ bool uses_dpcd : 1;
+
+ int id;
+};
#endif
#define nouveau_conn_atom(p) \
diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h
index 1ffcc0a491fd..77c2fed76e8b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_encoder.h
+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h
@@ -30,6 +30,7 @@
#include <subdev/bios/dcb.h>
#include <drm/drm_encoder_slave.h>
+#include <drm/drm_dp_helper.h>
#include <drm/drm_dp_mst_helper.h>
#include "dispnv04/disp.h"
struct nv50_head_atom;
--
2.31.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)
2021-05-14 18:14 ` Lyude Paul
` (10 preceding siblings ...)
(?)
@ 2021-05-14 18:32 ` Patchwork
-1 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-05-14 18:32 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)
URL : https://patchwork.freedesktop.org/series/84754/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
268e6a95dfed drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
e1cad9d60eec drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
9ce26ee2ba51 drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
beb0b699bc45 drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight
eeb1fae7ed93 drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
2dcb4ec0f19c drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT
342cf2c01c5b drm/i915/dpcd_bl: Print return codes for VESA backlight failures
d57f9740534c drm/dp: Extract i915's eDP backlight code into DRM helpers
44243fa04304 drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
-:238: CHECK:CAMELCASE: Avoid CamelCase: <DCB_CONNECTOR_eDP>
#238: FILE: drivers/gpu/drm/nouveau/nouveau_backlight.c:300:
+ if (nv_conn->type == DCB_CONNECTOR_eDP) {
total: 0 errors, 0 warnings, 1 checks, 302 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)
2021-05-14 18:14 ` Lyude Paul
` (11 preceding siblings ...)
(?)
@ 2021-05-14 18:35 ` Patchwork
-1 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-05-14 18:35 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)
URL : https://patchwork.freedesktop.org/series/84754/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:287:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:287:16: unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:287:16: unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:329:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:329:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:329:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:90:56: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)
2021-05-14 18:14 ` Lyude Paul
` (12 preceding siblings ...)
(?)
@ 2021-05-14 19:02 ` Patchwork
-1 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-05-14 19:02 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 12173 bytes --]
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)
URL : https://patchwork.freedesktop.org/series/84754/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10083 -> Patchwork_20128
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_20128 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20128, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20128:
### IGT changes ###
#### Warnings ####
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [INCOMPLETE][1] ([i915#2782] / [i915#2940]) -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bsw-nick/igt@i915_selftest@live@execlists.html
Known issues
------------
Here are the changes found in Patchwork_20128 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@nop-compute0:
- fi-ilk-650: NOTRUN -> [SKIP][3] ([fdo#109271]) +30 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-ilk-650/igt@amdgpu/amd_cs_nop@nop-compute0.html
* igt@gem_exec_fence@basic-await@vcs0:
- fi-bxt-dsi: [PASS][4] -> [FAIL][5] ([i915#3457])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bxt-dsi/igt@gem_exec_fence@basic-await@vcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bxt-dsi/igt@gem_exec_fence@basic-await@vcs0.html
* igt@gem_exec_fence@nb-await@rcs0:
- fi-glk-dsi: [PASS][6] -> [FAIL][7] ([i915#3457]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-glk-dsi/igt@gem_exec_fence@nb-await@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-glk-dsi/igt@gem_exec_fence@nb-await@rcs0.html
- fi-bsw-nick: [PASS][8] -> [FAIL][9] ([i915#3457]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-nick/igt@gem_exec_fence@nb-await@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bsw-nick/igt@gem_exec_fence@nb-await@rcs0.html
* igt@gem_exec_fence@nb-await@vecs0:
- fi-bsw-kefka: [PASS][10] -> [FAIL][11] ([i915#3457])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vecs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vecs0.html
- fi-bsw-n3050: [PASS][12] -> [FAIL][13] ([i915#3457]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-n3050/igt@gem_exec_fence@nb-await@vecs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bsw-n3050/igt@gem_exec_fence@nb-await@vecs0.html
* igt@gem_exec_suspend@basic-s3:
- fi-skl-6600u: [PASS][14] -> [INCOMPLETE][15] ([i915#198])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-skl-6600u/igt@gem_exec_suspend@basic-s3.html
* igt@i915_module_load@reload:
- fi-ilk-650: NOTRUN -> [DMESG-FAIL][16] ([i915#3457]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-ilk-650/igt@i915_module_load@reload.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ilk-650: NOTRUN -> [SKIP][17] ([fdo#109271] / [fdo#111827]) +8 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-ilk-650/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-ilk-650: NOTRUN -> [FAIL][18] ([i915#3457]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-ilk-650/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- fi-elk-e7500: [PASS][19] -> [FAIL][20] ([i915#53]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-elk-e7500/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-elk-e7500/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
- fi-ilk-650: NOTRUN -> [FAIL][21] ([i915#53]) +7 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-ilk-650/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-bwr-2160: [PASS][22] -> [FAIL][23] ([i915#53]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bwr-2160/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bwr-2160/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
#### Possible fixes ####
* igt@gem_exec_fence@basic-await@vcs0:
- fi-bsw-n3050: [FAIL][24] ([i915#3457]) -> [PASS][25] +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-n3050/igt@gem_exec_fence@basic-await@vcs0.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bsw-n3050/igt@gem_exec_fence@basic-await@vcs0.html
* igt@gem_exec_fence@nb-await@rcs0:
- fi-elk-e7500: [FAIL][26] ([i915#3457]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-elk-e7500/igt@gem_exec_fence@nb-await@rcs0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-elk-e7500/igt@gem_exec_fence@nb-await@rcs0.html
* igt@gem_exec_fence@nb-await@vecs0:
- fi-bsw-nick: [FAIL][28] ([i915#3457]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-nick/igt@gem_exec_fence@nb-await@vecs0.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bsw-nick/igt@gem_exec_fence@nb-await@vecs0.html
* igt@gem_wait@busy@all:
- fi-glk-dsi: [FAIL][30] ([i915#3457]) -> [PASS][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-glk-dsi/igt@gem_wait@busy@all.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-glk-dsi/igt@gem_wait@busy@all.html
- fi-bsw-kefka: [FAIL][32] ([i915#3177] / [i915#3457]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-kefka/igt@gem_wait@busy@all.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bsw-kefka/igt@gem_wait@busy@all.html
* igt@gem_wait@wait@all:
- fi-bwr-2160: [FAIL][34] ([i915#3457]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bwr-2160/igt@gem_wait@wait@all.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bwr-2160/igt@gem_wait@wait@all.html
* igt@kms_busy@basic@modeset:
- fi-ilk-650: [INCOMPLETE][36] ([i915#3457]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-ilk-650/igt@kms_busy@basic@modeset.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-ilk-650/igt@kms_busy@basic@modeset.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-bsw-kefka: [FAIL][38] ([i915#53]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-kefka/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bsw-kefka/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b:
- fi-elk-e7500: [FAIL][40] ([i915#53]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
#### Warnings ####
* igt@i915_module_load@reload:
- fi-bsw-kefka: [DMESG-FAIL][42] ([i915#1982] / [i915#3457]) -> [DMESG-WARN][43] ([i915#1982] / [i915#3457])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-bsw-kefka/igt@i915_module_load@reload.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-bsw-kefka/igt@i915_module_load@reload.html
- fi-glk-dsi: [DMESG-FAIL][44] ([i915#3457]) -> [DMESG-WARN][45] ([i915#3457])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-glk-dsi/igt@i915_module_load@reload.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-glk-dsi/igt@i915_module_load@reload.html
* igt@runner@aborted:
- fi-kbl-soraka: [FAIL][46] ([i915#1436] / [i915#3363]) -> [FAIL][47] ([i915#1436] / [i915#2426] / [i915#3363])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/fi-kbl-soraka/igt@runner@aborted.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/fi-kbl-soraka/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3177]: https://gitlab.freedesktop.org/drm/intel/issues/3177
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3457]: https://gitlab.freedesktop.org/drm/intel/issues/3457
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#541]: https://gitlab.freedesktop.org/drm/intel/issues/541
Participating hosts (40 -> 29)
------------------------------
Missing (11): fi-cml-u2 fi-rkl-11500t fi-ehl-1 fi-cml-s fi-skl-guc fi-tgl-1115g4 fi-bsw-cyan fi-kbl-x1275 fi-ehl-2 fi-bdw-samus fi-kbl-r
Build changes
-------------
* Linux: CI_DRM_10083 -> Patchwork_20128
CI-20190529: 20190529
CI_DRM_10083: 63c1a45e11736b26f82b6d6ad107c3ddd4b5c1c2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6084: 5c5734d8ee1afac871b69c4554ff14e9b56100e4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20128: 44243fa043043c2b1e270ab51cdc5afab151b876 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
44243fa04304 drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
d57f9740534c drm/dp: Extract i915's eDP backlight code into DRM helpers
342cf2c01c5b drm/i915/dpcd_bl: Print return codes for VESA backlight failures
2dcb4ec0f19c drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT
eeb1fae7ed93 drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
beb0b699bc45 drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight
9ce26ee2ba51 drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
e1cad9d60eec drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
268e6a95dfed drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/index.html
[-- Attachment #1.2: Type: text/html, Size: 14930 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)
2021-05-14 18:14 ` Lyude Paul
` (13 preceding siblings ...)
(?)
@ 2021-05-15 4:09 ` Patchwork
-1 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-05-15 4:09 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30299 bytes --]
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8)
URL : https://patchwork.freedesktop.org/series/84754/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10083_full -> Patchwork_20128_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20128_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20128_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20128_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-glk: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk7/igt@gem_ppgtt@blt-vs-render-ctx0.html
* igt@kms_flip_tiling@flip-changes-tiling@hdmi-a-1-pipe-c:
- shard-glk: [PASS][2] -> [FAIL][3] +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk8/igt@kms_flip_tiling@flip-changes-tiling@hdmi-a-1-pipe-c.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk7/igt@kms_flip_tiling@flip-changes-tiling@hdmi-a-1-pipe-c.html
#### Warnings ####
* igt@kms_plane_cursor@pipe-c-viewport-size-64:
- shard-tglb: [FAIL][4] ([i915#3457]) -> [FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-tglb8/igt@kms_plane_cursor@pipe-c-viewport-size-64.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb8/igt@kms_plane_cursor@pipe-c-viewport-size-64.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane@plane-position-covered@pipe-a-planes}:
- shard-glk: [PASS][6] -> [FAIL][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk9/igt@kms_plane@plane-position-covered@pipe-a-planes.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk8/igt@kms_plane@plane-position-covered@pipe-a-planes.html
### Piglit changes ###
#### Possible regressions ####
* spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 42 1 64 8 (NEW):
- pig-glk-j5005: NOTRUN -> [INCOMPLETE][8] +3 similar issues
[8]: None
New tests
---------
New tests have been introduced between CI_DRM_10083_full and Patchwork_20128_full:
### New Piglit tests (4) ###
* spec@arb_shader_image_load_store@max-size:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 42 1 128 1:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 42 1 128 2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_texture_barrier@arb_texture_barrier-blending-in-shader 512 42 1 64 8:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_20128_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_read@fault-buffer:
- shard-kbl: NOTRUN -> [DMESG-WARN][9] ([i915#3457])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl2/igt@drm_read@fault-buffer.html
* igt@gem_ctx_persistence@heartbeat-many:
- shard-glk: [PASS][10] -> [FAIL][11] ([i915#3457]) +22 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk3/igt@gem_ctx_persistence@heartbeat-many.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk6/igt@gem_ctx_persistence@heartbeat-many.html
* igt@gem_ctx_persistence@idempotent:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) +6 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-snb2/igt@gem_ctx_persistence@idempotent.html
* igt@gem_exec_fair@basic-deadline:
- shard-apl: NOTRUN -> [FAIL][13] ([i915#2846] / [i915#3457])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl7/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: NOTRUN -> [FAIL][14] ([i915#3457]) +8 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: NOTRUN -> [FAIL][15] ([i915#2842] / [i915#3457]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs1:
- shard-kbl: [PASS][16] -> [FAIL][17] ([i915#2842] / [i915#3457]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-kbl2/igt@gem_exec_fair@basic-pace@vcs1.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-snb: NOTRUN -> [SKIP][18] ([fdo#109271]) +398 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-snb6/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_gttfill@basic:
- shard-apl: [PASS][19] -> [FAIL][20] ([i915#3457])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-apl6/igt@gem_exec_gttfill@basic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl7/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_params@no-vebox:
- shard-tglb: NOTRUN -> [SKIP][21] ([fdo#109283])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb8/igt@gem_exec_params@no-vebox.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-iclb: NOTRUN -> [SKIP][22] ([fdo#109283])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_schedule@u-fairslice@vecs0:
- shard-glk: NOTRUN -> [FAIL][23] ([i915#3457]) +10 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk7/igt@gem_exec_schedule@u-fairslice@vecs0.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][24] -> [DMESG-WARN][25] ([i915#180]) +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-kbl3/igt@gem_exec_suspend@basic-s3.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl1/igt@gem_exec_suspend@basic-s3.html
* igt@gem_mmap_gtt@big-copy-odd:
- shard-glk: [PASS][26] -> [FAIL][27] ([i915#307])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk3/igt@gem_mmap_gtt@big-copy-odd.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk3/igt@gem_mmap_gtt@big-copy-odd.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-iclb: [PASS][28] -> [INCOMPLETE][29] ([i915#2910] / [i915#3468])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-iclb3/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb7/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-xy:
- shard-iclb: [PASS][30] -> [INCOMPLETE][31] ([i915#3468])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-iclb8/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb4/igt@gem_mmap_gtt@cpuset-basic-small-copy-xy.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-kbl: NOTRUN -> [INCOMPLETE][32] ([i915#3468])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl6/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
* igt@gem_mmap_gtt@fault-concurrent-y:
- shard-snb: NOTRUN -> [INCOMPLETE][33] ([i915#3468])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-snb6/igt@gem_mmap_gtt@fault-concurrent-y.html
* igt@gem_pwrite@basic-exhaustion:
- shard-kbl: NOTRUN -> [WARN][34] ([i915#2658])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl7/igt@gem_pwrite@basic-exhaustion.html
* igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs:
- shard-iclb: NOTRUN -> [INCOMPLETE][35] ([i915#3468])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
- shard-skl: NOTRUN -> [INCOMPLETE][36] ([i915#3468]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-skl7/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
- shard-apl: NOTRUN -> [INCOMPLETE][37] ([i915#3468]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl1/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
* igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs:
- shard-iclb: NOTRUN -> [SKIP][38] ([i915#768])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb3/igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled:
- shard-tglb: NOTRUN -> [INCOMPLETE][39] ([i915#3468])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb8/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html
- shard-glk: NOTRUN -> [INCOMPLETE][40] ([i915#3468])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk4/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled.html
* igt@gem_spin_batch@engines@vcs0:
- shard-apl: NOTRUN -> [FAIL][41] ([i915#2898] / [i915#3457]) +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl1/igt@gem_spin_batch@engines@vcs0.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-apl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#3323])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl7/igt@gem_userptr_blits@dmabuf-sync.html
- shard-glk: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3323])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk7/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@set-cache-level:
- shard-apl: NOTRUN -> [FAIL][44] ([i915#3324])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl1/igt@gem_userptr_blits@set-cache-level.html
* igt@gem_userptr_blits@vma-merge:
- shard-apl: NOTRUN -> [FAIL][45] ([i915#3318] / [i915#3457])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl7/igt@gem_userptr_blits@vma-merge.html
* igt@gen7_exec_parse@basic-allocation:
- shard-tglb: NOTRUN -> [SKIP][46] ([fdo#109289])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb1/igt@gen7_exec_parse@basic-allocation.html
- shard-iclb: NOTRUN -> [SKIP][47] ([fdo#109289])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb3/igt@gen7_exec_parse@basic-allocation.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#112306])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@i915_hangman@error-state-capture@rcs0:
- shard-glk: NOTRUN -> [DMESG-WARN][49] ([i915#3457]) +3 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk4/igt@i915_hangman@error-state-capture@rcs0.html
* igt@i915_hangman@error-state-capture@vcs1:
- shard-tglb: NOTRUN -> [DMESG-WARN][50] ([i915#3457]) +5 similar issues
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb8/igt@i915_hangman@error-state-capture@vcs1.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-tglb: NOTRUN -> [SKIP][51] ([i915#1904])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb1/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-dpms:
- shard-skl: NOTRUN -> [FAIL][52] ([i915#454])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-skl7/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rpm@gem-mmap-type@uc:
- shard-skl: NOTRUN -> [DMESG-WARN][53] ([i915#3475])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-skl7/igt@i915_pm_rpm@gem-mmap-type@uc.html
- shard-tglb: [PASS][54] -> [DMESG-WARN][55] ([i915#2411])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-tglb3/igt@i915_pm_rpm@gem-mmap-type@uc.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb8/igt@i915_pm_rpm@gem-mmap-type@uc.html
* igt@i915_pm_rpm@gem-mmap-type@wc:
- shard-tglb: [PASS][56] -> [DMESG-WARN][57] ([i915#2411] / [i915#3457])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-tglb3/igt@i915_pm_rpm@gem-mmap-type@wc.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb8/igt@i915_pm_rpm@gem-mmap-type@wc.html
- shard-skl: NOTRUN -> [DMESG-WARN][58] ([i915#3457]) +2 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-skl7/igt@i915_pm_rpm@gem-mmap-type@wc.html
* igt@i915_pm_rps@min-max-config-idle:
- shard-iclb: NOTRUN -> [DMESG-WARN][59] ([i915#3457]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@i915_pm_rps@min-max-config-idle.html
* igt@i915_pm_rps@min-max-config-loaded:
- shard-snb: NOTRUN -> [DMESG-WARN][60] ([i915#3457]) +2 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-snb2/igt@i915_pm_rps@min-max-config-loaded.html
* igt@i915_pm_sseu@full-enable:
- shard-apl: NOTRUN -> [DMESG-WARN][61] ([i915#3457]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl1/igt@i915_pm_sseu@full-enable.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][62] ([fdo#110725] / [fdo#111614])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-90:
- shard-tglb: NOTRUN -> [SKIP][63] ([fdo#111615])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-90.html
* igt@kms_big_joiner@basic:
- shard-iclb: NOTRUN -> [SKIP][64] ([i915#2705])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@kms_big_joiner@basic.html
* igt@kms_chamelium@dp-audio-edid:
- shard-tglb: NOTRUN -> [SKIP][65] ([fdo#109284] / [fdo#111827]) +4 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb1/igt@kms_chamelium@dp-audio-edid.html
* igt@kms_chamelium@hdmi-aspect-ratio:
- shard-skl: NOTRUN -> [SKIP][66] ([fdo#109271] / [fdo#111827]) +5 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-skl7/igt@kms_chamelium@hdmi-aspect-ratio.html
* igt@kms_chamelium@hdmi-crc-nonplanar-formats:
- shard-glk: NOTRUN -> [SKIP][67] ([fdo#109271] / [fdo#111827]) +5 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk7/igt@kms_chamelium@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium@hdmi-hpd-enable-disable-mode:
- shard-snb: NOTRUN -> [SKIP][68] ([fdo#109271] / [fdo#111827]) +21 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-snb5/igt@kms_chamelium@hdmi-hpd-enable-disable-mode.html
* igt@kms_chamelium@vga-hpd-with-enabled-mode:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109284] / [fdo#111827]) +5 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@kms_chamelium@vga-hpd-with-enabled-mode.html
* igt@kms_color@pipe-b-degamma:
- shard-glk: [PASS][70] -> [FAIL][71] ([i915#71])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk8/igt@kms_color@pipe-b-degamma.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk5/igt@kms_color@pipe-b-degamma.html
* igt@kms_color@pipe-c-ctm-0-75:
- shard-skl: [PASS][72] -> [DMESG-WARN][73] ([i915#1982])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-skl4/igt@kms_color@pipe-c-ctm-0-75.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-skl4/igt@kms_color@pipe-c-ctm-0-75.html
* igt@kms_color@pipe-d-degamma:
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109278] / [i915#1149]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb3/igt@kms_color@pipe-d-degamma.html
- shard-tglb: NOTRUN -> [FAIL][75] ([i915#1149])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb1/igt@kms_color@pipe-d-degamma.html
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271] / [fdo#111827]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl2/igt@kms_color_chamelium@pipe-b-ctm-0-25.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-apl: NOTRUN -> [SKIP][77] ([fdo#109271] / [fdo#111827]) +19 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl1/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-iclb: NOTRUN -> [SKIP][78] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_content_protection@lic:
- shard-apl: NOTRUN -> [TIMEOUT][79] ([i915#1319]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl1/igt@kms_content_protection@lic.html
* igt@kms_content_protection@uevent:
- shard-apl: NOTRUN -> [FAIL][80] ([i915#2105])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl7/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen:
- shard-iclb: NOTRUN -> [SKIP][81] ([fdo#109278] / [i915#3457]) +6 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-32x32-random:
- shard-tglb: NOTRUN -> [SKIP][82] ([i915#3319] / [i915#3457])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-32x32-random.html
* igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque:
- shard-glk: [PASS][83] -> [FAIL][84] ([i915#3444] / [i915#3457]) +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-glk4/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
- shard-tglb: [PASS][85] -> [FAIL][86] ([i915#2124] / [i915#3457]) +1 similar issue
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-alpha-opaque.html
* igt@kms_cursor_crc@pipe-a-cursor-size-change:
- shard-snb: NOTRUN -> [FAIL][87] ([i915#3457]) +5 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-snb6/igt@kms_cursor_crc@pipe-a-cursor-size-change.html
- shard-iclb: NOTRUN -> [FAIL][88] ([i915#3457]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb3/igt@kms_cursor_crc@pipe-a-cursor-size-change.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen:
- shard-kbl: [PASS][89] -> [FAIL][90] ([i915#3444] / [i915#3457])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl4/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- shard-skl: NOTRUN -> [FAIL][91] ([i915#3444] / [i915#3457]) +5 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen:
- shard-tglb: NOTRUN -> [FAIL][92] ([i915#2124] / [i915#3457]) +4 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-256x85-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-offscreen:
- shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#3457]) +26 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-32x32-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-kbl: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#3457]) +6 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-random:
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109278] / [fdo#109279] / [i915#3457]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@kms_cursor_crc@pipe-b-cursor-512x512-random.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen:
- shard-skl: [PASS][96] -> [FAIL][97] ([i915#3444] / [i915#3457]) +2 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-64x64-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque:
- shard-apl: NOTRUN -> [FAIL][98] ([i915#3444] / [i915#3457]) +5 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl1/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
- shard-iclb: [PASS][99] -> [FAIL][100] ([i915#3457])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-iclb5/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb8/igt@kms_cursor_crc@pipe-b-cursor-alpha-opaque.html
* igt@kms_cursor_crc@pipe-b-cursor-max-size-onscreen:
- shard-tglb: NOTRUN -> [SKIP][101] ([i915#3359] / [i915#3457])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-max-size-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-max-size-random:
- shard-skl: NOTRUN -> [SKIP][102] ([fdo#109271] / [i915#3457]) +10 similar issues
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-max-size-random.html
* igt@kms_cursor_crc@pipe-c-cursor-128x42-random:
- shard-apl: [PASS][103] -> [FAIL][104] ([i915#3444] / [i915#3457]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-128x42-random.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl6/igt@kms_cursor_crc@pipe-c-cursor-128x42-random.html
* igt@kms_cursor_crc@pipe-c-cursor-dpms:
- shard-glk: NOTRUN -> [FAIL][105] ([i915#3444] / [i915#3457]) +5 similar issues
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk7/igt@kms_cursor_crc@pipe-c-cursor-dpms.html
* igt@kms_cursor_crc@pipe-d-cursor-256x85-random:
- shard-glk: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#3457]) +5 similar issues
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk7/igt@kms_cursor_crc@pipe-d-cursor-256x85-random.html
* igt@kms_cursor_crc@pipe-d-cursor-32x10-sliding:
- shard-snb: NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#3457]) +58 similar issues
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-snb2/igt@kms_cursor_crc@pipe-d-cursor-32x10-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding:
- shard-tglb: NOTRUN -> [SKIP][108] ([fdo#109279] / [i915#3359] / [i915#3457]) +2 similar issues
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-512x512-sliding.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-top-edge:
- shard-iclb: NOTRUN -> [SKIP][109] ([fdo#109278]) +4 similar issues
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@kms_cursor_edge_walk@pipe-d-128x128-top-edge.html
* igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
- shard-iclb: NOTRUN -> [SKIP][110] ([fdo#109274] / [fdo#109278]) +1 similar issue
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb3/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: NOTRUN -> [INCOMPLETE][111] ([i915#155] / [i915#180] / [i915#636])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl2/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-tglb: NOTRUN -> [SKIP][112] ([fdo#111825]) +18 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-tglb8/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-iclb: NOTRUN -> [SKIP][113] ([fdo#109274])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: NOTRUN -> [DMESG-WARN][114] ([i915#180]) +2 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl7/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs:
- shard-apl: NOTRUN -> [SKIP][115] ([fdo#109271] / [i915#2672])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][116] ([fdo#109271] / [i915#2642])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt:
- shard-kbl: NOTRUN -> [SKIP][117] ([fdo#109271]) +40 similar issues
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][118] ([fdo#109280]) +15 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt:
- shard-skl: [PASS][119] -> [FAIL][120] ([i915#49])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10083/shard-skl8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-skl1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt:
- shard-glk: NOTRUN -> [SKIP][121] ([fdo#109271]) +38 similar issues
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-glk4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-apl: NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#533])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-7efc:
- shard-kbl: NOTRUN -> [FAIL][123] ([fdo#108145] / [i915#265]) +1 similar issue
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-kbl6/igt@kms_plane_alpha_blend@pipe-b-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][124] ([i915#265])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> [FAIL][125] ([fdo#108145] / [i915#265]) +1 similar issue
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-apl: NOTRUN -> [F
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20128/index.html
[-- Attachment #1.2: Type: text/html, Size: 33918 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev9)
2021-05-14 18:14 ` Lyude Paul
` (14 preceding siblings ...)
(?)
@ 2021-05-17 17:01 ` Patchwork
-1 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-05-17 17:01 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev9)
URL : https://patchwork.freedesktop.org/series/84754/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3ef024f74b90 drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
5f4e95c11492 drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
30191a9431c2 drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
e0af14b198b5 drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight
1734428bc4f6 drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
951e57b8ef02 drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT
ae8b9f4c3c14 drm/i915/dpcd_bl: Print return codes for VESA backlight failures
358a5c9c2820 drm/dp: Extract i915's eDP backlight code into DRM helpers
f8abfe784919 drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
-:238: CHECK:CAMELCASE: Avoid CamelCase: <DCB_CONNECTOR_eDP>
#238: FILE: drivers/gpu/drm/nouveau/nouveau_backlight.c:300:
+ if (nv_conn->type == DCB_CONNECTOR_eDP) {
total: 0 errors, 0 warnings, 1 checks, 302 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev9)
2021-05-14 18:14 ` Lyude Paul
` (15 preceding siblings ...)
(?)
@ 2021-05-17 17:03 ` Patchwork
-1 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-05-17 17:03 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev9)
URL : https://patchwork.freedesktop.org/series/84754/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:287:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:287:16: unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:287:16: unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:329:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:329:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:329:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:90:56: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev9)
2021-05-14 18:14 ` Lyude Paul
` (16 preceding siblings ...)
(?)
@ 2021-05-17 17:31 ` Patchwork
-1 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-05-17 17:31 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 22617 bytes --]
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev9)
URL : https://patchwork.freedesktop.org/series/84754/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10092 -> Patchwork_20137
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20137 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20137, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20137:
### IGT changes ###
#### Possible regressions ####
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-bdw-5557u/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@runner@aborted:
- {fi-rkl-11500t}: NOTRUN -> [FAIL][2]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-rkl-11500t/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_20137 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_cs_nop@sync-fork-compute0:
- fi-snb-2600: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html
* igt@amdgpu/amd_prime@i915-to-amd:
- fi-snb-2520m: NOTRUN -> [SKIP][4] ([fdo#109271]) +37 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-snb-2520m/igt@amdgpu/amd_prime@i915-to-amd.html
* igt@core_hotunplug@unbind-rebind:
- fi-bdw-5557u: NOTRUN -> [WARN][5] ([i915#2283])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-bdw-5557u/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_fence@basic-await@bcs0:
- fi-bsw-n3050: [PASS][6] -> [FAIL][7] ([i915#3457]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-bsw-n3050/igt@gem_exec_fence@basic-await@bcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-bsw-n3050/igt@gem_exec_fence@basic-await@bcs0.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-kbl-r: NOTRUN -> [SKIP][8] ([fdo#109271]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-r/igt@gem_exec_fence@basic-busy@bcs0.html
- fi-apl-guc: NOTRUN -> [SKIP][9] ([fdo#109271]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-apl-guc/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_exec_fence@nb-await@bcs0:
- fi-bsw-nick: [PASS][10] -> [FAIL][11] ([i915#3457]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-bsw-nick/igt@gem_exec_fence@nb-await@bcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-bsw-nick/igt@gem_exec_fence@nb-await@bcs0.html
* igt@gem_exec_fence@nb-await@vcs0:
- fi-glk-dsi: NOTRUN -> [FAIL][12] ([i915#3457]) +3 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-glk-dsi/igt@gem_exec_fence@nb-await@vcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-cfl-guc: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#2190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-guc/igt@gem_huc_copy@huc-copy.html
- fi-skl-6700k2: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-skl-6700k2/igt@gem_huc_copy@huc-copy.html
- fi-glk-dsi: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-glk-dsi/igt@gem_huc_copy@huc-copy.html
- fi-kbl-x1275: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-x1275/igt@gem_huc_copy@huc-copy.html
- fi-kbl-r: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-r/igt@gem_huc_copy@huc-copy.html
- fi-cfl-8109u: NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#2190])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8109u/igt@gem_huc_copy@huc-copy.html
- fi-cfl-8700k: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#2190])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8700k/igt@gem_huc_copy@huc-copy.html
* igt@gem_wait@wait@all:
- fi-bwr-2160: [PASS][20] -> [FAIL][21] ([i915#3457])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-bwr-2160/igt@gem_wait@wait@all.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-bwr-2160/igt@gem_wait@wait@all.html
* igt@i915_hangman@error-state-basic:
- fi-apl-guc: NOTRUN -> [DMESG-WARN][22] ([i915#1610])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-apl-guc/igt@i915_hangman@error-state-basic.html
* igt@i915_module_load@reload:
- fi-cfl-8700k: NOTRUN -> [DMESG-WARN][23] ([i915#3457]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8700k/igt@i915_module_load@reload.html
- fi-snb-2520m: NOTRUN -> [DMESG-WARN][24] ([i915#3457]) +1 similar issue
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-snb-2520m/igt@i915_module_load@reload.html
- fi-cfl-guc: NOTRUN -> [DMESG-WARN][25] ([i915#3457]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-guc/igt@i915_module_load@reload.html
- fi-skl-6700k2: NOTRUN -> [DMESG-WARN][26] ([i915#3457]) +1 similar issue
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-skl-6700k2/igt@i915_module_load@reload.html
- fi-glk-dsi: NOTRUN -> [DMESG-FAIL][27] ([i915#3457])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-glk-dsi/igt@i915_module_load@reload.html
- fi-kbl-x1275: NOTRUN -> [DMESG-WARN][28] ([i915#3457]) +1 similar issue
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-x1275/igt@i915_module_load@reload.html
* igt@i915_selftest@live@execlists:
- fi-kbl-r: NOTRUN -> [DMESG-FAIL][29] ([i915#3462])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-r/igt@i915_selftest@live@execlists.html
- fi-cfl-8109u: NOTRUN -> [INCOMPLETE][30] ([i915#3462])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8109u/igt@i915_selftest@live@execlists.html
- fi-glk-dsi: NOTRUN -> [DMESG-FAIL][31] ([i915#3462])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-glk-dsi/igt@i915_selftest@live@execlists.html
- fi-kbl-x1275: NOTRUN -> [DMESG-FAIL][32] ([i915#3462])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-x1275/igt@i915_selftest@live@execlists.html
- fi-cfl-8700k: NOTRUN -> [DMESG-FAIL][33] ([i915#3462])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8700k/igt@i915_selftest@live@execlists.html
- fi-skl-6700k2: NOTRUN -> [DMESG-FAIL][34] ([i915#3462])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-skl-6700k2/igt@i915_selftest@live@execlists.html
- fi-cfl-guc: NOTRUN -> [DMESG-FAIL][35] ([i915#3462])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-guc/igt@i915_selftest@live@execlists.html
- fi-bdw-5557u: NOTRUN -> [DMESG-FAIL][36] ([i915#3462])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-bdw-5557u/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@mman:
- fi-kbl-r: NOTRUN -> [DMESG-WARN][37] ([i915#3457]) +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-r/igt@i915_selftest@live@mman.html
- fi-bdw-5557u: NOTRUN -> [DMESG-WARN][38] ([i915#3457]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-bdw-5557u/igt@i915_selftest@live@mman.html
- fi-cfl-8109u: NOTRUN -> [DMESG-WARN][39] ([i915#3457]) +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8109u/igt@i915_selftest@live@mman.html
- fi-glk-dsi: NOTRUN -> [DMESG-WARN][40] ([i915#3457])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-glk-dsi/igt@i915_selftest@live@mman.html
* igt@kms_chamelium@dp-crc-fast:
- fi-bdw-5557u: NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +8 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-bdw-5557u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-edid-read:
- fi-cfl-guc: NOTRUN -> [SKIP][42] ([fdo#109271] / [fdo#111827]) +8 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-guc/igt@kms_chamelium@dp-edid-read.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-skl-6700k2: NOTRUN -> [SKIP][43] ([fdo#109271]) +13 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-skl-6700k2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-crc-fast:
- fi-kbl-x1275: NOTRUN -> [SKIP][44] ([fdo#109271] / [fdo#111827]) +8 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-x1275/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-edid-read:
- fi-kbl-r: NOTRUN -> [SKIP][45] ([fdo#109271] / [fdo#111827]) +8 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-r/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-glk-dsi: NOTRUN -> [SKIP][46] ([fdo#109271] / [fdo#111827]) +8 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-glk-dsi/igt@kms_chamelium@hdmi-hpd-fast.html
- fi-snb-2520m: NOTRUN -> [SKIP][47] ([fdo#109271] / [fdo#111827]) +8 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-snb-2520m/igt@kms_chamelium@hdmi-hpd-fast.html
- fi-cfl-8109u: NOTRUN -> [SKIP][48] ([fdo#109271] / [fdo#111827]) +8 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8109u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_chamelium@vga-edid-read:
- fi-cfl-8700k: NOTRUN -> [SKIP][49] ([fdo#109271] / [fdo#111827]) +8 similar issues
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8700k/igt@kms_chamelium@vga-edid-read.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-ilk-650: [PASS][50] -> [FAIL][51] ([i915#53])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-ilk-650/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-ilk-650/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
- fi-elk-e7500: [PASS][52] -> [FAIL][53] ([i915#53])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-elk-e7500/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-elk-e7500/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cfl-8700k: NOTRUN -> [SKIP][54] ([fdo#109271] / [i915#533])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8700k/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-cfl-guc: NOTRUN -> [SKIP][55] ([fdo#109271] / [i915#533])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-skl-6700k2: NOTRUN -> [SKIP][56] ([fdo#109271] / [i915#533])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-skl-6700k2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-x1275: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#533])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-x1275/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-cfl-8109u: NOTRUN -> [SKIP][58] ([fdo#109271] / [i915#533])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-glk-dsi: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#533])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-glk-dsi/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-kbl-r: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#533])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-r/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@cursor_plane_move:
- fi-bdw-5557u: NOTRUN -> [SKIP][61] ([fdo#109271]) +9 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-bdw-5557u/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_mmap_gtt:
- fi-cfl-8109u: NOTRUN -> [SKIP][62] ([fdo#109271]) +8 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8109u/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@primary_page_flip:
- fi-glk-dsi: NOTRUN -> [SKIP][63] ([fdo#109271]) +10 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-glk-dsi/igt@kms_psr@primary_page_flip.html
- fi-kbl-x1275: NOTRUN -> [SKIP][64] ([fdo#109271]) +8 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-x1275/igt@kms_psr@primary_page_flip.html
* igt@kms_psr@sprite_plane_onoff:
- fi-cfl-guc: NOTRUN -> [SKIP][65] ([fdo#109271]) +8 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-guc/igt@kms_psr@sprite_plane_onoff.html
* igt@prime_vgem@basic-userptr:
- fi-cfl-8700k: NOTRUN -> [SKIP][66] ([fdo#109271]) +8 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8700k/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-kbl-x1275: NOTRUN -> [FAIL][67] ([i915#1436] / [i915#3363])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-x1275/igt@runner@aborted.html
- fi-cfl-8700k: NOTRUN -> [FAIL][68] ([i915#3363])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8700k/igt@runner@aborted.html
- fi-cfl-8109u: NOTRUN -> [FAIL][69] ([i915#3363])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-8109u/igt@runner@aborted.html
- fi-glk-dsi: NOTRUN -> [FAIL][70] ([i915#2426] / [i915#3363] / [k.org#202321])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-glk-dsi/igt@runner@aborted.html
- fi-apl-guc: NOTRUN -> [FAIL][71] ([i915#2426] / [i915#3363])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-apl-guc/igt@runner@aborted.html
- fi-kbl-r: NOTRUN -> [FAIL][72] ([i915#1436] / [i915#3363])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-r/igt@runner@aborted.html
- fi-cfl-guc: NOTRUN -> [FAIL][73] ([i915#3363])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-cfl-guc/igt@runner@aborted.html
- fi-skl-6700k2: NOTRUN -> [FAIL][74] ([i915#1436] / [i915#2426] / [i915#3363])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-skl-6700k2/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_busy@busy@all:
- fi-bsw-n3050: [FAIL][75] ([i915#3457]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-bsw-n3050/igt@gem_busy@busy@all.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-bsw-n3050/igt@gem_busy@busy@all.html
* igt@gem_exec_fence@nb-await@vcs0:
- fi-bsw-nick: [FAIL][77] ([i915#3457]) -> [PASS][78] +2 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-bsw-nick/igt@gem_exec_fence@nb-await@vcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-bsw-nick/igt@gem_exec_fence@nb-await@vcs0.html
* igt@gem_wait@busy@all:
- fi-pnv-d510: [FAIL][79] ([i915#3457]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-pnv-d510/igt@gem_wait@busy@all.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-pnv-d510/igt@gem_wait@busy@all.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][81] ([i915#2782]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-elk-e7500: [FAIL][83] ([i915#53]) -> [PASS][84] +2 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-elk-e7500/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-elk-e7500/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html
#### Warnings ####
* igt@gem_exec_gttfill@basic:
- fi-ilk-650: [FAIL][85] ([i915#3457] / [i915#3472]) -> [FAIL][86] ([i915#3472])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-ilk-650/igt@gem_exec_gttfill@basic.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-ilk-650/igt@gem_exec_gttfill@basic.html
* igt@i915_module_load@reload:
- fi-skl-6600u: [DMESG-WARN][87] ([i915#1982] / [i915#3457]) -> [DMESG-WARN][88] ([i915#3457])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-skl-6600u/igt@i915_module_load@reload.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-skl-6600u/igt@i915_module_load@reload.html
* igt@i915_selftest@live@mman:
- fi-elk-e7500: [DMESG-WARN][89] ([i915#3457]) -> [DMESG-FAIL][90] ([i915#3457])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-elk-e7500/igt@i915_selftest@live@mman.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-elk-e7500/igt@i915_selftest@live@mman.html
* igt@runner@aborted:
- fi-kbl-guc: [FAIL][91] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][92] ([i915#1436] / [i915#3363])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10092/fi-kbl-guc/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/fi-kbl-guc/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1610]: https://gitlab.freedesktop.org/drm/intel/issues/1610
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
[i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
[i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3457]: https://gitlab.freedesktop.org/drm/intel/issues/3457
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#3468]: https://gitlab.freedesktop.org/drm/intel/issues/3468
[i915#3472]: https://gitlab.freedesktop.org/drm/intel/issues/3472
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321
Participating hosts (21 -> 30)
------------------------------
Additional (11): fi-rkl-11500t fi-bdw-5557u fi-glk-dsi fi-cfl-8700k fi-apl-guc fi-snb-2520m fi-cfl-guc fi-kbl-x1275 fi-cfl-8109u fi-skl-6700k2 fi-kbl-r
Missing (2): fi-jsl-1 fi-ilk-m540
Build changes
-------------
* Linux: CI_DRM_10092 -> Patchwork_20137
CI-20190529: 20190529
CI_DRM_10092: 3fe31283a0eede655eff70823b5bb79441ff54c3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6084: 5c5734d8ee1afac871b69c4554ff14e9b56100e4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20137: f8abfe7849198d8aa9af7a00fd7f3f7b24d06128 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f8abfe784919 drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
358a5c9c2820 drm/dp: Extract i915's eDP backlight code into DRM helpers
ae8b9f4c3c14 drm/i915/dpcd_bl: Print return codes for VESA backlight failures
951e57b8ef02 drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT
1734428bc4f6 drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
e0af14b198b5 drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight
30191a9431c2 drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
5f4e95c11492 drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
3ef024f74b90 drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20137/index.html
[-- Attachment #1.2: Type: text/html, Size: 30779 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev10)
2021-05-14 18:14 ` Lyude Paul
` (17 preceding siblings ...)
(?)
@ 2021-05-18 19:41 ` Patchwork
-1 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-05-18 19:41 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev10)
URL : https://patchwork.freedesktop.org/series/84754/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
634883ae67b3 drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
2f6dd64b21d7 drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
59188c6d0d55 drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
221bebf6b8c3 drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight
48f8c1dcc3bd drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
131869b89b71 drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT
a7cc151a9942 drm/i915/dpcd_bl: Print return codes for VESA backlight failures
428307dfe083 drm/dp: Extract i915's eDP backlight code into DRM helpers
65a3d8889dfd drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
-:238: CHECK:CAMELCASE: Avoid CamelCase: <DCB_CONNECTOR_eDP>
#238: FILE: drivers/gpu/drm/nouveau/nouveau_backlight.c:300:
+ if (nv_conn->type == DCB_CONNECTOR_eDP) {
total: 0 errors, 0 warnings, 1 checks, 302 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev10)
2021-05-14 18:14 ` Lyude Paul
` (18 preceding siblings ...)
(?)
@ 2021-05-18 19:44 ` Patchwork
-1 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-05-18 19:44 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev10)
URL : https://patchwork.freedesktop.org/series/84754/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:274:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1345:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1346:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1405:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:287:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:287:16: unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:287:16: unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:274:25: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:275:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:329:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:329:17: struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:329:17: struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.h:90:56: error: marked inline, but without a definition
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:270:49: error: static assertion failed: "amd_sriov_msg_vf2pf_
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev10)
2021-05-14 18:14 ` Lyude Paul
` (19 preceding siblings ...)
(?)
@ 2021-05-18 20:12 ` Patchwork
-1 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-05-18 20:12 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 14859 bytes --]
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev10)
URL : https://patchwork.freedesktop.org/series/84754/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10100 -> Patchwork_20147
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/index.html
Known issues
------------
Here are the changes found in Patchwork_20147 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@cs-compute:
- fi-elk-e7500: NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-elk-e7500/igt@amdgpu/amd_basic@cs-compute.html
* igt@gem_exec_fence@basic-await@vcs0:
- fi-bsw-kefka: [PASS][2] -> [FAIL][3] ([i915#3457])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@gem_exec_fence@basic-await@vcs0.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bsw-kefka/igt@gem_exec_fence@basic-await@vcs0.html
* igt@gem_exec_fence@nb-await@rcs0:
- fi-bsw-nick: [PASS][4] -> [FAIL][5] ([i915#3457]) +2 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-nick/igt@gem_exec_fence@nb-await@rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bsw-nick/igt@gem_exec_fence@nb-await@rcs0.html
* igt@gem_exec_fence@nb-await@vecs0:
- fi-bsw-n3050: [PASS][6] -> [FAIL][7] ([i915#3457]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-n3050/igt@gem_exec_fence@nb-await@vecs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bsw-n3050/igt@gem_exec_fence@nb-await@vecs0.html
* igt@gem_wait@busy@all:
- fi-apl-guc: [PASS][8] -> [FAIL][9] ([i915#3457])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-apl-guc/igt@gem_wait@busy@all.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-apl-guc/igt@gem_wait@busy@all.html
* igt@gem_wait@wait@all:
- fi-pnv-d510: [PASS][10] -> [FAIL][11] ([i915#3457])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-pnv-d510/igt@gem_wait@wait@all.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-pnv-d510/igt@gem_wait@wait@all.html
* igt@i915_selftest@live@mman:
- fi-elk-e7500: NOTRUN -> [DMESG-FAIL][12] ([i915#3457])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-elk-e7500/igt@i915_selftest@live@mman.html
* igt@kms_chamelium@dp-crc-fast:
- fi-kbl-7500u: [PASS][13] -> [FAIL][14] ([i915#1372])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a:
- fi-bwr-2160: [PASS][15] -> [FAIL][16] ([i915#53])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bwr-2160/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bwr-2160/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-a.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-elk-e7500: [PASS][17] -> [FAIL][18] ([i915#53])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-bsw-kefka: [PASS][19] -> [FAIL][20] ([i915#53])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bsw-kefka/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
#### Possible fixes ####
* igt@gem_exec_fence@basic-await@vcs0:
- fi-bsw-n3050: [FAIL][21] ([i915#3457]) -> [PASS][22] +2 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-n3050/igt@gem_exec_fence@basic-await@vcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bsw-n3050/igt@gem_exec_fence@basic-await@vcs0.html
* igt@gem_exec_fence@basic-await@vecs0:
- fi-bsw-nick: [FAIL][23] ([i915#3457]) -> [PASS][24] +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-nick/igt@gem_exec_fence@basic-await@vecs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bsw-nick/igt@gem_exec_fence@basic-await@vecs0.html
* igt@gem_exec_fence@nb-await@vcs0:
- fi-bsw-kefka: [FAIL][25] ([i915#3457]) -> [PASS][26] +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vcs0.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vcs0.html
* igt@gem_wait@busy@all:
- fi-bwr-2160: [FAIL][27] ([i915#3457]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bwr-2160/igt@gem_wait@busy@all.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bwr-2160/igt@gem_wait@busy@all.html
- fi-bsw-kefka: [FAIL][29] ([i915#3177] / [i915#3457]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@gem_wait@busy@all.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bsw-kefka/igt@gem_wait@busy@all.html
* igt@i915_selftest@live@hangcheck:
- {fi-tgl-dsi}: [DMESG-FAIL][31] ([i915#2927]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-tgl-dsi/igt@i915_selftest@live@hangcheck.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-tgl-dsi/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@sanitycheck:
- fi-elk-e7500: [SKIP][33] ([fdo#109271]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-elk-e7500/igt@i915_selftest@live@sanitycheck.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-elk-e7500/igt@i915_selftest@live@sanitycheck.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-elk-e7500: [FAIL][35] ([i915#53]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-elk-e7500/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-elk-e7500/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a:
- fi-bsw-kefka: [FAIL][37] ([i915#53]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bsw-kefka/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
- fi-ilk-650: [FAIL][39] ([i915#53]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-ilk-650/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-ilk-650/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
#### Warnings ####
* igt@gem_exec_gttfill@basic:
- fi-pnv-d510: [FAIL][41] ([i915#3472]) -> [FAIL][42] ([i915#3457] / [i915#3472])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
* igt@i915_selftest@live@execlists:
- fi-cfl-8109u: [INCOMPLETE][43] ([i915#3462]) -> [DMESG-FAIL][44] ([i915#3462])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-cfl-8109u/igt@i915_selftest@live@execlists.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-cfl-8109u/igt@i915_selftest@live@execlists.html
- fi-bsw-nick: [DMESG-FAIL][45] -> [INCOMPLETE][46] ([i915#2782] / [i915#2940])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bsw-nick/igt@i915_selftest@live@execlists.html
- fi-icl-u2: [DMESG-FAIL][47] ([i915#3462]) -> [INCOMPLETE][48] ([i915#2782] / [i915#3462])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-icl-u2/igt@i915_selftest@live@execlists.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-icl-u2/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@mman:
- fi-bwr-2160: [DMESG-FAIL][49] ([i915#3457]) -> [DMESG-WARN][50] ([i915#3457])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bwr-2160/igt@i915_selftest@live@mman.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bwr-2160/igt@i915_selftest@live@mman.html
* igt@runner@aborted:
- fi-cfl-8109u: [FAIL][51] ([i915#3363]) -> [FAIL][52] ([i915#2426] / [i915#3363])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-cfl-8109u/igt@runner@aborted.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-cfl-8109u/igt@runner@aborted.html
- fi-icl-u2: [FAIL][53] ([i915#2426] / [i915#2782] / [i915#3363]) -> [FAIL][54] ([i915#2782] / [i915#3363])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-icl-u2/igt@runner@aborted.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-icl-u2/igt@runner@aborted.html
- fi-kbl-r: [FAIL][55] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][56] ([i915#1436] / [i915#3363])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-kbl-r/igt@runner@aborted.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-kbl-r/igt@runner@aborted.html
- fi-bdw-5557u: [FAIL][57] ([i915#3462]) -> [FAIL][58] ([i915#1602] / [i915#2029])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bdw-5557u/igt@runner@aborted.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-bdw-5557u/igt@runner@aborted.html
- fi-kbl-guc: [FAIL][59] ([i915#1436] / [i915#3363]) -> [FAIL][60] ([i915#1436] / [i915#2426] / [i915#3363])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-kbl-guc/igt@runner@aborted.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-kbl-guc/igt@runner@aborted.html
- fi-cml-u2: [FAIL][61] ([i915#2082] / [i915#2426] / [i915#3363]) -> [FAIL][62] ([i915#3363])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-cml-u2/igt@runner@aborted.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-cml-u2/igt@runner@aborted.html
- fi-kbl-7567u: [FAIL][63] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][64] ([i915#1436] / [i915#3363])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-kbl-7567u/igt@runner@aborted.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/fi-kbl-7567u/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1372]: https://gitlab.freedesktop.org/drm/intel/issues/1372
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
[i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
[i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
[i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3177]: https://gitlab.freedesktop.org/drm/intel/issues/3177
[i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
[i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
[i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
[i915#3457]: https://gitlab.freedesktop.org/drm/intel/issues/3457
[i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
[i915#3468]: https://gitlab.freedesktop.org/drm/intel/issues/3468
[i915#3472]: https://gitlab.freedesktop.org/drm/intel/issues/3472
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
Participating hosts (43 -> 39)
------------------------------
Additional (1): fi-rkl-11500t
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_10100 -> Patchwork_20147
CI-20190529: 20190529
CI_DRM_10100: cde0422496c99357e2fe968c091bf88ae0e96cd3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6087: a1772be7dede83a4f65e5986fd7083a9c8f89083 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_20147: 65a3d8889dfd0406f2c65d82de741345cb899fce @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
65a3d8889dfd drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau
428307dfe083 drm/dp: Extract i915's eDP backlight code into DRM helpers
a7cc151a9942 drm/i915/dpcd_bl: Print return codes for VESA backlight failures
131869b89b71 drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT
48f8c1dcc3bd drm/i915/dpcd_bl: Move VESA backlight enabling code closer together
221bebf6b8c3 drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight
59188c6d0d55 drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit
2f6dd64b21d7 drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly
634883ae67b3 drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/index.html
[-- Attachment #1.2: Type: text/html, Size: 18861 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev10)
2021-05-14 18:14 ` Lyude Paul
` (20 preceding siblings ...)
(?)
@ 2021-05-19 23:29 ` Patchwork
-1 siblings, 0 replies; 62+ messages in thread
From: Patchwork @ 2021-05-19 23:29 UTC (permalink / raw)
To: Lyude Paul; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30300 bytes --]
== Series Details ==
Series: drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev10)
URL : https://patchwork.freedesktop.org/series/84754/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10100_full -> Patchwork_20147_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_20147_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_20147_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_20147_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_prime@basic-crc@second-to-first:
- shard-glk: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk4/igt@kms_prime@basic-crc@second-to-first.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes}:
- shard-glk: [PASS][2] -> [FAIL][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk1/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
### Piglit changes ###
#### Possible regressions ####
* spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-explicit-bvec4-u64vec4 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [INCOMPLETE][4] +7 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/pig-icl-1065g7/spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-explicit-bvec4-u64vec4.html
* spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-explicit-dvec2-i64vec2 (NEW):
- {pig-icl-1065g7}: NOTRUN -> [CRASH][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/pig-icl-1065g7/spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-explicit-dvec2-i64vec2.html
New tests
---------
New tests have been introduced between CI_DRM_10100_full and Patchwork_20147_full:
### New Piglit tests (9) ###
* spec@arb_gpu_shader_int64@execution@conversion@frag-conversion-implicit-ivec3-i64vec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader_int64@execution@conversion@frag-conversion-implicit-uint-uint64_t:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader_int64@execution@conversion@geom-conversion-explicit-bvec4-u64vec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader_int64@execution@conversion@geom-conversion-explicit-u64vec4-bvec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-explicit-bvec2-i64vec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-explicit-bvec4-u64vec4:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-explicit-dvec2-i64vec2:
- Statuses : 1 crash(s)
- Exec time: [0.55] s
* spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-explicit-dvec2-u64vec2:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
* spec@arb_gpu_shader_int64@execution@conversion@vert-conversion-explicit-u64vec3-ivec3:
- Statuses : 1 incomplete(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_20147_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-noreloc-purge-cache-random:
- shard-glk: NOTRUN -> [DMESG-FAIL][6] ([i915#3457]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk4/igt@api_intel_bb@blit-noreloc-purge-cache-random.html
* igt@drm_read@fault-buffer:
- shard-skl: NOTRUN -> [DMESG-WARN][7] ([i915#3457])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@drm_read@fault-buffer.html
* igt@gem_ctx_engines@invalid-engines:
- shard-snb: NOTRUN -> [INCOMPLETE][8] ([i915#3457] / [i915#3468])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-snb7/igt@gem_ctx_engines@invalid-engines.html
* igt@gem_ctx_persistence@engines-persistence@rcs0:
- shard-apl: [PASS][9] -> [FAIL][10] ([i915#3457]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-apl7/igt@gem_ctx_persistence@engines-persistence@rcs0.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@gem_ctx_persistence@engines-persistence@rcs0.html
* igt@gem_ctx_persistence@legacy-engines-persistence@vebox:
- shard-apl: NOTRUN -> [FAIL][11] ([i915#3457]) +9 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@gem_ctx_persistence@legacy-engines-persistence@vebox.html
* igt@gem_ctx_persistence@smoketest:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#1099]) +4 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-snb2/igt@gem_ctx_persistence@smoketest.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][13] -> [TIMEOUT][14] ([i915#2369] / [i915#3063] / [i915#3457])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-tglb3/igt@gem_eio@unwedge-stress.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-tglb5/igt@gem_eio@unwedge-stress.html
- shard-snb: NOTRUN -> [FAIL][15] ([i915#3354] / [i915#3457])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-snb7/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2842] / [i915#3457])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-kbl: [PASS][18] -> [FAIL][19] ([i915#2842] / [i915#3457]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl7/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-iclb: NOTRUN -> [FAIL][20] ([i915#2842] / [i915#3457])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-tglb: [PASS][21] -> [FAIL][22] ([i915#2842] / [i915#3457])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-tglb6/igt@gem_exec_fair@basic-pace@vcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-tglb2/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@gem_exec_fence@parallel@vcs0:
- shard-glk: [PASS][23] -> [FAIL][24] ([i915#3457]) +25 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk3/igt@gem_exec_fence@parallel@vcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk2/igt@gem_exec_fence@parallel@vcs0.html
* igt@gem_exec_gttfill@basic:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#3457] / [i915#3491])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk1/igt@gem_exec_gttfill@basic.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk1/igt@gem_exec_gttfill@basic.html
* igt@gem_exec_reloc@basic-wide-active@rcs0:
- shard-snb: NOTRUN -> [FAIL][27] ([i915#2389] / [i915#3457]) +2 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-snb7/igt@gem_exec_reloc@basic-wide-active@rcs0.html
* igt@gem_exec_whisper@basic-fds-priority:
- shard-glk: [PASS][28] -> [DMESG-WARN][29] ([i915#118] / [i915#95]) +3 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk3/igt@gem_exec_whisper@basic-fds-priority.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk2/igt@gem_exec_whisper@basic-fds-priority.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-snb: NOTRUN -> [INCOMPLETE][30] ([i915#3468]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-snb5/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@fault-concurrent-x:
- shard-kbl: NOTRUN -> [INCOMPLETE][31] ([i915#3468])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl3/igt@gem_mmap_gtt@fault-concurrent-x.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-glk: NOTRUN -> [FAIL][32] ([i915#3476])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk4/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
- shard-skl: NOTRUN -> [INCOMPLETE][33] ([i915#3468])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs:
- shard-apl: NOTRUN -> [INCOMPLETE][34] ([i915#3468]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@gem_render_copy@yf-tiled-ccs-to-y-tiled-ccs.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- shard-iclb: NOTRUN -> [SKIP][35] ([i915#768]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@gem_spin_batch@legacy@default:
- shard-apl: NOTRUN -> [FAIL][36] ([i915#2898] / [i915#3457]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@gem_spin_batch@legacy@default.html
* igt@gem_userptr_blits@input-checking:
- shard-apl: NOTRUN -> [DMESG-WARN][37] ([i915#3002])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@gem_userptr_blits@input-checking.html
* igt@gen3_mixed_blits:
- shard-iclb: NOTRUN -> [SKIP][38] ([fdo#109289])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@gen3_mixed_blits.html
* igt@i915_hangman@engine-hang@vcs0:
- shard-apl: NOTRUN -> [DMESG-WARN][39] ([i915#3457]) +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@i915_hangman@engine-hang@vcs0.html
* igt@i915_hangman@engine-hang@vecs0:
- shard-apl: NOTRUN -> [DMESG-FAIL][40] ([i915#3457]) +1 similar issue
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@i915_hangman@engine-hang@vecs0.html
* igt@i915_pm_dc@dc6-psr:
- shard-skl: NOTRUN -> [FAIL][41] ([i915#454])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
- shard-kbl: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#1937])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl3/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html
* igt@i915_pm_rpm@cursor-dpms:
- shard-apl: [PASS][43] -> [DMESG-WARN][44] ([i915#3457])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-apl7/igt@i915_pm_rpm@cursor-dpms.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@i915_pm_rpm@cursor-dpms.html
* igt@i915_pm_rpm@gem-mmap-type@uc:
- shard-skl: NOTRUN -> [DMESG-WARN][45] ([i915#1982] / [i915#3475])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@i915_pm_rpm@gem-mmap-type@uc.html
- shard-tglb: [PASS][46] -> [DMESG-WARN][47] ([i915#2411])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-tglb5/igt@i915_pm_rpm@gem-mmap-type@uc.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-tglb1/igt@i915_pm_rpm@gem-mmap-type@uc.html
- shard-kbl: [PASS][48] -> [DMESG-WARN][49] ([i915#3475])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl7/igt@i915_pm_rpm@gem-mmap-type@uc.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl4/igt@i915_pm_rpm@gem-mmap-type@uc.html
* igt@i915_pm_rpm@gem-mmap-type@wc:
- shard-tglb: [PASS][50] -> [DMESG-WARN][51] ([i915#2411] / [i915#3457])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-tglb5/igt@i915_pm_rpm@gem-mmap-type@wc.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-tglb1/igt@i915_pm_rpm@gem-mmap-type@wc.html
* igt@i915_pm_rps@waitboost:
- shard-snb: NOTRUN -> [DMESG-WARN][52] ([i915#3457]) +3 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-snb7/igt@i915_pm_rps@waitboost.html
* igt@i915_pm_sseu@full-enable:
- shard-glk: NOTRUN -> [DMESG-WARN][53] ([i915#3457])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk4/igt@i915_pm_sseu@full-enable.html
* igt@i915_selftest@live@execlists:
- shard-kbl: NOTRUN -> [DMESG-FAIL][54] ([i915#3462])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl4/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@hangcheck:
- shard-snb: NOTRUN -> [INCOMPLETE][55] ([i915#2782])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-snb7/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@mman:
- shard-kbl: NOTRUN -> [DMESG-WARN][56] ([i915#3457])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl4/igt@i915_selftest@live@mman.html
* igt@kms_big_fb@linear-32bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][57] ([fdo#110725] / [fdo#111614])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_big_fb@linear-32bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][58] ([fdo#110723])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_big_joiner@basic:
- shard-apl: NOTRUN -> [SKIP][59] ([fdo#109271] / [i915#2705])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo:
- shard-skl: NOTRUN -> [SKIP][60] ([fdo#109271] / [fdo#111304]) +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@kms_ccs@pipe-c-ccs-on-another-bo.html
* igt@kms_chamelium@hdmi-edid-change-during-suspend:
- shard-apl: NOTRUN -> [SKIP][61] ([fdo#109271] / [fdo#111827]) +13 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@kms_chamelium@hdmi-edid-change-during-suspend.html
* igt@kms_color@pipe-a-degamma:
- shard-glk: [PASS][62] -> [FAIL][63] ([fdo#108145] / [i915#71])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk8/igt@kms_color@pipe-a-degamma.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk8/igt@kms_color@pipe-a-degamma.html
* igt@kms_color@pipe-b-legacy-gamma:
- shard-glk: [PASS][64] -> [FAIL][65] ([i915#71])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk5/igt@kms_color@pipe-b-legacy-gamma.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk5/igt@kms_color@pipe-b-legacy-gamma.html
* igt@kms_color@pipe-c-degamma:
- shard-iclb: NOTRUN -> [FAIL][66] ([i915#1149])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_color@pipe-c-degamma.html
* igt@kms_color_chamelium@pipe-a-ctm-limited-range:
- shard-glk: NOTRUN -> [SKIP][67] ([fdo#109271] / [fdo#111827]) +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk4/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-b-ctm-limited-range:
- shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [fdo#111827]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl3/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html
* igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109284] / [fdo#111827]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html
* igt@kms_color_chamelium@pipe-c-ctm-red-to-blue:
- shard-snb: NOTRUN -> [SKIP][70] ([fdo#109271] / [fdo#111827]) +15 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-snb5/igt@kms_color_chamelium@pipe-c-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-c-degamma:
- shard-skl: NOTRUN -> [SKIP][71] ([fdo#109271] / [fdo#111827]) +10 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@kms_color_chamelium@pipe-c-degamma.html
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> [TIMEOUT][72] ([i915#1319])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
- shard-iclb: [PASS][73] -> [FAIL][74] ([i915#3457])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
- shard-kbl: [PASS][75] -> [FAIL][76] ([i915#3444] / [i915#3457]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
* igt@kms_cursor_crc@pipe-a-cursor-dpms:
- shard-skl: NOTRUN -> [FAIL][77] ([i915#3444] / [i915#3457]) +9 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-dpms.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen:
- shard-glk: NOTRUN -> [FAIL][78] ([i915#3444] / [i915#3457]) +2 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk4/igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
- shard-apl: [PASS][79] -> [FAIL][80] ([i915#3444] / [i915#3457])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen:
- shard-tglb: [PASS][81] -> [FAIL][82] ([i915#2124] / [i915#3457]) +6 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-tglb8/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-tglb7/igt@kms_cursor_crc@pipe-b-cursor-128x42-offscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen:
- shard-snb: NOTRUN -> [FAIL][83] ([i915#3457]) +4 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-snb2/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
- shard-iclb: NOTRUN -> [FAIL][84] ([i915#3457]) +2 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
- shard-snb: NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#3457]) +34 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-snb7/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
- shard-skl: NOTRUN -> [SKIP][86] ([fdo#109271] / [i915#3457]) +19 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen:
- shard-glk: [PASS][87] -> [FAIL][88] ([i915#3444] / [i915#3457]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk4/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk4/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
* igt@kms_cursor_crc@pipe-b-cursor-64x64-onscreen:
- shard-apl: NOTRUN -> [FAIL][89] ([i915#3444] / [i915#3457]) +2 similar issues
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-64x64-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-sliding:
- shard-kbl: NOTRUN -> [FAIL][90] ([i915#3444] / [i915#3457]) +4 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-128x128-sliding.html
* igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
- shard-kbl: NOTRUN -> [SKIP][91] ([fdo#109271] / [i915#3457]) +7 similar issues
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl3/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-512x512-random:
- shard-apl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#3457]) +11 similar issues
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@kms_cursor_crc@pipe-d-cursor-512x512-random.html
* igt@kms_cursor_crc@pipe-d-cursor-64x21-onscreen:
- shard-iclb: NOTRUN -> [SKIP][93] ([fdo#109278] / [i915#3457]) +2 similar issues
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_cursor_crc@pipe-d-cursor-64x21-onscreen.html
* igt@kms_cursor_crc@pipe-d-cursor-dpms:
- shard-glk: NOTRUN -> [SKIP][94] ([fdo#109271] / [i915#3457]) +5 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk4/igt@kms_cursor_crc@pipe-d-cursor-dpms.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109274] / [fdo#109278]) +2 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@pipe-d-torture-bo:
- shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271] / [i915#533]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@kms_cursor_legacy@pipe-d-torture-bo.html
* igt@kms_cursor_legacy@pipe-d-torture-move:
- shard-skl: NOTRUN -> [SKIP][97] ([fdo#109271]) +93 similar issues
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@kms_cursor_legacy@pipe-d-torture-move.html
* igt@kms_flip@2x-flip-vs-rmfb:
- shard-iclb: NOTRUN -> [SKIP][98] ([fdo#109274]) +1 similar issue
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_flip@2x-flip-vs-rmfb.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile:
- shard-apl: NOTRUN -> [SKIP][99] ([fdo#109271] / [i915#2642])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
- shard-iclb: NOTRUN -> [SKIP][100] ([fdo#109280]) +7 similar issues
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-kbl: [PASS][101] -> [DMESG-WARN][102] ([i915#180]) +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl1/igt@kms_hdr@bpc-switch-suspend.html
- shard-skl: NOTRUN -> [FAIL][103] ([i915#1188])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#533])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl3/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: NOTRUN -> [FAIL][105] ([fdo#108145] / [i915#265])
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
- shard-glk: NOTRUN -> [FAIL][106] ([fdo#108145] / [i915#265])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk4/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][107] ([i915#265])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-apl: [PASS][108] -> [FAIL][109] ([fdo#108145] / [i915#265])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
- shard-kbl: NOTRUN -> [FAIL][110] ([fdo#108145] / [i915#265])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][111] ([i915#265])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-apl6/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: NOTRUN -> [FAIL][112] ([fdo#108145] / [i915#265]) +2 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-d-alpha-7efc:
- shard-iclb: NOTRUN -> [SKIP][113] ([fdo#109278]) +1 similar issue
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_plane_alpha_blend@pipe-d-alpha-7efc.html
* igt@kms_plane_cursor@pipe-a-primary-size-128:
- shard-glk: NOTRUN -> [FAIL][114] ([i915#2657])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk4/igt@kms_plane_cursor@pipe-a-primary-size-128.html
* igt@kms_plane_cursor@pipe-a-primary-size-256:
- shard-iclb: NOTRUN -> [FAIL][115] ([i915#2657])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_plane_cursor@pipe-a-primary-size-256.html
* igt@kms_plane_cursor@pipe-a-primary-size-64:
- shard-skl: NOTRUN -> [FAIL][116] ([i915#2657])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@kms_plane_cursor@pipe-a-primary-size-64.html
* igt@kms_plane_cursor@pipe-a-viewport-size-128:
- shard-snb: NOTRUN -> [FAIL][117] ([i915#2657]) +1 similar issue
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-snb5/igt@kms_plane_cursor@pipe-a-viewport-size-128.html
* igt@kms_plane_cursor@pipe-b-viewport-size-256:
- shard-kbl: NOTRUN -> [FAIL][118] ([i915#2657])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-kbl3/igt@kms_plane_cursor@pipe-b-viewport-size-256.html
* igt@kms_plane_cursor@pipe-c-primary-size-64:
- shard-iclb: NOTRUN -> [FAIL][119] ([i915#2657] / [i915#3457])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-iclb3/igt@kms_plane_cursor@pipe-c-primary-size-64.html
* igt@kms_plane_cursor@pipe-c-viewport-size-128:
- shard-skl: NOTRUN -> [FAIL][120] ([i915#2657] / [i915#3457]) +2 similar issues
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-skl3/igt@kms_plane_cursor@pipe-c-viewport-size-128.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
- shard-glk: [PASS][121] -> [FAIL][122] ([i915#1779])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk5/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/shard-glk6/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-ar
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20147/index.html
[-- Attachment #1.2: Type: text/html, Size: 33929 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 8/9] drm/dp: Extract i915's eDP backlight code into DRM helpers
2021-05-14 18:15 ` [Nouveau] " Lyude Paul
(?)
(?)
@ 2021-05-21 20:02 ` Rodrigo Vivi
-1 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-05-21 20:02 UTC (permalink / raw)
To: Lyude Paul
Cc: intel-gfx, dri-devel, nouveau, David Airlie, Jani Nikula,
Uma Shankar, Anshuman Gupta, Dave Airlie, Thomas Zimmermann,
greg.depoire, Lucas De Marchi, Gwan-gyeong Mun, Sean Paul,
Rajeev Nandan, open list
On Fri, May 14, 2021 at 02:15:02PM -0400, Lyude Paul wrote:
> Since we're about to implement eDP backlight support in nouveau using the
> standard protocol from VESA, we might as well just take the code that's
> already written for this and move it into a set of shared DRM helpers.
>
> Note that these helpers are intended to handle DPCD related backlight
> control bits such as setting the brightness level over AUX, probing the
> backlight's TCON, enabling/disabling the backlight over AUX if supported,
> etc. Any PWM-related portions of backlight control are explicitly left up
> to the driver, as these will vary from platform to platform.
>
> The only exception to this is the calculation of the PWM frequency
> pre-divider value. This is because the only platform-specific information
> required for this is the PWM frequency of the panel, which the driver is
> expected to provide if available. The actual algorithm for calculating this
> value is standard and is defined in the eDP specification from VESA.
>
> Note that these helpers do not yet implement the full range of features
> the VESA backlight interface provides, and only provide the following
> functionality (all of which was already present in i915's DPCD backlight
> support):
>
> * Basic control of brightness levels
> * Basic probing of backlight capabilities
> * Helpers for enabling and disabling the backlight
>
> v3:
> * Split out changes to i915's backlight code to separate patches to make it
> easier to review
> v4:
> * Style/spelling changes from Thomas Zimmermann
> v5:
> * Start using new drm_dbg_*() functions
This version was indeed much easier to review. Thanks for addressing all the
comments.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Dave Airlie <airlied@gmail.com>
> Cc: greg.depoire@gmail.com
> ---
> drivers/gpu/drm/drm_dp_helper.c | 347 ++++++++++++++++++
> .../drm/i915/display/intel_display_types.h | 5 +-
> .../drm/i915/display/intel_dp_aux_backlight.c | 285 ++------------
> include/drm/drm_dp_helper.h | 48 +++
> 4 files changed, 427 insertions(+), 258 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 55b53df6ce34..24bbc710c825 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -3115,3 +3115,350 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
> return 0;
> }
> EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
> +
> +/**
> + * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + * @level: The brightness level to set
> + *
> + * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
> + * already have been enabled by the driver by calling drm_edp_backlight_enable().
> + *
> + * Returns: %0 on success, negative error code on failure
> + */
> +int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level)
> +{
> + int ret;
> + u8 buf[2] = { 0 };
> +
> + if (bl->lsb_reg_used) {
> + buf[0] = (level & 0xff00) >> 8;
> + buf[1] = (level & 0x00ff);
> + } else {
> + buf[0] = level;
> + }
> +
> + ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
> + if (ret != sizeof(buf)) {
> + drm_err(aux->drm_dev,
> + "%s: Failed to write aux backlight level: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_set_level);
> +
> +static int
> +drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + bool enable)
> +{
> + int ret;
> + u8 buf;
> +
> + /* The panel uses something other then DPCD for enabling its backlight */
> + if (!bl->aux_enable)
> + return 0;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
> + if (ret != 1) {
> + drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> + if (enable)
> + buf |= DP_EDP_BACKLIGHT_ENABLE;
> + else
> + buf &= ~DP_EDP_BACKLIGHT_ENABLE;
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
> + if (ret != 1) {
> + drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + * @level: The initial backlight level to set via AUX, if there is one
> + *
> + * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
> + * restoring any important backlight state such as the given backlight level, the brightness byte
> + * count, backlight frequency, etc.
> + *
> + * Note that certain panels, while supporting brightness level controls over DPCD, may not support
> + * having their backlights enabled via the standard %DP_EDP_DISPLAY_CONTROL_REGISTER. On such panels
> + * &drm_edp_backlight_info.aux_enable will be set to %false, this function will skip the step of
> + * programming the %DP_EDP_DISPLAY_CONTROL_REGISTER, and the driver must perform the required
> + * implementation specific step for enabling the backlight after calling this function.
> + *
> + * Returns: %0 on success, negative error code on failure.
> + */
> +int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + const u16 level)
> +{
> + int ret;
> + u8 dpcd_buf, new_dpcd_buf;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Failed to read backlight mode: %d\n", aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + new_dpcd_buf = dpcd_buf;
> +
> + if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> + new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
> + if (ret != 1)
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
> + aux->name, ret);
> + }
> +
> + if (bl->pwm_freq_pre_divider) {
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
> + if (ret != 1)
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Failed to write aux backlight frequency: %d\n",
> + aux->name, ret);
> + else
> + new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> + }
> +
> + if (new_dpcd_buf != dpcd_buf) {
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> + }
> +
> + ret = drm_edp_backlight_set_level(aux, bl, level);
> + if (ret < 0)
> + return ret;
> + ret = drm_edp_backlight_set_enable(aux, bl, true);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_enable);
> +
> +/**
> + * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + *
> + * This function handles disabling DPCD backlight controls on a panel over AUX. Note that some
> + * panels have backlights that are enabled/disabled by other means, despite having their brightness
> + * values controlled through DPCD. On such panels &drm_edp_backlight_info.aux_enable will be set to
> + * %false, this function will become a no-op (and we will skip updating
> + * %DP_EDP_DISPLAY_CONTROL_REGISTER), and the driver must take care to perform it's own
> + * implementation specific step for disabling the backlight.
> + *
> + * Returns: %0 on success or no-op, negative error code on failure.
> + */
> +int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
> +{
> + int ret;
> +
> + ret = drm_edp_backlight_set_enable(aux, bl, false);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_disable);
> +
> +static inline int
> +drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
> +{
> + int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
> + int ret;
> + u8 pn, pn_min, pn_max;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
> + aux->name, ret);
> + return -ENODEV;
> + }
> +
> + pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> + bl->max = (1 << pn) - 1;
> + if (!driver_pwm_freq_hz)
> + return 0;
> +
> + /*
> + * Set PWM Frequency divider to match desired frequency provided by the driver.
> + * The PWM Frequency is calculated as 27Mhz / (F x P).
> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> + */
> +
> + /* Find desired value of (F x P)
> + * Note that, if F x P is out of supported range, the maximum value or minimum value will
> + * applied automatically. So no need to check that.
> + */
> + fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
> +
> + /* Use highest possible value of Pn for more granularity of brightness adjustment while
> + * satifying the conditions below.
> + * - Pn is in the range of Pn_min and Pn_max
> + * - F is in the range of 1 and 255
> + * - FxP is within 25% of desired value.
> + * Note: 25% is arbitrary value and may need some tweak.
> + */
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> + pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> +
> + /* Ensure frequency is within 25% of desired value */
> + fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> + fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> + if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Driver defined backlight frequency (%d) out of range\n",
> + aux->name, driver_pwm_freq_hz);
> + return 0;
> + }
> +
> + for (pn = pn_max; pn >= pn_min; pn--) {
> + f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> + fxp_actual = f << pn;
> + if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
> + break;
> + }
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + bl->pwmgen_bit_count = pn;
> + bl->max = (1 << pn) - 1;
> +
> + if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
> + bl->pwm_freq_pre_divider = f;
> + drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
> + aux->name, driver_pwm_freq_hz);
> + }
> +
> + return 0;
> +}
> +
> +static inline int
> +drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u8 *current_mode)
> +{
> + int ret;
> + u8 buf[2];
> + u8 mode_reg;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
> + if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + int size = 1 + bl->lsb_reg_used;
> +
> + ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
> + if (ret != size) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + if (bl->lsb_reg_used)
> + return (buf[0] << 8) | buf[1];
> + else
> + return buf[0];
> + }
> +
> + /*
> + * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
> + * the driver should assume max brightness
> + */
> + return bl->max;
> +}
> +
> +/**
> + * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
> + * interface.
> + * @aux: The DP aux device to use for probing
> + * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
> + * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
> + * @edp_dpcd: A cached copy of the eDP DPCD
> + * @current_level: Where to store the probed brightness level
> + * @current_mode: Where to store the currently set backlight control mode
> + *
> + * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
> + * along with also probing the current and maximum supported brightness levels.
> + *
> + * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
> + * default frequency from the panel is used.
> + *
> + * Returns: %0 on success, negative error code on failure.
> + */
> +int
> +drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
> + u16 *current_level, u8 *current_mode)
> +{
> + int ret;
> +
> + if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
> + bl->aux_enable = true;
> + if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> + bl->lsb_reg_used = true;
> +
> + ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
> + if (ret < 0)
> + return ret;
> +
> + ret = drm_edp_backlight_probe_level(aux, bl, current_mode);
> + if (ret < 0)
> + return ret;
> + *current_level = ret;
> +
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Found backlight level=%d/%d pwm_freq_pre_divider=%d mode=%x\n",
> + aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, *current_mode);
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Backlight caps: pwmgen_bit_count=%d lsb_reg_used=%d aux_enable=%d\n",
> + aux->name, bl->pwmgen_bit_count, bl->lsb_reg_used, bl->aux_enable);
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_init);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d4a57bce71b1..8696b39da2fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -310,10 +310,7 @@ struct intel_panel {
> /* DPCD backlight */
> union {
> struct {
> - u8 pwmgen_bit_count;
> - u8 pwm_freq_pre_divider;
> - bool lsb_reg_used;
> - bool aux_enable;
> + struct drm_edp_backlight_info info;
> } vesa;
> struct {
> bool sdr_uses_aux;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 95f2df631052..6ac568617ef3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -270,114 +270,19 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
> }
>
> /* VESA backlight callbacks */
> -static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
> -{
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 mode_reg;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
> - return false;
> - }
> -
> - return (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
> - DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> -}
> -
> -/*
> - * Read the current backlight value from DPCD register(s) based
> - * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
> - */
> static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, enum pipe unused)
> {
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 read_val[2] = { 0x0 };
> - u16 level = 0;
> -
> - /*
> - * If we're not in DPCD control mode yet, the programmed brightness
> - * value is meaningless and we should assume max brightness
> - */
> - if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
> - return connector->panel.backlight.max;
> -
> - ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
> - sizeof(read_val));
> - if (ret != sizeof(read_val)) {
> - drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
> - return 0;
> - }
> -
> - if (connector->panel.backlight.edp.vesa.lsb_reg_used)
> - level = (read_val[0] << 8 | read_val[1]);
> - else
> - level = read_val[0];
> -
> - return level;
> + return connector->panel.backlight.level;
> }
>
> -/*
> - * Sends the current backlight level over the aux channel, checking if its using
> - * 8-bit or 16 bit value (MSB and LSB)
> - */
> static void
> -intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
> - u32 level)
> +intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, u32 level)
> {
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 vals[2] = { 0x0 };
> -
> - /* Write the MSB and/or LSB */
> - if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
> - vals[0] = (level & 0xFF00) >> 8;
> - vals[1] = (level & 0xFF);
> - } else {
> - vals[0] = level;
> - }
> -
> - ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
> - sizeof(vals));
> - if (ret != sizeof(vals)) {
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
> - return;
> - }
> -}
> -
> -static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
> -{
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 reg_val = 0;
> -
> - /* Early return when display use other mechanism to enable backlight. */
> - if (!connector->panel.backlight.edp.vesa.aux_enable)
> - return;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
> - return;
> - }
> -
> - if (enable)
> - reg_val |= DP_EDP_BACKLIGHT_ENABLE;
> - else
> - reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
> + struct intel_panel *panel = &connector->panel;
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
> - enabledisable(enable), ret);
> - }
> + drm_edp_backlight_set_level(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
> }
>
> static void
> @@ -385,170 +290,46 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state, u32 level)
> {
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> struct intel_panel *panel = &connector->panel;
> - int ret;
> - u8 dpcd_buf, new_dpcd_buf;
> - u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
> - return;
> - }
> -
> - new_dpcd_buf = dpcd_buf;
> -
> - if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> - new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> - new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> -
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
> - if (ret != 1)
> - drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
> - }
> -
> - if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
> - panel->backlight.edp.vesa.pwm_freq_pre_divider);
> - if (ret == 1)
> - new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> - else
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
> - ret);
> - }
> -
> - if (new_dpcd_buf != dpcd_buf) {
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
> - new_dpcd_buf);
> - if (ret != 1)
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
> - }
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - intel_dp_aux_vesa_set_backlight(conn_state, level);
> - set_vesa_backlight_enable(connector, true);
> + drm_edp_backlight_enable(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
> }
>
> static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
> u32 level)
> {
> - set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
> -}
> -
> -/*
> - * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
> - * The PWM Frequency is calculated as 27Mhz / (F x P).
> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> - */
> -static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
> -{
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> + struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
> struct intel_panel *panel = &connector->panel;
> - u32 max_backlight = 0;
> - int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
> - u8 pn, pn_min, pn_max;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
> - return 0;
> - }
> -
> - pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> - max_backlight = (1 << pn) - 1;
> -
> - /* Find desired value of (F x P)
> - * Note that, if F x P is out of supported range, the maximum value or
> - * minimum value will applied automatically. So no need to check that.
> - */
> - freq = i915->vbt.backlight.pwm_freq_hz;
> - drm_dbg_kms(&i915->drm, "VBT defined backlight frequency %u Hz\n",
> - freq);
> - if (!freq) {
> - drm_dbg_kms(&i915->drm,
> - "Use panel default backlight frequency\n");
> - return max_backlight;
> - }
> -
> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
> -
> - /* Use highest possible value of Pn for more granularity of brightness
> - * adjustment while satifying the conditions below.
> - * - Pn is in the range of Pn_min and Pn_max
> - * - F is in the range of 1 and 255
> - * - FxP is within 25% of desired value.
> - * Note: 25% is arbitrary value and may need some tweak.
> - */
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
> - return max_backlight;
> - }
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
> - return max_backlight;
> - }
> - pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> - pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> -
> - /* Ensure frequency is within 25% of desired value */
> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> -
> - if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> - drm_dbg_kms(&i915->drm,
> - "VBT defined backlight frequency out of range\n");
> - return max_backlight;
> - }
> -
> - for (pn = pn_max; pn >= pn_min; pn--) {
> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> - fxp_actual = f << pn;
> - if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
> - break;
> - }
> -
> - drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
> - return max_backlight;
> - }
> -
> - panel->backlight.edp.vesa.pwmgen_bit_count = pn;
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> - panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
> -
> - max_backlight = (1 << pn) - 1;
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - return max_backlight;
> + drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info);
> }
>
> -static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
> - enum pipe pipe)
> +static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe)
> {
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct intel_panel *panel = &connector->panel;
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + u16 current_level;
> + u8 current_mode;
> + int ret;
>
> - if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
> - panel->backlight.edp.vesa.aux_enable = true;
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> - panel->backlight.edp.vesa.lsb_reg_used = true;
> -
> - panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
> - if (!panel->backlight.max)
> - return -ENODEV;
> + ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,
> + i915->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
> + ¤t_level, ¤t_mode);
> + if (ret < 0)
> + return ret;
>
> + panel->backlight.max = panel->backlight.edp.vesa.info.max;
> panel->backlight.min = 0;
> - panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector, pipe);
> - panel->backlight.enabled = intel_dp_aux_vesa_backlight_dpcd_mode(connector) &&
> - panel->backlight.level != 0;
> + if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + panel->backlight.level = current_level;
> + panel->backlight.enabled = panel->backlight.level != 0;
> + } else {
> + panel->backlight.level = panel->backlight.max;
> + panel->backlight.enabled = false;
> + }
>
> return 0;
> }
> @@ -559,16 +340,12 @@ intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector)
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> - /* Check the eDP Display control capabilities registers to determine if
> - * the panel can support backlight control over the aux channel.
> - *
> - * TODO: We currently only support AUX only backlight configurations, not backlights which
> + /* TODO: We currently only support AUX only backlight configurations, not backlights which
> * require a mix of PWM and AUX controls to work. In the mean time, these machines typically
> * work just fine using normal PWM controls anyway.
> */
> - if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
> - (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> - (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
> + if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> + drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
> drm_dbg_kms(&i915->drm, "AUX Backlight Control Supported!\n");
> return true;
> }
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 06681bf46d81..0bd6396648b4 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1801,6 +1801,24 @@ drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> DP_MSA_TIMING_PAR_IGNORED;
> }
>
> +/**
> + * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
> + * @edp_dpcd: The DPCD to check
> + *
> + * Note that currently this function will return %false for panels which support various DPCD
> + * backlight features but which require the brightness be set through PWM, and don't support setting
> + * the brightness level via the DPCD. This is a TODO.
> + *
> + * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
> + * otherwise
> + */
> +static inline bool
> +drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
> +{
> + return (edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
> + (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP);
> +}
> +
> /*
> * DisplayPort AUX channel
> */
> @@ -2107,6 +2125,36 @@ drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
> return desc->quirks & BIT(quirk);
> }
>
> +/**
> + * struct drm_edp_backlight_info - Probed eDP backlight info struct
> + * @pwmgen_bit_count: The pwmgen bit count
> + * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
> + * @max: The maximum backlight level that may be set
> + * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
> + * @aux_enable: Does the panel support the AUX enable cap?
> + *
> + * This structure contains various data about an eDP backlight, which can be populated by using
> + * drm_edp_backlight_init().
> + */
> +struct drm_edp_backlight_info {
> + u8 pwmgen_bit_count;
> + u8 pwm_freq_pre_divider;
> + u16 max;
> +
> + bool lsb_reg_used : 1;
> + bool aux_enable : 1;
> +};
> +
> +int
> +drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
> + u16 *current_level, u8 *current_mode);
> +int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level);
> +int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level);
> +int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
> +
> #ifdef CONFIG_DRM_DP_CEC
> void drm_dp_cec_irq(struct drm_dp_aux *aux);
> void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Nouveau] [PATCH v6 8/9] drm/dp: Extract i915's eDP backlight code into DRM helpers
@ 2021-05-21 20:02 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-05-21 20:02 UTC (permalink / raw)
To: Lyude Paul
Cc: greg.depoire, Rajeev Nandan, David Airlie, nouveau, intel-gfx,
Lucas De Marchi, open list, dri-devel, Gwan-gyeong Mun,
Jani Nikula, Uma Shankar, Sean Paul, Anshuman Gupta, Dave Airlie
On Fri, May 14, 2021 at 02:15:02PM -0400, Lyude Paul wrote:
> Since we're about to implement eDP backlight support in nouveau using the
> standard protocol from VESA, we might as well just take the code that's
> already written for this and move it into a set of shared DRM helpers.
>
> Note that these helpers are intended to handle DPCD related backlight
> control bits such as setting the brightness level over AUX, probing the
> backlight's TCON, enabling/disabling the backlight over AUX if supported,
> etc. Any PWM-related portions of backlight control are explicitly left up
> to the driver, as these will vary from platform to platform.
>
> The only exception to this is the calculation of the PWM frequency
> pre-divider value. This is because the only platform-specific information
> required for this is the PWM frequency of the panel, which the driver is
> expected to provide if available. The actual algorithm for calculating this
> value is standard and is defined in the eDP specification from VESA.
>
> Note that these helpers do not yet implement the full range of features
> the VESA backlight interface provides, and only provide the following
> functionality (all of which was already present in i915's DPCD backlight
> support):
>
> * Basic control of brightness levels
> * Basic probing of backlight capabilities
> * Helpers for enabling and disabling the backlight
>
> v3:
> * Split out changes to i915's backlight code to separate patches to make it
> easier to review
> v4:
> * Style/spelling changes from Thomas Zimmermann
> v5:
> * Start using new drm_dbg_*() functions
This version was indeed much easier to review. Thanks for addressing all the
comments.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Dave Airlie <airlied@gmail.com>
> Cc: greg.depoire@gmail.com
> ---
> drivers/gpu/drm/drm_dp_helper.c | 347 ++++++++++++++++++
> .../drm/i915/display/intel_display_types.h | 5 +-
> .../drm/i915/display/intel_dp_aux_backlight.c | 285 ++------------
> include/drm/drm_dp_helper.h | 48 +++
> 4 files changed, 427 insertions(+), 258 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 55b53df6ce34..24bbc710c825 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -3115,3 +3115,350 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
> return 0;
> }
> EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
> +
> +/**
> + * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + * @level: The brightness level to set
> + *
> + * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
> + * already have been enabled by the driver by calling drm_edp_backlight_enable().
> + *
> + * Returns: %0 on success, negative error code on failure
> + */
> +int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level)
> +{
> + int ret;
> + u8 buf[2] = { 0 };
> +
> + if (bl->lsb_reg_used) {
> + buf[0] = (level & 0xff00) >> 8;
> + buf[1] = (level & 0x00ff);
> + } else {
> + buf[0] = level;
> + }
> +
> + ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
> + if (ret != sizeof(buf)) {
> + drm_err(aux->drm_dev,
> + "%s: Failed to write aux backlight level: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_set_level);
> +
> +static int
> +drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + bool enable)
> +{
> + int ret;
> + u8 buf;
> +
> + /* The panel uses something other then DPCD for enabling its backlight */
> + if (!bl->aux_enable)
> + return 0;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
> + if (ret != 1) {
> + drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> + if (enable)
> + buf |= DP_EDP_BACKLIGHT_ENABLE;
> + else
> + buf &= ~DP_EDP_BACKLIGHT_ENABLE;
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
> + if (ret != 1) {
> + drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + * @level: The initial backlight level to set via AUX, if there is one
> + *
> + * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
> + * restoring any important backlight state such as the given backlight level, the brightness byte
> + * count, backlight frequency, etc.
> + *
> + * Note that certain panels, while supporting brightness level controls over DPCD, may not support
> + * having their backlights enabled via the standard %DP_EDP_DISPLAY_CONTROL_REGISTER. On such panels
> + * &drm_edp_backlight_info.aux_enable will be set to %false, this function will skip the step of
> + * programming the %DP_EDP_DISPLAY_CONTROL_REGISTER, and the driver must perform the required
> + * implementation specific step for enabling the backlight after calling this function.
> + *
> + * Returns: %0 on success, negative error code on failure.
> + */
> +int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + const u16 level)
> +{
> + int ret;
> + u8 dpcd_buf, new_dpcd_buf;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Failed to read backlight mode: %d\n", aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + new_dpcd_buf = dpcd_buf;
> +
> + if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> + new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
> + if (ret != 1)
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
> + aux->name, ret);
> + }
> +
> + if (bl->pwm_freq_pre_divider) {
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
> + if (ret != 1)
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Failed to write aux backlight frequency: %d\n",
> + aux->name, ret);
> + else
> + new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> + }
> +
> + if (new_dpcd_buf != dpcd_buf) {
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> + }
> +
> + ret = drm_edp_backlight_set_level(aux, bl, level);
> + if (ret < 0)
> + return ret;
> + ret = drm_edp_backlight_set_enable(aux, bl, true);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_enable);
> +
> +/**
> + * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + *
> + * This function handles disabling DPCD backlight controls on a panel over AUX. Note that some
> + * panels have backlights that are enabled/disabled by other means, despite having their brightness
> + * values controlled through DPCD. On such panels &drm_edp_backlight_info.aux_enable will be set to
> + * %false, this function will become a no-op (and we will skip updating
> + * %DP_EDP_DISPLAY_CONTROL_REGISTER), and the driver must take care to perform it's own
> + * implementation specific step for disabling the backlight.
> + *
> + * Returns: %0 on success or no-op, negative error code on failure.
> + */
> +int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
> +{
> + int ret;
> +
> + ret = drm_edp_backlight_set_enable(aux, bl, false);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_disable);
> +
> +static inline int
> +drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
> +{
> + int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
> + int ret;
> + u8 pn, pn_min, pn_max;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
> + aux->name, ret);
> + return -ENODEV;
> + }
> +
> + pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> + bl->max = (1 << pn) - 1;
> + if (!driver_pwm_freq_hz)
> + return 0;
> +
> + /*
> + * Set PWM Frequency divider to match desired frequency provided by the driver.
> + * The PWM Frequency is calculated as 27Mhz / (F x P).
> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> + */
> +
> + /* Find desired value of (F x P)
> + * Note that, if F x P is out of supported range, the maximum value or minimum value will
> + * applied automatically. So no need to check that.
> + */
> + fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
> +
> + /* Use highest possible value of Pn for more granularity of brightness adjustment while
> + * satifying the conditions below.
> + * - Pn is in the range of Pn_min and Pn_max
> + * - F is in the range of 1 and 255
> + * - FxP is within 25% of desired value.
> + * Note: 25% is arbitrary value and may need some tweak.
> + */
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> + pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> +
> + /* Ensure frequency is within 25% of desired value */
> + fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> + fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> + if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Driver defined backlight frequency (%d) out of range\n",
> + aux->name, driver_pwm_freq_hz);
> + return 0;
> + }
> +
> + for (pn = pn_max; pn >= pn_min; pn--) {
> + f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> + fxp_actual = f << pn;
> + if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
> + break;
> + }
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + bl->pwmgen_bit_count = pn;
> + bl->max = (1 << pn) - 1;
> +
> + if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
> + bl->pwm_freq_pre_divider = f;
> + drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
> + aux->name, driver_pwm_freq_hz);
> + }
> +
> + return 0;
> +}
> +
> +static inline int
> +drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u8 *current_mode)
> +{
> + int ret;
> + u8 buf[2];
> + u8 mode_reg;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
> + if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + int size = 1 + bl->lsb_reg_used;
> +
> + ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
> + if (ret != size) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + if (bl->lsb_reg_used)
> + return (buf[0] << 8) | buf[1];
> + else
> + return buf[0];
> + }
> +
> + /*
> + * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
> + * the driver should assume max brightness
> + */
> + return bl->max;
> +}
> +
> +/**
> + * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
> + * interface.
> + * @aux: The DP aux device to use for probing
> + * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
> + * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
> + * @edp_dpcd: A cached copy of the eDP DPCD
> + * @current_level: Where to store the probed brightness level
> + * @current_mode: Where to store the currently set backlight control mode
> + *
> + * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
> + * along with also probing the current and maximum supported brightness levels.
> + *
> + * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
> + * default frequency from the panel is used.
> + *
> + * Returns: %0 on success, negative error code on failure.
> + */
> +int
> +drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
> + u16 *current_level, u8 *current_mode)
> +{
> + int ret;
> +
> + if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
> + bl->aux_enable = true;
> + if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> + bl->lsb_reg_used = true;
> +
> + ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
> + if (ret < 0)
> + return ret;
> +
> + ret = drm_edp_backlight_probe_level(aux, bl, current_mode);
> + if (ret < 0)
> + return ret;
> + *current_level = ret;
> +
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Found backlight level=%d/%d pwm_freq_pre_divider=%d mode=%x\n",
> + aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, *current_mode);
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Backlight caps: pwmgen_bit_count=%d lsb_reg_used=%d aux_enable=%d\n",
> + aux->name, bl->pwmgen_bit_count, bl->lsb_reg_used, bl->aux_enable);
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_init);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d4a57bce71b1..8696b39da2fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -310,10 +310,7 @@ struct intel_panel {
> /* DPCD backlight */
> union {
> struct {
> - u8 pwmgen_bit_count;
> - u8 pwm_freq_pre_divider;
> - bool lsb_reg_used;
> - bool aux_enable;
> + struct drm_edp_backlight_info info;
> } vesa;
> struct {
> bool sdr_uses_aux;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 95f2df631052..6ac568617ef3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -270,114 +270,19 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
> }
>
> /* VESA backlight callbacks */
> -static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
> -{
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 mode_reg;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
> - return false;
> - }
> -
> - return (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
> - DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> -}
> -
> -/*
> - * Read the current backlight value from DPCD register(s) based
> - * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
> - */
> static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, enum pipe unused)
> {
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 read_val[2] = { 0x0 };
> - u16 level = 0;
> -
> - /*
> - * If we're not in DPCD control mode yet, the programmed brightness
> - * value is meaningless and we should assume max brightness
> - */
> - if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
> - return connector->panel.backlight.max;
> -
> - ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
> - sizeof(read_val));
> - if (ret != sizeof(read_val)) {
> - drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
> - return 0;
> - }
> -
> - if (connector->panel.backlight.edp.vesa.lsb_reg_used)
> - level = (read_val[0] << 8 | read_val[1]);
> - else
> - level = read_val[0];
> -
> - return level;
> + return connector->panel.backlight.level;
> }
>
> -/*
> - * Sends the current backlight level over the aux channel, checking if its using
> - * 8-bit or 16 bit value (MSB and LSB)
> - */
> static void
> -intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
> - u32 level)
> +intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, u32 level)
> {
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 vals[2] = { 0x0 };
> -
> - /* Write the MSB and/or LSB */
> - if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
> - vals[0] = (level & 0xFF00) >> 8;
> - vals[1] = (level & 0xFF);
> - } else {
> - vals[0] = level;
> - }
> -
> - ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
> - sizeof(vals));
> - if (ret != sizeof(vals)) {
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
> - return;
> - }
> -}
> -
> -static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
> -{
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 reg_val = 0;
> -
> - /* Early return when display use other mechanism to enable backlight. */
> - if (!connector->panel.backlight.edp.vesa.aux_enable)
> - return;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
> - return;
> - }
> -
> - if (enable)
> - reg_val |= DP_EDP_BACKLIGHT_ENABLE;
> - else
> - reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
> + struct intel_panel *panel = &connector->panel;
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
> - enabledisable(enable), ret);
> - }
> + drm_edp_backlight_set_level(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
> }
>
> static void
> @@ -385,170 +290,46 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state, u32 level)
> {
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> struct intel_panel *panel = &connector->panel;
> - int ret;
> - u8 dpcd_buf, new_dpcd_buf;
> - u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
> - return;
> - }
> -
> - new_dpcd_buf = dpcd_buf;
> -
> - if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> - new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> - new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> -
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
> - if (ret != 1)
> - drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
> - }
> -
> - if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
> - panel->backlight.edp.vesa.pwm_freq_pre_divider);
> - if (ret == 1)
> - new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> - else
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
> - ret);
> - }
> -
> - if (new_dpcd_buf != dpcd_buf) {
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
> - new_dpcd_buf);
> - if (ret != 1)
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
> - }
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - intel_dp_aux_vesa_set_backlight(conn_state, level);
> - set_vesa_backlight_enable(connector, true);
> + drm_edp_backlight_enable(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
> }
>
> static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
> u32 level)
> {
> - set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
> -}
> -
> -/*
> - * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
> - * The PWM Frequency is calculated as 27Mhz / (F x P).
> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> - */
> -static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
> -{
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> + struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
> struct intel_panel *panel = &connector->panel;
> - u32 max_backlight = 0;
> - int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
> - u8 pn, pn_min, pn_max;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
> - return 0;
> - }
> -
> - pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> - max_backlight = (1 << pn) - 1;
> -
> - /* Find desired value of (F x P)
> - * Note that, if F x P is out of supported range, the maximum value or
> - * minimum value will applied automatically. So no need to check that.
> - */
> - freq = i915->vbt.backlight.pwm_freq_hz;
> - drm_dbg_kms(&i915->drm, "VBT defined backlight frequency %u Hz\n",
> - freq);
> - if (!freq) {
> - drm_dbg_kms(&i915->drm,
> - "Use panel default backlight frequency\n");
> - return max_backlight;
> - }
> -
> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
> -
> - /* Use highest possible value of Pn for more granularity of brightness
> - * adjustment while satifying the conditions below.
> - * - Pn is in the range of Pn_min and Pn_max
> - * - F is in the range of 1 and 255
> - * - FxP is within 25% of desired value.
> - * Note: 25% is arbitrary value and may need some tweak.
> - */
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
> - return max_backlight;
> - }
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
> - return max_backlight;
> - }
> - pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> - pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> -
> - /* Ensure frequency is within 25% of desired value */
> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> -
> - if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> - drm_dbg_kms(&i915->drm,
> - "VBT defined backlight frequency out of range\n");
> - return max_backlight;
> - }
> -
> - for (pn = pn_max; pn >= pn_min; pn--) {
> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> - fxp_actual = f << pn;
> - if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
> - break;
> - }
> -
> - drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
> - return max_backlight;
> - }
> -
> - panel->backlight.edp.vesa.pwmgen_bit_count = pn;
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> - panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
> -
> - max_backlight = (1 << pn) - 1;
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - return max_backlight;
> + drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info);
> }
>
> -static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
> - enum pipe pipe)
> +static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe)
> {
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct intel_panel *panel = &connector->panel;
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + u16 current_level;
> + u8 current_mode;
> + int ret;
>
> - if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
> - panel->backlight.edp.vesa.aux_enable = true;
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> - panel->backlight.edp.vesa.lsb_reg_used = true;
> -
> - panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
> - if (!panel->backlight.max)
> - return -ENODEV;
> + ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,
> + i915->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
> + ¤t_level, ¤t_mode);
> + if (ret < 0)
> + return ret;
>
> + panel->backlight.max = panel->backlight.edp.vesa.info.max;
> panel->backlight.min = 0;
> - panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector, pipe);
> - panel->backlight.enabled = intel_dp_aux_vesa_backlight_dpcd_mode(connector) &&
> - panel->backlight.level != 0;
> + if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + panel->backlight.level = current_level;
> + panel->backlight.enabled = panel->backlight.level != 0;
> + } else {
> + panel->backlight.level = panel->backlight.max;
> + panel->backlight.enabled = false;
> + }
>
> return 0;
> }
> @@ -559,16 +340,12 @@ intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector)
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> - /* Check the eDP Display control capabilities registers to determine if
> - * the panel can support backlight control over the aux channel.
> - *
> - * TODO: We currently only support AUX only backlight configurations, not backlights which
> + /* TODO: We currently only support AUX only backlight configurations, not backlights which
> * require a mix of PWM and AUX controls to work. In the mean time, these machines typically
> * work just fine using normal PWM controls anyway.
> */
> - if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
> - (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> - (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
> + if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> + drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
> drm_dbg_kms(&i915->drm, "AUX Backlight Control Supported!\n");
> return true;
> }
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 06681bf46d81..0bd6396648b4 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1801,6 +1801,24 @@ drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> DP_MSA_TIMING_PAR_IGNORED;
> }
>
> +/**
> + * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
> + * @edp_dpcd: The DPCD to check
> + *
> + * Note that currently this function will return %false for panels which support various DPCD
> + * backlight features but which require the brightness be set through PWM, and don't support setting
> + * the brightness level via the DPCD. This is a TODO.
> + *
> + * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
> + * otherwise
> + */
> +static inline bool
> +drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
> +{
> + return (edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
> + (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP);
> +}
> +
> /*
> * DisplayPort AUX channel
> */
> @@ -2107,6 +2125,36 @@ drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
> return desc->quirks & BIT(quirk);
> }
>
> +/**
> + * struct drm_edp_backlight_info - Probed eDP backlight info struct
> + * @pwmgen_bit_count: The pwmgen bit count
> + * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
> + * @max: The maximum backlight level that may be set
> + * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
> + * @aux_enable: Does the panel support the AUX enable cap?
> + *
> + * This structure contains various data about an eDP backlight, which can be populated by using
> + * drm_edp_backlight_init().
> + */
> +struct drm_edp_backlight_info {
> + u8 pwmgen_bit_count;
> + u8 pwm_freq_pre_divider;
> + u16 max;
> +
> + bool lsb_reg_used : 1;
> + bool aux_enable : 1;
> +};
> +
> +int
> +drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
> + u16 *current_level, u8 *current_mode);
> +int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level);
> +int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level);
> +int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
> +
> #ifdef CONFIG_DRM_DP_CEC
> void drm_dp_cec_irq(struct drm_dp_aux *aux);
> void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
> --
> 2.31.1
>
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 8/9] drm/dp: Extract i915's eDP backlight code into DRM helpers
@ 2021-05-21 20:02 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-05-21 20:02 UTC (permalink / raw)
To: Lyude Paul
Cc: greg.depoire, Rajeev Nandan, David Airlie, nouveau, intel-gfx,
Lucas De Marchi, open list, dri-devel, Gwan-gyeong Mun,
Jani Nikula, Uma Shankar, Sean Paul, Thomas Zimmermann,
Anshuman Gupta, Dave Airlie
On Fri, May 14, 2021 at 02:15:02PM -0400, Lyude Paul wrote:
> Since we're about to implement eDP backlight support in nouveau using the
> standard protocol from VESA, we might as well just take the code that's
> already written for this and move it into a set of shared DRM helpers.
>
> Note that these helpers are intended to handle DPCD related backlight
> control bits such as setting the brightness level over AUX, probing the
> backlight's TCON, enabling/disabling the backlight over AUX if supported,
> etc. Any PWM-related portions of backlight control are explicitly left up
> to the driver, as these will vary from platform to platform.
>
> The only exception to this is the calculation of the PWM frequency
> pre-divider value. This is because the only platform-specific information
> required for this is the PWM frequency of the panel, which the driver is
> expected to provide if available. The actual algorithm for calculating this
> value is standard and is defined in the eDP specification from VESA.
>
> Note that these helpers do not yet implement the full range of features
> the VESA backlight interface provides, and only provide the following
> functionality (all of which was already present in i915's DPCD backlight
> support):
>
> * Basic control of brightness levels
> * Basic probing of backlight capabilities
> * Helpers for enabling and disabling the backlight
>
> v3:
> * Split out changes to i915's backlight code to separate patches to make it
> easier to review
> v4:
> * Style/spelling changes from Thomas Zimmermann
> v5:
> * Start using new drm_dbg_*() functions
This version was indeed much easier to review. Thanks for addressing all the
comments.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Dave Airlie <airlied@gmail.com>
> Cc: greg.depoire@gmail.com
> ---
> drivers/gpu/drm/drm_dp_helper.c | 347 ++++++++++++++++++
> .../drm/i915/display/intel_display_types.h | 5 +-
> .../drm/i915/display/intel_dp_aux_backlight.c | 285 ++------------
> include/drm/drm_dp_helper.h | 48 +++
> 4 files changed, 427 insertions(+), 258 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 55b53df6ce34..24bbc710c825 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -3115,3 +3115,350 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
> return 0;
> }
> EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
> +
> +/**
> + * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + * @level: The brightness level to set
> + *
> + * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
> + * already have been enabled by the driver by calling drm_edp_backlight_enable().
> + *
> + * Returns: %0 on success, negative error code on failure
> + */
> +int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level)
> +{
> + int ret;
> + u8 buf[2] = { 0 };
> +
> + if (bl->lsb_reg_used) {
> + buf[0] = (level & 0xff00) >> 8;
> + buf[1] = (level & 0x00ff);
> + } else {
> + buf[0] = level;
> + }
> +
> + ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
> + if (ret != sizeof(buf)) {
> + drm_err(aux->drm_dev,
> + "%s: Failed to write aux backlight level: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_set_level);
> +
> +static int
> +drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + bool enable)
> +{
> + int ret;
> + u8 buf;
> +
> + /* The panel uses something other then DPCD for enabling its backlight */
> + if (!bl->aux_enable)
> + return 0;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
> + if (ret != 1) {
> + drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> + if (enable)
> + buf |= DP_EDP_BACKLIGHT_ENABLE;
> + else
> + buf &= ~DP_EDP_BACKLIGHT_ENABLE;
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
> + if (ret != 1) {
> + drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + * @level: The initial backlight level to set via AUX, if there is one
> + *
> + * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
> + * restoring any important backlight state such as the given backlight level, the brightness byte
> + * count, backlight frequency, etc.
> + *
> + * Note that certain panels, while supporting brightness level controls over DPCD, may not support
> + * having their backlights enabled via the standard %DP_EDP_DISPLAY_CONTROL_REGISTER. On such panels
> + * &drm_edp_backlight_info.aux_enable will be set to %false, this function will skip the step of
> + * programming the %DP_EDP_DISPLAY_CONTROL_REGISTER, and the driver must perform the required
> + * implementation specific step for enabling the backlight after calling this function.
> + *
> + * Returns: %0 on success, negative error code on failure.
> + */
> +int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + const u16 level)
> +{
> + int ret;
> + u8 dpcd_buf, new_dpcd_buf;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Failed to read backlight mode: %d\n", aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + new_dpcd_buf = dpcd_buf;
> +
> + if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> + new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
> + if (ret != 1)
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
> + aux->name, ret);
> + }
> +
> + if (bl->pwm_freq_pre_divider) {
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
> + if (ret != 1)
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Failed to write aux backlight frequency: %d\n",
> + aux->name, ret);
> + else
> + new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> + }
> +
> + if (new_dpcd_buf != dpcd_buf) {
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> + }
> +
> + ret = drm_edp_backlight_set_level(aux, bl, level);
> + if (ret < 0)
> + return ret;
> + ret = drm_edp_backlight_set_enable(aux, bl, true);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_enable);
> +
> +/**
> + * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + *
> + * This function handles disabling DPCD backlight controls on a panel over AUX. Note that some
> + * panels have backlights that are enabled/disabled by other means, despite having their brightness
> + * values controlled through DPCD. On such panels &drm_edp_backlight_info.aux_enable will be set to
> + * %false, this function will become a no-op (and we will skip updating
> + * %DP_EDP_DISPLAY_CONTROL_REGISTER), and the driver must take care to perform it's own
> + * implementation specific step for disabling the backlight.
> + *
> + * Returns: %0 on success or no-op, negative error code on failure.
> + */
> +int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
> +{
> + int ret;
> +
> + ret = drm_edp_backlight_set_enable(aux, bl, false);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_disable);
> +
> +static inline int
> +drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
> +{
> + int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
> + int ret;
> + u8 pn, pn_min, pn_max;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
> + aux->name, ret);
> + return -ENODEV;
> + }
> +
> + pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> + bl->max = (1 << pn) - 1;
> + if (!driver_pwm_freq_hz)
> + return 0;
> +
> + /*
> + * Set PWM Frequency divider to match desired frequency provided by the driver.
> + * The PWM Frequency is calculated as 27Mhz / (F x P).
> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> + */
> +
> + /* Find desired value of (F x P)
> + * Note that, if F x P is out of supported range, the maximum value or minimum value will
> + * applied automatically. So no need to check that.
> + */
> + fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
> +
> + /* Use highest possible value of Pn for more granularity of brightness adjustment while
> + * satifying the conditions below.
> + * - Pn is in the range of Pn_min and Pn_max
> + * - F is in the range of 1 and 255
> + * - FxP is within 25% of desired value.
> + * Note: 25% is arbitrary value and may need some tweak.
> + */
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> + pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> +
> + /* Ensure frequency is within 25% of desired value */
> + fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> + fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> + if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Driver defined backlight frequency (%d) out of range\n",
> + aux->name, driver_pwm_freq_hz);
> + return 0;
> + }
> +
> + for (pn = pn_max; pn >= pn_min; pn--) {
> + f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> + fxp_actual = f << pn;
> + if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
> + break;
> + }
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + bl->pwmgen_bit_count = pn;
> + bl->max = (1 << pn) - 1;
> +
> + if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
> + bl->pwm_freq_pre_divider = f;
> + drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
> + aux->name, driver_pwm_freq_hz);
> + }
> +
> + return 0;
> +}
> +
> +static inline int
> +drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u8 *current_mode)
> +{
> + int ret;
> + u8 buf[2];
> + u8 mode_reg;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
> + if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + int size = 1 + bl->lsb_reg_used;
> +
> + ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
> + if (ret != size) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + if (bl->lsb_reg_used)
> + return (buf[0] << 8) | buf[1];
> + else
> + return buf[0];
> + }
> +
> + /*
> + * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
> + * the driver should assume max brightness
> + */
> + return bl->max;
> +}
> +
> +/**
> + * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
> + * interface.
> + * @aux: The DP aux device to use for probing
> + * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
> + * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
> + * @edp_dpcd: A cached copy of the eDP DPCD
> + * @current_level: Where to store the probed brightness level
> + * @current_mode: Where to store the currently set backlight control mode
> + *
> + * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
> + * along with also probing the current and maximum supported brightness levels.
> + *
> + * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
> + * default frequency from the panel is used.
> + *
> + * Returns: %0 on success, negative error code on failure.
> + */
> +int
> +drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
> + u16 *current_level, u8 *current_mode)
> +{
> + int ret;
> +
> + if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
> + bl->aux_enable = true;
> + if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> + bl->lsb_reg_used = true;
> +
> + ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
> + if (ret < 0)
> + return ret;
> +
> + ret = drm_edp_backlight_probe_level(aux, bl, current_mode);
> + if (ret < 0)
> + return ret;
> + *current_level = ret;
> +
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Found backlight level=%d/%d pwm_freq_pre_divider=%d mode=%x\n",
> + aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, *current_mode);
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Backlight caps: pwmgen_bit_count=%d lsb_reg_used=%d aux_enable=%d\n",
> + aux->name, bl->pwmgen_bit_count, bl->lsb_reg_used, bl->aux_enable);
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_init);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d4a57bce71b1..8696b39da2fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -310,10 +310,7 @@ struct intel_panel {
> /* DPCD backlight */
> union {
> struct {
> - u8 pwmgen_bit_count;
> - u8 pwm_freq_pre_divider;
> - bool lsb_reg_used;
> - bool aux_enable;
> + struct drm_edp_backlight_info info;
> } vesa;
> struct {
> bool sdr_uses_aux;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 95f2df631052..6ac568617ef3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -270,114 +270,19 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
> }
>
> /* VESA backlight callbacks */
> -static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
> -{
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 mode_reg;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
> - return false;
> - }
> -
> - return (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
> - DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> -}
> -
> -/*
> - * Read the current backlight value from DPCD register(s) based
> - * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
> - */
> static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, enum pipe unused)
> {
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 read_val[2] = { 0x0 };
> - u16 level = 0;
> -
> - /*
> - * If we're not in DPCD control mode yet, the programmed brightness
> - * value is meaningless and we should assume max brightness
> - */
> - if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
> - return connector->panel.backlight.max;
> -
> - ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
> - sizeof(read_val));
> - if (ret != sizeof(read_val)) {
> - drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
> - return 0;
> - }
> -
> - if (connector->panel.backlight.edp.vesa.lsb_reg_used)
> - level = (read_val[0] << 8 | read_val[1]);
> - else
> - level = read_val[0];
> -
> - return level;
> + return connector->panel.backlight.level;
> }
>
> -/*
> - * Sends the current backlight level over the aux channel, checking if its using
> - * 8-bit or 16 bit value (MSB and LSB)
> - */
> static void
> -intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
> - u32 level)
> +intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, u32 level)
> {
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 vals[2] = { 0x0 };
> -
> - /* Write the MSB and/or LSB */
> - if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
> - vals[0] = (level & 0xFF00) >> 8;
> - vals[1] = (level & 0xFF);
> - } else {
> - vals[0] = level;
> - }
> -
> - ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
> - sizeof(vals));
> - if (ret != sizeof(vals)) {
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
> - return;
> - }
> -}
> -
> -static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
> -{
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 reg_val = 0;
> -
> - /* Early return when display use other mechanism to enable backlight. */
> - if (!connector->panel.backlight.edp.vesa.aux_enable)
> - return;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
> - return;
> - }
> -
> - if (enable)
> - reg_val |= DP_EDP_BACKLIGHT_ENABLE;
> - else
> - reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
> + struct intel_panel *panel = &connector->panel;
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
> - enabledisable(enable), ret);
> - }
> + drm_edp_backlight_set_level(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
> }
>
> static void
> @@ -385,170 +290,46 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state, u32 level)
> {
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> struct intel_panel *panel = &connector->panel;
> - int ret;
> - u8 dpcd_buf, new_dpcd_buf;
> - u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
> - return;
> - }
> -
> - new_dpcd_buf = dpcd_buf;
> -
> - if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> - new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> - new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> -
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
> - if (ret != 1)
> - drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
> - }
> -
> - if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
> - panel->backlight.edp.vesa.pwm_freq_pre_divider);
> - if (ret == 1)
> - new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> - else
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
> - ret);
> - }
> -
> - if (new_dpcd_buf != dpcd_buf) {
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
> - new_dpcd_buf);
> - if (ret != 1)
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
> - }
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - intel_dp_aux_vesa_set_backlight(conn_state, level);
> - set_vesa_backlight_enable(connector, true);
> + drm_edp_backlight_enable(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
> }
>
> static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
> u32 level)
> {
> - set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
> -}
> -
> -/*
> - * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
> - * The PWM Frequency is calculated as 27Mhz / (F x P).
> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> - */
> -static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
> -{
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> + struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
> struct intel_panel *panel = &connector->panel;
> - u32 max_backlight = 0;
> - int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
> - u8 pn, pn_min, pn_max;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
> - return 0;
> - }
> -
> - pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> - max_backlight = (1 << pn) - 1;
> -
> - /* Find desired value of (F x P)
> - * Note that, if F x P is out of supported range, the maximum value or
> - * minimum value will applied automatically. So no need to check that.
> - */
> - freq = i915->vbt.backlight.pwm_freq_hz;
> - drm_dbg_kms(&i915->drm, "VBT defined backlight frequency %u Hz\n",
> - freq);
> - if (!freq) {
> - drm_dbg_kms(&i915->drm,
> - "Use panel default backlight frequency\n");
> - return max_backlight;
> - }
> -
> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
> -
> - /* Use highest possible value of Pn for more granularity of brightness
> - * adjustment while satifying the conditions below.
> - * - Pn is in the range of Pn_min and Pn_max
> - * - F is in the range of 1 and 255
> - * - FxP is within 25% of desired value.
> - * Note: 25% is arbitrary value and may need some tweak.
> - */
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
> - return max_backlight;
> - }
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
> - return max_backlight;
> - }
> - pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> - pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> -
> - /* Ensure frequency is within 25% of desired value */
> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> -
> - if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> - drm_dbg_kms(&i915->drm,
> - "VBT defined backlight frequency out of range\n");
> - return max_backlight;
> - }
> -
> - for (pn = pn_max; pn >= pn_min; pn--) {
> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> - fxp_actual = f << pn;
> - if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
> - break;
> - }
> -
> - drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
> - return max_backlight;
> - }
> -
> - panel->backlight.edp.vesa.pwmgen_bit_count = pn;
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> - panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
> -
> - max_backlight = (1 << pn) - 1;
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - return max_backlight;
> + drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info);
> }
>
> -static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
> - enum pipe pipe)
> +static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe)
> {
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct intel_panel *panel = &connector->panel;
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + u16 current_level;
> + u8 current_mode;
> + int ret;
>
> - if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
> - panel->backlight.edp.vesa.aux_enable = true;
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> - panel->backlight.edp.vesa.lsb_reg_used = true;
> -
> - panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
> - if (!panel->backlight.max)
> - return -ENODEV;
> + ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,
> + i915->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
> + ¤t_level, ¤t_mode);
> + if (ret < 0)
> + return ret;
>
> + panel->backlight.max = panel->backlight.edp.vesa.info.max;
> panel->backlight.min = 0;
> - panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector, pipe);
> - panel->backlight.enabled = intel_dp_aux_vesa_backlight_dpcd_mode(connector) &&
> - panel->backlight.level != 0;
> + if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + panel->backlight.level = current_level;
> + panel->backlight.enabled = panel->backlight.level != 0;
> + } else {
> + panel->backlight.level = panel->backlight.max;
> + panel->backlight.enabled = false;
> + }
>
> return 0;
> }
> @@ -559,16 +340,12 @@ intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector)
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> - /* Check the eDP Display control capabilities registers to determine if
> - * the panel can support backlight control over the aux channel.
> - *
> - * TODO: We currently only support AUX only backlight configurations, not backlights which
> + /* TODO: We currently only support AUX only backlight configurations, not backlights which
> * require a mix of PWM and AUX controls to work. In the mean time, these machines typically
> * work just fine using normal PWM controls anyway.
> */
> - if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
> - (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> - (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
> + if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> + drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
> drm_dbg_kms(&i915->drm, "AUX Backlight Control Supported!\n");
> return true;
> }
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 06681bf46d81..0bd6396648b4 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1801,6 +1801,24 @@ drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> DP_MSA_TIMING_PAR_IGNORED;
> }
>
> +/**
> + * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
> + * @edp_dpcd: The DPCD to check
> + *
> + * Note that currently this function will return %false for panels which support various DPCD
> + * backlight features but which require the brightness be set through PWM, and don't support setting
> + * the brightness level via the DPCD. This is a TODO.
> + *
> + * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
> + * otherwise
> + */
> +static inline bool
> +drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
> +{
> + return (edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
> + (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP);
> +}
> +
> /*
> * DisplayPort AUX channel
> */
> @@ -2107,6 +2125,36 @@ drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
> return desc->quirks & BIT(quirk);
> }
>
> +/**
> + * struct drm_edp_backlight_info - Probed eDP backlight info struct
> + * @pwmgen_bit_count: The pwmgen bit count
> + * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
> + * @max: The maximum backlight level that may be set
> + * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
> + * @aux_enable: Does the panel support the AUX enable cap?
> + *
> + * This structure contains various data about an eDP backlight, which can be populated by using
> + * drm_edp_backlight_init().
> + */
> +struct drm_edp_backlight_info {
> + u8 pwmgen_bit_count;
> + u8 pwm_freq_pre_divider;
> + u16 max;
> +
> + bool lsb_reg_used : 1;
> + bool aux_enable : 1;
> +};
> +
> +int
> +drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
> + u16 *current_level, u8 *current_mode);
> +int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level);
> +int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level);
> +int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
> +
> #ifdef CONFIG_DRM_DP_CEC
> void drm_dp_cec_irq(struct drm_dp_aux *aux);
> void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Intel-gfx] [PATCH v6 8/9] drm/dp: Extract i915's eDP backlight code into DRM helpers
@ 2021-05-21 20:02 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-05-21 20:02 UTC (permalink / raw)
To: Lyude Paul
Cc: greg.depoire, Rajeev Nandan, David Airlie, nouveau, intel-gfx,
Lucas De Marchi, open list, dri-devel, Jani Nikula, Sean Paul,
Thomas Zimmermann, Dave Airlie
On Fri, May 14, 2021 at 02:15:02PM -0400, Lyude Paul wrote:
> Since we're about to implement eDP backlight support in nouveau using the
> standard protocol from VESA, we might as well just take the code that's
> already written for this and move it into a set of shared DRM helpers.
>
> Note that these helpers are intended to handle DPCD related backlight
> control bits such as setting the brightness level over AUX, probing the
> backlight's TCON, enabling/disabling the backlight over AUX if supported,
> etc. Any PWM-related portions of backlight control are explicitly left up
> to the driver, as these will vary from platform to platform.
>
> The only exception to this is the calculation of the PWM frequency
> pre-divider value. This is because the only platform-specific information
> required for this is the PWM frequency of the panel, which the driver is
> expected to provide if available. The actual algorithm for calculating this
> value is standard and is defined in the eDP specification from VESA.
>
> Note that these helpers do not yet implement the full range of features
> the VESA backlight interface provides, and only provide the following
> functionality (all of which was already present in i915's DPCD backlight
> support):
>
> * Basic control of brightness levels
> * Basic probing of backlight capabilities
> * Helpers for enabling and disabling the backlight
>
> v3:
> * Split out changes to i915's backlight code to separate patches to make it
> easier to review
> v4:
> * Style/spelling changes from Thomas Zimmermann
> v5:
> * Start using new drm_dbg_*() functions
This version was indeed much easier to review. Thanks for addressing all the
comments.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Dave Airlie <airlied@gmail.com>
> Cc: greg.depoire@gmail.com
> ---
> drivers/gpu/drm/drm_dp_helper.c | 347 ++++++++++++++++++
> .../drm/i915/display/intel_display_types.h | 5 +-
> .../drm/i915/display/intel_dp_aux_backlight.c | 285 ++------------
> include/drm/drm_dp_helper.h | 48 +++
> 4 files changed, 427 insertions(+), 258 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 55b53df6ce34..24bbc710c825 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -3115,3 +3115,350 @@ int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
> return 0;
> }
> EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
> +
> +/**
> + * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + * @level: The brightness level to set
> + *
> + * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
> + * already have been enabled by the driver by calling drm_edp_backlight_enable().
> + *
> + * Returns: %0 on success, negative error code on failure
> + */
> +int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level)
> +{
> + int ret;
> + u8 buf[2] = { 0 };
> +
> + if (bl->lsb_reg_used) {
> + buf[0] = (level & 0xff00) >> 8;
> + buf[1] = (level & 0x00ff);
> + } else {
> + buf[0] = level;
> + }
> +
> + ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
> + if (ret != sizeof(buf)) {
> + drm_err(aux->drm_dev,
> + "%s: Failed to write aux backlight level: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_set_level);
> +
> +static int
> +drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + bool enable)
> +{
> + int ret;
> + u8 buf;
> +
> + /* The panel uses something other then DPCD for enabling its backlight */
> + if (!bl->aux_enable)
> + return 0;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
> + if (ret != 1) {
> + drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> + if (enable)
> + buf |= DP_EDP_BACKLIGHT_ENABLE;
> + else
> + buf &= ~DP_EDP_BACKLIGHT_ENABLE;
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
> + if (ret != 1) {
> + drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + * @level: The initial backlight level to set via AUX, if there is one
> + *
> + * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
> + * restoring any important backlight state such as the given backlight level, the brightness byte
> + * count, backlight frequency, etc.
> + *
> + * Note that certain panels, while supporting brightness level controls over DPCD, may not support
> + * having their backlights enabled via the standard %DP_EDP_DISPLAY_CONTROL_REGISTER. On such panels
> + * &drm_edp_backlight_info.aux_enable will be set to %false, this function will skip the step of
> + * programming the %DP_EDP_DISPLAY_CONTROL_REGISTER, and the driver must perform the required
> + * implementation specific step for enabling the backlight after calling this function.
> + *
> + * Returns: %0 on success, negative error code on failure.
> + */
> +int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + const u16 level)
> +{
> + int ret;
> + u8 dpcd_buf, new_dpcd_buf;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Failed to read backlight mode: %d\n", aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + new_dpcd_buf = dpcd_buf;
> +
> + if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> + new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
> + if (ret != 1)
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
> + aux->name, ret);
> + }
> +
> + if (bl->pwm_freq_pre_divider) {
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
> + if (ret != 1)
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Failed to write aux backlight frequency: %d\n",
> + aux->name, ret);
> + else
> + new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> + }
> +
> + if (new_dpcd_buf != dpcd_buf) {
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, new_dpcd_buf);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> + }
> +
> + ret = drm_edp_backlight_set_level(aux, bl, level);
> + if (ret < 0)
> + return ret;
> + ret = drm_edp_backlight_set_enable(aux, bl, true);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_enable);
> +
> +/**
> + * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
> + * @aux: The DP AUX channel to use
> + * @bl: Backlight capability info from drm_edp_backlight_init()
> + *
> + * This function handles disabling DPCD backlight controls on a panel over AUX. Note that some
> + * panels have backlights that are enabled/disabled by other means, despite having their brightness
> + * values controlled through DPCD. On such panels &drm_edp_backlight_info.aux_enable will be set to
> + * %false, this function will become a no-op (and we will skip updating
> + * %DP_EDP_DISPLAY_CONTROL_REGISTER), and the driver must take care to perform it's own
> + * implementation specific step for disabling the backlight.
> + *
> + * Returns: %0 on success or no-op, negative error code on failure.
> + */
> +int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
> +{
> + int ret;
> +
> + ret = drm_edp_backlight_set_enable(aux, bl, false);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_disable);
> +
> +static inline int
> +drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
> +{
> + int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
> + int ret;
> + u8 pn, pn_min, pn_max;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
> + aux->name, ret);
> + return -ENODEV;
> + }
> +
> + pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> + bl->max = (1 << pn) - 1;
> + if (!driver_pwm_freq_hz)
> + return 0;
> +
> + /*
> + * Set PWM Frequency divider to match desired frequency provided by the driver.
> + * The PWM Frequency is calculated as 27Mhz / (F x P).
> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> + */
> +
> + /* Find desired value of (F x P)
> + * Note that, if F x P is out of supported range, the maximum value or minimum value will
> + * applied automatically. So no need to check that.
> + */
> + fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
> +
> + /* Use highest possible value of Pn for more granularity of brightness adjustment while
> + * satifying the conditions below.
> + * - Pn is in the range of Pn_min and Pn_max
> + * - F is in the range of 1 and 255
> + * - FxP is within 25% of desired value.
> + * Note: 25% is arbitrary value and may need some tweak.
> + */
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> + pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> +
> + /* Ensure frequency is within 25% of desired value */
> + fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> + fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> + if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Driver defined backlight frequency (%d) out of range\n",
> + aux->name, driver_pwm_freq_hz);
> + return 0;
> + }
> +
> + for (pn = pn_max; pn >= pn_min; pn--) {
> + f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> + fxp_actual = f << pn;
> + if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
> + break;
> + }
> +
> + ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
> + aux->name, ret);
> + return 0;
> + }
> + bl->pwmgen_bit_count = pn;
> + bl->max = (1 << pn) - 1;
> +
> + if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
> + bl->pwm_freq_pre_divider = f;
> + drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
> + aux->name, driver_pwm_freq_hz);
> + }
> +
> + return 0;
> +}
> +
> +static inline int
> +drm_edp_backlight_probe_level(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u8 *current_mode)
> +{
> + int ret;
> + u8 buf[2];
> + u8 mode_reg;
> +
> + ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
> + if (ret != 1) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
> + if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + int size = 1 + bl->lsb_reg_used;
> +
> + ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
> + if (ret != size) {
> + drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
> + aux->name, ret);
> + return ret < 0 ? ret : -EIO;
> + }
> +
> + if (bl->lsb_reg_used)
> + return (buf[0] << 8) | buf[1];
> + else
> + return buf[0];
> + }
> +
> + /*
> + * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
> + * the driver should assume max brightness
> + */
> + return bl->max;
> +}
> +
> +/**
> + * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
> + * interface.
> + * @aux: The DP aux device to use for probing
> + * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
> + * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
> + * @edp_dpcd: A cached copy of the eDP DPCD
> + * @current_level: Where to store the probed brightness level
> + * @current_mode: Where to store the currently set backlight control mode
> + *
> + * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
> + * along with also probing the current and maximum supported brightness levels.
> + *
> + * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
> + * default frequency from the panel is used.
> + *
> + * Returns: %0 on success, negative error code on failure.
> + */
> +int
> +drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
> + u16 *current_level, u8 *current_mode)
> +{
> + int ret;
> +
> + if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
> + bl->aux_enable = true;
> + if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> + bl->lsb_reg_used = true;
> +
> + ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
> + if (ret < 0)
> + return ret;
> +
> + ret = drm_edp_backlight_probe_level(aux, bl, current_mode);
> + if (ret < 0)
> + return ret;
> + *current_level = ret;
> +
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Found backlight level=%d/%d pwm_freq_pre_divider=%d mode=%x\n",
> + aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, *current_mode);
> + drm_dbg_kms(aux->drm_dev,
> + "%s: Backlight caps: pwmgen_bit_count=%d lsb_reg_used=%d aux_enable=%d\n",
> + aux->name, bl->pwmgen_bit_count, bl->lsb_reg_used, bl->aux_enable);
> + return 0;
> +}
> +EXPORT_SYMBOL(drm_edp_backlight_init);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index d4a57bce71b1..8696b39da2fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -310,10 +310,7 @@ struct intel_panel {
> /* DPCD backlight */
> union {
> struct {
> - u8 pwmgen_bit_count;
> - u8 pwm_freq_pre_divider;
> - bool lsb_reg_used;
> - bool aux_enable;
> + struct drm_edp_backlight_info info;
> } vesa;
> struct {
> bool sdr_uses_aux;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 95f2df631052..6ac568617ef3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -270,114 +270,19 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi
> }
>
> /* VESA backlight callbacks */
> -static bool intel_dp_aux_vesa_backlight_dpcd_mode(struct intel_connector *connector)
> -{
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 mode_reg;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
> - return false;
> - }
> -
> - return (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) ==
> - DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> -}
> -
> -/*
> - * Read the current backlight value from DPCD register(s) based
> - * on if 8-bit(MSB) or 16-bit(MSB and LSB) values are supported
> - */
> static u32 intel_dp_aux_vesa_get_backlight(struct intel_connector *connector, enum pipe unused)
> {
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 read_val[2] = { 0x0 };
> - u16 level = 0;
> -
> - /*
> - * If we're not in DPCD control mode yet, the programmed brightness
> - * value is meaningless and we should assume max brightness
> - */
> - if (!intel_dp_aux_vesa_backlight_dpcd_mode(connector))
> - return connector->panel.backlight.max;
> -
> - ret = drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, &read_val,
> - sizeof(read_val));
> - if (ret != sizeof(read_val)) {
> - drm_dbg_kms(&i915->drm, "Failed to read brightness level: %d\n", ret);
> - return 0;
> - }
> -
> - if (connector->panel.backlight.edp.vesa.lsb_reg_used)
> - level = (read_val[0] << 8 | read_val[1]);
> - else
> - level = read_val[0];
> -
> - return level;
> + return connector->panel.backlight.level;
> }
>
> -/*
> - * Sends the current backlight level over the aux channel, checking if its using
> - * 8-bit or 16 bit value (MSB and LSB)
> - */
> static void
> -intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
> - u32 level)
> +intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state, u32 level)
> {
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 vals[2] = { 0x0 };
> -
> - /* Write the MSB and/or LSB */
> - if (connector->panel.backlight.edp.vesa.lsb_reg_used) {
> - vals[0] = (level & 0xFF00) >> 8;
> - vals[1] = (level & 0xFF);
> - } else {
> - vals[0] = level;
> - }
> -
> - ret = drm_dp_dpcd_write(&intel_dp->aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, vals,
> - sizeof(vals));
> - if (ret != sizeof(vals)) {
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight level: %d\n", ret);
> - return;
> - }
> -}
> -
> -static void set_vesa_backlight_enable(struct intel_connector *connector, bool enable)
> -{
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - int ret;
> - u8 reg_val = 0;
> -
> - /* Early return when display use other mechanism to enable backlight. */
> - if (!connector->panel.backlight.edp.vesa.aux_enable)
> - return;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, ®_val);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read eDP display control register: %d\n", ret);
> - return;
> - }
> -
> - if (enable)
> - reg_val |= DP_EDP_BACKLIGHT_ENABLE;
> - else
> - reg_val &= ~(DP_EDP_BACKLIGHT_ENABLE);
> + struct intel_panel *panel = &connector->panel;
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_DISPLAY_CONTROL_REGISTER, reg_val);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to %s aux backlight: %d\n",
> - enabledisable(enable), ret);
> - }
> + drm_edp_backlight_set_level(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
> }
>
> static void
> @@ -385,170 +290,46 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state, u32 level)
> {
> struct intel_connector *connector = to_intel_connector(conn_state->connector);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> struct intel_panel *panel = &connector->panel;
> - int ret;
> - u8 dpcd_buf, new_dpcd_buf;
> - u8 pwmgen_bit_count = panel->backlight.edp.vesa.pwmgen_bit_count;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &dpcd_buf);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read backlight mode: %d\n", ret);
> - return;
> - }
> -
> - new_dpcd_buf = dpcd_buf;
> -
> - if ((dpcd_buf & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK) != DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> - new_dpcd_buf &= ~DP_EDP_BACKLIGHT_CONTROL_MODE_MASK;
> - new_dpcd_buf |= DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
> -
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pwmgen_bit_count);
> - if (ret != 1)
> - drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
> - }
> -
> - if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
> - panel->backlight.edp.vesa.pwm_freq_pre_divider);
> - if (ret == 1)
> - new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> - else
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency: %d\n",
> - ret);
> - }
> -
> - if (new_dpcd_buf != dpcd_buf) {
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER,
> - new_dpcd_buf);
> - if (ret != 1)
> - drm_dbg_kms(&i915->drm, "Failed to write aux backlight mode: %d\n", ret);
> - }
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - intel_dp_aux_vesa_set_backlight(conn_state, level);
> - set_vesa_backlight_enable(connector, true);
> + drm_edp_backlight_enable(&intel_dp->aux, &panel->backlight.edp.vesa.info, level);
> }
>
> static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state *old_conn_state,
> u32 level)
> {
> - set_vesa_backlight_enable(to_intel_connector(old_conn_state->connector), false);
> -}
> -
> -/*
> - * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
> - * The PWM Frequency is calculated as 27Mhz / (F x P).
> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> - */
> -static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
> -{
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> + struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
> struct intel_panel *panel = &connector->panel;
> - u32 max_backlight = 0;
> - int ret, freq, fxp, fxp_min, fxp_max, fxp_actual, f = 1;
> - u8 pn, pn_min, pn_max;
> -
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap: %d\n", ret);
> - return 0;
> - }
> -
> - pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> - max_backlight = (1 << pn) - 1;
> -
> - /* Find desired value of (F x P)
> - * Note that, if F x P is out of supported range, the maximum value or
> - * minimum value will applied automatically. So no need to check that.
> - */
> - freq = i915->vbt.backlight.pwm_freq_hz;
> - drm_dbg_kms(&i915->drm, "VBT defined backlight frequency %u Hz\n",
> - freq);
> - if (!freq) {
> - drm_dbg_kms(&i915->drm,
> - "Use panel default backlight frequency\n");
> - return max_backlight;
> - }
> -
> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
> -
> - /* Use highest possible value of Pn for more granularity of brightness
> - * adjustment while satifying the conditions below.
> - * - Pn is in the range of Pn_min and Pn_max
> - * - F is in the range of 1 and 255
> - * - FxP is within 25% of desired value.
> - * Note: 25% is arbitrary value and may need some tweak.
> - */
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap min: %d\n", ret);
> - return max_backlight;
> - }
> - ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to read pwmgen bit count cap max: %d\n", ret);
> - return max_backlight;
> - }
> - pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> - pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> -
> - /* Ensure frequency is within 25% of desired value */
> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> -
> - if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> - drm_dbg_kms(&i915->drm,
> - "VBT defined backlight frequency out of range\n");
> - return max_backlight;
> - }
> -
> - for (pn = pn_max; pn >= pn_min; pn--) {
> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> - fxp_actual = f << pn;
> - if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
> - break;
> - }
> -
> - drm_dbg_kms(&i915->drm, "Using eDP pwmgen bit count of %d\n", pn);
> - ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
> - if (ret != 1) {
> - drm_dbg_kms(&i915->drm, "Failed to write aux pwmgen bit count: %d\n", ret);
> - return max_backlight;
> - }
> -
> - panel->backlight.edp.vesa.pwmgen_bit_count = pn;
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> - panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
> -
> - max_backlight = (1 << pn) - 1;
> + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder);
>
> - return max_backlight;
> + drm_edp_backlight_disable(&intel_dp->aux, &panel->backlight.edp.vesa.info);
> }
>
> -static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector,
> - enum pipe pipe)
> +static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe)
> {
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct intel_panel *panel = &connector->panel;
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> + u16 current_level;
> + u8 current_mode;
> + int ret;
>
> - if (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
> - panel->backlight.edp.vesa.aux_enable = true;
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
> - panel->backlight.edp.vesa.lsb_reg_used = true;
> -
> - panel->backlight.max = intel_dp_aux_vesa_calc_max_backlight(connector);
> - if (!panel->backlight.max)
> - return -ENODEV;
> + ret = drm_edp_backlight_init(&intel_dp->aux, &panel->backlight.edp.vesa.info,
> + i915->vbt.backlight.pwm_freq_hz, intel_dp->edp_dpcd,
> + ¤t_level, ¤t_mode);
> + if (ret < 0)
> + return ret;
>
> + panel->backlight.max = panel->backlight.edp.vesa.info.max;
> panel->backlight.min = 0;
> - panel->backlight.level = intel_dp_aux_vesa_get_backlight(connector, pipe);
> - panel->backlight.enabled = intel_dp_aux_vesa_backlight_dpcd_mode(connector) &&
> - panel->backlight.level != 0;
> + if (current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
> + panel->backlight.level = current_level;
> + panel->backlight.enabled = panel->backlight.level != 0;
> + } else {
> + panel->backlight.level = panel->backlight.max;
> + panel->backlight.enabled = false;
> + }
>
> return 0;
> }
> @@ -559,16 +340,12 @@ intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector)
> struct intel_dp *intel_dp = intel_attached_dp(connector);
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> - /* Check the eDP Display control capabilities registers to determine if
> - * the panel can support backlight control over the aux channel.
> - *
> - * TODO: We currently only support AUX only backlight configurations, not backlights which
> + /* TODO: We currently only support AUX only backlight configurations, not backlights which
> * require a mix of PWM and AUX controls to work. In the mean time, these machines typically
> * work just fine using normal PWM controls anyway.
> */
> - if (intel_dp->edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP &&
> - (intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> - (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)) {
> + if ((intel_dp->edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) &&
> + drm_edp_backlight_supported(intel_dp->edp_dpcd)) {
> drm_dbg_kms(&i915->drm, "AUX Backlight Control Supported!\n");
> return true;
> }
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 06681bf46d81..0bd6396648b4 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -1801,6 +1801,24 @@ drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
> DP_MSA_TIMING_PAR_IGNORED;
> }
>
> +/**
> + * drm_edp_backlight_supported() - Check an eDP DPCD for VESA backlight support
> + * @edp_dpcd: The DPCD to check
> + *
> + * Note that currently this function will return %false for panels which support various DPCD
> + * backlight features but which require the brightness be set through PWM, and don't support setting
> + * the brightness level via the DPCD. This is a TODO.
> + *
> + * Returns: %True if @edp_dpcd indicates that VESA backlight controls are supported, %false
> + * otherwise
> + */
> +static inline bool
> +drm_edp_backlight_supported(const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
> +{
> + return (edp_dpcd[1] & DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP) &&
> + (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP);
> +}
> +
> /*
> * DisplayPort AUX channel
> */
> @@ -2107,6 +2125,36 @@ drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
> return desc->quirks & BIT(quirk);
> }
>
> +/**
> + * struct drm_edp_backlight_info - Probed eDP backlight info struct
> + * @pwmgen_bit_count: The pwmgen bit count
> + * @pwm_freq_pre_divider: The PWM frequency pre-divider value being used for this backlight, if any
> + * @max: The maximum backlight level that may be set
> + * @lsb_reg_used: Do we also write values to the DP_EDP_BACKLIGHT_BRIGHTNESS_LSB register?
> + * @aux_enable: Does the panel support the AUX enable cap?
> + *
> + * This structure contains various data about an eDP backlight, which can be populated by using
> + * drm_edp_backlight_init().
> + */
> +struct drm_edp_backlight_info {
> + u8 pwmgen_bit_count;
> + u8 pwm_freq_pre_divider;
> + u16 max;
> +
> + bool lsb_reg_used : 1;
> + bool aux_enable : 1;
> +};
> +
> +int
> +drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
> + u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
> + u16 *current_level, u8 *current_mode);
> +int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level);
> +int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
> + u16 level);
> +int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl);
> +
> #ifdef CONFIG_DRM_DP_CEC
> void drm_dp_cec_irq(struct drm_dp_aux *aux);
> void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
> --
> 2.31.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
2021-05-14 18:14 ` [Nouveau] " Lyude Paul
(?)
(?)
@ 2021-05-21 20:03 ` Rodrigo Vivi
-1 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-05-21 20:03 UTC (permalink / raw)
To: Lyude Paul, Jani Nikula
Cc: intel-gfx, dri-devel, nouveau, Rajeev Nandan, greg.depoire,
David Airlie, Lucas De Marchi, open list, Anshuman Gupta,
Jani Nikula, Uma Shankar, Sean Paul, Dave Airlie,
Gwan-gyeong Mun
On Fri, May 14, 2021 at 02:14:55PM -0400, Lyude Paul wrote:
> Noticed this while moving all of the VESA backlight code in i915 over to
> DRM helpers: it would appear that we calculate the frequency value we want
> to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
> actually changes during runtime. So, let's simplify things by just caching
> this value in intel_panel.backlight, and re-writing it as-needed.
>
> Changes since v1:
> * Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
> DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
This looks okay to me now... Jani, agree?
>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Dave Airlie <airlied@gmail.com>
> Cc: greg.depoire@gmail.com
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> .../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
> 2 files changed, 20 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9c0adfc60c6f..7054a37363fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -311,6 +311,7 @@ struct intel_panel {
> union {
> struct {
> u8 pwmgen_bit_count;
> + u8 pwm_freq_pre_divider;
> } vesa;
> struct {
> bool sdr_uses_aux;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 8e9ac9ba1d38..68bfe50ada59 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
> }
> }
>
> -/*
> - * Set PWM Frequency divider to match desired frequency in vbt.
> - * The PWM Frequency is calculated as 27Mhz / (F x P).
> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> - */
> -static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
> -{
> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
> - int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
> -
> - freq = dev_priv->vbt.backlight.pwm_freq_hz;
> - if (!freq) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Use panel default backlight frequency\n");
> - return false;
> - }
> -
> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> - fxp_actual = f << pn;
> -
> - /* Ensure frequency is within 25% of desired value */
> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> -
> - if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
> - drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
> - return false;
> - }
> -
> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
> - DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Failed to write aux backlight freq\n");
> - return false;
> - }
> - return true;
> -}
> -
> static void
> intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state, u32 level)
> @@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> break;
> }
>
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> - if (intel_dp_aux_vesa_set_pwm_freq(connector))
> + if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
> + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
> + panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
> new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> + else
> + drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
> + }
>
> if (new_dpcd_buf != dpcd_buf) {
> if (drm_dp_dpcd_writeb(&intel_dp->aux,
> @@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
> false);
> }
>
> +/*
> + * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
> + * The PWM Frequency is calculated as 27Mhz / (F x P).
> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> + */
> static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> @@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
> pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>
> + /* Ensure frequency is within 25% of desired value */
> fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> +
> if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> drm_dbg_kms(&i915->drm,
> "VBT defined backlight frequency out of range\n");
> @@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
> "Failed to write aux pwmgen bit count\n");
> return max_backlight;
> }
> +
> panel->backlight.edp.vesa.pwmgen_bit_count = pn;
> + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> + panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
>
> max_backlight = (1 << pn) - 1;
>
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Nouveau] [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
@ 2021-05-21 20:03 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-05-21 20:03 UTC (permalink / raw)
To: Lyude Paul, Jani Nikula
Cc: Jani Nikula, Rajeev Nandan, greg.depoire, nouveau, intel-gfx,
Lucas De Marchi, open list, dri-devel, Gwan-gyeong Mun,
David Airlie, Uma Shankar, Sean Paul, Anshuman Gupta,
Dave Airlie
On Fri, May 14, 2021 at 02:14:55PM -0400, Lyude Paul wrote:
> Noticed this while moving all of the VESA backlight code in i915 over to
> DRM helpers: it would appear that we calculate the frequency value we want
> to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
> actually changes during runtime. So, let's simplify things by just caching
> this value in intel_panel.backlight, and re-writing it as-needed.
>
> Changes since v1:
> * Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
> DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
This looks okay to me now... Jani, agree?
>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Dave Airlie <airlied@gmail.com>
> Cc: greg.depoire@gmail.com
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> .../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
> 2 files changed, 20 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9c0adfc60c6f..7054a37363fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -311,6 +311,7 @@ struct intel_panel {
> union {
> struct {
> u8 pwmgen_bit_count;
> + u8 pwm_freq_pre_divider;
> } vesa;
> struct {
> bool sdr_uses_aux;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 8e9ac9ba1d38..68bfe50ada59 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
> }
> }
>
> -/*
> - * Set PWM Frequency divider to match desired frequency in vbt.
> - * The PWM Frequency is calculated as 27Mhz / (F x P).
> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> - */
> -static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
> -{
> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
> - int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
> -
> - freq = dev_priv->vbt.backlight.pwm_freq_hz;
> - if (!freq) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Use panel default backlight frequency\n");
> - return false;
> - }
> -
> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> - fxp_actual = f << pn;
> -
> - /* Ensure frequency is within 25% of desired value */
> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> -
> - if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
> - drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
> - return false;
> - }
> -
> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
> - DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Failed to write aux backlight freq\n");
> - return false;
> - }
> - return true;
> -}
> -
> static void
> intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state, u32 level)
> @@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> break;
> }
>
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> - if (intel_dp_aux_vesa_set_pwm_freq(connector))
> + if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
> + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
> + panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
> new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> + else
> + drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
> + }
>
> if (new_dpcd_buf != dpcd_buf) {
> if (drm_dp_dpcd_writeb(&intel_dp->aux,
> @@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
> false);
> }
>
> +/*
> + * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
> + * The PWM Frequency is calculated as 27Mhz / (F x P).
> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> + */
> static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> @@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
> pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>
> + /* Ensure frequency is within 25% of desired value */
> fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> +
> if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> drm_dbg_kms(&i915->drm,
> "VBT defined backlight frequency out of range\n");
> @@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
> "Failed to write aux pwmgen bit count\n");
> return max_backlight;
> }
> +
> panel->backlight.edp.vesa.pwmgen_bit_count = pn;
> + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> + panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
>
> max_backlight = (1 << pn) - 1;
>
> --
> 2.31.1
>
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
@ 2021-05-21 20:03 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-05-21 20:03 UTC (permalink / raw)
To: Lyude Paul, Jani Nikula
Cc: Jani Nikula, Rajeev Nandan, greg.depoire, nouveau, intel-gfx,
Lucas De Marchi, open list, dri-devel, Gwan-gyeong Mun,
David Airlie, Uma Shankar, Sean Paul, Anshuman Gupta,
Dave Airlie
On Fri, May 14, 2021 at 02:14:55PM -0400, Lyude Paul wrote:
> Noticed this while moving all of the VESA backlight code in i915 over to
> DRM helpers: it would appear that we calculate the frequency value we want
> to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
> actually changes during runtime. So, let's simplify things by just caching
> this value in intel_panel.backlight, and re-writing it as-needed.
>
> Changes since v1:
> * Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
> DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
This looks okay to me now... Jani, agree?
>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Dave Airlie <airlied@gmail.com>
> Cc: greg.depoire@gmail.com
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> .../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
> 2 files changed, 20 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9c0adfc60c6f..7054a37363fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -311,6 +311,7 @@ struct intel_panel {
> union {
> struct {
> u8 pwmgen_bit_count;
> + u8 pwm_freq_pre_divider;
> } vesa;
> struct {
> bool sdr_uses_aux;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 8e9ac9ba1d38..68bfe50ada59 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
> }
> }
>
> -/*
> - * Set PWM Frequency divider to match desired frequency in vbt.
> - * The PWM Frequency is calculated as 27Mhz / (F x P).
> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> - */
> -static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
> -{
> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
> - int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
> -
> - freq = dev_priv->vbt.backlight.pwm_freq_hz;
> - if (!freq) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Use panel default backlight frequency\n");
> - return false;
> - }
> -
> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> - fxp_actual = f << pn;
> -
> - /* Ensure frequency is within 25% of desired value */
> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> -
> - if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
> - drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
> - return false;
> - }
> -
> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
> - DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Failed to write aux backlight freq\n");
> - return false;
> - }
> - return true;
> -}
> -
> static void
> intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state, u32 level)
> @@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> break;
> }
>
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> - if (intel_dp_aux_vesa_set_pwm_freq(connector))
> + if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
> + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
> + panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
> new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> + else
> + drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
> + }
>
> if (new_dpcd_buf != dpcd_buf) {
> if (drm_dp_dpcd_writeb(&intel_dp->aux,
> @@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
> false);
> }
>
> +/*
> + * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
> + * The PWM Frequency is calculated as 27Mhz / (F x P).
> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> + */
> static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> @@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
> pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>
> + /* Ensure frequency is within 25% of desired value */
> fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> +
> if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> drm_dbg_kms(&i915->drm,
> "VBT defined backlight frequency out of range\n");
> @@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
> "Failed to write aux pwmgen bit count\n");
> return max_backlight;
> }
> +
> panel->backlight.edp.vesa.pwmgen_bit_count = pn;
> + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> + panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
>
> max_backlight = (1 << pn) - 1;
>
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Intel-gfx] [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
@ 2021-05-21 20:03 ` Rodrigo Vivi
0 siblings, 0 replies; 62+ messages in thread
From: Rodrigo Vivi @ 2021-05-21 20:03 UTC (permalink / raw)
To: Lyude Paul, Jani Nikula
Cc: Jani Nikula, Rajeev Nandan, greg.depoire, nouveau, intel-gfx,
Lucas De Marchi, open list, dri-devel, David Airlie, Sean Paul,
Dave Airlie
On Fri, May 14, 2021 at 02:14:55PM -0400, Lyude Paul wrote:
> Noticed this while moving all of the VESA backlight code in i915 over to
> DRM helpers: it would appear that we calculate the frequency value we want
> to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
> actually changes during runtime. So, let's simplify things by just caching
> this value in intel_panel.backlight, and re-writing it as-needed.
>
> Changes since v1:
> * Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
> DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
This looks okay to me now... Jani, agree?
>
> Signed-off-by: Lyude Paul <lyude@redhat.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Cc: Dave Airlie <airlied@gmail.com>
> Cc: greg.depoire@gmail.com
> ---
> .../drm/i915/display/intel_display_types.h | 1 +
> .../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
> 2 files changed, 20 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9c0adfc60c6f..7054a37363fb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -311,6 +311,7 @@ struct intel_panel {
> union {
> struct {
> u8 pwmgen_bit_count;
> + u8 pwm_freq_pre_divider;
> } vesa;
> struct {
> bool sdr_uses_aux;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 8e9ac9ba1d38..68bfe50ada59 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
> }
> }
>
> -/*
> - * Set PWM Frequency divider to match desired frequency in vbt.
> - * The PWM Frequency is calculated as 27Mhz / (F x P).
> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> - */
> -static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
> -{
> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
> - struct intel_dp *intel_dp = intel_attached_dp(connector);
> - const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
> - int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
> -
> - freq = dev_priv->vbt.backlight.pwm_freq_hz;
> - if (!freq) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Use panel default backlight frequency\n");
> - return false;
> - }
> -
> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
> - fxp_actual = f << pn;
> -
> - /* Ensure frequency is within 25% of desired value */
> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> -
> - if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
> - drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
> - return false;
> - }
> -
> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
> - DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
> - drm_dbg_kms(&dev_priv->drm,
> - "Failed to write aux backlight freq\n");
> - return false;
> - }
> - return true;
> -}
> -
> static void
> intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state, u32 level)
> @@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
> break;
> }
>
> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> - if (intel_dp_aux_vesa_set_pwm_freq(connector))
> + if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
> + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
> + panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
> new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
> + else
> + drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
> + }
>
> if (new_dpcd_buf != dpcd_buf) {
> if (drm_dp_dpcd_writeb(&intel_dp->aux,
> @@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
> false);
> }
>
> +/*
> + * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
> + * The PWM Frequency is calculated as 27Mhz / (F x P).
> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
> + */
> static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
> {
> struct drm_i915_private *i915 = to_i915(connector->base.dev);
> @@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
> pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
> pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>
> + /* Ensure frequency is within 25% of desired value */
> fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
> fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
> +
> if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
> drm_dbg_kms(&i915->drm,
> "VBT defined backlight frequency out of range\n");
> @@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
> "Failed to write aux pwmgen bit count\n");
> return max_backlight;
> }
> +
> panel->backlight.edp.vesa.pwmgen_bit_count = pn;
> + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
> + panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
>
> max_backlight = (1 << pn) - 1;
>
> --
> 2.31.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
2021-05-21 20:03 ` [Nouveau] " Rodrigo Vivi
(?)
(?)
@ 2021-06-01 19:13 ` Jani Nikula
-1 siblings, 0 replies; 62+ messages in thread
From: Jani Nikula @ 2021-06-01 19:13 UTC (permalink / raw)
To: Rodrigo Vivi, Lyude Paul
Cc: intel-gfx, dri-devel, nouveau, Rajeev Nandan, greg.depoire,
David Airlie, Lucas De Marchi, open list, Anshuman Gupta,
Uma Shankar, Sean Paul, Dave Airlie, Gwan-gyeong Mun
On Fri, 21 May 2021, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Fri, May 14, 2021 at 02:14:55PM -0400, Lyude Paul wrote:
>> Noticed this while moving all of the VESA backlight code in i915 over to
>> DRM helpers: it would appear that we calculate the frequency value we want
>> to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
>> actually changes during runtime. So, let's simplify things by just caching
>> this value in intel_panel.backlight, and re-writing it as-needed.
>>
>> Changes since v1:
>> * Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
>> DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
>
> This looks okay to me now... Jani, agree?
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>>
>> Signed-off-by: Lyude Paul <lyude@redhat.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Dave Airlie <airlied@gmail.com>
>> Cc: greg.depoire@gmail.com
>> ---
>> .../drm/i915/display/intel_display_types.h | 1 +
>> .../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
>> 2 files changed, 20 insertions(+), 46 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 9c0adfc60c6f..7054a37363fb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -311,6 +311,7 @@ struct intel_panel {
>> union {
>> struct {
>> u8 pwmgen_bit_count;
>> + u8 pwm_freq_pre_divider;
>> } vesa;
>> struct {
>> bool sdr_uses_aux;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> index 8e9ac9ba1d38..68bfe50ada59 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> @@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
>> }
>> }
>>
>> -/*
>> - * Set PWM Frequency divider to match desired frequency in vbt.
>> - * The PWM Frequency is calculated as 27Mhz / (F x P).
>> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
>> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
>> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
>> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
>> - */
>> -static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
>> -{
>> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> - struct intel_dp *intel_dp = intel_attached_dp(connector);
>> - const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
>> - int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
>> -
>> - freq = dev_priv->vbt.backlight.pwm_freq_hz;
>> - if (!freq) {
>> - drm_dbg_kms(&dev_priv->drm,
>> - "Use panel default backlight frequency\n");
>> - return false;
>> - }
>> -
>> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
>> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
>> - fxp_actual = f << pn;
>> -
>> - /* Ensure frequency is within 25% of desired value */
>> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
>> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
>> -
>> - if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
>> - drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
>> - return false;
>> - }
>> -
>> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
>> - DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
>> - drm_dbg_kms(&dev_priv->drm,
>> - "Failed to write aux backlight freq\n");
>> - return false;
>> - }
>> - return true;
>> -}
>> -
>> static void
>> intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
>> const struct drm_connector_state *conn_state, u32 level)
>> @@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
>> break;
>> }
>>
>> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
>> - if (intel_dp_aux_vesa_set_pwm_freq(connector))
>> + if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
>> + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
>> + panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
>> new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
>> + else
>> + drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
>> + }
>>
>> if (new_dpcd_buf != dpcd_buf) {
>> if (drm_dp_dpcd_writeb(&intel_dp->aux,
>> @@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
>> false);
>> }
>>
>> +/*
>> + * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
>> + * The PWM Frequency is calculated as 27Mhz / (F x P).
>> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
>> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
>> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
>> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
>> + */
>> static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
>> {
>> struct drm_i915_private *i915 = to_i915(connector->base.dev);
>> @@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
>> pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>> pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>>
>> + /* Ensure frequency is within 25% of desired value */
>> fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
>> fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
>> +
>> if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
>> drm_dbg_kms(&i915->drm,
>> "VBT defined backlight frequency out of range\n");
>> @@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
>> "Failed to write aux pwmgen bit count\n");
>> return max_backlight;
>> }
>> +
>> panel->backlight.edp.vesa.pwmgen_bit_count = pn;
>> + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
>> + panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
>>
>> max_backlight = (1 << pn) - 1;
>>
>> --
>> 2.31.1
>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Nouveau] [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
@ 2021-06-01 19:13 ` Jani Nikula
0 siblings, 0 replies; 62+ messages in thread
From: Jani Nikula @ 2021-06-01 19:13 UTC (permalink / raw)
To: Rodrigo Vivi, Lyude Paul
Cc: Rajeev Nandan, greg.depoire, nouveau, intel-gfx, Lucas De Marchi,
open list, dri-devel, Gwan-gyeong Mun, David Airlie, Uma Shankar,
Sean Paul, Anshuman Gupta, Dave Airlie
On Fri, 21 May 2021, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Fri, May 14, 2021 at 02:14:55PM -0400, Lyude Paul wrote:
>> Noticed this while moving all of the VESA backlight code in i915 over to
>> DRM helpers: it would appear that we calculate the frequency value we want
>> to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
>> actually changes during runtime. So, let's simplify things by just caching
>> this value in intel_panel.backlight, and re-writing it as-needed.
>>
>> Changes since v1:
>> * Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
>> DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
>
> This looks okay to me now... Jani, agree?
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>>
>> Signed-off-by: Lyude Paul <lyude@redhat.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Dave Airlie <airlied@gmail.com>
>> Cc: greg.depoire@gmail.com
>> ---
>> .../drm/i915/display/intel_display_types.h | 1 +
>> .../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
>> 2 files changed, 20 insertions(+), 46 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 9c0adfc60c6f..7054a37363fb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -311,6 +311,7 @@ struct intel_panel {
>> union {
>> struct {
>> u8 pwmgen_bit_count;
>> + u8 pwm_freq_pre_divider;
>> } vesa;
>> struct {
>> bool sdr_uses_aux;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> index 8e9ac9ba1d38..68bfe50ada59 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> @@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
>> }
>> }
>>
>> -/*
>> - * Set PWM Frequency divider to match desired frequency in vbt.
>> - * The PWM Frequency is calculated as 27Mhz / (F x P).
>> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
>> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
>> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
>> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
>> - */
>> -static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
>> -{
>> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> - struct intel_dp *intel_dp = intel_attached_dp(connector);
>> - const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
>> - int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
>> -
>> - freq = dev_priv->vbt.backlight.pwm_freq_hz;
>> - if (!freq) {
>> - drm_dbg_kms(&dev_priv->drm,
>> - "Use panel default backlight frequency\n");
>> - return false;
>> - }
>> -
>> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
>> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
>> - fxp_actual = f << pn;
>> -
>> - /* Ensure frequency is within 25% of desired value */
>> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
>> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
>> -
>> - if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
>> - drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
>> - return false;
>> - }
>> -
>> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
>> - DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
>> - drm_dbg_kms(&dev_priv->drm,
>> - "Failed to write aux backlight freq\n");
>> - return false;
>> - }
>> - return true;
>> -}
>> -
>> static void
>> intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
>> const struct drm_connector_state *conn_state, u32 level)
>> @@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
>> break;
>> }
>>
>> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
>> - if (intel_dp_aux_vesa_set_pwm_freq(connector))
>> + if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
>> + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
>> + panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
>> new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
>> + else
>> + drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
>> + }
>>
>> if (new_dpcd_buf != dpcd_buf) {
>> if (drm_dp_dpcd_writeb(&intel_dp->aux,
>> @@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
>> false);
>> }
>>
>> +/*
>> + * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
>> + * The PWM Frequency is calculated as 27Mhz / (F x P).
>> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
>> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
>> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
>> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
>> + */
>> static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
>> {
>> struct drm_i915_private *i915 = to_i915(connector->base.dev);
>> @@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
>> pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>> pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>>
>> + /* Ensure frequency is within 25% of desired value */
>> fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
>> fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
>> +
>> if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
>> drm_dbg_kms(&i915->drm,
>> "VBT defined backlight frequency out of range\n");
>> @@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
>> "Failed to write aux pwmgen bit count\n");
>> return max_backlight;
>> }
>> +
>> panel->backlight.edp.vesa.pwmgen_bit_count = pn;
>> + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
>> + panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
>>
>> max_backlight = (1 << pn) - 1;
>>
>> --
>> 2.31.1
>>
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Nouveau mailing list
Nouveau@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/nouveau
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
@ 2021-06-01 19:13 ` Jani Nikula
0 siblings, 0 replies; 62+ messages in thread
From: Jani Nikula @ 2021-06-01 19:13 UTC (permalink / raw)
To: Rodrigo Vivi, Lyude Paul
Cc: Rajeev Nandan, greg.depoire, nouveau, intel-gfx, Lucas De Marchi,
open list, dri-devel, Gwan-gyeong Mun, David Airlie, Uma Shankar,
Sean Paul, Anshuman Gupta, Dave Airlie
On Fri, 21 May 2021, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Fri, May 14, 2021 at 02:14:55PM -0400, Lyude Paul wrote:
>> Noticed this while moving all of the VESA backlight code in i915 over to
>> DRM helpers: it would appear that we calculate the frequency value we want
>> to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
>> actually changes during runtime. So, let's simplify things by just caching
>> this value in intel_panel.backlight, and re-writing it as-needed.
>>
>> Changes since v1:
>> * Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
>> DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
>
> This looks okay to me now... Jani, agree?
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>>
>> Signed-off-by: Lyude Paul <lyude@redhat.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Dave Airlie <airlied@gmail.com>
>> Cc: greg.depoire@gmail.com
>> ---
>> .../drm/i915/display/intel_display_types.h | 1 +
>> .../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
>> 2 files changed, 20 insertions(+), 46 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 9c0adfc60c6f..7054a37363fb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -311,6 +311,7 @@ struct intel_panel {
>> union {
>> struct {
>> u8 pwmgen_bit_count;
>> + u8 pwm_freq_pre_divider;
>> } vesa;
>> struct {
>> bool sdr_uses_aux;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> index 8e9ac9ba1d38..68bfe50ada59 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> @@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
>> }
>> }
>>
>> -/*
>> - * Set PWM Frequency divider to match desired frequency in vbt.
>> - * The PWM Frequency is calculated as 27Mhz / (F x P).
>> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
>> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
>> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
>> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
>> - */
>> -static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
>> -{
>> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> - struct intel_dp *intel_dp = intel_attached_dp(connector);
>> - const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
>> - int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
>> -
>> - freq = dev_priv->vbt.backlight.pwm_freq_hz;
>> - if (!freq) {
>> - drm_dbg_kms(&dev_priv->drm,
>> - "Use panel default backlight frequency\n");
>> - return false;
>> - }
>> -
>> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
>> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
>> - fxp_actual = f << pn;
>> -
>> - /* Ensure frequency is within 25% of desired value */
>> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
>> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
>> -
>> - if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
>> - drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
>> - return false;
>> - }
>> -
>> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
>> - DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
>> - drm_dbg_kms(&dev_priv->drm,
>> - "Failed to write aux backlight freq\n");
>> - return false;
>> - }
>> - return true;
>> -}
>> -
>> static void
>> intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
>> const struct drm_connector_state *conn_state, u32 level)
>> @@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
>> break;
>> }
>>
>> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
>> - if (intel_dp_aux_vesa_set_pwm_freq(connector))
>> + if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
>> + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
>> + panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
>> new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
>> + else
>> + drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
>> + }
>>
>> if (new_dpcd_buf != dpcd_buf) {
>> if (drm_dp_dpcd_writeb(&intel_dp->aux,
>> @@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
>> false);
>> }
>>
>> +/*
>> + * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
>> + * The PWM Frequency is calculated as 27Mhz / (F x P).
>> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
>> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
>> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
>> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
>> + */
>> static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
>> {
>> struct drm_i915_private *i915 = to_i915(connector->base.dev);
>> @@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
>> pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>> pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>>
>> + /* Ensure frequency is within 25% of desired value */
>> fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
>> fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
>> +
>> if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
>> drm_dbg_kms(&i915->drm,
>> "VBT defined backlight frequency out of range\n");
>> @@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
>> "Failed to write aux pwmgen bit count\n");
>> return max_backlight;
>> }
>> +
>> panel->backlight.edp.vesa.pwmgen_bit_count = pn;
>> + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
>> + panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
>>
>> max_backlight = (1 << pn) - 1;
>>
>> --
>> 2.31.1
>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [Intel-gfx] [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations
@ 2021-06-01 19:13 ` Jani Nikula
0 siblings, 0 replies; 62+ messages in thread
From: Jani Nikula @ 2021-06-01 19:13 UTC (permalink / raw)
To: Rodrigo Vivi, Lyude Paul
Cc: Rajeev Nandan, greg.depoire, nouveau, intel-gfx, Lucas De Marchi,
open list, dri-devel, David Airlie, Sean Paul, Dave Airlie
On Fri, 21 May 2021, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Fri, May 14, 2021 at 02:14:55PM -0400, Lyude Paul wrote:
>> Noticed this while moving all of the VESA backlight code in i915 over to
>> DRM helpers: it would appear that we calculate the frequency value we want
>> to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
>> actually changes during runtime. So, let's simplify things by just caching
>> this value in intel_panel.backlight, and re-writing it as-needed.
>>
>> Changes since v1:
>> * Wrap panel->backlight.edp.vesa.pwm_freq_pre_divider in
>> DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP check - Jani
>
> This looks okay to me now... Jani, agree?
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>>
>> Signed-off-by: Lyude Paul <lyude@redhat.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> Cc: Dave Airlie <airlied@gmail.com>
>> Cc: greg.depoire@gmail.com
>> ---
>> .../drm/i915/display/intel_display_types.h | 1 +
>> .../drm/i915/display/intel_dp_aux_backlight.c | 65 ++++++-------------
>> 2 files changed, 20 insertions(+), 46 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 9c0adfc60c6f..7054a37363fb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -311,6 +311,7 @@ struct intel_panel {
>> union {
>> struct {
>> u8 pwmgen_bit_count;
>> + u8 pwm_freq_pre_divider;
>> } vesa;
>> struct {
>> bool sdr_uses_aux;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> index 8e9ac9ba1d38..68bfe50ada59 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
>> @@ -373,50 +373,6 @@ intel_dp_aux_vesa_set_backlight(const struct drm_connector_state *conn_state,
>> }
>> }
>>
>> -/*
>> - * Set PWM Frequency divider to match desired frequency in vbt.
>> - * The PWM Frequency is calculated as 27Mhz / (F x P).
>> - * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
>> - * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
>> - * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
>> - * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
>> - */
>> -static bool intel_dp_aux_vesa_set_pwm_freq(struct intel_connector *connector)
>> -{
>> - struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
>> - struct intel_dp *intel_dp = intel_attached_dp(connector);
>> - const u8 pn = connector->panel.backlight.edp.vesa.pwmgen_bit_count;
>> - int freq, fxp, f, fxp_actual, fxp_min, fxp_max;
>> -
>> - freq = dev_priv->vbt.backlight.pwm_freq_hz;
>> - if (!freq) {
>> - drm_dbg_kms(&dev_priv->drm,
>> - "Use panel default backlight frequency\n");
>> - return false;
>> - }
>> -
>> - fxp = DIV_ROUND_CLOSEST(KHz(DP_EDP_BACKLIGHT_FREQ_BASE_KHZ), freq);
>> - f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
>> - fxp_actual = f << pn;
>> -
>> - /* Ensure frequency is within 25% of desired value */
>> - fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
>> - fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
>> -
>> - if (fxp_min > fxp_actual || fxp_actual > fxp_max) {
>> - drm_dbg_kms(&dev_priv->drm, "Actual frequency out of range\n");
>> - return false;
>> - }
>> -
>> - if (drm_dp_dpcd_writeb(&intel_dp->aux,
>> - DP_EDP_BACKLIGHT_FREQ_SET, (u8) f) < 0) {
>> - drm_dbg_kms(&dev_priv->drm,
>> - "Failed to write aux backlight freq\n");
>> - return false;
>> - }
>> - return true;
>> -}
>> -
>> static void
>> intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
>> const struct drm_connector_state *conn_state, u32 level)
>> @@ -459,9 +415,13 @@ intel_dp_aux_vesa_enable_backlight(const struct intel_crtc_state *crtc_state,
>> break;
>> }
>>
>> - if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
>> - if (intel_dp_aux_vesa_set_pwm_freq(connector))
>> + if (panel->backlight.edp.vesa.pwm_freq_pre_divider) {
>> + if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_EDP_BACKLIGHT_FREQ_SET,
>> + panel->backlight.edp.vesa.pwm_freq_pre_divider) == 1)
>> new_dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
>> + else
>> + drm_dbg_kms(&i915->drm, "Failed to write aux backlight frequency\n");
>> + }
>>
>> if (new_dpcd_buf != dpcd_buf) {
>> if (drm_dp_dpcd_writeb(&intel_dp->aux,
>> @@ -482,6 +442,14 @@ static void intel_dp_aux_vesa_disable_backlight(const struct drm_connector_state
>> false);
>> }
>>
>> +/*
>> + * Compute PWM frequency divider value based off the frequency provided to us by the vbt.
>> + * The PWM Frequency is calculated as 27Mhz / (F x P).
>> + * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
>> + * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
>> + * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
>> + * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
>> + */
>> static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connector)
>> {
>> struct drm_i915_private *i915 = to_i915(connector->base.dev);
>> @@ -533,8 +501,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
>> pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>> pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
>>
>> + /* Ensure frequency is within 25% of desired value */
>> fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
>> fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
>> +
>> if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
>> drm_dbg_kms(&i915->drm,
>> "VBT defined backlight frequency out of range\n");
>> @@ -555,7 +525,10 @@ static u32 intel_dp_aux_vesa_calc_max_backlight(struct intel_connector *connecto
>> "Failed to write aux pwmgen bit count\n");
>> return max_backlight;
>> }
>> +
>> panel->backlight.edp.vesa.pwmgen_bit_count = pn;
>> + if (intel_dp->edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP)
>> + panel->backlight.edp.vesa.pwm_freq_pre_divider = f;
>>
>> max_backlight = (1 << pn) - 1;
>>
>> --
>> 2.31.1
>>
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 62+ messages in thread
end of thread, other threads:[~2021-06-01 19:13 UTC | newest]
Thread overview: 62+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-14 18:14 [Nouveau] [PATCH v6 0/9] drm: Extract DPCD backlight helpers from i915, add support in nouveau Lyude Paul
2021-05-14 18:14 ` [Intel-gfx] " Lyude Paul
2021-05-14 18:14 ` Lyude Paul
2021-05-14 18:14 ` [PATCH v6 1/9] drm/i915/dpcd_bl: Remove redundant AUX backlight frequency calculations Lyude Paul
2021-05-14 18:14 ` [Intel-gfx] " Lyude Paul
2021-05-14 18:14 ` Lyude Paul
2021-05-14 18:14 ` [Nouveau] " Lyude Paul
2021-05-21 20:03 ` Rodrigo Vivi
2021-05-21 20:03 ` [Intel-gfx] " Rodrigo Vivi
2021-05-21 20:03 ` Rodrigo Vivi
2021-05-21 20:03 ` [Nouveau] " Rodrigo Vivi
2021-06-01 19:13 ` Jani Nikula
2021-06-01 19:13 ` [Intel-gfx] " Jani Nikula
2021-06-01 19:13 ` Jani Nikula
2021-06-01 19:13 ` [Nouveau] " Jani Nikula
2021-05-14 18:14 ` [PATCH v6 2/9] drm/i915/dpcd_bl: Handle drm_dpcd_read/write() return values correctly Lyude Paul
2021-05-14 18:14 ` [Intel-gfx] " Lyude Paul
2021-05-14 18:14 ` Lyude Paul
2021-05-14 18:14 ` [Nouveau] " Lyude Paul
2021-05-14 18:14 ` [PATCH v6 3/9] drm/i915/dpcd_bl: Cleanup intel_dp_aux_vesa_enable_backlight() a bit Lyude Paul
2021-05-14 18:14 ` [Intel-gfx] " Lyude Paul
2021-05-14 18:14 ` Lyude Paul
2021-05-14 18:14 ` [Nouveau] " Lyude Paul
2021-05-14 18:14 ` [PATCH v6 4/9] drm/i915/dpcd_bl: Cache some backlight capabilities in intel_panel.backlight Lyude Paul
2021-05-14 18:14 ` [Intel-gfx] " Lyude Paul
2021-05-14 18:14 ` Lyude Paul
2021-05-14 18:14 ` [Nouveau] " Lyude Paul
2021-05-14 18:14 ` [PATCH v6 5/9] drm/i915/dpcd_bl: Move VESA backlight enabling code closer together Lyude Paul
2021-05-14 18:14 ` [Intel-gfx] " Lyude Paul
2021-05-14 18:14 ` Lyude Paul
2021-05-14 18:14 ` [Nouveau] " Lyude Paul
2021-05-14 18:15 ` [PATCH v6 6/9] drm/i915/dpcd_bl: Return early in vesa_calc_max_backlight if we can't read PWMGEN_BIT_COUNT Lyude Paul
2021-05-14 18:15 ` [Intel-gfx] " Lyude Paul
2021-05-14 18:15 ` Lyude Paul
2021-05-14 18:15 ` [Nouveau] " Lyude Paul
2021-05-14 18:15 ` [PATCH v6 7/9] drm/i915/dpcd_bl: Print return codes for VESA backlight failures Lyude Paul
2021-05-14 18:15 ` [Intel-gfx] " Lyude Paul
2021-05-14 18:15 ` Lyude Paul
2021-05-14 18:15 ` [Nouveau] " Lyude Paul
2021-05-14 18:15 ` [PATCH v6 8/9] drm/dp: Extract i915's eDP backlight code into DRM helpers Lyude Paul
2021-05-14 18:15 ` [Intel-gfx] " Lyude Paul
2021-05-14 18:15 ` Lyude Paul
2021-05-14 18:15 ` [Nouveau] " Lyude Paul
2021-05-21 20:02 ` Rodrigo Vivi
2021-05-21 20:02 ` [Intel-gfx] " Rodrigo Vivi
2021-05-21 20:02 ` Rodrigo Vivi
2021-05-21 20:02 ` [Nouveau] " Rodrigo Vivi
2021-05-14 18:15 ` [PATCH v6 9/9] drm/nouveau/kms/nv50-: Add basic DPCD backlight support for nouveau Lyude Paul
2021-05-14 18:15 ` [Intel-gfx] " Lyude Paul
2021-05-14 18:15 ` Lyude Paul
2021-05-14 18:15 ` [Nouveau] " Lyude Paul
2021-05-14 18:32 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev8) Patchwork
2021-05-14 18:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-14 19:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-15 4:09 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-05-17 17:01 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev9) Patchwork
2021-05-17 17:03 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-17 17:31 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-05-18 19:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm: Extract DPCD backlight helpers from i915, add support in nouveau (rev10) Patchwork
2021-05-18 19:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-18 20:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-19 23:29 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.