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* [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support
@ 2021-05-15  3:10 Matt Roper
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 01/23] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
                   ` (26 more replies)
  0 siblings, 27 replies; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

Many of the ALD-P patches have received review and landed on drm-tip
now.  Let's rebase and resend the remaining patches that still need
review (or have prereq patches that need review).

Previous version of the series was
        https://patchwork.freedesktop.org/series/89899/#rev2

Aside from general rebasing, this version also updates the DP
translation tables in since the bspec was just updated with new values.

Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>

Anusha Srivatsa (4):
  drm/i915/adl_p: Setup ports/phys
  drm/i915/adl_p: Add PLL Support
  drm/i915/adlp: Add PIPE_MISC2 programming
  drm/i915/adl_p: Update memory bandwidth parameters

Gwan-gyeong Mun (4):
  drm/i915/display: Replace dc3co_enabled with dc3co_exitline on
    intel_psr struct
  drm/i915/display: Remove a redundant function argument from
    intel_psr_enable_source()
  drm/i915/display: Add PSR interrupt error check function
  drm/i915/display: Introduce new intel_psr_pause/resume function

Imre Deak (1):
  drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL

José Roberto de Souza (3):
  drm/i915/adl_p: Handle TC cold
  drm/i915/adl_p: Implement TC sequences
  drm/i915/adl_p: Don't config MBUS and DBUF during display
    initialization

Manasi Navare (1):
  drm/i915/xelpd: Add VRR guardband for VRR CTL

Matt Roper (2):
  drm/i915/xelpd: Enhanced pipe underrun reporting
  drm/i915/adl_p: Add dedicated SAGV watermarks

Mika Kahola (2):
  drm/i915/adl_p: Tx escape clock with DSI
  drm/i915/adl_p: Define and use ADL-P specific DP translation tables

Vandita Kulkarni (5):
  drm/i915/xelpd: Support DP1.4 compression BPPs
  drm/i915/xelpd: Calculate VDSC RC parameters
  drm/i915/xelpd: Add rc_qp_table for rcparams calculation
  drm/i915/adl_p: Add ddb allocation support
  drm/i915/adl_p: MBUS programming

Ville Syrjälä (1):
  drm/i915: Introduce MBUS relative dbuf offsets

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/icl_dsi.c        |  21 +-
 drivers/gpu/drm/i915/display/intel_atomic.c   |  20 ++
 drivers/gpu/drm/i915/display/intel_atomic.h   |   1 +
 drivers/gpu/drm/i915/display/intel_bw.c       |   2 +-
 drivers/gpu/drm/i915/display/intel_ddi.c      |  43 ++-
 .../drm/i915/display/intel_ddi_buf_trans.c    |  53 +++
 .../drm/i915/display/intel_ddi_buf_trans.h    |   4 +
 drivers/gpu/drm/i915/display/intel_display.c  |  77 ++++-
 .../drm/i915/display/intel_display_power.c    |   9 +-
 .../drm/i915/display/intel_display_types.h    |   5 +-
 drivers/gpu/drm/i915/display/intel_dp.c       |   1 +
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c |  69 +++-
 .../drm/i915/display/intel_fifo_underrun.c    |  57 +++-
 drivers/gpu/drm/i915/display/intel_psr.c      | 131 ++++++--
 drivers/gpu/drm/i915/display/intel_psr.h      |   2 +
 .../gpu/drm/i915/display/intel_qp_tables.c    | 311 ++++++++++++++++++
 .../gpu/drm/i915/display/intel_qp_tables.h    |  14 +
 drivers/gpu/drm/i915/display/intel_tc.c       | 134 +++++++-
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 105 +++++-
 drivers/gpu/drm/i915/display/intel_vrr.c      |  58 +++-
 drivers/gpu/drm/i915/i915_drv.h               |   5 +
 drivers/gpu/drm/i915/i915_irq.c               |  19 +-
 drivers/gpu/drm/i915/i915_irq.h               |   1 +
 drivers/gpu/drm/i915/i915_reg.h               | 135 ++++++--
 drivers/gpu/drm/i915/intel_pm.c               | 303 ++++++++++++++++-
 drivers/gpu/drm/i915/intel_pm.h               |   2 +-
 27 files changed, 1440 insertions(+), 143 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h

-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 01/23] drm/i915/xelpd: Enhanced pipe underrun reporting
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17  6:52   ` Lisovskiy, Stanislav
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
                   ` (25 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

XE_LPD brings enhanced underrun recovery:  the hardware can somewhat
mitigate underruns by using an interpolated replacement pixel (soft
underrun) or the previous pixel (hard underrun).  Furthermore, underruns
can now be caused downstream by the port, even if the pipe itself is
operating properly.  The interrupt register and PIPE_STATUS register
give us extra bits to recognize hard/soft underruns and determine
whether the underrun was caused by the port, so we'll use that
information to print some more descriptive errors when underruns occur.

v2:
 - Keep ICL's PIPE_STATUS defined separately from the old GMCH pipe
   status register.  (Ville)
 - Only read/clear the PIPE_STATUS register on platforms with
   display ver >= 11. (Lucas)
v3:
 - Actually enable+unmask all the new underrun interrupts, clear stale
   bits out from PIPE_STATUS before enabling the interrupts, report all
   FIFO underruns errors at once, rename a bunch of stuff to unconfuse
   vs. PIPESTAT. (Ville)

Bspec: 50335
Bspec: 50366
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../drm/i915/display/intel_fifo_underrun.c    | 57 +++++++++++++++++--
 drivers/gpu/drm/i915/i915_irq.c               | 19 ++++++-
 drivers/gpu/drm/i915/i915_irq.h               |  1 +
 drivers/gpu/drm/i915/i915_reg.h               |  9 +++
 4 files changed, 77 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index 3315aa1d4d5a..eb841960840d 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -185,15 +185,34 @@ static void ivb_set_fifo_underrun_reporting(struct drm_device *dev,
 	}
 }
 
+static u32
+icl_pipe_status_underrun_mask(struct drm_i915_private *dev_priv)
+{
+	u32 mask = PIPE_STATUS_UNDERRUN;
+
+	if (DISPLAY_VER(dev_priv) >= 13)
+		mask |= PIPE_STATUS_SOFT_UNDERRUN_XELPD |
+			PIPE_STATUS_HARD_UNDERRUN_XELPD |
+			PIPE_STATUS_PORT_UNDERRUN_XELPD;
+
+	return mask;
+}
+
 static void bdw_set_fifo_underrun_reporting(struct drm_device *dev,
 					    enum pipe pipe, bool enable)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
+	u32 mask = gen8_de_pipe_underrun_mask(dev_priv);
 
-	if (enable)
-		bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
-	else
-		bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
+	if (enable) {
+		if (DISPLAY_VER(dev_priv) >= 11)
+			intel_de_write(dev_priv, ICL_PIPESTATUS(pipe),
+				       icl_pipe_status_underrun_mask(dev_priv));
+
+		bdw_enable_pipe_irq(dev_priv, pipe, mask);
+	} else {
+		bdw_disable_pipe_irq(dev_priv, pipe, mask);
+	}
 }
 
 static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
@@ -373,6 +392,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 					 enum pipe pipe)
 {
 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+	u32 underruns = 0;
 
 	/* We may be called too early in init, thanks BIOS! */
 	if (crtc == NULL)
@@ -383,10 +403,35 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
 	    crtc->cpu_fifo_underrun_disabled)
 		return;
 
+	/*
+	 * Starting with display version 11, the PIPE_STAT register records
+	 * whether an underrun has happened, and on XELPD+, it will also record
+	 * whether the underrun was soft/hard and whether it was triggered by
+	 * the downstream port logic.  We should clear these bits (which use
+	 * write-1-to-clear logic) too.
+	 *
+	 * Note that although the IIR gives us the same underrun and soft/hard
+	 * information, PIPE_STAT is the only place we can find out whether
+	 * the underrun was caused by the downstream port.
+	 */
+	if (DISPLAY_VER(dev_priv) >= 11) {
+		underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) &
+			icl_pipe_status_underrun_mask(dev_priv);
+		intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns);
+	}
+
 	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
 		trace_intel_cpu_fifo_underrun(dev_priv, pipe);
-		drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n",
-			pipe_name(pipe));
+
+		if (DISPLAY_VER(dev_priv) >= 11)
+			drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun: %s%s%s%s\n",
+				pipe_name(pipe),
+				underruns & PIPE_STATUS_SOFT_UNDERRUN_XELPD ? "soft," : "",
+				underruns & PIPE_STATUS_HARD_UNDERRUN_XELPD ? "hard," : "",
+				underruns & PIPE_STATUS_PORT_UNDERRUN_XELPD ? "port," : "",
+				underruns & PIPE_STATUS_UNDERRUN ? "transcoder," : "");
+		else
+			drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
 	}
 
 	intel_fbc_handle_fifo_underrun_irq(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d4611c643446..957d401186d2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2425,6 +2425,17 @@ static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
 		return GEN8_PIPE_PRIMARY_FLIP_DONE;
 }
 
+u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv)
+{
+	u32 mask = GEN8_PIPE_FIFO_UNDERRUN;
+
+	if (DISPLAY_VER(dev_priv) >= 13)
+		mask |= XELPD_PIPE_SOFT_UNDERRUN |
+			XELPD_PIPE_HARD_UNDERRUN;
+
+	return mask;
+}
+
 static irqreturn_t
 gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 {
@@ -2536,7 +2547,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
 		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
 			hsw_pipe_crc_irq_handler(dev_priv, pipe);
 
-		if (iir & GEN8_PIPE_FIFO_UNDERRUN)
+		if (iir & gen8_de_pipe_underrun_mask(dev_priv))
 			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
 
 		fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
@@ -3173,7 +3184,8 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask)
 {
 	struct intel_uncore *uncore = &dev_priv->uncore;
-	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
+	u32 extra_ier = GEN8_PIPE_VBLANK |
+		gen8_de_pipe_underrun_mask(dev_priv) |
 		gen8_de_pipe_flip_done_mask(dev_priv);
 	enum pipe pipe;
 
@@ -3757,7 +3769,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
 	}
 
 	de_pipe_enables = de_pipe_masked |
-		GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
+		GEN8_PIPE_VBLANK |
+		gen8_de_pipe_underrun_mask(dev_priv) |
 		gen8_de_pipe_flip_done_mask(dev_priv);
 
 	de_port_enables = de_port_masked;
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 25f25cd95818..db34d5dbe402 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -100,6 +100,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask);
 void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
 				     u8 pipe_mask);
+u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv);
 
 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
 				     ktime_t *vblank_time, bool in_vblank_irq);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 089b5a59bed3..506a5aa0646b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6158,6 +6158,13 @@ enum {
 #define   SKL_BOTTOM_COLOR_CSC_ENABLE	(1 << 30)
 #define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
 
+#define _ICL_PIPE_A_STATUS			0x70058
+#define ICL_PIPESTATUS(pipe)			_MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
+#define   PIPE_STATUS_UNDERRUN				REG_BIT(31)
+#define   PIPE_STATUS_SOFT_UNDERRUN_XELPD		REG_BIT(28)
+#define   PIPE_STATUS_HARD_UNDERRUN_XELPD		REG_BIT(27)
+#define   PIPE_STATUS_PORT_UNDERRUN_XELPD		REG_BIT(26)
+
 #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
 #define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
 #define   PIPEB_HLINE_INT_EN			(1 << 28)
@@ -7814,6 +7821,8 @@ enum {
 #define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
 #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
 #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
+#define  XELPD_PIPE_SOFT_UNDERRUN	(1 << 22)
+#define  XELPD_PIPE_HARD_UNDERRUN	(1 << 21)
 #define  GEN8_PIPE_CURSOR_FAULT		(1 << 10)
 #define  GEN8_PIPE_SPRITE_FAULT		(1 << 9)
 #define  GEN8_PIPE_PRIMARY_FAULT	(1 << 8)
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4 compression BPPs
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 01/23] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17 15:18   ` Jani Nikula
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 03/23] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
                   ` (24 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Support compression BPPs from bpc to uncompressed BPP -1.
So far we have 8,10,12 as valid compressed BPPS now the
support is extended.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 5c9222283044..16cdec9a4aa3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -521,6 +521,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 	drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 		    max_bpp_small_joiner_ram);
 
+
 	/*
 	 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 	 * check, output bpp from small joiner RAM check)
-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 03/23] drm/i915/xelpd: Calculate VDSC RC parameters
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 01/23] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-18 18:06   ` Navare, Manasi
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 04/23] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
                   ` (23 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: Juha-Pekka Heikkil, Mohammed Khajapasha

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Add methods to calculate rc parameters for all bpps, against the fixed
arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444
formats.  Our hw doesn't support YUV compression yet.  The calculations
used here are from VESA C model for DSC 1.1

v2:
 - Checkpatch fixes

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Juha-Pekka Heikkil <juha-pekka.heikkila@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Mohammed Khajapasha <mohammed.khajapasha@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 97 ++++++++++++++++++++---
 1 file changed, 87 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index efc3184d8315..02e86d2be395 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -5,7 +5,7 @@
  * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
  *         Manasi Navare <manasi.d.navare@intel.com>
  */
-
+#include <linux/limits.h>
 #include "i915_drv.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
@@ -373,12 +373,74 @@ static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state)
 	return true;
 }
 
+static void
+calculate_rc_params(struct rc_parameters *rc,
+		    struct drm_dsc_config *vdsc_cfg)
+{
+	int bpc = vdsc_cfg->bits_per_component;
+	int bpp = vdsc_cfg->bits_per_pixel >> 4;
+	int ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };
+	int ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
+	int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
+	int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
+	int qp_bpc_modifier = (bpc - 8) * 2;
+	u32 res, buf_i;
+
+	if (vdsc_cfg->slice_height >= 8)
+		rc->first_line_bpg_offset =
+			12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
+	else
+		rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
+
+	/* Our hw supports only 444 modes as of today */
+	if (bpp >= 12)
+		rc->initial_offset = 2048;
+	else if (bpp >= 10)
+		rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
+	else if (bpp >= 8)
+		rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
+	else
+		rc->initial_offset = 6144;
+
+	/* initial_xmit_delay = rc_model_size/2/compression_bpp */
+	rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
+
+	rc->flatness_min_qp = 3 + qp_bpc_modifier;
+	rc->flatness_max_qp = 12 + qp_bpc_modifier;
+
+	rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
+	rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
+
+	for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
+		/* Calculate range_bgp_offset */
+		if (bpp <= 6) {
+			rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
+		} else if (bpp <= 8) {
+			res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
+			rc->rc_range_params[buf_i].range_bpg_offset =
+								ofs_und6[buf_i] + res;
+		} else if (bpp <= 12) {
+			rc->rc_range_params[buf_i].range_bpg_offset =
+								ofs_und8[buf_i];
+		} else if (bpp <= 15) {
+			res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
+			rc->rc_range_params[buf_i].range_bpg_offset =
+								ofs_und12[buf_i] + res;
+		} else {
+			rc->rc_range_params[buf_i].range_bpg_offset =
+								ofs_und15[buf_i];
+		}
+	}
+}
+
 int intel_dsc_compute_params(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config)
 {
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
 	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
 	const struct rc_parameters *rc_params;
+	struct rc_parameters *rc = NULL;
 	u8 i = 0;
 
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
@@ -413,9 +475,24 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
 		vdsc_cfg->rc_buf_thresh[13] = 0x7D;
 	}
 
-	rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component);
-	if (!rc_params)
-		return -EINVAL;
+	/*
+	 * From XE_LPD onwards we supports compression bpps in steps of 1
+	 * upto uncompressed bpp-1, hence add calculations for all the rc
+	 * parameters
+	 */
+	if (DISPLAY_VER(dev_priv) >= 13) {
+		rc = kmalloc(sizeof(*rc), GFP_KERNEL);
+		if (!rc)
+			return -ENOMEM;
+
+		calculate_rc_params(rc, vdsc_cfg);
+		rc_params = rc;
+	} else {
+		rc_params = get_rc_params(compressed_bpp,
+					  vdsc_cfg->bits_per_component);
+		if (!rc_params)
+			return -EINVAL;
+	}
 
 	vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
 	vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
@@ -441,20 +518,20 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
 
 	/*
 	 * BitsPerComponent value determines mux_word_size:
-	 * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
-	 * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
-	 * 48 bits
+	 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
+	 * 48 bits otherwise 64
 	 */
-	if (vdsc_cfg->bits_per_component == 8 ||
-	    vdsc_cfg->bits_per_component == 10)
+	if (vdsc_cfg->bits_per_component <= 10)
 		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
-	else if (vdsc_cfg->bits_per_component == 12)
+	else
 		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
 
 	/* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
 	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
 
+	kfree(rc);
+
 	return 0;
 }
 
-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 04/23] drm/i915/xelpd: Add rc_qp_table for rcparams calculation
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (2 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 03/23] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 05/23] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
                   ` (22 subsequent siblings)
  26 siblings, 0 replies; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by
the VESA C model for DSC 1.1

v2:
 - Add include guard to header (Jani)
 - Move the big tables to a .c file (Chris, Jani, Lucas)
v3:
 - Make tables 'static const' and add lookup functions to index into
   them.  (Jani)
v3.1:
 - Include missing .h file.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/Makefile                 |   1 +
 .../gpu/drm/i915/display/intel_qp_tables.c    | 311 ++++++++++++++++++
 .../gpu/drm/i915/display/intel_qp_tables.h    |  14 +
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  10 +-
 4 files changed, 335 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_qp_tables.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index d0d936d9137b..4a4d30d8a10a 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -263,6 +263,7 @@ i915-y += \
 	display/intel_lvds.o \
 	display/intel_panel.o \
 	display/intel_pps.o \
+	display/intel_qp_tables.o \
 	display/intel_sdvo.o \
 	display/intel_tv.o \
 	display/intel_vdsc.o \
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.c b/drivers/gpu/drm/i915/display/intel_qp_tables.c
new file mode 100644
index 000000000000..05f6876799ac
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include <drm/drm_dsc.h>
+
+#include "i915_utils.h"
+#include "intel_qp_tables.h"
+
+/* from BPP 6 to 24 in steps of 0.5 */
+#define RC_RANGE_QP444_8BPC_MAX_NUM_BPP		37
+
+/* from BPP 6 to 30 in steps of 0.5 */
+#define RC_RANGE_QP444_10BPC_MAX_NUM_BPP	49
+
+/* from BPP 6 to 36 in steps of 0.5 */
+#define RC_RANGE_QP444_12BPC_MAX_NUM_BPP	61
+
+/*
+ * These qp tables are as per the C model
+ * and it has the rows pointing to bpps which increment
+ * in steps of 0.5
+ * We do not support fractional bpps as of today,
+ * hence we would skip the fractional bpps during
+ * our references for qp calclulations.
+ */
+static const u8 rc_range_minqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
+	  1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 1, 1, 1, 1, 1, 1, 1,
+	  1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+	{ 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1,
+	  1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 },
+	{ 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
+	  2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+	{ 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2,
+	  2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+	{ 6, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
+	  3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0 },
+	{ 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3,
+	  3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+	{ 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4,
+	  4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
+	{ 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 4,
+	  4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
+	{ 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5,
+	  5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1 },
+	{ 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 8, 8,
+	  8, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3 }
+};
+
+static const u8 rc_range_maxqp444_8bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_8BPC_MAX_NUM_BPP] = {
+	{ 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 6, 6, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 1, 1, 1, 1, 1, 1,
+	  1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+	{ 8, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 2, 2, 1, 1, 1, 1, 1,
+	  1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+	{ 8, 8, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 4, 3, 3, 2, 2, 2, 2, 2,
+	  2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+	{ 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 2, 2, 2, 2, 2,
+	  2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 0 },
+	{ 9, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
+	  3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1 },
+	{ 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 4, 4, 3, 3, 3, 3, 3,
+	  3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1 },
+	{ 10, 10, 9, 9, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 6, 5, 5, 4, 4, 4, 4, 3,
+	  3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1 },
+	{ 11, 11, 10, 10, 9, 9, 9, 9, 9, 9, 8, 8, 8, 7, 7, 6, 6, 5, 5, 5, 5, 5,
+	  4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1 },
+	{ 12, 11, 11, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 8, 8, 7, 6, 6, 5, 5, 5,
+	  5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1 },
+	{ 12, 12, 11, 11, 10, 10, 10, 10, 10, 10, 9, 9, 9, 8, 8, 7, 7, 6, 6, 6,
+	  5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1 },
+	{ 12, 12, 12, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7,
+	  6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1 },
+	{ 12, 12, 12, 12, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 8, 8, 7, 7, 7,
+	  6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 1 },
+	{ 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 8, 8, 8,
+	  8, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2 },
+	{ 15, 15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 9,
+	  9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 5, 4, 4, 4, 4 }
+};
+
+static const u8 rc_range_minqp444_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_10BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0 },
+	{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1,
+	  1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0 },
+	{ 7, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2,
+	  2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0 },
+	{ 7, 7, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3,
+	  3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0 },
+	{ 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 3,
+	  3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0 },
+	{ 9, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 4,
+	  4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 0, 0, 0,
+	  0, 0, 0 },
+	{ 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 5, 5, 5, 5, 5,
+	  4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 0, 0,
+	  0, 0, 0 },
+	{ 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 5,
+	  5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 0,
+	  0, 0, 0 },
+	{ 9, 9, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 5,
+	  5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1,
+	  1, 0, 0 },
+	{ 10, 9, 9, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6,
+	  6, 6, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1,
+	  1, 1, 0 },
+	{ 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 7, 7, 7, 7, 7, 6,
+	  6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 2, 2, 2, 1,
+	  1, 1, 1 },
+	{ 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 8, 8,
+	  7, 7, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2,
+	  2, 1, 1, 1 },
+	{ 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8,
+	  8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2,
+	  2, 2, 2, 1 },
+	{ 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11,
+	  11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4,
+	  4, 3, 3, 3, 3, 2, 2, 2, 2, 1 },
+	{ 18, 18, 17, 17, 16, 16, 16, 16, 15, 15, 14, 14, 14, 14, 13, 13, 13,
+	  12, 12, 12, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 9, 8, 8, 7, 7, 7, 7,
+	  7, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3 }
+};
+
+static const u8 rc_range_maxqp444_10bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_10BPC_MAX_NUM_BPP] = {
+	{ 8, 8, 8, 8, 8, 8, 7, 7, 7, 6, 5, 5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2,
+	  1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0 },
+	{ 10, 10, 9, 9, 8, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3,
+	  3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0 },
+	{ 12, 11, 11, 10, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 7, 6, 6, 5, 5, 5, 4,
+	  4, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,
+	  0, 0, 0, 0 },
+	{ 12, 12, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 8, 7, 7, 6,
+	  6, 6, 5, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 1, 1, 1, 1,
+	  1, 0, 0, 0, 0, 0, 0 },
+	{ 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 8, 8, 7,
+	  6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1,
+	  1, 1, 1, 0, 0, 0, 0, 0 },
+	{ 13, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 10, 9, 8, 8,
+	  7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5, 5, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2,
+	  2, 2, 1, 1, 1, 1, 0, 0 },
+	{ 13, 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 8, 8,
+	  7, 7, 7, 7, 7, 6, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2,
+	  2, 2, 2, 1, 1, 1, 1, 1 },
+	{ 14, 14, 13, 13, 12, 12, 12, 12, 12, 12, 12, 12, 12, 11, 11, 10, 9, 9,
+	  8, 8, 8, 8, 7, 7, 7, 7, 6, 6, 6, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3, 3, 3,
+	  3, 2, 2, 2, 1, 1, 1, 1 },
+	{ 15, 15, 14, 14, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 11, 10, 10, 9,
+	  9, 9, 9, 9, 8, 8, 8, 8, 7, 7, 6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 3,
+	  3, 3, 2, 2, 2, 2, 1, 1 },
+	{ 16, 15, 15, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 12, 12, 11, 10,
+	  10, 9, 9, 9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4,
+	  4, 3, 3, 3, 2, 2, 2, 2, 1 },
+	{ 16, 16, 15, 15, 14, 14, 14, 14, 14, 14, 13, 13, 13, 12, 12, 11, 11,
+	  10, 10, 10, 9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5,
+	  4, 4, 4, 3, 3, 3, 2, 2, 2, 2 },
+	{ 16, 16, 16, 15, 15, 15, 14, 14, 14, 14, 13, 13, 13, 13, 12, 12, 12,
+	  11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5,
+	  5, 4, 4, 4, 4, 3, 3, 2, 2, 2 },
+	{ 16, 16, 16, 16, 15, 15, 15, 15, 15, 14, 14, 13, 13, 13, 12, 12, 12,
+	  11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 6, 6, 6, 6, 5, 5, 5,
+	  5, 4, 4, 4, 4, 3, 3, 3, 3, 2 },
+	{ 17, 17, 17, 17, 16, 16, 15, 15, 15, 15, 14, 14, 14, 14, 13, 13, 12,
+	  12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 7, 7, 6, 6, 6,
+	  6, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 2 },
+	{ 19, 19, 18, 18, 17, 17, 17, 17, 16, 16, 15, 15, 15, 15, 14, 14, 14,
+	  13, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8,
+	  8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 4 }
+};
+
+static const u8 rc_range_minqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC_MAX_NUM_BPP] = {
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+	  1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 11, 10, 10, 9, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 6, 5, 5, 4, 4, 4, 3, 3, 3, 3,
+	  3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 11, 11, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 7, 6, 6, 6, 6, 6, 5, 5, 5,
+	  5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 8, 7, 7, 7,
+	  7, 5, 5, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1,
+	  1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 13, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 9, 9, 8, 8,
+	  8, 8, 6, 6, 6, 6, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 2, 2, 2,
+	  2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 13, 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 9, 9, 9, 9,
+	  9, 9, 9, 8, 8, 8, 7, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 3, 3,
+	  3, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0 },
+	{ 13, 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 10, 10, 10,
+	  10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 4, 4,
+	  4, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0 },
+	{ 13, 13, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,
+	  11, 11, 11, 10, 10, 10, 10, 9, 9, 8, 7, 7, 7, 7, 7, 6, 6, 6, 6, 6, 6, 5, 5,
+	  5, 4, 4, 4, 4, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0 },
+	{ 14, 13, 13, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11, 11,
+	  11, 11, 11, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 6, 6, 5,
+	  5, 5, 4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 1, 1, 0 },
+	{ 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12,
+	  12, 11, 11, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8, 8, 7, 7, 7,
+	  6, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1 },
+	{ 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
+	  13, 12, 12, 11, 11, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 8,
+	  7, 7, 7, 7, 6, 6, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1 },
+	{ 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13, 13,
+	  13, 12, 12, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 9, 9, 9, 9, 8, 8, 8, 8,
+	  7, 7, 7, 7, 6, 6, 6, 6, 5, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1, 1, 1 },
+	{ 17, 17, 17, 17, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15, 15,
+	  15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 9, 9, 9, 9, 8, 8,
+	  7, 7, 7, 7, 7, 6, 6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 1 },
+	{ 22, 22, 21, 21, 20, 20, 20, 20, 19, 19, 18, 18, 18, 18, 17, 17, 17, 16, 16,
+	  16, 15, 15, 15, 15, 14, 14, 13, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 11,
+	  10, 10, 9, 9, 9, 9, 9, 8, 8, 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 3 }
+};
+
+static const u8 rc_range_maxqp444_12bpc[DSC_NUM_BUF_RANGES][RC_RANGE_QP444_12BPC_MAX_NUM_BPP] = {
+	{ 12, 12, 12, 12, 12, 12, 11, 11, 11, 10, 9, 9, 6, 6, 5, 5, 5, 4, 4, 4, 4, 4,
+	  4, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0,
+	  0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 14, 14, 13, 13, 12, 12, 12, 12, 12, 12, 11, 11, 9, 9, 9, 8, 8, 7, 7, 7, 7, 5,
+	  5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+	  1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 16, 15, 15, 14, 13, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 11, 10, 10, 9, 9,
+	  9, 7, 7, 7, 7, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 1, 1,
+	  1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 16, 16, 15, 15, 14, 14, 14, 14, 14, 14, 14, 14, 13, 13, 13, 12, 11, 11, 10,
+	  10, 10, 8, 8, 8, 8, 8, 7, 7, 6, 5, 5, 5, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 3, 2,
+	  2, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
+	{ 17, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 14, 13, 12, 12, 11, 10,
+	  10, 10, 10, 8, 8, 8, 8, 8, 8, 7, 7, 7, 6, 6, 5, 5, 5, 4, 4, 4, 4, 3, 3, 3, 3,
+	  2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0 },
+	{ 17, 16, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 14, 14, 14, 13, 12, 12, 11,
+	  11, 11, 11, 9, 9, 9, 9, 8, 8, 8, 8, 7, 6, 6, 6, 6, 6, 5, 5, 5, 5, 4, 4, 4, 3,
+	  3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0 },
+	{ 17, 17, 16, 16, 15, 15, 15, 15, 15, 15, 15, 15, 15, 14, 14, 13, 12, 12, 11,
+	  11, 11, 11, 11, 10, 10, 10, 9, 9, 9, 8, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6, 5, 5,
+	  5, 5, 4, 4, 4, 3, 3, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 0 },
+	{ 18, 18, 17, 17, 16, 16, 16, 16, 16, 16, 16, 16, 16, 15, 15, 14, 13, 13, 12,
+	  12, 12, 12, 11, 11, 11, 11, 10, 10, 10, 8, 8, 8, 7, 7, 7, 7, 7, 7, 6, 6, 6,
+	  6, 5, 5, 5, 4, 4, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 1, 1, 1, 1 },
+	{ 19, 19, 18, 18, 17, 17, 17, 17, 17, 17, 16, 16, 16, 15, 15, 14, 14, 13, 13,
+	  13, 13, 13, 12, 12, 12, 12, 11, 11, 10, 9, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 6,
+	  6, 6, 5, 5, 5, 5, 4, 4, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 1, 1 },
+	{ 20, 19, 19, 18, 18, 18, 17, 17, 17, 17, 17, 17, 17, 16, 16, 15, 14, 14, 13,
+	  13, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 9, 9, 9, 9, 8, 8, 8, 8, 8, 7, 7,
+	  6, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3, 2, 2, 1 },
+	{ 20, 20, 19, 19, 18, 18, 18, 18, 18, 18, 17, 17, 17, 16, 16, 15, 15, 14, 14,
+	  14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9,
+	  8, 8, 8, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 4, 3, 3, 3, 3, 2, 2, 2 },
+	{ 20, 20, 20, 19, 19, 19, 18, 18, 18, 18, 17, 17, 17, 17, 16, 16, 16, 15, 15,
+	  15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9,
+	  9, 8, 8, 8, 8, 7, 7, 6, 6, 6, 5, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2 },
+	{ 20, 20, 20, 20, 19, 19, 19, 19, 19, 18, 18, 17, 17, 17, 16, 16, 16, 15, 15,
+	  15, 14, 14, 13, 13, 13, 13, 12, 12, 11, 11, 11, 11, 10, 10, 10, 10, 9, 9, 9,
+	  9, 8, 8, 8, 8, 7, 7, 7, 7, 6, 5, 5, 5, 4, 4, 4, 4, 3, 3, 2, 2, 2 },
+	{ 21, 21, 21, 21, 20, 20, 19, 19, 19, 19, 18, 18, 18, 18, 17, 17, 16, 16, 16,
+	  16, 15, 15, 14, 14, 14, 14, 13, 13, 12, 12, 12, 12, 11, 11, 10, 10, 10, 10,
+	  9, 9, 8, 8, 8, 8, 8, 7, 7, 7, 6, 6, 6, 6, 5, 5, 4, 4, 4, 4, 3, 3, 2 },
+	{ 23, 23, 22, 22, 21, 21, 21, 21, 20, 20, 19, 19, 19, 19, 18, 18, 18, 17, 17,
+	  17, 16, 16, 16, 16, 15, 15, 14, 14, 14, 14, 14, 13, 13, 12, 12, 12, 12, 12,
+	  11, 11, 10, 10, 10, 10, 10, 9, 9, 8, 8, 8, 8, 8, 7, 7, 6, 6, 6, 6, 5, 5, 4 }
+};
+
+#define PARAM_TABLE(_minmax, _bpc, _row, _col)  do { \
+	if (bpc == _bpc) \
+		return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+} while (0)
+
+u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i)
+{
+	PARAM_TABLE(min, 8, buf_i, bpp_i);
+	PARAM_TABLE(min, 10, buf_i, bpp_i);
+	PARAM_TABLE(min, 12, buf_i, bpp_i);
+
+	MISSING_CASE(bpc);
+	return 0;
+}
+
+u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i)
+{
+	PARAM_TABLE(max, 8, buf_i, bpp_i);
+	PARAM_TABLE(max, 10, buf_i, bpp_i);
+	PARAM_TABLE(max, 12, buf_i, bpp_i);
+
+	MISSING_CASE(bpc);
+	return 0;
+}
+
+
diff --git a/drivers/gpu/drm/i915/display/intel_qp_tables.h b/drivers/gpu/drm/i915/display/intel_qp_tables.h
new file mode 100644
index 000000000000..9fb3c36bd7c6
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_qp_tables.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#ifndef _INTEL_QP_TABLES_H_
+#define _INTEL_QP_TABLES_H_
+
+#include <linux/types.h>
+
+u8 intel_lookup_range_min_qp(int bpc, int buf_i, int bpp_i);
+u8 intel_lookup_range_max_qp(int bpc, int buf_i, int bpp_i);
+
+#endif
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 02e86d2be395..19cd9531c115 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -11,6 +11,7 @@
 #include "intel_display_types.h"
 #include "intel_dsi.h"
 #include "intel_vdsc.h"
+#include "intel_qp_tables.h"
 
 enum ROW_INDEX_BPP {
 	ROW_INDEX_6BPP = 0,
@@ -384,7 +385,7 @@ calculate_rc_params(struct rc_parameters *rc,
 	int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
 	int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
 	int qp_bpc_modifier = (bpc - 8) * 2;
-	u32 res, buf_i;
+	u32 res, buf_i, bpp_i;
 
 	if (vdsc_cfg->slice_height >= 8)
 		rc->first_line_bpg_offset =
@@ -411,7 +412,14 @@ calculate_rc_params(struct rc_parameters *rc,
 	rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
 	rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
 
+	bpp_i  = (2 * (bpp - 6));
 	for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
+		/* Read range_minqp and range_max_qp from qp tables */
+		rc->rc_range_params[buf_i].range_min_qp =
+			intel_lookup_range_min_qp(bpc, buf_i, bpp_i);
+		rc->rc_range_params[buf_i].range_max_qp =
+			intel_lookup_range_max_qp(bpc, buf_i, bpp_i);
+
 		/* Calculate range_bgp_offset */
 		if (bpp <= 6) {
 			rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
-- 
2.25.4

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 05/23] drm/i915/xelpd: Add VRR guardband for VRR CTL
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (3 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 04/23] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-24 13:40   ` Aditya Swarup
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 06/23] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
                   ` (21 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Manasi Navare <manasi.d.navare@intel.com>

On XE_LPD, VRR CTL register adds a new VRR Guardband bitfield
replacing the pipeline full and deprecating the pipeline override
bit.

This patch adds this corresponding bitfield in the register defs,
crtc state vrr structure and populates this in vrr compute
config and vrr enable functions. It also adds the corresponding
HW state readout for this field.

Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  8 ++-
 .../drm/i915/display/intel_display_types.h    |  2 +-
 drivers/gpu/drm/i915/display/intel_vrr.c      | 58 +++++++++++++------
 drivers/gpu/drm/i915/i915_drv.h               |  3 +
 drivers/gpu/drm/i915/i915_reg.h               |  2 +
 5 files changed, 53 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 422b59ebf6dc..ce44f18340ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7631,10 +7631,11 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
 	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
 		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
 
-	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
+	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
 		    yesno(pipe_config->vrr.enable),
 		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
-		    pipe_config->vrr.pipeline_full, pipe_config->vrr.flipline,
+		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
+		    pipe_config->vrr.flipline,
 		    intel_vrr_vmin_vblank_start(pipe_config),
 		    intel_vrr_vmax_vblank_start(pipe_config));
 
@@ -8640,6 +8641,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(vrr.vmax);
 	PIPE_CONF_CHECK_I(vrr.flipline);
 	PIPE_CONF_CHECK_I(vrr.pipeline_full);
+	PIPE_CONF_CHECK_I(vrr.guardband);
 
 	PIPE_CONF_CHECK_BOOL(has_psr);
 	PIPE_CONF_CHECK_BOOL(has_psr2);
@@ -12200,6 +12202,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
 
 	i915->framestart_delay = 1; /* 1-4 */
 
+	i915->window2_delay = 0; /* No DSB so no window2 delay */
+
 	intel_mode_config_init(i915);
 
 	ret = intel_cdclk_init(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9c0adfc60c6f..9e9f768e2d7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1202,7 +1202,7 @@ struct intel_crtc_state {
 	struct {
 		bool enable;
 		u8 pipeline_full;
-		u16 flipline, vmin, vmax;
+		u16 flipline, vmin, vmax, guardband;
 	} vrr;
 
 	/* Stream Splitter for eDP MSO */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 046210ae1de0..c335b1dbafcf 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -68,7 +68,10 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
 	/* The hw imposes the extra scanline before frame start */
-	return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
+	if (DISPLAY_VER(i915) >= 13)
+		return crtc_state->vrr.guardband + i915->framestart_delay + 1;
+	else
+		return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
 }
 
 int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
@@ -86,6 +89,8 @@ void
 intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 			 struct drm_connector_state *conn_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	struct intel_connector *connector =
 		to_intel_connector(conn_state->connector);
 	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
@@ -124,17 +129,26 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 	crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
 
 	/*
-	 * FIXME: s/4/framestart_delay+1/ to get consistent
-	 * earliest/latest points for register latching regardless
-	 * of the framestart_delay used?
-	 *
-	 * FIXME: this really needs the extra scanline to provide consistent
-	 * behaviour for all framestart_delay values. Otherwise with
-	 * framestart_delay==3 we will end up extending the min vblank by
-	 * one extra line.
+	 * For XE_LPD+, we use guardband and pipeline override
+	 * is deprecated.
 	 */
-	crtc_state->vrr.pipeline_full =
-		min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
+	if (DISPLAY_VER(i915) >= 13)
+		crtc_state->vrr.guardband =
+			crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
+			i915->window2_delay;
+	else
+		/*
+		 * FIXME: s/4/framestart_delay+1/ to get consistent
+		 * earliest/latest points for register latching regardless
+		 * of the framestart_delay used?
+		 *
+		 * FIXME: this really needs the extra scanline to provide consistent
+		 * behaviour for all framestart_delay values. Otherwise with
+		 * framestart_delay==3 we will end up extending the min vblank by
+		 * one extra line.
+		 */
+		crtc_state->vrr.pipeline_full =
+			min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
 
 	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 }
@@ -149,10 +163,15 @@ void intel_vrr_enable(struct intel_encoder *encoder,
 	if (!crtc_state->vrr.enable)
 		return;
 
-	trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
-		VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
-		VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
-		VRR_CTL_PIPELINE_FULL_OVERRIDE;
+	if (DISPLAY_VER(dev_priv) >= 13)
+		trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
+			VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
+			XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
+	else
+		trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
+			VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
+			VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
+			VRR_CTL_PIPELINE_FULL_OVERRIDE;
 
 	intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
 	intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
@@ -199,8 +218,13 @@ void intel_vrr_get_config(struct intel_crtc *crtc,
 	if (!crtc_state->vrr.enable)
 		return;
 
-	if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
-		crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
+	if (DISPLAY_VER(dev_priv) >= 13)
+		crtc_state->vrr.guardband =
+			REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
+	else
+		if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
+			crtc_state->vrr.pipeline_full =
+				REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
 	if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
 		crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
 	crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 39b5e019c1a5..6eb6c6acd81e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1139,6 +1139,9 @@ struct drm_i915_private {
 
 	u8 framestart_delay;
 
+	/* Window2 specifies time required to program DSB (Window2) in number of scan lines */
+	u8 window2_delay;
+
 	u8 pch_ssc_use;
 
 	/* For i915gm/i945gm vblank irq workaround */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 506a5aa0646b..dbb75cd087d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4376,6 +4376,8 @@ enum {
 #define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
 #define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
 #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
+#define	  XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
+#define	  XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
 
 #define _TRANS_VRR_VMAX_A		0x60424
 #define _TRANS_VRR_VMAX_B		0x61424
-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 06/23] drm/i915/adl_p: Add dedicated SAGV watermarks
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (4 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 05/23] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17  6:49   ` Lisovskiy, Stanislav
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 07/23] drm/i915/adl_p: Setup ports/phys Matt Roper
                   ` (20 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

XE_LPD reduces the number of regular watermark latency levels from 8
to 6 on non-dgfx platforms.  However the hardware also adds a special
purpose SAGV wateramrk (and an accompanying transition watermark) that
will be used by the hardware in place of the level 0 values during SAGV
transitions.

Bspec: 49325, 49326, 50419
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++
 drivers/gpu/drm/i915/i915_drv.h              |  2 +
 drivers/gpu/drm/i915/i915_reg.h              | 59 ++++++++++++++------
 drivers/gpu/drm/i915/intel_pm.c              | 54 ++++++++++++++++--
 4 files changed, 126 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ce44f18340ee..2c2c5676dc30 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8752,6 +8752,38 @@ static void verify_wm_state(struct intel_crtc *crtc,
 				hw_wm_level->lines);
 		}
 
+		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
+		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
+
+		if (HAS_HW_SAGV_WM(dev_priv) &&
+		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				plane->base.base.id, plane->base.name,
+				sw_wm_level->enable,
+				sw_wm_level->blocks,
+				sw_wm_level->lines,
+				hw_wm_level->enable,
+				hw_wm_level->blocks,
+				hw_wm_level->lines);
+		}
+
+		hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
+		sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
+
+		if (HAS_HW_SAGV_WM(dev_priv) &&
+		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
+			drm_err(&dev_priv->drm,
+				"[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
+				plane->base.base.id, plane->base.name,
+				sw_wm_level->enable,
+				sw_wm_level->blocks,
+				sw_wm_level->lines,
+				hw_wm_level->enable,
+				hw_wm_level->blocks,
+				hw_wm_level->lines);
+		}
+
 		/* DDB */
 		hw_ddb_entry = &hw->ddb_y[plane->id];
 		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6eb6c6acd81e..d7583a01e135 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -590,6 +590,8 @@ i915_fence_timeout(const struct drm_i915_private *i915)
 /* Amount of SAGV/QGV points, BSpec precisely defines this */
 #define I915_NUM_QGV_POINTS 8
 
+#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
+
 struct ddi_vbt_port_info {
 	/* Non-NULL if port present. */
 	struct intel_bios_encoder_data *devdata;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dbb75cd087d3..ab6ffe036841 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6435,16 +6435,28 @@ enum {
 /* Watermark register definitions for SKL */
 #define _CUR_WM_A_0		0x70140
 #define _CUR_WM_B_0		0x71140
+#define _CUR_WM_SAGV_A		0x70158
+#define _CUR_WM_SAGV_B		0x71158
+#define _CUR_WM_SAGV_TRANS_A	0x7015C
+#define _CUR_WM_SAGV_TRANS_B	0x7115C
+#define _CUR_WM_TRANS_A		0x70168
+#define _CUR_WM_TRANS_B		0x71168
 #define _PLANE_WM_1_A_0		0x70240
 #define _PLANE_WM_1_B_0		0x71240
 #define _PLANE_WM_2_A_0		0x70340
 #define _PLANE_WM_2_B_0		0x71340
-#define _PLANE_WM_TRANS_1_A_0	0x70268
-#define _PLANE_WM_TRANS_1_B_0	0x71268
-#define _PLANE_WM_TRANS_2_A_0	0x70368
-#define _PLANE_WM_TRANS_2_B_0	0x71368
-#define _CUR_WM_TRANS_A_0	0x70168
-#define _CUR_WM_TRANS_B_0	0x71168
+#define _PLANE_WM_SAGV_1_A	0x70258
+#define _PLANE_WM_SAGV_1_B	0x71258
+#define _PLANE_WM_SAGV_2_A	0x70358
+#define _PLANE_WM_SAGV_2_B	0x71358
+#define _PLANE_WM_SAGV_TRANS_1_A	0x7025C
+#define _PLANE_WM_SAGV_TRANS_1_B	0x7125C
+#define _PLANE_WM_SAGV_TRANS_2_A	0x7035C
+#define _PLANE_WM_SAGV_TRANS_2_B	0x7135C
+#define _PLANE_WM_TRANS_1_A	0x70268
+#define _PLANE_WM_TRANS_1_B	0x71268
+#define _PLANE_WM_TRANS_2_A	0x70368
+#define _PLANE_WM_TRANS_2_B	0x71368
 #define   PLANE_WM_EN		(1 << 31)
 #define   PLANE_WM_IGNORE_LINES	(1 << 30)
 #define   PLANE_WM_LINES_MASK	REG_GENMASK(26, 14)
@@ -6452,19 +6464,32 @@ enum {
 
 #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
 #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
-#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
-
+#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
+#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
+#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
 #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
 #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
-#define _PLANE_WM_BASE(pipe, plane)	\
-			_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
-#define PLANE_WM(pipe, plane, level)	\
-			_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
-#define _PLANE_WM_TRANS_1(pipe)	\
-			_PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
-#define _PLANE_WM_TRANS_2(pipe)	\
-			_PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
-#define PLANE_WM_TRANS(pipe, plane)	\
+#define _PLANE_WM_BASE(pipe, plane) \
+	_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
+#define PLANE_WM(pipe, plane, level) \
+	_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
+#define _PLANE_WM_SAGV_1(pipe) \
+	_PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
+#define _PLANE_WM_SAGV_2(pipe) \
+	_PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
+#define PLANE_WM_SAGV(pipe, plane) \
+	_MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
+#define _PLANE_WM_SAGV_TRANS_1(pipe) \
+	_PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
+#define _PLANE_WM_SAGV_TRANS_2(pipe) \
+	_PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
+#define PLANE_WM_SAGV_TRANS(pipe, plane) \
+	_MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
+#define _PLANE_WM_TRANS_1(pipe) \
+	_PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
+#define _PLANE_WM_TRANS_2(pipe) \
+	_PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
+#define PLANE_WM_TRANS(pipe, plane) \
 	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
 
 /* define the Watermark register on Ironlake */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 15d9a64e7b4c..95fda20d5547 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2983,7 +2983,9 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
 int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
 {
 	/* how many WM levels are we expecting */
-	if (DISPLAY_VER(dev_priv) >= 9)
+	if (HAS_HW_SAGV_WM(dev_priv))
+		return 5;
+	else if (DISPLAY_VER(dev_priv) >= 9)
 		return 7;
 	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		return 4;
@@ -4011,8 +4013,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
 		 * latter from the plane commit hooks (especially in the legacy
 		 * cursor case)
 		 */
-		pipe_wm->use_sagv_wm = DISPLAY_VER(dev_priv) >= 12 &&
-				       intel_can_enable_sagv(dev_priv, new_bw_state);
+		pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(dev_priv) &&
+			DISPLAY_VER(dev_priv) >= 12 &&
+			intel_can_enable_sagv(dev_priv, new_bw_state);
 	}
 
 	if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
@@ -5619,6 +5622,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   skl_plane_trans_wm(pipe_wm, plane_id));
 
+	if (HAS_HW_SAGV_WM(dev_priv)) {
+		skl_write_wm_level(dev_priv, PLANE_WM_SAGV(pipe, plane_id),
+				   &wm->sagv.wm0);
+		skl_write_wm_level(dev_priv, PLANE_WM_SAGV_TRANS(pipe, plane_id),
+				   &wm->sagv.trans_wm);
+	}
+
 	if (DISPLAY_VER(dev_priv) >= 11) {
 		skl_ddb_entry_write(dev_priv,
 				    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
@@ -5652,6 +5662,15 @@ void skl_write_cursor_wm(struct intel_plane *plane,
 	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe),
 			   skl_plane_trans_wm(pipe_wm, plane_id));
 
+	if (HAS_HW_SAGV_WM(dev_priv)) {
+		const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+		skl_write_wm_level(dev_priv, CUR_WM_SAGV(pipe),
+				   &wm->sagv.wm0);
+		skl_write_wm_level(dev_priv, CUR_WM_SAGV_TRANS(pipe),
+				   &wm->sagv.trans_wm);
+	}
+
 	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
 }
 
@@ -6016,6 +6035,15 @@ static bool skl_plane_selected_wm_equals(struct intel_plane *plane,
 			return false;
 	}
 
+	if (HAS_HW_SAGV_WM(i915)) {
+		const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id];
+		const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id];
+
+		if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) ||
+		    !skl_wm_level_equals(&old_wm->sagv.trans_wm, &new_wm->sagv.trans_wm))
+			return false;
+	}
+
 	return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id),
 				   skl_plane_trans_wm(new_pipe_wm, plane->id));
 }
@@ -6234,7 +6262,25 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 
 		skl_wm_level_from_reg_val(val, &wm->trans_wm);
 
-		if (DISPLAY_VER(dev_priv) >= 12) {
+		if (HAS_HW_SAGV_WM(dev_priv)) {
+			if (plane_id != PLANE_CURSOR)
+				val = intel_uncore_read(&dev_priv->uncore,
+							PLANE_WM_SAGV(pipe, plane_id));
+			else
+				val = intel_uncore_read(&dev_priv->uncore,
+							CUR_WM_SAGV(pipe));
+
+			skl_wm_level_from_reg_val(val, &wm->sagv.wm0);
+
+			if (plane_id != PLANE_CURSOR)
+				val = intel_uncore_read(&dev_priv->uncore,
+							PLANE_WM_SAGV_TRANS(pipe, plane_id));
+			else
+				val = intel_uncore_read(&dev_priv->uncore,
+							CUR_WM_SAGV_TRANS(pipe));
+
+			skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm);
+		} else if (DISPLAY_VER(dev_priv) >= 12) {
 			wm->sagv.wm0 = wm->wm[0];
 			wm->sagv.trans_wm = wm->trans_wm;
 		}
-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 07/23] drm/i915/adl_p: Setup ports/phys
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (5 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 06/23] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17 18:01   ` Imre Deak
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold Matt Roper
                   ` (19 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4.
The first two are connected to combo phys while
the rest are connected to TC phys.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2c2c5676dc30..f7b25a723f87 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3675,7 +3675,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
 
 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
 {
-	if (IS_TIGERLAKE(dev_priv))
+	if (IS_ALDERLAKE_P(dev_priv))
+		return phy >= PHY_F && phy <= PHY_I;
+	else if (IS_TIGERLAKE(dev_priv))
 		return phy >= PHY_D && phy <= PHY_I;
 	else if (IS_ICELAKE(dev_priv))
 		return phy >= PHY_C && phy <= PHY_F;
@@ -11253,7 +11255,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	if (IS_ALDERLAKE_S(dev_priv)) {
+	if (IS_ALDERLAKE_P(dev_priv)) {
+		intel_ddi_init(dev_priv, PORT_A);
+		intel_ddi_init(dev_priv, PORT_B);
+		intel_ddi_init(dev_priv, PORT_TC1);
+		intel_ddi_init(dev_priv, PORT_TC2);
+		intel_ddi_init(dev_priv, PORT_TC3);
+		intel_ddi_init(dev_priv, PORT_TC4);
+	} else if (IS_ALDERLAKE_S(dev_priv)) {
 		intel_ddi_init(dev_priv, PORT_A);
 		intel_ddi_init(dev_priv, PORT_TC1);
 		intel_ddi_init(dev_priv, PORT_TC2);
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (6 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 07/23] drm/i915/adl_p: Setup ports/phys Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17 14:53   ` Imre Deak
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 09/23] drm/i915/adl_p: Implement TC sequences Matt Roper
                   ` (18 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: José Roberto de Souza <jose.souza@intel.com>

On ADL-P TC cold is exited and blocked when legacy aux is powered,
that is exacly the same of what ICL need for static TC ports.

TODO: When a TBT hub or monitor is connected it will cause TBT and
legacy aux to be powered at the same time, hopefully this will not
cause any issues but if it do, some rework will be needed.

v2:
 - skip icl_tc_port_assert_ref_held() warn on, adl-p uses aux to
   block TC cold

BSpec: 55480
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++-
 drivers/gpu/drm/i915/display/intel_tc.c            | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 54c6d65011ee..29d2f1d0cffd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -551,7 +551,8 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
 	if (drm_WARN_ON(&dev_priv->drm, !dig_port))
 		return;
 
-	if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
+	if (IS_ALDERLAKE_P(dev_priv) ||
+	    (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port))
 		return;
 
 	drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index e325463acddd..1b108dea5fed 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -28,7 +28,7 @@ tc_cold_get_power_domain(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 
-	if (DISPLAY_VER(i915) == 11)
+	if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) == 11)
 		return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
 	else
 		return POWER_DOMAIN_TC_COLD_OFF;
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 09/23] drm/i915/adl_p: Implement TC sequences
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (7 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17 15:12   ` Imre Deak
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 10/23] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
                   ` (17 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: José Roberto de Souza <jose.souza@intel.com>

ADL-P have basically the same TC connection and disconnection
sequences as ICL and TGL, the major difference is the new registers.

So here adding functions without the icl prefix in the name and
making the new functions call the platform specific function to access
the correct register.

v2:
 - Retain DDI TC PHY ownership flag during modesetting.

BSpec: 55480
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |   6 ++
 drivers/gpu/drm/i915/display/intel_tc.c  | 132 +++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h          |  10 ++
 3 files changed, 137 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index eccbdd42d223..38a4f251b9c9 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -252,12 +252,18 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 				      const struct intel_crtc_state *crtc_state)
 {
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+	enum phy phy = intel_port_to_phy(i915, encoder->port);
 
 	intel_dp->DP = dig_port->saved_port_bits |
 		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 	intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
+
+	if (IS_ALDERLAKE_P(i915) &&
+	    intel_phy_is_tc(i915, phy) && dig_port->tc_mode != TC_PORT_TBT_ALT)
+		intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 }
 
 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 1b108dea5fed..718e38c46dc0 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -205,7 +205,7 @@ static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
 	dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
 }
 
-static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
+static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	struct intel_uncore *uncore = &i915->uncore;
@@ -238,6 +238,40 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
 	return mask;
 }
 
+static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+	u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
+	struct intel_uncore *uncore = &i915->uncore;
+	u32 val, mask = 0;
+
+	val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
+	if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT)
+		mask |= BIT(TC_PORT_DP_ALT);
+	if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT)
+		mask |= BIT(TC_PORT_TBT_ALT);
+
+	if (intel_uncore_read(uncore, SDEISR) & isr_bit)
+		mask |= BIT(TC_PORT_LEGACY);
+
+	/* The sink can be connected only in a single mode. */
+	if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1))
+		tc_port_fixup_legacy_flag(dig_port, mask);
+
+	return mask;
+}
+
+static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+	if (IS_ALDERLAKE_P(i915))
+		return adl_tc_port_live_status_mask(dig_port);
+
+	return icl_tc_port_live_status_mask(dig_port);
+}
+
 static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -256,6 +290,33 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
 	return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
 }
 
+static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	struct intel_uncore *uncore = &i915->uncore;
+	u32 val;
+
+	val = intel_uncore_read(uncore, TCSS_DDI_STATUS(dig_port->tc_phy_fia_idx));
+	if (val == 0xffffffff) {
+		drm_dbg_kms(&i915->drm,
+			    "Port %s: PHY in TCCOLD, assuming not complete\n",
+			    dig_port->tc_port_name);
+		return false;
+	}
+
+	return val & TCSS_DDI_STATUS_READY;
+}
+
+static bool tc_phy_status_complete(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+	if (IS_ALDERLAKE_P(i915))
+		return adl_tc_phy_status_complete(dig_port);
+
+	return icl_tc_phy_status_complete(dig_port);
+}
+
 static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
 				      bool take)
 {
@@ -280,7 +341,7 @@ static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
 	intel_uncore_write(uncore,
 			   PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
 
-	if (!take && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
+	if (!take && wait_for(!tc_phy_status_complete(dig_port), 10))
 		drm_dbg_kms(&i915->drm,
 			    "Port %s: PHY complete clear timed out\n",
 			    dig_port->tc_port_name);
@@ -288,6 +349,34 @@ static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
 	return true;
 }
 
+static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
+				      bool take)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	struct intel_uncore *uncore = &i915->uncore;
+	enum port port = dig_port->base.port;
+	u32 val;
+
+	val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
+	if (take)
+		val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+	else
+		val &= ~DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+	intel_uncore_write(uncore, DDI_BUF_CTL(port), val);
+
+	return true;
+}
+
+static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+	if (IS_ALDERLAKE_P(i915))
+		return adl_tc_phy_take_ownership(dig_port, take);
+
+	return icl_tc_phy_take_ownership(dig_port, take);
+}
+
 static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -306,6 +395,27 @@ static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
 	return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
 }
 
+static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	struct intel_uncore *uncore = &i915->uncore;
+	enum port port = dig_port->base.port;
+	u32 val;
+
+	val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
+	return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+}
+
+static bool tc_phy_is_owned(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
+	if (IS_ALDERLAKE_P(i915))
+		return adl_tc_phy_is_owned(dig_port);
+
+	return icl_tc_phy_is_owned(dig_port);
+}
+
 /*
  * This function implements the first part of the Connect Flow described by our
  * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
@@ -323,13 +433,13 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 	int max_lanes;
 
-	if (!icl_tc_phy_status_complete(dig_port)) {
+	if (!tc_phy_status_complete(dig_port)) {
 		drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n",
 			    dig_port->tc_port_name);
 		goto out_set_tbt_alt_mode;
 	}
 
-	if (!icl_tc_phy_take_ownership(dig_port, true) &&
+	if (!tc_phy_take_ownership(dig_port, true) &&
 	    !drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
 		goto out_set_tbt_alt_mode;
 
@@ -364,7 +474,7 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
 	return;
 
 out_release_phy:
-	icl_tc_phy_take_ownership(dig_port, false);
+	tc_phy_take_ownership(dig_port, false);
 out_set_tbt_alt_mode:
 	dig_port->tc_mode = TC_PORT_TBT_ALT;
 }
@@ -380,7 +490,7 @@ static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
 		/* Nothing to do, we never disconnect from legacy mode */
 		break;
 	case TC_PORT_DP_ALT:
-		icl_tc_phy_take_ownership(dig_port, false);
+		tc_phy_take_ownership(dig_port, false);
 		dig_port->tc_mode = TC_PORT_TBT_ALT;
 		break;
 	case TC_PORT_TBT_ALT:
@@ -395,13 +505,13 @@ static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
 {
 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
 
-	if (!icl_tc_phy_status_complete(dig_port)) {
+	if (!tc_phy_status_complete(dig_port)) {
 		drm_dbg_kms(&i915->drm, "Port %s: PHY status not complete\n",
 			    dig_port->tc_port_name);
 		return dig_port->tc_mode == TC_PORT_TBT_ALT;
 	}
 
-	if (!icl_tc_phy_is_owned(dig_port)) {
+	if (!tc_phy_is_owned(dig_port)) {
 		drm_dbg_kms(&i915->drm, "Port %s: PHY not owned\n",
 			    dig_port->tc_port_name);
 
@@ -419,8 +529,8 @@ intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
 	u32 live_status_mask = tc_port_live_status_mask(dig_port);
 	enum tc_port_mode mode;
 
-	if (!icl_tc_phy_is_owned(dig_port) ||
-	    drm_WARN_ON(&i915->drm, !icl_tc_phy_status_complete(dig_port)))
+	if (!tc_phy_is_owned(dig_port) ||
+	    drm_WARN_ON(&i915->drm, !tc_phy_status_complete(dig_port)))
 		return TC_PORT_TBT_ALT;
 
 	mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT;
@@ -442,7 +552,7 @@ intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
 	if (live_status_mask)
 		return fls(live_status_mask) - 1;
 
-	return icl_tc_phy_status_complete(dig_port) &&
+	return tc_phy_status_complete(dig_port) &&
 	       dig_port->tc_legacy_port ? TC_PORT_LEGACY :
 					  TC_PORT_TBT_ALT;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ab6ffe036841..65af0d84d75b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10160,6 +10160,7 @@ enum skl_power_gate {
 #define  DDI_BUF_EMP_MASK			(0xf << 24)
 #define  DDI_BUF_PORT_REVERSAL			(1 << 16)
 #define  DDI_BUF_IS_IDLE			(1 << 7)
+#define  DDI_BUF_CTL_TC_PHY_OWNERSHIP		REG_BIT(6)
 #define  DDI_A_4_LANES				(1 << 4)
 #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
 #define  DDI_PORT_WIDTH_MASK			(7 << 1)
@@ -12596,6 +12597,15 @@ enum skl_power_gate {
 #define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 4))
 #define   DP_PIN_ASSIGNMENT(idx, x)		((x) << ((idx) * 4))
 
+#define _TCSS_DDI_STATUS_1			0x161500
+#define _TCSS_DDI_STATUS_2			0x161504
+#define TCSS_DDI_STATUS(tc)			_MMIO(_PICK_EVEN(tc, \
+								 _TCSS_DDI_STATUS_1, \
+								 _TCSS_DDI_STATUS_2))
+#define  TCSS_DDI_STATUS_READY			REG_BIT(2)
+#define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT	REG_BIT(1)
+#define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT	REG_BIT(0)
+
 /* This register controls the Display State Buffer (DSB) engines. */
 #define _DSBSL_INSTANCE_BASE		0x70B00
 #define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 10/23] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (8 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 09/23] drm/i915/adl_p: Implement TC sequences Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-18 11:58   ` Lisovskiy, Stanislav
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 11/23] drm/i915/adl_p: Add ddb allocation support Matt Roper
                   ` (16 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: José Roberto de Souza <jose.souza@intel.com>

Alderlake-P don't have programing sequences for MBUS or DBUF during
display initializaiton, instead it requires programing to those
registers during modeset because it to depend on the pipes left
enabled.

Bspec: 49213
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 29d2f1d0cffd..26d2eba87486 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5246,6 +5246,9 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
 {
 	enum dbuf_slice slice;
 
+	if (IS_ALDERLAKE_P(dev_priv))
+		return;
+
 	for_each_dbuf_slice(dev_priv, slice)
 		intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
 			     DBUF_TRACKER_STATE_SERVICE_MASK,
@@ -5257,6 +5260,9 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
 	unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
 	u32 mask, val, i;
 
+	if (IS_ALDERLAKE_P(dev_priv))
+		return;
+
 	mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
 		MBUS_ABOX_BT_CREDIT_POOL2_MASK |
 		MBUS_ABOX_B_CREDIT_MASK |
-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 11/23] drm/i915/adl_p: Add ddb allocation support
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (9 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 10/23] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-18 12:22   ` Lisovskiy, Stanislav
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 12/23] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
                   ` (15 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

On adlp the two mbuses have two display pipes and
two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on
Mbus2. The Mbus can be joined and all the DBUFS can be
used on Pipe A or B.

Bspec: 49255
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  22 ++++--
 drivers/gpu/drm/i915/intel_pm.c | 121 +++++++++++++++++++++++++++++++-
 2 files changed, 138 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 65af0d84d75b..47be6054d480 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7308,7 +7308,7 @@ enum {
 
 #define _PLANE_BUF_CFG_1_B			0x7127c
 #define _PLANE_BUF_CFG_2_B			0x7137c
-#define  DDB_ENTRY_MASK				0x7FF /* skl+: 10 bits, icl+ 11 bits */
+#define  DDB_ENTRY_MASK				0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
 #define  DDB_ENTRY_END_SHIFT			16
 #define _PLANE_BUF_CFG_1(pipe)	\
 	_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
@@ -8145,9 +8145,23 @@ enum {
 #define  DISP_DATA_PARTITION_5_6	(1 << 6)
 #define  DISP_IPC_ENABLE		(1 << 3)
 
-#define _DBUF_CTL_S1				0x45008
-#define _DBUF_CTL_S2				0x44FE8
-#define DBUF_CTL_S(slice)			_MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
+/*
+ * The below are numbered starting from "S1" on gen11/gen12, but starting
+ * with gen13 display, the bspec switches to a 0-based numbering scheme
+ * (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
+ * We'll just use the 0-based numbering here for all platforms since it's the
+ * way things will be named by the hardware team going forward, plus it's more
+ * consistent with how most of the rest of our registers are named.
+ */
+#define _DBUF_CTL_S0				0x45008
+#define _DBUF_CTL_S1				0x44FE8
+#define _DBUF_CTL_S2				0x44300
+#define _DBUF_CTL_S3				0x44304
+#define DBUF_CTL_S(slice)			_MMIO(_PICK(slice, \
+							    _DBUF_CTL_S0, \
+							    _DBUF_CTL_S1, \
+							    _DBUF_CTL_S2, \
+							    _DBUF_CTL_S3))
 #define  DBUF_POWER_REQUEST			REG_BIT(31)
 #define  DBUF_POWER_STATE			REG_BIT(30)
 #define  DBUF_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(23, 19)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 95fda20d5547..411ec468d02a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4558,6 +4558,118 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
 	{}
 };
 
+static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
+	{
+		.active_pipes = BIT(PIPE_A),
+		.dbuf_mask = {
+			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_B),
+		.dbuf_mask = {
+			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
+		.dbuf_mask = {
+			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_C),
+		.dbuf_mask = {
+			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
+		.dbuf_mask = {
+			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
+		.dbuf_mask = {
+			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+		.dbuf_mask = {
+			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_D),
+		.dbuf_mask = {
+			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
+		.dbuf_mask = {
+			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
+		.dbuf_mask = {
+			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
+		.dbuf_mask = {
+			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
+		.dbuf_mask = {
+			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
+		.dbuf_mask = {
+			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+		.dbuf_mask = {
+			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+		},
+	},
+	{
+		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+		.dbuf_mask = {
+			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
+			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
+		},
+	},
+	{}
+
+};
+
 static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
 			      const struct dbuf_slice_conf_entry *dbuf_slices)
 {
@@ -4597,12 +4709,19 @@ static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
 	return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs);
 }
 
+static u32 adlp_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
+{
+	return compute_dbuf_slices(pipe, active_pipes, adlp_allowed_dbufs);
+}
+
 static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
-	if (DISPLAY_VER(dev_priv) == 12)
+	if (IS_ALDERLAKE_P(dev_priv))
+		return adlp_compute_dbuf_slices(pipe, active_pipes);
+	else if (DISPLAY_VER(dev_priv) == 12)
 		return tgl_compute_dbuf_slices(pipe, active_pipes);
 	else if (DISPLAY_VER(dev_priv) == 11)
 		return icl_compute_dbuf_slices(pipe, active_pipes);
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 12/23] drm/i915: Introduce MBUS relative dbuf offsets
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (10 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 11/23] drm/i915/adl_p: Add ddb allocation support Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17  6:38   ` Lisovskiy, Stanislav
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 13/23] drm/i915/adl_p: MBUS programming Matt Roper
                   ` (14 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The dbuf slices are going to be split across several MBUS units.
The actual dbuf programming will use offsets relative to the
MBUS unit. To accommodate that we shall store the MBUS relative
offsets into the dbuf_state->ddb[] and crtc_state->plane_ddb*[].

For crtc_state->wm.skl.ddb however we want to stick to global
offsets as we use this to sanity check that the ddb allocations
don't overlap between pipes.

Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 40 ++++++++++++++++++++++++++++-----
 1 file changed, 34 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 411ec468d02a..cbbd966f710e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4057,6 +4057,20 @@ skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask,
 	WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);
 }
 
+static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
+{
+	struct skl_ddb_entry ddb;
+
+	if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2)))
+		slice_mask = BIT(DBUF_S1);
+	else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))
+		slice_mask = BIT(DBUF_S3);
+
+	skl_ddb_entry_for_slices(i915, slice_mask, &ddb);
+
+	return ddb.start;
+}
+
 u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
 			    const struct skl_ddb_entry *entry)
 {
@@ -4149,6 +4163,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
 	struct intel_crtc_state *crtc_state;
 	struct skl_ddb_entry ddb_slices;
 	enum pipe pipe = crtc->pipe;
+	unsigned int mbus_offset;
 	u32 ddb_range_size;
 	u32 dbuf_slice_mask;
 	u32 start, end;
@@ -4163,6 +4178,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
 	dbuf_slice_mask = new_dbuf_state->slices[pipe];
 
 	skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices);
+	mbus_offset = mbus_ddb_offset(dev_priv, dbuf_slice_mask);
 	ddb_range_size = skl_ddb_entry_size(&ddb_slices);
 
 	intel_crtc_dbuf_weights(new_dbuf_state, pipe,
@@ -4171,11 +4187,11 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
 	start = ddb_range_size * weight_start / weight_total;
 	end = ddb_range_size * weight_end / weight_total;
 
-	new_dbuf_state->ddb[pipe].start = ddb_slices.start + start;
-	new_dbuf_state->ddb[pipe].end = ddb_slices.start + end;
-
+	new_dbuf_state->ddb[pipe].start = ddb_slices.start - mbus_offset + start;
+	new_dbuf_state->ddb[pipe].end = ddb_slices.start - mbus_offset + end;
 out:
-	if (skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
+	if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&
+	    skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
 				&new_dbuf_state->ddb[pipe]))
 		return 0;
 
@@ -4187,7 +4203,12 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
 	if (IS_ERR(crtc_state))
 		return PTR_ERR(crtc_state);
 
-	crtc_state->wm.skl.ddb = new_dbuf_state->ddb[pipe];
+	/*
+	 * Used for checking overlaps, so we need absolute
+	 * offsets instead of MBUS relative offsets.
+	 */
+	crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;
+	crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;
 
 	drm_dbg_kms(&dev_priv->drm,
 		    "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n",
@@ -6416,6 +6437,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
 		enum pipe pipe = crtc->pipe;
+		unsigned int mbus_offset;
 		enum plane_id plane_id;
 
 		skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
@@ -6441,7 +6463,13 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
 
 		dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
 
-		crtc_state->wm.skl.ddb = dbuf_state->ddb[pipe];
+		/*
+		 * Used for checking overlaps, so we need absolute
+		 * offsets instead of MBUS relative offsets.
+		 */
+		mbus_offset = mbus_ddb_offset(dev_priv, dbuf_state->slices[pipe]);
+		crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;
+		crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
 
 		drm_dbg_kms(&dev_priv->drm,
 			    "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n",
-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 13/23] drm/i915/adl_p: MBUS programming
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (11 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 12/23] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 14/23] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
                   ` (13 subsequent siblings)
  26 siblings, 0 replies; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Vandita Kulkarni <vandita.kulkarni@intel.com>

Update MBUS_CTL register if the 2 mbus can be joined as per the current
DDB allocation and active pipes, also update hashing mode and pipe
select bits as  per the sequence mentioned in the bspec.

Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic.c  | 20 +++++
 drivers/gpu/drm/i915/display/intel_atomic.h  |  1 +
 drivers/gpu/drm/i915/display/intel_display.c |  3 +
 drivers/gpu/drm/i915/i915_reg.h              | 11 +++
 drivers/gpu/drm/i915/intel_pm.c              | 92 ++++++++++++++++++--
 drivers/gpu/drm/i915/intel_pm.h              |  2 +-
 6 files changed, 120 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 88f424020a5f..b4e7ac51aa31 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -187,6 +187,26 @@ intel_connector_needs_modeset(struct intel_atomic_state *state,
 									    new_conn_state->crtc)));
 }
 
+/**
+ * intel_any_crtc_needs_modeset - check if any CRTC needs a modeset
+ * @state: the atomic state corresponding to this modeset
+ *
+ * Returns true if any CRTC in @state needs a modeset.
+ */
+bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state)
+{
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *crtc_state;
+	int i;
+
+	for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+		if (intel_crtc_needs_modeset(crtc_state))
+			return true;
+	}
+
+	return false;
+}
+
 struct intel_digital_connector_state *
 intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
 					 struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 62a3365ed5e6..d2700c74c9da 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -35,6 +35,7 @@ struct drm_connector_state *
 intel_digital_connector_duplicate_state(struct drm_connector *connector);
 bool intel_connector_needs_modeset(struct intel_atomic_state *state,
 				   struct drm_connector *connector);
+bool intel_any_crtc_needs_modeset(struct intel_atomic_state *state);
 struct intel_digital_connector_state *
 intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
 					 struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f7b25a723f87..dd248995c53d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -9959,6 +9959,9 @@ static int intel_atomic_check(struct drm_device *dev,
 	if (ret)
 		goto fail;
 
+	if (intel_any_crtc_needs_modeset(state))
+		any_ms = true;
+
 	if (any_ms) {
 		ret = intel_modeset_checks(state);
 		if (ret)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 47be6054d480..0e7a2616b3cd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2935,6 +2935,15 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define MBUS_BBOX_CTL_S1		_MMIO(0x45040)
 #define MBUS_BBOX_CTL_S2		_MMIO(0x45044)
 
+#define MBUS_CTL			_MMIO(0x4438C)
+#define MBUS_JOIN			REG_BIT(31)
+#define MBUS_HASHING_MODE_MASK		REG_BIT(30)
+#define MBUS_HASHING_MODE_2x2		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
+#define MBUS_HASHING_MODE_1x4		REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
+#define MBUS_JOIN_PIPE_SELECT_MASK	REG_GENMASK(28, 26)
+#define MBUS_JOIN_PIPE_SELECT(pipe)	REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
+#define MBUS_JOIN_PIPE_SELECT_NONE	MBUS_JOIN_PIPE_SELECT(7)
+
 #define HDPORT_STATE			_MMIO(0x45050)
 #define   HDPORT_DPLL_USED_MASK		REG_GENMASK(15, 12)
 #define   HDPORT_DDI_USED(phy)		REG_BIT(2 * (phy) + 1)
@@ -8166,6 +8175,8 @@ enum {
 #define  DBUF_POWER_STATE			REG_BIT(30)
 #define  DBUF_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(23, 19)
 #define  DBUF_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
+#define  DBUF_MIN_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(18, 16) /* ADL-P+ */
+#define  DBUF_MIN_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
 
 #define GEN7_MSG_CTL	_MMIO(0x45010)
 #define  WAIT_FOR_PCH_RESET_ACK		(1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cbbd966f710e..00f3dead20ad 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4266,7 +4266,6 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
 static void skl_ddb_entry_init_from_hw(struct drm_i915_private *dev_priv,
 				       struct skl_ddb_entry *entry, u32 reg)
 {
-
 	entry->start = reg & DDB_ENTRY_MASK;
 	entry->end = (reg >> DDB_ENTRY_END_SHIFT) & DDB_ENTRY_MASK;
 
@@ -4391,6 +4390,7 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
 struct dbuf_slice_conf_entry {
 	u8 active_pipes;
 	u8 dbuf_mask[I915_MAX_PIPES];
+	bool join_mbus;
 };
 
 /*
@@ -4583,14 +4583,16 @@ static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
 	{
 		.active_pipes = BIT(PIPE_A),
 		.dbuf_mask = {
-			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
+			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
 		},
+		.join_mbus = true,
 	},
 	{
 		.active_pipes = BIT(PIPE_B),
 		.dbuf_mask = {
-			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
+			[PIPE_B] = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4),
 		},
+		.join_mbus = true,
 	},
 	{
 		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
@@ -4691,6 +4693,23 @@ static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
 
 };
 
+static bool check_mbus_joined(u8 active_pipes,
+			      const struct dbuf_slice_conf_entry *dbuf_slices)
+{
+	int i;
+
+	for (i = 0; i < dbuf_slices[i].active_pipes; i++) {
+		if (dbuf_slices[i].active_pipes == active_pipes)
+			return dbuf_slices[i].join_mbus;
+	}
+	return false;
+}
+
+static bool adlp_check_mbus_joined(u8 active_pipes)
+{
+	return check_mbus_joined(active_pipes, adlp_allowed_dbufs);
+}
+
 static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
 			      const struct dbuf_slice_conf_entry *dbuf_slices)
 {
@@ -5972,16 +5991,29 @@ skl_compute_ddb(struct intel_atomic_state *state)
 
 	new_dbuf_state->enabled_slices = intel_dbuf_enabled_slices(new_dbuf_state);
 
-	if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices) {
+	if (IS_ALDERLAKE_P(dev_priv))
+		new_dbuf_state->joined_mbus = adlp_check_mbus_joined(new_dbuf_state->active_pipes);
+
+	if (old_dbuf_state->enabled_slices != new_dbuf_state->enabled_slices ||
+	    old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
 		ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
 		if (ret)
 			return ret;
 
+		if (old_dbuf_state->joined_mbus != new_dbuf_state->joined_mbus) {
+			/* TODO: Implement vblank synchronized MBUS joining changes */
+			ret = intel_modeset_all_pipes(state);
+			if (ret)
+				return ret;
+		}
+
 		drm_dbg_kms(&dev_priv->drm,
-			    "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x)\n",
+			    "Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
 			    old_dbuf_state->enabled_slices,
 			    new_dbuf_state->enabled_slices,
-			    INTEL_INFO(dev_priv)->dbuf.slice_mask);
+			    INTEL_INFO(dev_priv)->dbuf.slice_mask,
+			    yesno(old_dbuf_state->joined_mbus),
+			    yesno(new_dbuf_state->joined_mbus));
 	}
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
@@ -6433,6 +6465,9 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
 		to_intel_dbuf_state(dev_priv->dbuf.obj.state);
 	struct intel_crtc *crtc;
 
+	if (IS_ALDERLAKE_P(dev_priv))
+		dbuf_state->joined_mbus = intel_de_read(dev_priv, MBUS_CTL) & MBUS_JOIN;
+
 	for_each_intel_crtc(&dev_priv->drm, crtc) {
 		struct intel_crtc_state *crtc_state =
 			to_intel_crtc_state(crtc->base.state);
@@ -6472,10 +6507,11 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
 		crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
 
 		drm_dbg_kms(&dev_priv->drm,
-			    "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n",
+			    "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x, mbus joined: %s\n",
 			    crtc->base.base.id, crtc->base.name,
 			    dbuf_state->slices[pipe], dbuf_state->ddb[pipe].start,
-			    dbuf_state->ddb[pipe].end, dbuf_state->active_pipes);
+			    dbuf_state->ddb[pipe].end, dbuf_state->active_pipes,
+			    yesno(dbuf_state->joined_mbus));
 	}
 
 	dbuf_state->enabled_slices = dev_priv->dbuf.enabled_slices;
@@ -8009,6 +8045,45 @@ int intel_dbuf_init(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
+/*
+ * Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
+ * update the request state of all DBUS slices.
+ */
+static void update_mbus_pre_enable(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	u32 mbus_ctl, dbuf_min_tracker_val;
+	enum dbuf_slice slice;
+	const struct intel_dbuf_state *dbuf_state =
+		intel_atomic_get_new_dbuf_state(state);
+
+	if (!IS_ALDERLAKE_P(dev_priv))
+		return;
+
+	/*
+	 * TODO: Implement vblank synchronized MBUS joining changes.
+	 * Must be properly coordinated with dbuf reprogramming.
+	 */
+	if (dbuf_state->joined_mbus) {
+		mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
+			MBUS_JOIN_PIPE_SELECT_NONE;
+		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
+	} else {
+		mbus_ctl = MBUS_HASHING_MODE_2x2 |
+			MBUS_JOIN_PIPE_SELECT_NONE;
+		dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
+	}
+
+	intel_de_rmw(dev_priv, MBUS_CTL,
+		     MBUS_HASHING_MODE_MASK | MBUS_JOIN |
+		     MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
+
+	for_each_dbuf_slice(dev_priv, slice)
+		intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
+			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+			     dbuf_min_tracker_val);
+}
+
 void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
 {
 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -8023,6 +8098,7 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
 
 	WARN_ON(!new_dbuf_state->base.changed);
 
+	update_mbus_pre_enable(state);
 	gen9_dbuf_slices_update(dev_priv,
 				old_dbuf_state->enabled_slices |
 				new_dbuf_state->enabled_slices);
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 669c8d505677..bac72c859a84 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -78,9 +78,9 @@ struct intel_dbuf_state {
 	struct skl_ddb_entry ddb[I915_MAX_PIPES];
 	unsigned int weight[I915_MAX_PIPES];
 	u8 slices[I915_MAX_PIPES];
-
 	u8 enabled_slices;
 	u8 active_pipes;
+	bool joined_mbus;
 };
 
 int intel_dbuf_init(struct drm_i915_private *dev_priv);
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 14/23] drm/i915/adl_p: Tx escape clock with DSI
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (12 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 13/23] drm/i915/adl_p: MBUS programming Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17  7:36   ` Kulkarni, Vandita
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Matt Roper
                   ` (12 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Mika Kahola <mika.kahola@intel.com>

Today when the DSI controller is paired with the Combo-PHY it
uses the high-speed (HS) Word clock for its low power (LP)
transmit PPI communication to the DPHY. The interface signaling
only changes state at an Escape clock frequency (i.e. its
effectively running on a virtual Tx Escape clock that is controlled
by counters w/in the controller), but all the interface flops are
running off the HS clock.

This has the following drawbacks:

 * It is a deviation from the PPI spec which assumes signaling is
   running on a physical Escape clock
 * The PV timings are over constrained (HS timed to 312.5MHz vs.
   an Escape clock of 20MHz max)

This feature is proposing to change the LP Tx communication between
the controller and the DPHY from a virtual Tx Escape clock to a physical
clock.

To do this we need to program two "M" divisors. One for the usual
DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV register and one for MIPIO_DWORD8.

For DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV registers the "M" is calculated
as following

Nt = ceil(f_link/160) (theoretical word clock)
Nact = max[3, Nt + (Nt + 1)%2] (actual word clock)
M = Nact * 8

For MIPIO_DWORD8 register, the divisor "M" is calculated as following

M = (Nact - 1)/2

BSpec: 55171

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 21 +++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h        |  6 ++++++
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ce544e20f35c..27251b97f0c3 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -363,10 +363,19 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 	enum port port;
 	int afe_clk_khz;
-	u32 esc_clk_div_m;
+	int theo_word_clk, act_word_clk;
+	u32 esc_clk_div_m, esc_clk_div_m_phy;
 
 	afe_clk_khz = afe_clk(encoder, crtc_state);
-	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
+
+	if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
+		theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
+		act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
+		esc_clk_div_m = act_word_clk * 8;
+		esc_clk_div_m_phy = (act_word_clk - 1)/2;
+	} else {
+		esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
+	}
 
 	for_each_dsi_port(port, intel_dsi->ports) {
 		intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
@@ -379,6 +388,14 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
 			       esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 		intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
 	}
+
+	if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
+		for_each_dsi_port(port, intel_dsi->ports) {
+			intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
+				       esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
+			intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
+		}
+	}
 }
 
 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0e7a2616b3cd..2906dff26868 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -11336,6 +11336,12 @@ enum skl_power_gate {
 #define  ICL_ESC_CLK_DIV_SHIFT			0
 #define DSI_MAX_ESC_CLK			20000		/* in KHz */
 
+#define _ADL_MIPIO_REG			0x180
+#define ADL_MIPIO_DW(port, dw)		_MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw))
+#define   TX_ESC_CLK_DIV_PHY_SEL	REGBIT(16)
+#define   TX_ESC_CLK_DIV_PHY_MASK	REG_GENMASK(23, 16)
+#define   TX_ESC_CLK_DIV_PHY		REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)
+
 #define _DSI_CMD_FRMCTL_0		0x6b034
 #define _DSI_CMD_FRMCTL_1		0x6b834
 #define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (13 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 14/23] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17  6:39   ` Gupta, Anshuman
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 16/23] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() Matt Roper
                   ` (11 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

It replaces dc3co_enabled with dc3co_exitline on intel_psr struct.  And
it saves dc3co_exitline, not dc3co_enabled, so we can use dc3co_exitline
without intel_crtc_state on other psr internal function like as
intel_psr_enable_source().

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c           | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9e9f768e2d7f..b8d1f702d808 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1498,7 +1498,7 @@ struct intel_psr {
 	bool sink_not_reliable;
 	bool irq_aux_error;
 	u16 su_x_granularity;
-	bool dc3co_enabled;
+	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
 	struct delayed_work dc3co_work;
 	struct drm_dp_vsc_sdp vsc;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index acaf3d459821..5bafd0de6ad9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -638,7 +638,7 @@ static void tgl_dc3co_disable_work(struct work_struct *work)
 
 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
 {
-	if (!intel_dp->psr.dc3co_enabled)
+	if (!intel_dp->psr.dc3co_exitline)
 		return;
 
 	cancel_delayed_work(&intel_dp->psr.dc3co_work);
@@ -1010,7 +1010,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 
 	psr_irq_control(intel_dp);
 
-	if (crtc_state->dc3co_exitline) {
+	if (intel_dp->psr.dc3co_exitline) {
 		u32 val;
 
 		/*
@@ -1019,7 +1019,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		 */
 		val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
 		val &= ~EXITLINE_MASK;
-		val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
+		val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
 		val |= EXITLINE_ENABLE;
 		intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
 	}
@@ -1044,11 +1044,11 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
 	intel_dp->psr.busy_frontbuffer_bits = 0;
 	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
-	intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
 	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
 	/* DC5/DC6 requires at least 6 idle frames */
 	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
 	intel_dp->psr.dc3co_exit_delay = val;
+	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
 	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
 
 	/*
@@ -1818,7 +1818,7 @@ tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
 {
 	mutex_lock(&intel_dp->psr.lock);
 
-	if (!intel_dp->psr.dc3co_enabled)
+	if (!intel_dp->psr.dc3co_exitline)
 		goto unlock;
 
 	if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 16/23] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source()
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (14 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-19  6:49   ` Anshuman Gupta
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 17/23] drm/i915/display: Add PSR interrupt error check function Matt Roper
                   ` (10 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

It removes intel_crtc_state from function argument of
intel_psr_enable_source() in order to use intel_psr_enable_source()
without intel_crtc_state on other psr internal functions.
And we can get cpu_trancoder from intel_psr, therefore we don't need to
pass intel_crtc_state to this function.

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5bafd0de6ad9..cc85083dcd28 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -969,11 +969,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
 	intel_dp->psr.active = true;
 }
 
-static void intel_psr_enable_source(struct intel_dp *intel_dp,
-				    const struct intel_crtc_state *crtc_state)
+static void intel_psr_enable_source(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
 	u32 mask;
 
 	/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
@@ -1080,7 +1079,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 				     &intel_dp->psr.vsc);
 	intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
 	intel_psr_enable_sink(intel_dp);
-	intel_psr_enable_source(intel_dp, crtc_state);
+	intel_psr_enable_source(intel_dp);
 	intel_dp->psr.enabled = true;
 
 	intel_psr_activate(intel_dp);
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 17/23] drm/i915/display: Add PSR interrupt error check function
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (15 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 16/23] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17 17:03   ` Souza, Jose
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function Matt Roper
                   ` (9 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

In order to reuse code of PSR interrupt error check on other PSR functions,
it adds psr_interrupt_error_check() function.

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 47 +++++++++++++++---------
 1 file changed, 29 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index cc85083dcd28..4a63d10876ce 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1029,27 +1029,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
 			     IGNORE_PSR2_HW_TRACKING : 0);
 }
 
-static void intel_psr_enable_locked(struct intel_dp *intel_dp,
-				    const struct intel_crtc_state *crtc_state,
-				    const struct drm_connector_state *conn_state)
+static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
 {
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
-	struct intel_encoder *encoder = &dig_port->base;
 	u32 val;
 
-	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
-
-	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
-	intel_dp->psr.busy_frontbuffer_bits = 0;
-	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
-	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
-	/* DC5/DC6 requires at least 6 idle frames */
-	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
-	intel_dp->psr.dc3co_exit_delay = val;
-	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
-	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
-
 	/*
 	 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
 	 * will still keep the error set even after the reset done in the
@@ -1070,9 +1054,36 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 		intel_dp->psr.sink_not_reliable = true;
 		drm_dbg_kms(&dev_priv->drm,
 			    "PSR interruption error set, not enabling PSR\n");
-		return;
+		return false;
 	}
 
+	return true;
+}
+
+static void intel_psr_enable_locked(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state,
+				    const struct drm_connector_state *conn_state)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
+	struct intel_encoder *encoder = &dig_port->base;
+	u32 val;
+
+	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
+
+	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+	intel_dp->psr.busy_frontbuffer_bits = 0;
+	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
+	/* DC5/DC6 requires at least 6 idle frames */
+	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
+	intel_dp->psr.dc3co_exit_delay = val;
+	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
+	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
+
+	if (!psr_interrupt_error_check(intel_dp))
+		return;
+
 	drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
 		    intel_dp->psr.psr2_enabled ? "2" : "1");
 	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (16 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 17/23] drm/i915/display: Add PSR interrupt error check function Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17 16:58   ` Souza, Jose
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
                   ` (8 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

This introduces the following function that can enable and disable psr
without intel_crtc_state/drm_connector_state when intel_psr is already
enabled with current intel_crtc_state and drm_connector_state information.

- intel_psr_pause(): Pause current PSR. it deactivates current psr state.
- intel_psr_resume(): Resume paused PSR without intel_crtc_state and
                      drm_connector_state. It activates paused psr state.

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 93 ++++++++++++++++---
 drivers/gpu/drm/i915/display/intel_psr.h      |  2 +
 3 files changed, 82 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b8d1f702d808..ee7cbdd7db87 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1482,6 +1482,7 @@ struct intel_psr {
 	bool sink_support;
 	bool source_support;
 	bool enabled;
+	bool paused;
 	enum pipe pipe;
 	enum transcoder transcoder;
 	bool active;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 4a63d10876ce..d4df3f5e7918 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1060,34 +1060,23 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
 	return true;
 }
 
-static void intel_psr_enable_locked(struct intel_dp *intel_dp,
-				    const struct intel_crtc_state *crtc_state,
-				    const struct drm_connector_state *conn_state)
+static void _intel_psr_enable_locked(struct intel_dp *intel_dp,
+				     const struct intel_crtc_state *crtc_state)
 {
 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_encoder *encoder = &dig_port->base;
-	u32 val;
 
 	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
 
-	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
 	intel_dp->psr.busy_frontbuffer_bits = 0;
-	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
-	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
-	/* DC5/DC6 requires at least 6 idle frames */
-	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
-	intel_dp->psr.dc3co_exit_delay = val;
-	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
-	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
 
 	if (!psr_interrupt_error_check(intel_dp))
 		return;
 
 	drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
 		    intel_dp->psr.psr2_enabled ? "2" : "1");
-	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
-				     &intel_dp->psr.vsc);
+
 	intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
 	intel_psr_enable_sink(intel_dp);
 	intel_psr_enable_source(intel_dp);
@@ -1096,6 +1085,28 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	intel_psr_activate(intel_dp);
 }
 
+static void intel_psr_enable_locked(struct intel_dp *intel_dp,
+				    const struct intel_crtc_state *crtc_state,
+				    const struct drm_connector_state *conn_state)
+{
+	u32 val;
+
+	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
+	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
+	/* DC5/DC6 requires at least 6 idle frames */
+	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
+	intel_dp->psr.dc3co_exit_delay = val;
+	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
+	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
+	intel_dp->psr.paused = false;
+
+	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
+				     &intel_dp->psr.vsc);
+
+	_intel_psr_enable_locked(intel_dp, crtc_state);
+}
+
 /**
  * intel_psr_enable - Enable PSR
  * @intel_dp: Intel DP
@@ -1233,6 +1244,60 @@ void intel_psr_disable(struct intel_dp *intel_dp,
 	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
 }
 
+/**
+ * intel_psr_pause - Pause PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after enabling psr.
+ */
+void intel_psr_pause(struct intel_dp *intel_dp)
+{
+	struct intel_psr *psr = &intel_dp->psr;
+
+	if (!CAN_PSR(intel_dp))
+		return;
+
+	mutex_lock(&psr->lock);
+
+	if (!psr->active) {
+		mutex_unlock(&psr->lock);
+		return;
+	}
+
+	intel_psr_exit(intel_dp);
+	psr->paused = true;
+
+	mutex_unlock(&psr->lock);
+
+	cancel_work_sync(&psr->work);
+	cancel_delayed_work_sync(&psr->dc3co_work);
+}
+
+/**
+ * intel_psr_resume - Resume PSR
+ * @intel_dp: Intel DP
+ *
+ * This function need to be called after pausing psr.
+ */
+void intel_psr_resume(struct intel_dp *intel_dp)
+{
+	struct intel_psr *psr = &intel_dp->psr;
+
+	if (!CAN_PSR(intel_dp))
+		return;
+
+	mutex_lock(&psr->lock);
+
+	if (!psr->paused)
+		goto unlock;
+
+	psr->paused = false;
+	intel_psr_activate(intel_dp);
+
+unlock:
+	mutex_unlock(&psr->lock);
+}
+
 static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
 {
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index e3db85e97f4c..641521b101c8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -51,5 +51,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
 					const struct intel_crtc_state *crtc_state,
 					const struct intel_plane_state *plane_state,
 					int color_plane);
+void intel_psr_pause(struct intel_dp *intel_dp);
+void intel_psr_resume(struct intel_dp *intel_dp);
 
 #endif /* __INTEL_PSR_H__ */
-- 
2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (17 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17 23:02   ` Clint Taylor
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 20/23] drm/i915/adl_p: Add PLL Support Matt Roper
                   ` (7 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Mika Kahola <mika.kahola@intel.com>

Define and use DP voltage swing and pre-emphasis translation tables
for ADL-P.

v2:
 - Update according to recent bspec updates; there are now separate
   tables for RBR/HBR and HBR2/HBR3.  (Anusha)

BSpec: 54956
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c      |  7 ++-
 .../drm/i915/display/intel_ddi_buf_trans.c    | 53 +++++++++++++++++++
 .../drm/i915/display/intel_ddi_buf_trans.h    |  4 ++
 3 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 38a4f251b9c9..e0adb14ecd0d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -985,6 +985,8 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
 	if (DISPLAY_VER(dev_priv) >= 12) {
 		if (intel_phy_is_combo(dev_priv, phy))
 			tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
+		else if (IS_ALDERLAKE_P(dev_priv))
+			adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
 		else
 			tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
 	} else if (DISPLAY_VER(dev_priv) == 11) {
@@ -1431,7 +1433,10 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
 		return;
 
-	ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
+	if (IS_ALDERLAKE_P(dev_priv))
+		ddi_translations = adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
+	else
+		ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
 
 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
 		return;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
index 7bcdd5c12028..b6388d93c3ea 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
@@ -735,6 +735,34 @@ static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr
 	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
 };
 
+static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr[] = {
+				/* VS	pre-emp	Non-trans mV	Pre-emph dB */
+	{ 0x7, 0x0, 0x01 },	/* 0	0	400mV		0 dB */
+	{ 0x5, 0x0, 0x06 },	/* 0	1	400mV		3.5 dB */
+	{ 0x2, 0x0, 0x0B },	/* 0	2	400mV		6 dB */
+	{ 0x0, 0x0, 0x17 },	/* 0	3	400mV		9.5 dB */
+	{ 0x5, 0x0, 0x00 },	/* 1	0	600mV		0 dB */
+	{ 0x2, 0x0, 0x08 },	/* 1	1	600mV		3.5 dB */
+	{ 0x0, 0x0, 0x14 },	/* 1	2	600mV		6 dB */
+	{ 0x2, 0x0, 0x00 },	/* 2	0	800mV		0 dB */
+	{ 0x0, 0x0, 0x0B },	/* 2	1	800mV		3.5 dB */
+	{ 0x0, 0x0, 0x00 },	/* 3	0	1200mV		0 dB */
+};
+
+static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3[] = {
+				/* VS	pre-emp	Non-trans mV	Pre-emph dB */
+	{ 0x7, 0x0, 0x00 },	/* 0	0	400mV		0 dB */
+	{ 0x5, 0x0, 0x04 },	/* 0	1	400mV		3.5 dB */
+	{ 0x2, 0x0, 0x0A },	/* 0	2	400mV		6 dB */
+	{ 0x0, 0x0, 0x18 },	/* 0	3	400mV		9.5 dB */
+	{ 0x5, 0x0, 0x00 },	/* 1	0	600mV		0 dB */
+	{ 0x2, 0x0, 0x06 },	/* 1	1	600mV		3.5 dB */
+	{ 0x0, 0x0, 0x14 },	/* 1	2	600mV		6 dB */
+	{ 0x2, 0x0, 0x00 },	/* 2	0	800mV		0 dB */
+	{ 0x0, 0x0, 0x09 },	/* 2	1	800mV		3.5 dB */
+	{ 0x0, 0x0, 0x00 },	/* 3	0	1200mV		0 dB */
+};
+
 bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
 {
 	return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
@@ -1348,6 +1376,31 @@ tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
 		return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
 }
 
+static const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
+			  const struct intel_crtc_state *crtc_state,
+			  int *n_entries)
+{
+	if (crtc_state->port_clock > 270000) {
+		*n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3);
+		return adlp_dkl_phy_dp_ddi_trans_hbr;
+	} else {
+		*n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr);
+		return adlp_dkl_phy_dp_ddi_trans_hbr;
+	}
+}
+
+const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
+		      const struct intel_crtc_state *crtc_state,
+		      int *n_entries)
+{
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
+		return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
+	else
+		return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
+}
+
 int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
 			       const struct intel_crtc_state *crtc_state,
 			       int *default_entry)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
index f8f0ef87e977..4c2efab38642 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
@@ -67,6 +67,10 @@ bxt_get_buf_trans(struct intel_encoder *encoder,
 		  const struct intel_crtc_state *crtc_state,
 		  int *n_entries);
 
+const struct tgl_dkl_phy_ddi_buf_trans *
+adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
+		       const struct intel_crtc_state *crtc_state,
+		       int *n_entries);
 const struct cnl_ddi_buf_trans *
 tgl_get_combo_buf_trans(struct intel_encoder *encoder,
 			const struct intel_crtc_state *crtc_state,
-- 
2.25.4

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 20/23] drm/i915/adl_p: Add PLL Support
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (18 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17 21:55   ` Clint Taylor
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 21/23] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Matt Roper
                   ` (6 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx; +Cc: Lucas De Marchi

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

The clocks in ALD_P is similar to that of TGL.
The combo PLLs  use the same DPLL0, DPLL1 and TBT_PLL.

This patch adds the helper function intel_mg_pll_enable_reg()
which is similar to intel_combo_pll_enable_reg() for being lookup
place for PLL_ENABLE register in combo phy cases.

Bspec: 55409,55316
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69 ++++++++++++++-----
 drivers/gpu/drm/i915/i915_reg.h               |  8 +++
 2 files changed, 60 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index 18bfe8d09277..71ac57670043 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -149,6 +149,16 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
 			pll->info->name, onoff(state), onoff(cur_state));
 }
 
+static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
+{
+	return TC_PORT_1 + id - DPLL_ID_ICL_MGPLL1;
+}
+
+enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
+{
+	return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;
+}
+
 static i915_reg_t
 intel_combo_pll_enable_reg(struct drm_i915_private *i915,
 			   struct intel_shared_dpll *pll)
@@ -161,6 +171,19 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
 	return CNL_DPLL_ENABLE(pll->info->id);
 }
 
+static i915_reg_t
+intel_tc_pll_enable_reg(struct drm_i915_private *i915,
+			struct intel_shared_dpll *pll)
+{
+	const enum intel_dpll_id id = pll->info->id;
+	enum tc_port tc_port = icl_pll_id_to_tc_port(id);
+
+	if (IS_ALDERLAKE_P(i915))
+		return ADLP_PORTTC_PLL_ENABLE(tc_port);
+
+	return MG_PLL_ENABLE(tc_port);
+}
+
 /**
  * intel_prepare_shared_dpll - call a dpll's prepare hook
  * @crtc_state: CRTC, and its state, which has a shared dpll
@@ -3120,16 +3143,6 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
 		pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
 }
 
-static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
-{
-	return id - DPLL_ID_ICL_MGPLL1;
-}
-
-enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
-{
-	return tc_port + DPLL_ID_ICL_MGPLL1;
-}
-
 static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
 				     u32 *target_dco_khz,
 				     struct intel_dpll_hw_state *state,
@@ -3728,12 +3741,14 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	bool ret = false;
 	u32 val;
 
+	i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
+
 	wakeref = intel_display_power_get_if_enabled(dev_priv,
 						     POWER_DOMAIN_DISPLAY_CORE);
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
+	val = intel_de_read(dev_priv, enable_reg);
 	if (!(val & PLL_ENABLE))
 		goto out;
 
@@ -3797,7 +3812,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
 	if (!wakeref)
 		return false;
 
-	val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
+	val = intel_de_read(dev_priv, intel_tc_pll_enable_reg(dev_priv, pll));
 	if (!(val & PLL_ENABLE))
 		goto out;
 
@@ -4169,8 +4184,7 @@ static void tbt_pll_enable(struct drm_i915_private *dev_priv,
 static void mg_pll_enable(struct drm_i915_private *dev_priv,
 			  struct intel_shared_dpll *pll)
 {
-	i915_reg_t enable_reg =
-		MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+	i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
 
 	icl_pll_power_enable(dev_priv, pll, enable_reg);
 
@@ -4249,8 +4263,7 @@ static void tbt_pll_disable(struct drm_i915_private *dev_priv,
 static void mg_pll_disable(struct drm_i915_private *dev_priv,
 			   struct intel_shared_dpll *pll)
 {
-	i915_reg_t enable_reg =
-		MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
+	i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
 
 	icl_pll_disable(dev_priv, pll, enable_reg);
 }
@@ -4416,6 +4429,26 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
 	.dump_hw_state = icl_dump_hw_state,
 };
 
+static const struct dpll_info adlp_plls[] = {
+	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
+	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
+	{ "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
+	{ "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
+	{ "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
+	{ "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
+	{ "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
+	{ },
+};
+
+static const struct intel_dpll_mgr adlp_pll_mgr = {
+	.dpll_info = adlp_plls,
+	.get_dplls = icl_get_dplls,
+	.put_dplls = icl_put_dplls,
+	.update_active_dpll = icl_update_active_dpll,
+	.update_ref_clks = icl_update_dpll_ref_clks,
+	.dump_hw_state = icl_dump_hw_state,
+};
+
 /**
  * intel_shared_dpll_init - Initialize shared DPLLs
  * @dev: drm device
@@ -4429,7 +4462,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
 	const struct dpll_info *dpll_info;
 	int i;
 
-	if (IS_ALDERLAKE_S(dev_priv))
+	if (IS_ALDERLAKE_P(dev_priv))
+		dpll_mgr = &adlp_pll_mgr;
+	else if (IS_ALDERLAKE_S(dev_priv))
 		dpll_mgr = &adls_pll_mgr;
 	else if (IS_DG1(dev_priv))
 		dpll_mgr = &dg1_pll_mgr;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2906dff26868..063f56a301fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10548,6 +10548,14 @@ enum skl_power_gate {
 #define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
 					   _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
 
+/* ADL-P Type C PLL */
+#define PORTTC1_PLL_ENABLE	0x46038
+#define PORTTC2_PLL_ENABLE	0x46040
+
+#define ADLP_PORTTC_PLL_ENABLE(tc_port)		_MMIO_PORT((tc_port), \
+							    PORTTC1_PLL_ENABLE, \
+							    PORTTC2_PLL_ENABLE)
+
 #define _MG_REFCLKIN_CTL_PORT1				0x16892C
 #define _MG_REFCLKIN_CTL_PORT2				0x16992C
 #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 21/23] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (19 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 20/23] drm/i915/adl_p: Add PLL Support Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17 17:01   ` Souza, Jose
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 22/23] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
                   ` (5 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Imre Deak <imre.deak@intel.com>

On ADL_P besides programming the PLL accordingly the DP/HDMI link rate
should be also programmed to the DDI_BUF_CTL register, do that.

Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 36 ++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h          |  1 +
 2 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index e0adb14ecd0d..3d8918674153 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -249,6 +249,31 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 	}
 }
 
+static u32 ddi_buf_phy_link_rate(int port_clock)
+{
+	switch (port_clock) {
+	case 162000:
+		return DDI_BUF_PHY_LINK_RATE(0);
+	case 216000:
+		return DDI_BUF_PHY_LINK_RATE(4);
+	case 243000:
+		return DDI_BUF_PHY_LINK_RATE(5);
+	case 270000:
+		return DDI_BUF_PHY_LINK_RATE(1);
+	case 324000:
+		return DDI_BUF_PHY_LINK_RATE(6);
+	case 432000:
+		return DDI_BUF_PHY_LINK_RATE(7);
+	case 540000:
+		return DDI_BUF_PHY_LINK_RATE(2);
+	case 810000:
+		return DDI_BUF_PHY_LINK_RATE(3);
+	default:
+		MISSING_CASE(port_clock);
+		return DDI_BUF_PHY_LINK_RATE(0);
+	}
+}
+
 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 				      const struct intel_crtc_state *crtc_state)
 {
@@ -261,9 +286,11 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
 	intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
 
-	if (IS_ALDERLAKE_P(i915) &&
-	    intel_phy_is_tc(i915, phy) && dig_port->tc_mode != TC_PORT_TBT_ALT)
-		intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+	if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
+		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
+		if (dig_port->tc_mode != TC_PORT_TBT_ALT)
+			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+	}
 }
 
 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
@@ -3168,6 +3195,9 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
 	/* In HDMI/DVI mode, the port width, and swing/emphasis values
 	 * are ignored so nothing special needs to be done besides
 	 * enabling the port.
+	 *
+	 * On ADL_P the PHY link rate and lane count must be programmed but
+	 * these are both 0 for HDMI.
 	 */
 	intel_de_write(dev_priv, DDI_BUF_CTL(port),
 		       dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 063f56a301fb..9b8da4a6a0ae 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10183,6 +10183,7 @@ enum skl_power_gate {
 #define  DDI_BUF_CTL_ENABLE			(1 << 31)
 #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
 #define  DDI_BUF_EMP_MASK			(0xf << 24)
+#define  DDI_BUF_PHY_LINK_RATE(r)		((r) << 20)
 #define  DDI_BUF_PORT_REVERSAL			(1 << 16)
 #define  DDI_BUF_IS_IDLE			(1 << 7)
 #define  DDI_BUF_CTL_TC_PHY_OWNERSHIP		REG_BIT(6)
-- 
2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 22/23] drm/i915/adlp: Add PIPE_MISC2 programming
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (20 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 21/23] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17 21:46   ` Clint Taylor
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 23/23] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
                   ` (4 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

When scalers are enabled, we need to program underrun
bubble counter to 0x50 to avoid Soft Pipe A underruns.
Make sure other bits dont get overwritten.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h              |  7 +++++++
 2 files changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dd248995c53d..85077caa3744 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5716,8 +5716,12 @@ static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
 static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	const struct intel_crtc_scaler_state *scaler_state =
+		&crtc_state->scaler_state;
+
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	u32 val = 0;
+	int i;
 
 	switch (crtc_state->pipe_bpp) {
 	case 18:
@@ -5756,6 +5760,23 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
 	if (DISPLAY_VER(dev_priv) >= 12)
 		val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
 
+	if (IS_ALDERLAKE_P(dev_priv)) {
+		bool scaler_in_use = false;
+
+		for (i = 0; i < crtc->num_scalers; i++) {
+			if (!scaler_state->scalers[i].in_use)
+				continue;
+
+			scaler_in_use = true;
+			break;
+		}
+
+		intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
+			     PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
+			     scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
+			     PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
+	}
+
 	intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9b8da4a6a0ae..6fd126b64727 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6163,6 +6163,13 @@ enum {
 #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
 #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
 
+#define _PIPE_MISC2_A					0x7002C
+#define _PIPE_MISC2_B					0x7102C
+#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN		(0x50 << 24)
+#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS		(0x14 << 24)
+#define   PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK	(0xff << 24)
+#define PIPE_MISC2(pipe)					_MMIO_PIPE2(pipe, _PIPE_MISC2_A)
+
 /* Skylake+ pipe bottom (background) color */
 #define _SKL_BOTTOM_COLOR_A		0x70034
 #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE	(1 << 31)
-- 
2.25.4

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] [PATCH v4 23/23] drm/i915/adl_p: Update memory bandwidth parameters
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (21 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 22/23] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
@ 2021-05-15  3:10 ` Matt Roper
  2021-05-17 17:02   ` Souza, Jose
  2021-05-15  4:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alder Lake-P Support (rev3) Patchwork
                   ` (3 subsequent siblings)
  26 siblings, 1 reply; 57+ messages in thread
From: Matt Roper @ 2021-05-15  3:10 UTC (permalink / raw)
  To: intel-gfx

From: Anusha Srivatsa <anusha.srivatsa@intel.com>

ADL_P has same memory characteristics as ADL_S platform.

Bspec: 64631

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index a35435083b60..3a1ba52266a7 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -267,7 +267,7 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 	if (!HAS_DISPLAY(dev_priv))
 		return;
 
-	if (IS_ALDERLAKE_S(dev_priv))
+	if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
 		icl_get_bw_info(dev_priv, &adls_sa_info);
 	else if (IS_ROCKETLAKE(dev_priv))
 		icl_get_bw_info(dev_priv, &rkl_sa_info);
-- 
2.25.4

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alder Lake-P Support (rev3)
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (22 preceding siblings ...)
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 23/23] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
@ 2021-05-15  4:51 ` Patchwork
  2021-05-15  4:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
                   ` (2 subsequent siblings)
  26 siblings, 0 replies; 57+ messages in thread
From: Patchwork @ 2021-05-15  4:51 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: Alder Lake-P Support (rev3)
URL   : https://patchwork.freedesktop.org/series/89899/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1f1476bbdc3a drm/i915/xelpd: Enhanced pipe underrun reporting
0018489cbe17 drm/i915/xelpd: Support DP1.4 compression BPPs
-:23: CHECK:LINE_SPACING: Please don't use multiple blank lines
#23: FILE: drivers/gpu/drm/i915/display/intel_dp.c:524:
 
+

total: 0 errors, 0 warnings, 1 checks, 7 lines checked
b87e6b06fa3d drm/i915/xelpd: Calculate VDSC RC parameters
09597ccfe6b7 drm/i915/xelpd: Add rc_qp_table for rcparams calculation
-:36: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#36: 
new file mode 100644

-:326: CHECK:MACRO_ARG_PRECEDENCE: Macro argument '_bpc' may be better as '(_bpc)' to avoid precedence issues
#326: FILE: drivers/gpu/drm/i915/display/intel_qp_tables.c:286:
+#define PARAM_TABLE(_minmax, _bpc, _row, _col)  do { \
+	if (bpc == _bpc) \
+		return rc_range_##_minmax##qp444_##_bpc##bpc[_row][_col]; \
+} while (0)

-:351: CHECK:LINE_SPACING: Please don't use multiple blank lines
#351: FILE: drivers/gpu/drm/i915/display/intel_qp_tables.c:311:
+
+

total: 0 errors, 1 warnings, 2 checks, 361 lines checked
86b0a49caa0c drm/i915/xelpd: Add VRR guardband for VRR CTL
-:189: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#189: FILE: drivers/gpu/drm/i915/i915_reg.h:4380:
+#define	  XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))

total: 0 errors, 1 warnings, 0 checks, 142 lines checked
aec612c383d6 drm/i915/adl_p: Add dedicated SAGV watermarks
-:68: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects?
#68: FILE: drivers/gpu/drm/i915/i915_drv.h:593:
+#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))

-:132: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#132: FILE: drivers/gpu/drm/i915/i915_reg.h:6472:
+#define _PLANE_WM_BASE(pipe, plane) \
+	_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))

-:140: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#140: FILE: drivers/gpu/drm/i915/i915_reg.h:6480:
+#define PLANE_WM_SAGV(pipe, plane) \
+	_MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))

-:146: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#146: FILE: drivers/gpu/drm/i915/i915_reg.h:6486:
+#define PLANE_WM_SAGV_TRANS(pipe, plane) \
+	_MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))

-:152: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#152: FILE: drivers/gpu/drm/i915/i915_reg.h:6492:
+#define PLANE_WM_TRANS(pipe, plane) \
 	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))

total: 0 errors, 0 warnings, 5 checks, 213 lines checked
ab38e9a19e25 drm/i915/adl_p: Setup ports/phys
9091d510c87e drm/i915/adl_p: Handle TC cold
59056339187a drm/i915/adl_p: Implement TC sequences
0f8f45b4eab0 drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
ca87410c9f8e drm/i915/adl_p: Add ddb allocation support
-:26: WARNING:LONG_LINE_COMMENT: line length of 102 exceeds 100 columns
#26: FILE: drivers/gpu/drm/i915/i915_reg.h:7311:
+#define  DDB_ENTRY_MASK				0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */

total: 0 errors, 1 warnings, 0 checks, 172 lines checked
06e65debe409 drm/i915: Introduce MBUS relative dbuf offsets
9c7584fd868b drm/i915/adl_p: MBUS programming
-:102: WARNING:LONG_LINE: line length of 123 exceeds 100 columns
#102: FILE: drivers/gpu/drm/i915/i915_reg.h:8179:
+#define  DBUF_MIN_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */

total: 0 errors, 1 warnings, 0 checks, 236 lines checked
74e6c6938518 drm/i915/adl_p: Tx escape clock with DSI
-:65: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#65: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:375:
+		esc_clk_div_m_phy = (act_word_clk - 1)/2;
 		                                      ^

total: 0 errors, 0 warnings, 1 checks, 47 lines checked
2fb9ed851bb9 drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct
faf766443c65 drm/i915/display: Remove a redundant function argument from intel_psr_enable_source()
4b21bdb8b22f drm/i915/display: Add PSR interrupt error check function
5cf544ca43f8 drm/i915/display: Introduce new intel_psr_pause/resume function
8fa95e0f0503 drm/i915/adl_p: Define and use ADL-P specific DP translation tables
-:96: WARNING:UNNECESSARY_ELSE: else is not generally useful after a break or return
#96: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1387:
+		return adlp_dkl_phy_dp_ddi_trans_hbr;
+	} else {

-:104: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#104: FILE: drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c:1395:
+adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
+		      const struct intel_crtc_state *crtc_state,

total: 0 errors, 1 warnings, 1 checks, 94 lines checked
782c3c115c01 drm/i915/adl_p: Add PLL Support
2dd4e736791e drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL
da50af1ce2e4 drm/i915/adlp: Add PIPE_MISC2 programming
ca9ff5dd218c drm/i915/adl_p: Update memory bandwidth parameters


_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Alder Lake-P Support (rev3)
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (23 preceding siblings ...)
  2021-05-15  4:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alder Lake-P Support (rev3) Patchwork
@ 2021-05-15  4:53 ` Patchwork
  2021-05-15  5:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  2021-05-17 23:41 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Alder Lake-P Support (rev4) Patchwork
  26 siblings, 0 replies; 57+ messages in thread
From: Patchwork @ 2021-05-15  4:53 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

== Series Details ==

Series: Alder Lake-P Support (rev3)
URL   : https://patchwork.freedesktop.org/series/89899/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_display.c:1887:21:    expected struct i915_vma *[assigned] vma
+drivers/gpu/drm/i915/display/intel_display.c:1887:21:    got void [noderef] __iomem *[assigned] iomem
+drivers/gpu/drm/i915/display/intel_display.c:1887:21: warning: incorrect type in assignment (different address spaces)
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:27:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:32:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:49:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_engine_stats.h:56:9: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/gt/intel_reset.c:1329:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/intel_ring_submission.c:1203:24: warning: Using plain integer as NULL pointer
+drivers/gpu/drm/i915/i915_perf.c:1434:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1488:15: warning: memset with byte count of 16777216
+./include/asm-generic/bitops/find.h:112:45: warning: shift count is negative (-262080)
+./include/asm-generic/bitops/find.h:32:31: warning: shift count is negative (-262080)
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:409:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block


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^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BAT: failure for Alder Lake-P Support (rev3)
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (24 preceding siblings ...)
  2021-05-15  4:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2021-05-15  5:22 ` Patchwork
  2021-05-17 23:41 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Alder Lake-P Support (rev4) Patchwork
  26 siblings, 0 replies; 57+ messages in thread
From: Patchwork @ 2021-05-15  5:22 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 12256 bytes --]

== Series Details ==

Series: Alder Lake-P Support (rev3)
URL   : https://patchwork.freedesktop.org/series/89899/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10086 -> Patchwork_20133
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_20133 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20133, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20133:

### IGT changes ###

#### Possible regressions ####

  * igt@core_hotunplug@unbind-rebind:
    - fi-bwr-2160:        [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bwr-2160/igt@core_hotunplug@unbind-rebind.html

  * igt@gem_exec_fence@basic-await@bcs0:
    - fi-bsw-nick:        [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bsw-nick/igt@gem_exec_fence@basic-await@bcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bsw-nick/igt@gem_exec_fence@basic-await@bcs0.html

  
Known issues
------------

  Here are the changes found in Patchwork_20133 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fence@basic-await@bcs0:
    - fi-bsw-n3050:       NOTRUN -> [FAIL][5] ([i915#3457]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bsw-n3050/igt@gem_exec_fence@basic-await@bcs0.html

  * igt@gem_exec_fence@nb-await@bcs0:
    - fi-bsw-nick:        [PASS][6] -> [FAIL][7] ([i915#3457]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bsw-nick/igt@gem_exec_fence@nb-await@bcs0.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bsw-nick/igt@gem_exec_fence@nb-await@bcs0.html

  * igt@gem_exec_fence@nb-await@vecs0:
    - fi-bsw-kefka:       [PASS][8] -> [FAIL][9] ([i915#3457])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vecs0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vecs0.html

  * igt@gem_exec_gttfill@basic:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][10] ([fdo#109271])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bsw-n3050/igt@gem_exec_gttfill@basic.html

  * igt@gem_exec_suspend@basic-s3:
    - fi-bsw-n3050:       NOTRUN -> [INCOMPLETE][11] ([i915#3159])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bsw-n3050/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_wait@busy@all:
    - fi-bsw-kefka:       [PASS][12] -> [FAIL][13] ([i915#3177] / [i915#3457])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bsw-kefka/igt@gem_wait@busy@all.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bsw-kefka/igt@gem_wait@busy@all.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
    - fi-pnv-d510:        [PASS][14] -> [FAIL][15] ([i915#53]) +1 similar issue
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-pnv-d510/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-pnv-d510/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
    - fi-elk-e7500:       [PASS][16] -> [FAIL][17] ([i915#53])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-elk-e7500/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-elk-e7500/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-bwr-2160:        [PASS][18] -> [FAIL][19] ([i915#53])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bwr-2160/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bwr-2160/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
    - fi-ilk-650:         [PASS][20] -> [FAIL][21] ([i915#53])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-ilk-650/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-ilk-650/igt@kms_pipe_crc_basic@read-crc-pipe-b.html

  
#### Possible fixes ####

  * igt@gem_exec_fence@nb-await@vcs0:
    - fi-bsw-kefka:       [FAIL][22] ([i915#3457]) -> [PASS][23] +1 similar issue
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vcs0.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vcs0.html

  * igt@gem_wait@busy@all:
    - fi-bsw-nick:        [FAIL][24] ([i915#3177] / [i915#3457]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bsw-nick/igt@gem_wait@busy@all.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bsw-nick/igt@gem_wait@busy@all.html

  * igt@gem_wait@wait@all:
    - fi-bwr-2160:        [FAIL][26] ([i915#3457]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bwr-2160/igt@gem_wait@wait@all.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bwr-2160/igt@gem_wait@wait@all.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-elk-e7500:       [FAIL][28] ([i915#53]) -> [PASS][29] +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-bwr-2160:        [FAIL][30] ([i915#53]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bwr-2160/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bwr-2160/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
#### Warnings ####

  * igt@gem_exec_gttfill@basic:
    - fi-ilk-650:         [FAIL][32] ([i915#3457] / [i915#3472]) -> [FAIL][33] ([i915#3472])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-ilk-650/igt@gem_exec_gttfill@basic.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-ilk-650/igt@gem_exec_gttfill@basic.html

  * igt@i915_module_load@reload:
    - fi-elk-e7500:       [DMESG-FAIL][34] ([i915#3457]) -> [DMESG-WARN][35] ([i915#3457])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-elk-e7500/igt@i915_module_load@reload.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-elk-e7500/igt@i915_module_load@reload.html
    - fi-bsw-kefka:       [DMESG-FAIL][36] ([i915#1982] / [i915#3457]) -> [DMESG-WARN][37] ([i915#1982] / [i915#3457])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bsw-kefka/igt@i915_module_load@reload.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bsw-kefka/igt@i915_module_load@reload.html
    - fi-bsw-nick:        [DMESG-WARN][38] ([i915#3457]) -> [DMESG-FAIL][39] ([i915#3457])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bsw-nick/igt@i915_module_load@reload.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bsw-nick/igt@i915_module_load@reload.html

  * igt@i915_selftest@live@mman:
    - fi-bwr-2160:        [DMESG-FAIL][40] ([i915#3457]) -> [DMESG-WARN][41] ([i915#3457])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bwr-2160/igt@i915_selftest@live@mman.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bwr-2160/igt@i915_selftest@live@mman.html

  * igt@runner@aborted:
    - fi-bdw-5557u:       [FAIL][42] -> [FAIL][43] ([i915#1602] / [i915#2029])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-bdw-5557u/igt@runner@aborted.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-bdw-5557u/igt@runner@aborted.html
    - fi-skl-6700k2:      [FAIL][44] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][45] ([i915#1436] / [i915#3363])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10086/fi-skl-6700k2/igt@runner@aborted.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/fi-skl-6700k2/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2029]: https://gitlab.freedesktop.org/drm/intel/issues/2029
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
  [i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
  [i915#3159]: https://gitlab.freedesktop.org/drm/intel/issues/3159
  [i915#3177]: https://gitlab.freedesktop.org/drm/intel/issues/3177
  [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3457]: https://gitlab.freedesktop.org/drm/intel/issues/3457
  [i915#3472]: https://gitlab.freedesktop.org/drm/intel/issues/3472
  [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53


Participating hosts (32 -> 31)
------------------------------

  Additional (1): fi-bsw-n3050 
  Missing    (2): fi-rkl-11500t fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_10086 -> Patchwork_20133

  CI-20190529: 20190529
  CI_DRM_10086: a73c87ed6301c646ae2958b305c2b000104636e7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6084: 5c5734d8ee1afac871b69c4554ff14e9b56100e4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_20133: ca9ff5dd218c9c70b24a0d237e009ddf645a7a38 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ca9ff5dd218c drm/i915/adl_p: Update memory bandwidth parameters
da50af1ce2e4 drm/i915/adlp: Add PIPE_MISC2 programming
2dd4e736791e drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL
782c3c115c01 drm/i915/adl_p: Add PLL Support
8fa95e0f0503 drm/i915/adl_p: Define and use ADL-P specific DP translation tables
5cf544ca43f8 drm/i915/display: Introduce new intel_psr_pause/resume function
4b21bdb8b22f drm/i915/display: Add PSR interrupt error check function
faf766443c65 drm/i915/display: Remove a redundant function argument from intel_psr_enable_source()
2fb9ed851bb9 drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct
74e6c6938518 drm/i915/adl_p: Tx escape clock with DSI
9c7584fd868b drm/i915/adl_p: MBUS programming
06e65debe409 drm/i915: Introduce MBUS relative dbuf offsets
ca87410c9f8e drm/i915/adl_p: Add ddb allocation support
0f8f45b4eab0 drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
59056339187a drm/i915/adl_p: Implement TC sequences
9091d510c87e drm/i915/adl_p: Handle TC cold
ab38e9a19e25 drm/i915/adl_p: Setup ports/phys
aec612c383d6 drm/i915/adl_p: Add dedicated SAGV watermarks
86b0a49caa0c drm/i915/xelpd: Add VRR guardband for VRR CTL
09597ccfe6b7 drm/i915/xelpd: Add rc_qp_table for rcparams calculation
b87e6b06fa3d drm/i915/xelpd: Calculate VDSC RC parameters
0018489cbe17 drm/i915/xelpd: Support DP1.4 compression BPPs
1f1476bbdc3a drm/i915/xelpd: Enhanced pipe underrun reporting

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20133/index.html

[-- Attachment #1.2: Type: text/html, Size: 15048 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 12/23] drm/i915: Introduce MBUS relative dbuf offsets
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 12/23] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
@ 2021-05-17  6:38   ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 57+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-17  6:38 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Fri, May 14, 2021 at 08:10:24PM -0700, Matt Roper wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The dbuf slices are going to be split across several MBUS units.
> The actual dbuf programming will use offsets relative to the
> MBUS unit. To accommodate that we shall store the MBUS relative
> offsets into the dbuf_state->ddb[] and crtc_state->plane_ddb*[].
> 
> For crtc_state->wm.skl.ddb however we want to stick to global
> offsets as we use this to sanity check that the ddb allocations
> don't overlap between pipes.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 40 ++++++++++++++++++++++++++++-----
>  1 file changed, 34 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 411ec468d02a..cbbd966f710e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4057,6 +4057,20 @@ skl_ddb_entry_for_slices(struct drm_i915_private *dev_priv, u8 slice_mask,
>  	WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);
>  }
>  
> +static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
> +{
> +	struct skl_ddb_entry ddb;
> +
> +	if (slice_mask & (BIT(DBUF_S1) | BIT(DBUF_S2)))
> +		slice_mask = BIT(DBUF_S1);
> +	else if (slice_mask & (BIT(DBUF_S3) | BIT(DBUF_S4)))
> +		slice_mask = BIT(DBUF_S3);
> +
> +	skl_ddb_entry_for_slices(i915, slice_mask, &ddb);
> +
> +	return ddb.start;
> +}
> +
>  u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *dev_priv,
>  			    const struct skl_ddb_entry *entry)
>  {
> @@ -4149,6 +4163,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
>  	struct intel_crtc_state *crtc_state;
>  	struct skl_ddb_entry ddb_slices;
>  	enum pipe pipe = crtc->pipe;
> +	unsigned int mbus_offset;
>  	u32 ddb_range_size;
>  	u32 dbuf_slice_mask;
>  	u32 start, end;
> @@ -4163,6 +4178,7 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
>  	dbuf_slice_mask = new_dbuf_state->slices[pipe];
>  
>  	skl_ddb_entry_for_slices(dev_priv, dbuf_slice_mask, &ddb_slices);
> +	mbus_offset = mbus_ddb_offset(dev_priv, dbuf_slice_mask);
>  	ddb_range_size = skl_ddb_entry_size(&ddb_slices);
>  
>  	intel_crtc_dbuf_weights(new_dbuf_state, pipe,
> @@ -4171,11 +4187,11 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
>  	start = ddb_range_size * weight_start / weight_total;
>  	end = ddb_range_size * weight_end / weight_total;
>  
> -	new_dbuf_state->ddb[pipe].start = ddb_slices.start + start;
> -	new_dbuf_state->ddb[pipe].end = ddb_slices.start + end;
> -
> +	new_dbuf_state->ddb[pipe].start = ddb_slices.start - mbus_offset + start;
> +	new_dbuf_state->ddb[pipe].end = ddb_slices.start - mbus_offset + end;
>  out:
> -	if (skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
> +	if (old_dbuf_state->slices[pipe] == new_dbuf_state->slices[pipe] &&
> +	    skl_ddb_entry_equal(&old_dbuf_state->ddb[pipe],
>  				&new_dbuf_state->ddb[pipe]))
>  		return 0;
>  
> @@ -4187,7 +4203,12 @@ skl_crtc_allocate_ddb(struct intel_atomic_state *state, struct intel_crtc *crtc)
>  	if (IS_ERR(crtc_state))
>  		return PTR_ERR(crtc_state);
>  
> -	crtc_state->wm.skl.ddb = new_dbuf_state->ddb[pipe];
> +	/*
> +	 * Used for checking overlaps, so we need absolute
> +	 * offsets instead of MBUS relative offsets.
> +	 */
> +	crtc_state->wm.skl.ddb.start = mbus_offset + new_dbuf_state->ddb[pipe].start;
> +	crtc_state->wm.skl.ddb.end = mbus_offset + new_dbuf_state->ddb[pipe].end;
>  
>  	drm_dbg_kms(&dev_priv->drm,
>  		    "[CRTC:%d:%s] dbuf slices 0x%x -> 0x%x, ddb (%d - %d) -> (%d - %d), active pipes 0x%x -> 0x%x\n",
> @@ -6416,6 +6437,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  		struct intel_crtc_state *crtc_state =
>  			to_intel_crtc_state(crtc->base.state);
>  		enum pipe pipe = crtc->pipe;
> +		unsigned int mbus_offset;
>  		enum plane_id plane_id;
>  
>  		skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
> @@ -6441,7 +6463,13 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
>  
>  		dbuf_state->weight[pipe] = intel_crtc_ddb_weight(crtc_state);
>  
> -		crtc_state->wm.skl.ddb = dbuf_state->ddb[pipe];
> +		/*
> +		 * Used for checking overlaps, so we need absolute
> +		 * offsets instead of MBUS relative offsets.
> +		 */
> +		mbus_offset = mbus_ddb_offset(dev_priv, dbuf_state->slices[pipe]);
> +		crtc_state->wm.skl.ddb.start = mbus_offset + dbuf_state->ddb[pipe].start;
> +		crtc_state->wm.skl.ddb.end = mbus_offset + dbuf_state->ddb[pipe].end;
>  
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "[CRTC:%d:%s] dbuf slices 0x%x, ddb (%d - %d), active pipes 0x%x\n",
> -- 
> 2.25.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Matt Roper
@ 2021-05-17  6:39   ` Gupta, Anshuman
  0 siblings, 0 replies; 57+ messages in thread
From: Gupta, Anshuman @ 2021-05-17  6:39 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx



> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Saturday, May 15, 2021 8:40 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>; Ville Syrjälä
> <ville.syrjala@linux.intel.com>; Souza, Jose <jose.souza@intel.com>; Gupta,
> Anshuman <anshuman.gupta@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with
> dc3co_exitline on intel_psr struct
> 
> From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> 
> It replaces dc3co_enabled with dc3co_exitline on intel_psr struct.  And it saves
> dc3co_exitline, not dc3co_enabled, so we can use dc3co_exitline without
> intel_crtc_state on other psr internal function like as intel_psr_enable_source().
> 
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Looks good to me.
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h |  2 +-
>  drivers/gpu/drm/i915/display/intel_psr.c           | 10 +++++-----
>  2 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9e9f768e2d7f..b8d1f702d808 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1498,7 +1498,7 @@ struct intel_psr {
>  	bool sink_not_reliable;
>  	bool irq_aux_error;
>  	u16 su_x_granularity;
> -	bool dc3co_enabled;
> +	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
>  	struct delayed_work dc3co_work;
>  	struct drm_dp_vsc_sdp vsc;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index acaf3d459821..5bafd0de6ad9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -638,7 +638,7 @@ static void tgl_dc3co_disable_work(struct work_struct
> *work)
> 
>  static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)  {
> -	if (!intel_dp->psr.dc3co_enabled)
> +	if (!intel_dp->psr.dc3co_exitline)
>  		return;
> 
>  	cancel_delayed_work(&intel_dp->psr.dc3co_work);
> @@ -1010,7 +1010,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
> 
>  	psr_irq_control(intel_dp);
> 
> -	if (crtc_state->dc3co_exitline) {
> +	if (intel_dp->psr.dc3co_exitline) {
>  		u32 val;
> 
>  		/*
> @@ -1019,7 +1019,7 @@ static void intel_psr_enable_source(struct intel_dp
> *intel_dp,
>  		 */
>  		val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
>  		val &= ~EXITLINE_MASK;
> -		val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
> +		val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
>  		val |= EXITLINE_ENABLE;
>  		intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
>  	}
> @@ -1044,11 +1044,11 @@ static void intel_psr_enable_locked(struct intel_dp
> *intel_dp,
>  	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
>  	intel_dp->psr.busy_frontbuffer_bits = 0;
>  	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> -	intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
>  	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
>  	/* DC5/DC6 requires at least 6 idle frames */
>  	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
>  	intel_dp->psr.dc3co_exit_delay = val;
> +	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
>  	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> >enable_psr2_sel_fetch;
> 
>  	/*
> @@ -1818,7 +1818,7 @@ tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned
> int frontbuffer_bits,  {
>  	mutex_lock(&intel_dp->psr.lock);
> 
> -	if (!intel_dp->psr.dc3co_enabled)
> +	if (!intel_dp->psr.dc3co_exitline)
>  		goto unlock;
> 
>  	if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
> --
> 2.25.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 06/23] drm/i915/adl_p: Add dedicated SAGV watermarks
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 06/23] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
@ 2021-05-17  6:49   ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 57+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-17  6:49 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Fri, May 14, 2021 at 08:10:18PM -0700, Matt Roper wrote:
> XE_LPD reduces the number of regular watermark latency levels from 8
> to 6 on non-dgfx platforms.  However the hardware also adds a special
> purpose SAGV wateramrk (and an accompanying transition watermark) that
> will be used by the hardware in place of the level 0 values during SAGV
> transitions.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> Bspec: 49325, 49326, 50419
> Cc: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 32 +++++++++++
>  drivers/gpu/drm/i915/i915_drv.h              |  2 +
>  drivers/gpu/drm/i915/i915_reg.h              | 59 ++++++++++++++------
>  drivers/gpu/drm/i915/intel_pm.c              | 54 ++++++++++++++++--
>  4 files changed, 126 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ce44f18340ee..2c2c5676dc30 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8752,6 +8752,38 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  				hw_wm_level->lines);
>  		}
>  
> +		hw_wm_level = &hw->wm.planes[plane->id].sagv.wm0;
> +		sw_wm_level = &sw_wm->planes[plane->id].sagv.wm0;
> +
> +		if (HAS_HW_SAGV_WM(dev_priv) &&
> +		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
> +			drm_err(&dev_priv->drm,
> +				"[PLANE:%d:%s] mismatch in SAGV WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> +				plane->base.base.id, plane->base.name,
> +				sw_wm_level->enable,
> +				sw_wm_level->blocks,
> +				sw_wm_level->lines,
> +				hw_wm_level->enable,
> +				hw_wm_level->blocks,
> +				hw_wm_level->lines);
> +		}
> +
> +		hw_wm_level = &hw->wm.planes[plane->id].sagv.trans_wm;
> +		sw_wm_level = &sw_wm->planes[plane->id].sagv.trans_wm;
> +
> +		if (HAS_HW_SAGV_WM(dev_priv) &&
> +		    !skl_wm_level_equals(hw_wm_level, sw_wm_level)) {
> +			drm_err(&dev_priv->drm,
> +				"[PLANE:%d:%s] mismatch in SAGV trans WM (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> +				plane->base.base.id, plane->base.name,
> +				sw_wm_level->enable,
> +				sw_wm_level->blocks,
> +				sw_wm_level->lines,
> +				hw_wm_level->enable,
> +				hw_wm_level->blocks,
> +				hw_wm_level->lines);
> +		}
> +
>  		/* DDB */
>  		hw_ddb_entry = &hw->ddb_y[plane->id];
>  		sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane->id];
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6eb6c6acd81e..d7583a01e135 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -590,6 +590,8 @@ i915_fence_timeout(const struct drm_i915_private *i915)
>  /* Amount of SAGV/QGV points, BSpec precisely defines this */
>  #define I915_NUM_QGV_POINTS 8
>  
> +#define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915))
> +
>  struct ddi_vbt_port_info {
>  	/* Non-NULL if port present. */
>  	struct intel_bios_encoder_data *devdata;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dbb75cd087d3..ab6ffe036841 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6435,16 +6435,28 @@ enum {
>  /* Watermark register definitions for SKL */
>  #define _CUR_WM_A_0		0x70140
>  #define _CUR_WM_B_0		0x71140
> +#define _CUR_WM_SAGV_A		0x70158
> +#define _CUR_WM_SAGV_B		0x71158
> +#define _CUR_WM_SAGV_TRANS_A	0x7015C
> +#define _CUR_WM_SAGV_TRANS_B	0x7115C
> +#define _CUR_WM_TRANS_A		0x70168
> +#define _CUR_WM_TRANS_B		0x71168
>  #define _PLANE_WM_1_A_0		0x70240
>  #define _PLANE_WM_1_B_0		0x71240
>  #define _PLANE_WM_2_A_0		0x70340
>  #define _PLANE_WM_2_B_0		0x71340
> -#define _PLANE_WM_TRANS_1_A_0	0x70268
> -#define _PLANE_WM_TRANS_1_B_0	0x71268
> -#define _PLANE_WM_TRANS_2_A_0	0x70368
> -#define _PLANE_WM_TRANS_2_B_0	0x71368
> -#define _CUR_WM_TRANS_A_0	0x70168
> -#define _CUR_WM_TRANS_B_0	0x71168
> +#define _PLANE_WM_SAGV_1_A	0x70258
> +#define _PLANE_WM_SAGV_1_B	0x71258
> +#define _PLANE_WM_SAGV_2_A	0x70358
> +#define _PLANE_WM_SAGV_2_B	0x71358
> +#define _PLANE_WM_SAGV_TRANS_1_A	0x7025C
> +#define _PLANE_WM_SAGV_TRANS_1_B	0x7125C
> +#define _PLANE_WM_SAGV_TRANS_2_A	0x7035C
> +#define _PLANE_WM_SAGV_TRANS_2_B	0x7135C
> +#define _PLANE_WM_TRANS_1_A	0x70268
> +#define _PLANE_WM_TRANS_1_B	0x71268
> +#define _PLANE_WM_TRANS_2_A	0x70368
> +#define _PLANE_WM_TRANS_2_B	0x71368
>  #define   PLANE_WM_EN		(1 << 31)
>  #define   PLANE_WM_IGNORE_LINES	(1 << 30)
>  #define   PLANE_WM_LINES_MASK	REG_GENMASK(26, 14)
> @@ -6452,19 +6464,32 @@ enum {
>  
>  #define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
>  #define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
> -#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A_0, _CUR_WM_TRANS_B_0)
> -
> +#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
> +#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
> +#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
>  #define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0)
>  #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0)
> -#define _PLANE_WM_BASE(pipe, plane)	\
> -			_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
> -#define PLANE_WM(pipe, plane, level)	\
> -			_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
> -#define _PLANE_WM_TRANS_1(pipe)	\
> -			_PIPE(pipe, _PLANE_WM_TRANS_1_A_0, _PLANE_WM_TRANS_1_B_0)
> -#define _PLANE_WM_TRANS_2(pipe)	\
> -			_PIPE(pipe, _PLANE_WM_TRANS_2_A_0, _PLANE_WM_TRANS_2_B_0)
> -#define PLANE_WM_TRANS(pipe, plane)	\
> +#define _PLANE_WM_BASE(pipe, plane) \
> +	_PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe))
> +#define PLANE_WM(pipe, plane, level) \
> +	_MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level)))
> +#define _PLANE_WM_SAGV_1(pipe) \
> +	_PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B)
> +#define _PLANE_WM_SAGV_2(pipe) \
> +	_PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B)
> +#define PLANE_WM_SAGV(pipe, plane) \
> +	_MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe)))
> +#define _PLANE_WM_SAGV_TRANS_1(pipe) \
> +	_PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B)
> +#define _PLANE_WM_SAGV_TRANS_2(pipe) \
> +	_PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B)
> +#define PLANE_WM_SAGV_TRANS(pipe, plane) \
> +	_MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe)))
> +#define _PLANE_WM_TRANS_1(pipe) \
> +	_PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B)
> +#define _PLANE_WM_TRANS_2(pipe) \
> +	_PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B)
> +#define PLANE_WM_TRANS(pipe, plane) \
>  	_MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe)))
>  
>  /* define the Watermark register on Ironlake */
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 15d9a64e7b4c..95fda20d5547 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2983,7 +2983,9 @@ static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
>  int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
>  {
>  	/* how many WM levels are we expecting */
> -	if (DISPLAY_VER(dev_priv) >= 9)
> +	if (HAS_HW_SAGV_WM(dev_priv))
> +		return 5;
> +	else if (DISPLAY_VER(dev_priv) >= 9)
>  		return 7;
>  	else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
>  		return 4;
> @@ -4011,8 +4013,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
>  		 * latter from the plane commit hooks (especially in the legacy
>  		 * cursor case)
>  		 */
> -		pipe_wm->use_sagv_wm = DISPLAY_VER(dev_priv) >= 12 &&
> -				       intel_can_enable_sagv(dev_priv, new_bw_state);
> +		pipe_wm->use_sagv_wm = !HAS_HW_SAGV_WM(dev_priv) &&
> +			DISPLAY_VER(dev_priv) >= 12 &&
> +			intel_can_enable_sagv(dev_priv, new_bw_state);
>  	}
>  
>  	if (intel_can_enable_sagv(dev_priv, new_bw_state) !=
> @@ -5619,6 +5622,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
>  	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
>  			   skl_plane_trans_wm(pipe_wm, plane_id));
>  
> +	if (HAS_HW_SAGV_WM(dev_priv)) {
> +		skl_write_wm_level(dev_priv, PLANE_WM_SAGV(pipe, plane_id),
> +				   &wm->sagv.wm0);
> +		skl_write_wm_level(dev_priv, PLANE_WM_SAGV_TRANS(pipe, plane_id),
> +				   &wm->sagv.trans_wm);
> +	}
> +
>  	if (DISPLAY_VER(dev_priv) >= 11) {
>  		skl_ddb_entry_write(dev_priv,
>  				    PLANE_BUF_CFG(pipe, plane_id), ddb_y);
> @@ -5652,6 +5662,15 @@ void skl_write_cursor_wm(struct intel_plane *plane,
>  	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe),
>  			   skl_plane_trans_wm(pipe_wm, plane_id));
>  
> +	if (HAS_HW_SAGV_WM(dev_priv)) {
> +		const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
> +
> +		skl_write_wm_level(dev_priv, CUR_WM_SAGV(pipe),
> +				   &wm->sagv.wm0);
> +		skl_write_wm_level(dev_priv, CUR_WM_SAGV_TRANS(pipe),
> +				   &wm->sagv.trans_wm);
> +	}
> +
>  	skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
>  }
>  
> @@ -6016,6 +6035,15 @@ static bool skl_plane_selected_wm_equals(struct intel_plane *plane,
>  			return false;
>  	}
>  
> +	if (HAS_HW_SAGV_WM(i915)) {
> +		const struct skl_plane_wm *old_wm = &old_pipe_wm->planes[plane->id];
> +		const struct skl_plane_wm *new_wm = &new_pipe_wm->planes[plane->id];
> +
> +		if (!skl_wm_level_equals(&old_wm->sagv.wm0, &new_wm->sagv.wm0) ||
> +		    !skl_wm_level_equals(&old_wm->sagv.trans_wm, &new_wm->sagv.trans_wm))
> +			return false;
> +	}
> +
>  	return skl_wm_level_equals(skl_plane_trans_wm(old_pipe_wm, plane->id),
>  				   skl_plane_trans_wm(new_pipe_wm, plane->id));
>  }
> @@ -6234,7 +6262,25 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  
>  		skl_wm_level_from_reg_val(val, &wm->trans_wm);
>  
> -		if (DISPLAY_VER(dev_priv) >= 12) {
> +		if (HAS_HW_SAGV_WM(dev_priv)) {
> +			if (plane_id != PLANE_CURSOR)
> +				val = intel_uncore_read(&dev_priv->uncore,
> +							PLANE_WM_SAGV(pipe, plane_id));
> +			else
> +				val = intel_uncore_read(&dev_priv->uncore,
> +							CUR_WM_SAGV(pipe));
> +
> +			skl_wm_level_from_reg_val(val, &wm->sagv.wm0);
> +
> +			if (plane_id != PLANE_CURSOR)
> +				val = intel_uncore_read(&dev_priv->uncore,
> +							PLANE_WM_SAGV_TRANS(pipe, plane_id));
> +			else
> +				val = intel_uncore_read(&dev_priv->uncore,
> +							CUR_WM_SAGV_TRANS(pipe));
> +
> +			skl_wm_level_from_reg_val(val, &wm->sagv.trans_wm);
> +		} else if (DISPLAY_VER(dev_priv) >= 12) {
>  			wm->sagv.wm0 = wm->wm[0];
>  			wm->sagv.trans_wm = wm->trans_wm;
>  		}
> -- 
> 2.25.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 01/23] drm/i915/xelpd: Enhanced pipe underrun reporting
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 01/23] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
@ 2021-05-17  6:52   ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 57+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-17  6:52 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi

On Fri, May 14, 2021 at 08:10:13PM -0700, Matt Roper wrote:
> XE_LPD brings enhanced underrun recovery:  the hardware can somewhat
> mitigate underruns by using an interpolated replacement pixel (soft
> underrun) or the previous pixel (hard underrun).  Furthermore, underruns
> can now be caused downstream by the port, even if the pipe itself is
> operating properly.  The interrupt register and PIPE_STATUS register
> give us extra bits to recognize hard/soft underruns and determine
> whether the underrun was caused by the port, so we'll use that
> information to print some more descriptive errors when underruns occur.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> v2:
>  - Keep ICL's PIPE_STATUS defined separately from the old GMCH pipe
>    status register.  (Ville)
>  - Only read/clear the PIPE_STATUS register on platforms with
>    display ver >= 11. (Lucas)
> v3:
>  - Actually enable+unmask all the new underrun interrupts, clear stale
>    bits out from PIPE_STATUS before enabling the interrupts, report all
>    FIFO underruns errors at once, rename a bunch of stuff to unconfuse
>    vs. PIPESTAT. (Ville)
> 
> Bspec: 50335
> Bspec: 50366
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../drm/i915/display/intel_fifo_underrun.c    | 57 +++++++++++++++++--
>  drivers/gpu/drm/i915/i915_irq.c               | 19 ++++++-
>  drivers/gpu/drm/i915/i915_irq.h               |  1 +
>  drivers/gpu/drm/i915/i915_reg.h               |  9 +++
>  4 files changed, 77 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index 3315aa1d4d5a..eb841960840d 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -185,15 +185,34 @@ static void ivb_set_fifo_underrun_reporting(struct drm_device *dev,
>  	}
>  }
>  
> +static u32
> +icl_pipe_status_underrun_mask(struct drm_i915_private *dev_priv)
> +{
> +	u32 mask = PIPE_STATUS_UNDERRUN;
> +
> +	if (DISPLAY_VER(dev_priv) >= 13)
> +		mask |= PIPE_STATUS_SOFT_UNDERRUN_XELPD |
> +			PIPE_STATUS_HARD_UNDERRUN_XELPD |
> +			PIPE_STATUS_PORT_UNDERRUN_XELPD;
> +
> +	return mask;
> +}
> +
>  static void bdw_set_fifo_underrun_reporting(struct drm_device *dev,
>  					    enum pipe pipe, bool enable)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	u32 mask = gen8_de_pipe_underrun_mask(dev_priv);
>  
> -	if (enable)
> -		bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
> -	else
> -		bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);
> +	if (enable) {
> +		if (DISPLAY_VER(dev_priv) >= 11)
> +			intel_de_write(dev_priv, ICL_PIPESTATUS(pipe),
> +				       icl_pipe_status_underrun_mask(dev_priv));
> +
> +		bdw_enable_pipe_irq(dev_priv, pipe, mask);
> +	} else {
> +		bdw_disable_pipe_irq(dev_priv, pipe, mask);
> +	}
>  }
>  
>  static void ibx_set_fifo_underrun_reporting(struct drm_device *dev,
> @@ -373,6 +392,7 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
>  					 enum pipe pipe)
>  {
>  	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> +	u32 underruns = 0;
>  
>  	/* We may be called too early in init, thanks BIOS! */
>  	if (crtc == NULL)
> @@ -383,10 +403,35 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,
>  	    crtc->cpu_fifo_underrun_disabled)
>  		return;
>  
> +	/*
> +	 * Starting with display version 11, the PIPE_STAT register records
> +	 * whether an underrun has happened, and on XELPD+, it will also record
> +	 * whether the underrun was soft/hard and whether it was triggered by
> +	 * the downstream port logic.  We should clear these bits (which use
> +	 * write-1-to-clear logic) too.
> +	 *
> +	 * Note that although the IIR gives us the same underrun and soft/hard
> +	 * information, PIPE_STAT is the only place we can find out whether
> +	 * the underrun was caused by the downstream port.
> +	 */
> +	if (DISPLAY_VER(dev_priv) >= 11) {
> +		underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) &
> +			icl_pipe_status_underrun_mask(dev_priv);
> +		intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns);
> +	}
> +
>  	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {
>  		trace_intel_cpu_fifo_underrun(dev_priv, pipe);
> -		drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n",
> -			pipe_name(pipe));
> +
> +		if (DISPLAY_VER(dev_priv) >= 11)
> +			drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun: %s%s%s%s\n",
> +				pipe_name(pipe),
> +				underruns & PIPE_STATUS_SOFT_UNDERRUN_XELPD ? "soft," : "",
> +				underruns & PIPE_STATUS_HARD_UNDERRUN_XELPD ? "hard," : "",
> +				underruns & PIPE_STATUS_PORT_UNDERRUN_XELPD ? "port," : "",
> +				underruns & PIPE_STATUS_UNDERRUN ? "transcoder," : "");
> +		else
> +			drm_err(&dev_priv->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
>  	}
>  
>  	intel_fbc_handle_fifo_underrun_irq(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index d4611c643446..957d401186d2 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -2425,6 +2425,17 @@ static u32 gen8_de_pipe_flip_done_mask(struct drm_i915_private *i915)
>  		return GEN8_PIPE_PRIMARY_FLIP_DONE;
>  }
>  
> +u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv)
> +{
> +	u32 mask = GEN8_PIPE_FIFO_UNDERRUN;
> +
> +	if (DISPLAY_VER(dev_priv) >= 13)
> +		mask |= XELPD_PIPE_SOFT_UNDERRUN |
> +			XELPD_PIPE_HARD_UNDERRUN;
> +
> +	return mask;
> +}
> +
>  static irqreturn_t
>  gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  {
> @@ -2536,7 +2547,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>  		if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>  			hsw_pipe_crc_irq_handler(dev_priv, pipe);
>  
> -		if (iir & GEN8_PIPE_FIFO_UNDERRUN)
> +		if (iir & gen8_de_pipe_underrun_mask(dev_priv))
>  			intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
>  
>  		fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
> @@ -3173,7 +3184,8 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>  				     u8 pipe_mask)
>  {
>  	struct intel_uncore *uncore = &dev_priv->uncore;
> -	u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
> +	u32 extra_ier = GEN8_PIPE_VBLANK |
> +		gen8_de_pipe_underrun_mask(dev_priv) |
>  		gen8_de_pipe_flip_done_mask(dev_priv);
>  	enum pipe pipe;
>  
> @@ -3757,7 +3769,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>  	}
>  
>  	de_pipe_enables = de_pipe_masked |
> -		GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN |
> +		GEN8_PIPE_VBLANK |
> +		gen8_de_pipe_underrun_mask(dev_priv) |
>  		gen8_de_pipe_flip_done_mask(dev_priv);
>  
>  	de_port_enables = de_port_masked;
> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
> index 25f25cd95818..db34d5dbe402 100644
> --- a/drivers/gpu/drm/i915/i915_irq.h
> +++ b/drivers/gpu/drm/i915/i915_irq.h
> @@ -100,6 +100,7 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>  				     u8 pipe_mask);
>  void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
>  				     u8 pipe_mask);
> +u32 gen8_de_pipe_underrun_mask(struct drm_i915_private *dev_priv);
>  
>  bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
>  				     ktime_t *vblank_time, bool in_vblank_irq);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 089b5a59bed3..506a5aa0646b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6158,6 +6158,13 @@ enum {
>  #define   SKL_BOTTOM_COLOR_CSC_ENABLE	(1 << 30)
>  #define SKL_BOTTOM_COLOR(pipe)		_MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
>  
> +#define _ICL_PIPE_A_STATUS			0x70058
> +#define ICL_PIPESTATUS(pipe)			_MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
> +#define   PIPE_STATUS_UNDERRUN				REG_BIT(31)
> +#define   PIPE_STATUS_SOFT_UNDERRUN_XELPD		REG_BIT(28)
> +#define   PIPE_STATUS_HARD_UNDERRUN_XELPD		REG_BIT(27)
> +#define   PIPE_STATUS_PORT_UNDERRUN_XELPD		REG_BIT(26)
> +
>  #define VLV_DPFLIPSTAT				_MMIO(VLV_DISPLAY_BASE + 0x70028)
>  #define   PIPEB_LINE_COMPARE_INT_EN		(1 << 29)
>  #define   PIPEB_HLINE_INT_EN			(1 << 28)
> @@ -7814,6 +7821,8 @@ enum {
>  #define  GEN8_PIPE_FIFO_UNDERRUN	(1 << 31)
>  #define  GEN8_PIPE_CDCLK_CRC_ERROR	(1 << 29)
>  #define  GEN8_PIPE_CDCLK_CRC_DONE	(1 << 28)
> +#define  XELPD_PIPE_SOFT_UNDERRUN	(1 << 22)
> +#define  XELPD_PIPE_HARD_UNDERRUN	(1 << 21)
>  #define  GEN8_PIPE_CURSOR_FAULT		(1 << 10)
>  #define  GEN8_PIPE_SPRITE_FAULT		(1 << 9)
>  #define  GEN8_PIPE_PRIMARY_FAULT	(1 << 8)
> -- 
> 2.25.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 14/23] drm/i915/adl_p: Tx escape clock with DSI
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 14/23] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
@ 2021-05-17  7:36   ` Kulkarni, Vandita
  0 siblings, 0 replies; 57+ messages in thread
From: Kulkarni, Vandita @ 2021-05-17  7:36 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

> -----Original Message-----
> From: Roper, Matthew D <matthew.d.roper@intel.com>
> Sent: Saturday, May 15, 2021 8:40 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kahola, Mika <mika.kahola@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; Taylor, Clinton A
> <clinton.a.taylor@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>
> Subject: [PATCH v4 14/23] drm/i915/adl_p: Tx escape clock with DSI
> 
> From: Mika Kahola <mika.kahola@intel.com>
> 
> Today when the DSI controller is paired with the Combo-PHY it uses the high-
> speed (HS) Word clock for its low power (LP) transmit PPI communication to
> the DPHY. The interface signaling only changes state at an Escape clock
> frequency (i.e. its effectively running on a virtual Tx Escape clock that is
> controlled by counters w/in the controller), but all the interface flops are
> running off the HS clock.
> 
> This has the following drawbacks:
> 
>  * It is a deviation from the PPI spec which assumes signaling is
>    running on a physical Escape clock
>  * The PV timings are over constrained (HS timed to 312.5MHz vs.
>    an Escape clock of 20MHz max)
> 
> This feature is proposing to change the LP Tx communication between the
> controller and the DPHY from a virtual Tx Escape clock to a physical clock.
> 
> To do this we need to program two "M" divisors. One for the usual
> DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV register and one for
> MIPIO_DWORD8.
> 
> For DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV registers the "M" is calculated
> as following
> 
> Nt = ceil(f_link/160) (theoretical word clock) Nact = max[3, Nt + (Nt + 1)%2]
> (actual word clock) M = Nact * 8
> 
> For MIPIO_DWORD8 register, the divisor "M" is calculated as following
> 
> M = (Nact - 1)/2
> 
> BSpec: 55171
> 
> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Looks good to me.
Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com>

> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c | 21 +++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h        |  6 ++++++
>  2 files changed, 25 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index ce544e20f35c..27251b97f0c3 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -363,10 +363,19 @@ static void gen11_dsi_program_esc_clk_div(struct
> intel_encoder *encoder,
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
>  	enum port port;
>  	int afe_clk_khz;
> -	u32 esc_clk_div_m;
> +	int theo_word_clk, act_word_clk;
> +	u32 esc_clk_div_m, esc_clk_div_m_phy;
> 
>  	afe_clk_khz = afe_clk(encoder, crtc_state);
> -	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
> +
> +	if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
> +		theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 *
> DSI_MAX_ESC_CLK);
> +		act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1)
> % 2);
> +		esc_clk_div_m = act_word_clk * 8;
> +		esc_clk_div_m_phy = (act_word_clk - 1)/2;
> +	} else {
> +		esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz,
> DSI_MAX_ESC_CLK);
> +	}
> 
>  	for_each_dsi_port(port, intel_dsi->ports) {
>  		intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port), @@ -
> 379,6 +388,14 @@ static void gen11_dsi_program_esc_clk_div(struct
> intel_encoder *encoder,
>  			       esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
>  		intel_de_posting_read(dev_priv,
> ICL_DPHY_ESC_CLK_DIV(port));
>  	}
> +
> +	if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
> +		for_each_dsi_port(port, intel_dsi->ports) {
> +			intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
> +				       esc_clk_div_m_phy &
> TX_ESC_CLK_DIV_PHY);
> +			intel_de_posting_read(dev_priv,
> ADL_MIPIO_DW(port, 8));
> +		}
> +	}
>  }
> 
>  static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index 0e7a2616b3cd..2906dff26868
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -11336,6 +11336,12 @@ enum skl_power_gate {
>  #define  ICL_ESC_CLK_DIV_SHIFT			0
>  #define DSI_MAX_ESC_CLK			20000		/* in KHz */
> 
> +#define _ADL_MIPIO_REG			0x180
> +#define ADL_MIPIO_DW(port, dw)
> 	_MMIO(_ICL_COMBOPHY(port) + _ADL_MIPIO_REG + 4 * (dw))
> +#define   TX_ESC_CLK_DIV_PHY_SEL	REGBIT(16)
> +#define   TX_ESC_CLK_DIV_PHY_MASK	REG_GENMASK(23, 16)
> +#define   TX_ESC_CLK_DIV_PHY
> 	REG_FIELD_PREP(TX_ESC_CLK_DIV_PHY_MASK, 0x7f)
> +
>  #define _DSI_CMD_FRMCTL_0		0x6b034
>  #define _DSI_CMD_FRMCTL_1		0x6b834
>  #define DSI_CMD_FRMCTL(port)		_MMIO_PORT(port,	\
> --
> 2.25.4

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold Matt Roper
@ 2021-05-17 14:53   ` Imre Deak
  2021-05-17 23:15     ` Souza, Jose
  0 siblings, 1 reply; 57+ messages in thread
From: Imre Deak @ 2021-05-17 14:53 UTC (permalink / raw)
  To: Jose Souza; +Cc: intel-gfx

On Fri, May 14, 2021 at 08:10:20PM -0700, Matt Roper wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> On ADL-P TC cold is exited and blocked when legacy aux is powered,
> that is exacly the same of what ICL need for static TC ports.
> 
> TODO: When a TBT hub or monitor is connected it will cause TBT and
> legacy aux to be powered at the same time, hopefully this will not
> cause any issues but if it do, some rework will be needed.
> 
> v2:
>  - skip icl_tc_port_assert_ref_held() warn on, adl-p uses aux to
>    block TC cold
> 
> BSpec: 55480
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++-
>  drivers/gpu/drm/i915/display/intel_tc.c            | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 54c6d65011ee..29d2f1d0cffd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -551,7 +551,8 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
>  	if (drm_WARN_ON(&dev_priv->drm, !dig_port))
>  		return;
>  
> -	if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
> +	if (IS_ALDERLAKE_P(dev_priv) ||

A TC port reference is held whenever enabling the port's AUX power
domain (so whenever blocking TC-cold for instance), so this shouldn't be
needed.

OTOH, the !aux_powered check in intel_tc_port_reset_mode() needs this
exception, since there TC-cold must be blocked and so AUX will be
enabled as opposed to other platforms.

Also, in icl_tc_phy_aux_power_well_enable() we need to avoid the power
well enabling timeout error message, since it won't get enabled unless
something is actually plugged to the TC connector.

> +	    (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port))
>  		return;
>  
>  	drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index e325463acddd..1b108dea5fed 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -28,7 +28,7 @@ tc_cold_get_power_domain(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>  
> -	if (DISPLAY_VER(i915) == 11)
> +	if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) == 11)
>  		return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
>  	else
>  		return POWER_DOMAIN_TC_COLD_OFF;
> -- 
> 2.25.4
> 
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 09/23] drm/i915/adl_p: Implement TC sequences
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 09/23] drm/i915/adl_p: Implement TC sequences Matt Roper
@ 2021-05-17 15:12   ` Imre Deak
  0 siblings, 0 replies; 57+ messages in thread
From: Imre Deak @ 2021-05-17 15:12 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Fri, May 14, 2021 at 08:10:21PM -0700, Matt Roper wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> ADL-P have basically the same TC connection and disconnection
> sequences as ICL and TGL, the major difference is the new registers.
> 
> So here adding functions without the icl prefix in the name and
> making the new functions call the platform specific function to access
> the correct register.
> 
> v2:
>  - Retain DDI TC PHY ownership flag during modesetting.
> 
> BSpec: 55480
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c |   6 ++
>  drivers/gpu/drm/i915/display/intel_tc.c  | 132 +++++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h          |  10 ++
>  3 files changed, 137 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index eccbdd42d223..38a4f251b9c9 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -252,12 +252,18 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
>  static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
>  				      const struct intel_crtc_state *crtc_state)
>  {
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>  	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>  	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +	enum phy phy = intel_port_to_phy(i915, encoder->port);
>  
>  	intel_dp->DP = dig_port->saved_port_bits |
>  		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
>  	intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
> +
> +	if (IS_ALDERLAKE_P(i915) &&
> +	    intel_phy_is_tc(i915, phy) && dig_port->tc_mode != TC_PORT_TBT_ALT)
> +		intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>  }
>  
>  static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 1b108dea5fed..718e38c46dc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -205,7 +205,7 @@ static void tc_port_fixup_legacy_flag(struct intel_digital_port *dig_port,
>  	dig_port->tc_legacy_port = !dig_port->tc_legacy_port;
>  }
>  
> -static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
> +static u32 icl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>  	struct intel_uncore *uncore = &i915->uncore;
> @@ -238,6 +238,40 @@ static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
>  	return mask;
>  }
>  
> +static u32 adl_tc_port_live_status_mask(struct intel_digital_port *dig_port)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
> +	u32 isr_bit = i915->hotplug.pch_hpd[dig_port->base.hpd_pin];
> +	struct intel_uncore *uncore = &i915->uncore;
> +	u32 val, mask = 0;
> +
> +	val = intel_uncore_read(uncore, TCSS_DDI_STATUS(tc_port));
> +	if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT)
> +		mask |= BIT(TC_PORT_DP_ALT);
> +	if (val & TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT)
> +		mask |= BIT(TC_PORT_TBT_ALT);
> +
> +	if (intel_uncore_read(uncore, SDEISR) & isr_bit)
> +		mask |= BIT(TC_PORT_LEGACY);
> +
> +	/* The sink can be connected only in a single mode. */
> +	if (!drm_WARN_ON(&i915->drm, hweight32(mask) > 1))
> +		tc_port_fixup_legacy_flag(dig_port, mask);
> +
> +	return mask;
> +}
> +
> +static u32 tc_port_live_status_mask(struct intel_digital_port *dig_port)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +
> +	if (IS_ALDERLAKE_P(i915))
> +		return adl_tc_port_live_status_mask(dig_port);
> +
> +	return icl_tc_port_live_status_mask(dig_port);
> +}
> +
>  static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -256,6 +290,33 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
>  	return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
>  }
>  
> +static bool adl_tc_phy_status_complete(struct intel_digital_port *dig_port)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	struct intel_uncore *uncore = &i915->uncore;
> +	u32 val;
> +
> +	val = intel_uncore_read(uncore, TCSS_DDI_STATUS(dig_port->tc_phy_fia_idx));
> +	if (val == 0xffffffff) {
> +		drm_dbg_kms(&i915->drm,
> +			    "Port %s: PHY in TCCOLD, assuming not complete\n",
> +			    dig_port->tc_port_name);
> +		return false;
> +	}
> +
> +	return val & TCSS_DDI_STATUS_READY;
> +}
> +
> +static bool tc_phy_status_complete(struct intel_digital_port *dig_port)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +
> +	if (IS_ALDERLAKE_P(i915))
> +		return adl_tc_phy_status_complete(dig_port);
> +
> +	return icl_tc_phy_status_complete(dig_port);
> +}
> +
>  static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
>  				      bool take)
>  {
> @@ -280,7 +341,7 @@ static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
>  	intel_uncore_write(uncore,
>  			   PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
>  
> -	if (!take && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
> +	if (!take && wait_for(!tc_phy_status_complete(dig_port), 10))
>  		drm_dbg_kms(&i915->drm,
>  			    "Port %s: PHY complete clear timed out\n",
>  			    dig_port->tc_port_name);
> @@ -288,6 +349,34 @@ static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
>  	return true;
>  }
>  
> +static bool adl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
> +				      bool take)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	struct intel_uncore *uncore = &i915->uncore;
> +	enum port port = dig_port->base.port;
> +	u32 val;
> +
> +	val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
> +	if (take)
> +		val |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> +	else
> +		val &= ~DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> +	intel_uncore_write(uncore, DDI_BUF_CTL(port), val);
> +
> +	return true;
> +}
> +
> +static bool tc_phy_take_ownership(struct intel_digital_port *dig_port, bool take)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +
> +	if (IS_ALDERLAKE_P(i915))
> +		return adl_tc_phy_take_ownership(dig_port, take);
> +
> +	return icl_tc_phy_take_ownership(dig_port, take);
> +}
> +
>  static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> @@ -306,6 +395,27 @@ static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
>  	return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
>  }
>  
> +static bool adl_tc_phy_is_owned(struct intel_digital_port *dig_port)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +	struct intel_uncore *uncore = &i915->uncore;
> +	enum port port = dig_port->base.port;
> +	u32 val;
> +
> +	val = intel_uncore_read(uncore, DDI_BUF_CTL(port));
> +	return val & DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> +}
> +
> +static bool tc_phy_is_owned(struct intel_digital_port *dig_port)
> +{
> +	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> +
> +	if (IS_ALDERLAKE_P(i915))
> +		return adl_tc_phy_is_owned(dig_port);
> +
> +	return icl_tc_phy_is_owned(dig_port);
> +}
> +
>  /*
>   * This function implements the first part of the Connect Flow described by our
>   * specification, Gen11 TypeC Programming chapter. The rest of the flow (reading
> @@ -323,13 +433,13 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>  	int max_lanes;
>  
> -	if (!icl_tc_phy_status_complete(dig_port)) {
> +	if (!tc_phy_status_complete(dig_port)) {
>  		drm_dbg_kms(&i915->drm, "Port %s: PHY not ready\n",
>  			    dig_port->tc_port_name);
>  		goto out_set_tbt_alt_mode;
>  	}
>  
> -	if (!icl_tc_phy_take_ownership(dig_port, true) &&
> +	if (!tc_phy_take_ownership(dig_port, true) &&
>  	    !drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
>  		goto out_set_tbt_alt_mode;
>  
> @@ -364,7 +474,7 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
>  	return;
>  
>  out_release_phy:
> -	icl_tc_phy_take_ownership(dig_port, false);
> +	tc_phy_take_ownership(dig_port, false);
>  out_set_tbt_alt_mode:
>  	dig_port->tc_mode = TC_PORT_TBT_ALT;
>  }
> @@ -380,7 +490,7 @@ static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
>  		/* Nothing to do, we never disconnect from legacy mode */
>  		break;
>  	case TC_PORT_DP_ALT:
> -		icl_tc_phy_take_ownership(dig_port, false);
> +		tc_phy_take_ownership(dig_port, false);
>  		dig_port->tc_mode = TC_PORT_TBT_ALT;
>  		break;
>  	case TC_PORT_TBT_ALT:
> @@ -395,13 +505,13 @@ static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
>  {
>  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
>  
> -	if (!icl_tc_phy_status_complete(dig_port)) {
> +	if (!tc_phy_status_complete(dig_port)) {
>  		drm_dbg_kms(&i915->drm, "Port %s: PHY status not complete\n",
>  			    dig_port->tc_port_name);
>  		return dig_port->tc_mode == TC_PORT_TBT_ALT;
>  	}
>  
> -	if (!icl_tc_phy_is_owned(dig_port)) {
> +	if (!tc_phy_is_owned(dig_port)) {
>  		drm_dbg_kms(&i915->drm, "Port %s: PHY not owned\n",
>  			    dig_port->tc_port_name);
>  
> @@ -419,8 +529,8 @@ intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
>  	u32 live_status_mask = tc_port_live_status_mask(dig_port);
>  	enum tc_port_mode mode;
>  
> -	if (!icl_tc_phy_is_owned(dig_port) ||
> -	    drm_WARN_ON(&i915->drm, !icl_tc_phy_status_complete(dig_port)))
> +	if (!tc_phy_is_owned(dig_port) ||
> +	    drm_WARN_ON(&i915->drm, !tc_phy_status_complete(dig_port)))
>  		return TC_PORT_TBT_ALT;
>  
>  	mode = dig_port->tc_legacy_port ? TC_PORT_LEGACY : TC_PORT_DP_ALT;
> @@ -442,7 +552,7 @@ intel_tc_port_get_target_mode(struct intel_digital_port *dig_port)
>  	if (live_status_mask)
>  		return fls(live_status_mask) - 1;
>  
> -	return icl_tc_phy_status_complete(dig_port) &&
> +	return tc_phy_status_complete(dig_port) &&
>  	       dig_port->tc_legacy_port ? TC_PORT_LEGACY :
>  					  TC_PORT_TBT_ALT;
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index ab6ffe036841..65af0d84d75b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10160,6 +10160,7 @@ enum skl_power_gate {
>  #define  DDI_BUF_EMP_MASK			(0xf << 24)
>  #define  DDI_BUF_PORT_REVERSAL			(1 << 16)
>  #define  DDI_BUF_IS_IDLE			(1 << 7)
> +#define  DDI_BUF_CTL_TC_PHY_OWNERSHIP		REG_BIT(6)
>  #define  DDI_A_4_LANES				(1 << 4)
>  #define  DDI_PORT_WIDTH(width)			(((width) - 1) << 1)
>  #define  DDI_PORT_WIDTH_MASK			(7 << 1)
> @@ -12596,6 +12597,15 @@ enum skl_power_gate {
>  #define   DP_PIN_ASSIGNMENT_MASK(idx)		(0xf << ((idx) * 4))
>  #define   DP_PIN_ASSIGNMENT(idx, x)		((x) << ((idx) * 4))
>  
> +#define _TCSS_DDI_STATUS_1			0x161500
> +#define _TCSS_DDI_STATUS_2			0x161504
> +#define TCSS_DDI_STATUS(tc)			_MMIO(_PICK_EVEN(tc, \
> +								 _TCSS_DDI_STATUS_1, \
> +								 _TCSS_DDI_STATUS_2))
> +#define  TCSS_DDI_STATUS_READY			REG_BIT(2)
> +#define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT	REG_BIT(1)
> +#define  TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT	REG_BIT(0)
> +
>  /* This register controls the Display State Buffer (DSB) engines. */
>  #define _DSBSL_INSTANCE_BASE		0x70B00
>  #define DSBSL_INSTANCE(pipe, id)	(_DSBSL_INSTANCE_BASE + \
> -- 
> 2.25.4
> 
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4 compression BPPs
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
@ 2021-05-17 15:18   ` Jani Nikula
  2021-05-18  6:33     ` Kulkarni, Vandita
  0 siblings, 1 reply; 57+ messages in thread
From: Jani Nikula @ 2021-05-17 15:18 UTC (permalink / raw)
  To: Matt Roper, intel-gfx

On Fri, 14 May 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
>
> Support compression BPPs from bpc to uncompressed BPP -1.
> So far we have 8,10,12 as valid compressed BPPS now the
> support is extended.
>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dp.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 5c9222283044..16cdec9a4aa3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -521,6 +521,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
>  	drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
>  		    max_bpp_small_joiner_ram);
>  
> +
>  	/*
>  	 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
>  	 * check, output bpp from small joiner RAM check)

What happened here? This is the full patch?


-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function Matt Roper
@ 2021-05-17 16:58   ` Souza, Jose
  2021-05-18  9:33     ` Mun, Gwan-gyeong
  0 siblings, 1 reply; 57+ messages in thread
From: Souza, Jose @ 2021-05-17 16:58 UTC (permalink / raw)
  To: Mun, Gwan-gyeong, Roper, Matthew D, intel-gfx

On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> 
> This introduces the following function that can enable and disable psr
> without intel_crtc_state/drm_connector_state when intel_psr is already
> enabled with current intel_crtc_state and drm_connector_state information.
> 
> - intel_psr_pause(): Pause current PSR. it deactivates current psr state.
> - intel_psr_resume(): Resume paused PSR without intel_crtc_state and
>                       drm_connector_state. It activates paused psr state.
> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_psr.c      | 93 ++++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_psr.h      |  2 +
>  3 files changed, 82 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b8d1f702d808..ee7cbdd7db87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1482,6 +1482,7 @@ struct intel_psr {
>  	bool sink_support;
>  	bool source_support;
>  	bool enabled;
> +	bool paused;
>  	enum pipe pipe;
>  	enum transcoder transcoder;
>  	bool active;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 4a63d10876ce..d4df3f5e7918 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1060,34 +1060,23 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
>  	return true;
>  }
>  
> -static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> -				    const struct intel_crtc_state *crtc_state,
> -				    const struct drm_connector_state *conn_state)
> +static void _intel_psr_enable_locked(struct intel_dp *intel_dp,
> +				     const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	struct intel_encoder *encoder = &dig_port->base;
> -	u32 val;
>  
>  	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
>  
> -	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
>  	intel_dp->psr.busy_frontbuffer_bits = 0;
> -	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> -	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> -	/* DC5/DC6 requires at least 6 idle frames */
> -	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> -	intel_dp->psr.dc3co_exit_delay = val;
> -	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> -	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
>  
>  	if (!psr_interrupt_error_check(intel_dp))
>  		return;
>  
>  	drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
>  		    intel_dp->psr.psr2_enabled ? "2" : "1");
> -	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> -				     &intel_dp->psr.vsc);
> +
>  	intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
>  	intel_psr_enable_sink(intel_dp);
>  	intel_psr_enable_source(intel_dp);
> @@ -1096,6 +1085,28 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
>  	intel_psr_activate(intel_dp);
>  }
>  
> +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> +				    const struct intel_crtc_state *crtc_state,
> +				    const struct drm_connector_state *conn_state)
> +{
> +	u32 val;
> +
> +	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> +	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> +	/* DC5/DC6 requires at least 6 idle frames */
> +	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> +	intel_dp->psr.dc3co_exit_delay = val;
> +	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
> +	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> +	intel_dp->psr.paused = false;
> +
> +	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,
> +				     &intel_dp->psr.vsc);
> +
> +	_intel_psr_enable_locked(intel_dp, crtc_state);
> +}
> +
>  /**
>   * intel_psr_enable - Enable PSR
>   * @intel_dp: Intel DP
> @@ -1233,6 +1244,60 @@ void intel_psr_disable(struct intel_dp *intel_dp,
>  	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
>  }
>  
> +/**
> + * intel_psr_pause - Pause PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after enabling psr.
> + */
> +void intel_psr_pause(struct intel_dp *intel_dp)
> +{
> +	struct intel_psr *psr = &intel_dp->psr;
> +
> +	if (!CAN_PSR(intel_dp))
> +		return;
> +
> +	mutex_lock(&psr->lock);
> +
> +	if (!psr->active) {
> +		mutex_unlock(&psr->lock);
> +		return;
> +	}
> +
> +	intel_psr_exit(intel_dp);
> +	psr->paused = true;
> +
> +	mutex_unlock(&psr->lock);
> +
> +	cancel_work_sync(&psr->work);
> +	cancel_delayed_work_sync(&psr->dc3co_work);
> +}
> +
> +/**
> + * intel_psr_resume - Resume PSR
> + * @intel_dp: Intel DP
> + *
> + * This function need to be called after pausing psr.
> + */
> +void intel_psr_resume(struct intel_dp *intel_dp)
> +{
> +	struct intel_psr *psr = &intel_dp->psr;
> +
> +	if (!CAN_PSR(intel_dp))
> +		return;
> +
> +	mutex_lock(&psr->lock);
> +
> +	if (!psr->paused)
> +		goto unlock;
> +
> +	psr->paused = false;
> +	intel_psr_activate(intel_dp);

This patch is doing a bunch of changes around the intel_psr_enable but then it is calling intel_psr_activate().

> +
> +unlock:
> +	mutex_unlock(&psr->lock);
> +}
> +
>  static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
> index e3db85e97f4c..641521b101c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -51,5 +51,7 @@ void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane,
>  					const struct intel_crtc_state *crtc_state,
>  					const struct intel_plane_state *plane_state,
>  					int color_plane);
> +void intel_psr_pause(struct intel_dp *intel_dp);
> +void intel_psr_resume(struct intel_dp *intel_dp);
>  
>  #endif /* __INTEL_PSR_H__ */

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 21/23] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 21/23] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Matt Roper
@ 2021-05-17 17:01   ` Souza, Jose
  0 siblings, 0 replies; 57+ messages in thread
From: Souza, Jose @ 2021-05-17 17:01 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> From: Imre Deak <imre.deak@intel.com>
> 
> On ADL_P besides programming the PLL accordingly the DP/HDMI link rate
> should be also programmed to the DDI_BUF_CTL register, do that.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 36 ++++++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h          |  1 +
>  2 files changed, 34 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index e0adb14ecd0d..3d8918674153 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -249,6 +249,31 @@ static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
>  	}
>  }
>  
> +static u32 ddi_buf_phy_link_rate(int port_clock)
> +{
> +	switch (port_clock) {
> +	case 162000:
> +		return DDI_BUF_PHY_LINK_RATE(0);
> +	case 216000:
> +		return DDI_BUF_PHY_LINK_RATE(4);
> +	case 243000:
> +		return DDI_BUF_PHY_LINK_RATE(5);
> +	case 270000:
> +		return DDI_BUF_PHY_LINK_RATE(1);
> +	case 324000:
> +		return DDI_BUF_PHY_LINK_RATE(6);
> +	case 432000:
> +		return DDI_BUF_PHY_LINK_RATE(7);
> +	case 540000:
> +		return DDI_BUF_PHY_LINK_RATE(2);
> +	case 810000:
> +		return DDI_BUF_PHY_LINK_RATE(3);
> +	default:
> +		MISSING_CASE(port_clock);
> +		return DDI_BUF_PHY_LINK_RATE(0);
> +	}
> +}
> +
>  static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
>  				      const struct intel_crtc_state *crtc_state)
>  {
> @@ -261,9 +286,11 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
>  		DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
>  	intel_dp->DP |= DDI_PORT_WIDTH(crtc_state->lane_count);
>  
> -	if (IS_ALDERLAKE_P(i915) &&
> -	    intel_phy_is_tc(i915, phy) && dig_port->tc_mode != TC_PORT_TBT_ALT)
> -		intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> +	if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> +		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> +		if (dig_port->tc_mode != TC_PORT_TBT_ALT)
> +			intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> +	}
>  }
>  
>  static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
> @@ -3168,6 +3195,9 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>  	/* In HDMI/DVI mode, the port width, and swing/emphasis values
>  	 * are ignored so nothing special needs to be done besides
>  	 * enabling the port.
> +	 *
> +	 * On ADL_P the PHY link rate and lane count must be programmed but
> +	 * these are both 0 for HDMI.
>  	 */
>  	intel_de_write(dev_priv, DDI_BUF_CTL(port),
>  		       dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 063f56a301fb..9b8da4a6a0ae 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10183,6 +10183,7 @@ enum skl_power_gate {
>  #define  DDI_BUF_CTL_ENABLE			(1 << 31)
>  #define  DDI_BUF_TRANS_SELECT(n)	((n) << 24)
>  #define  DDI_BUF_EMP_MASK			(0xf << 24)
> +#define  DDI_BUF_PHY_LINK_RATE(r)		((r) << 20)
>  #define  DDI_BUF_PORT_REVERSAL			(1 << 16)
>  #define  DDI_BUF_IS_IDLE			(1 << 7)
>  #define  DDI_BUF_CTL_TC_PHY_OWNERSHIP		REG_BIT(6)

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 23/23] drm/i915/adl_p: Update memory bandwidth parameters
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 23/23] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
@ 2021-05-17 17:02   ` Souza, Jose
  0 siblings, 0 replies; 57+ messages in thread
From: Souza, Jose @ 2021-05-17 17:02 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> 
> ADL_P has same memory characteristics as ADL_S platform.
> 
> Bspec: 64631
> 

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>


> Cc: José Roberto de Souza <jose.souza@intel.com>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index a35435083b60..3a1ba52266a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -267,7 +267,7 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>  	if (!HAS_DISPLAY(dev_priv))
>  		return;
>  
> -	if (IS_ALDERLAKE_S(dev_priv))
> +	if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
>  		icl_get_bw_info(dev_priv, &adls_sa_info);
>  	else if (IS_ROCKETLAKE(dev_priv))
>  		icl_get_bw_info(dev_priv, &rkl_sa_info);

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 17/23] drm/i915/display: Add PSR interrupt error check function
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 17/23] drm/i915/display: Add PSR interrupt error check function Matt Roper
@ 2021-05-17 17:03   ` Souza, Jose
  0 siblings, 0 replies; 57+ messages in thread
From: Souza, Jose @ 2021-05-17 17:03 UTC (permalink / raw)
  To: Roper, Matthew D, intel-gfx

On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> 
> In order to reuse code of PSR interrupt error check on other PSR functions,
> it adds psr_interrupt_error_check() function.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>

> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 47 +++++++++++++++---------
>  1 file changed, 29 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index cc85083dcd28..4a63d10876ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1029,27 +1029,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp)
>  			     IGNORE_PSR2_HW_TRACKING : 0);
>  }
>  
> -static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> -				    const struct intel_crtc_state *crtc_state,
> -				    const struct drm_connector_state *conn_state)
> +static bool psr_interrupt_error_check(struct intel_dp *intel_dp)
>  {
> -	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	struct intel_encoder *encoder = &dig_port->base;
>  	u32 val;
>  
> -	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> -
> -	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> -	intel_dp->psr.busy_frontbuffer_bits = 0;
> -	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> -	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> -	/* DC5/DC6 requires at least 6 idle frames */
> -	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> -	intel_dp->psr.dc3co_exit_delay = val;
> -	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> -	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
> -
>  	/*
>  	 * If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
>  	 * will still keep the error set even after the reset done in the
> @@ -1070,9 +1054,36 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
>  		intel_dp->psr.sink_not_reliable = true;
>  		drm_dbg_kms(&dev_priv->drm,
>  			    "PSR interruption error set, not enabling PSR\n");
> -		return;
> +		return false;
>  	}
>  
> +	return true;
> +}
> +
> +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> +				    const struct intel_crtc_state *crtc_state,
> +				    const struct drm_connector_state *conn_state)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> +	struct intel_encoder *encoder = &dig_port->base;
> +	u32 val;
> +
> +	drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> +
> +	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> +	intel_dp->psr.busy_frontbuffer_bits = 0;
> +	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> +	/* DC5/DC6 requires at least 6 idle frames */
> +	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
> +	intel_dp->psr.dc3co_exit_delay = val;
> +	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> +	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
> +
> +	if (!psr_interrupt_error_check(intel_dp))
> +		return;
> +
>  	drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
>  		    intel_dp->psr.psr2_enabled ? "2" : "1");
>  	intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state, conn_state,

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 07/23] drm/i915/adl_p: Setup ports/phys
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 07/23] drm/i915/adl_p: Setup ports/phys Matt Roper
@ 2021-05-17 18:01   ` Imre Deak
  0 siblings, 0 replies; 57+ messages in thread
From: Imre Deak @ 2021-05-17 18:01 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx, Lucas De Marchi

On Fri, May 14, 2021 at 08:10:19PM -0700, Matt Roper wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
> 
> The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4.
> The first two are connected to combo phys while
> the rest are connected to TC phys.
> 
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Clinton Taylor <clinton.a.taylor@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Swathi Dhanavanthri <swathi.dhanavanthri@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2c2c5676dc30..f7b25a723f87 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3675,7 +3675,9 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
>  
>  bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
>  {
> -	if (IS_TIGERLAKE(dev_priv))
> +	if (IS_ALDERLAKE_P(dev_priv))
> +		return phy >= PHY_F && phy <= PHY_I;
> +	else if (IS_TIGERLAKE(dev_priv))
>  		return phy >= PHY_D && phy <= PHY_I;
>  	else if (IS_ICELAKE(dev_priv))
>  		return phy >= PHY_C && phy <= PHY_F;
> @@ -11253,7 +11255,14 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv)
>  	if (!HAS_DISPLAY(dev_priv))
>  		return;
>  
> -	if (IS_ALDERLAKE_S(dev_priv)) {
> +	if (IS_ALDERLAKE_P(dev_priv)) {
> +		intel_ddi_init(dev_priv, PORT_A);
> +		intel_ddi_init(dev_priv, PORT_B);
> +		intel_ddi_init(dev_priv, PORT_TC1);
> +		intel_ddi_init(dev_priv, PORT_TC2);
> +		intel_ddi_init(dev_priv, PORT_TC3);
> +		intel_ddi_init(dev_priv, PORT_TC4);
> +	} else if (IS_ALDERLAKE_S(dev_priv)) {
>  		intel_ddi_init(dev_priv, PORT_A);
>  		intel_ddi_init(dev_priv, PORT_TC1);
>  		intel_ddi_init(dev_priv, PORT_TC2);
> -- 
> 2.25.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 22/23] drm/i915/adlp: Add PIPE_MISC2 programming
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 22/23] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
@ 2021-05-17 21:46   ` Clint Taylor
  0 siblings, 0 replies; 57+ messages in thread
From: Clint Taylor @ 2021-05-17 21:46 UTC (permalink / raw)
  To: Matt Roper, intel-gfx

Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>

-Clint


On 5/14/21 8:10 PM, Matt Roper wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> When scalers are enabled, we need to program underrun
> bubble counter to 0x50 to avoid Soft Pipe A underruns.
> Make sure other bits dont get overwritten.
>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Clint Taylor <clinton.a.taylor@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display.c | 21 ++++++++++++++++++++
>   drivers/gpu/drm/i915/i915_reg.h              |  7 +++++++
>   2 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index dd248995c53d..85077caa3744 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5716,8 +5716,12 @@ static void hsw_set_pipeconf(const struct intel_crtc_state *crtc_state)
>   static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	const struct intel_crtc_scaler_state *scaler_state =
> +		&crtc_state->scaler_state;
> +
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	u32 val = 0;
> +	int i;
>   
>   	switch (crtc_state->pipe_bpp) {
>   	case 18:
> @@ -5756,6 +5760,23 @@ static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
>   	if (DISPLAY_VER(dev_priv) >= 12)
>   		val |= PIPEMISC_PIXEL_ROUNDING_TRUNC;
>   
> +	if (IS_ALDERLAKE_P(dev_priv)) {
> +		bool scaler_in_use = false;
> +
> +		for (i = 0; i < crtc->num_scalers; i++) {
> +			if (!scaler_state->scalers[i].in_use)
> +				continue;
> +
> +			scaler_in_use = true;
> +			break;
> +		}
> +
> +		intel_de_rmw(dev_priv, PIPE_MISC2(crtc->pipe),
> +			     PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK,
> +			     scaler_in_use ? PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN :
> +			     PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS);
> +	}
> +
>   	intel_de_write(dev_priv, PIPEMISC(crtc->pipe), val);
>   }
>   
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9b8da4a6a0ae..6fd126b64727 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6163,6 +6163,13 @@ enum {
>   #define   PIPEMISC_DITHER_TYPE_SP	(0 << 2)
>   #define PIPEMISC(pipe)			_MMIO_PIPE2(pipe, _PIPE_MISC_A)
>   
> +#define _PIPE_MISC2_A					0x7002C
> +#define _PIPE_MISC2_B					0x7102C
> +#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_EN		(0x50 << 24)
> +#define   PIPE_MISC2_BUBBLE_COUNTER_SCALER_DIS		(0x14 << 24)
> +#define   PIPE_MISC2_UNDERRUN_BUBBLE_COUNTER_MASK	(0xff << 24)
> +#define PIPE_MISC2(pipe)					_MMIO_PIPE2(pipe, _PIPE_MISC2_A)
> +
>   /* Skylake+ pipe bottom (background) color */
>   #define _SKL_BOTTOM_COLOR_A		0x70034
>   #define   SKL_BOTTOM_COLOR_GAMMA_ENABLE	(1 << 31)
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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 20/23] drm/i915/adl_p: Add PLL Support
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 20/23] drm/i915/adl_p: Add PLL Support Matt Roper
@ 2021-05-17 21:55   ` Clint Taylor
  0 siblings, 0 replies; 57+ messages in thread
From: Clint Taylor @ 2021-05-17 21:55 UTC (permalink / raw)
  To: Matt Roper, intel-gfx; +Cc: Lucas De Marchi

Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>

-Clint


On 5/14/21 8:10 PM, Matt Roper wrote:
> From: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> The clocks in ALD_P is similar to that of TGL.
> The combo PLLs  use the same DPLL0, DPLL1 and TBT_PLL.
>
> This patch adds the helper function intel_mg_pll_enable_reg()
> which is similar to intel_combo_pll_enable_reg() for being lookup
> place for PLL_ENABLE register in combo phy cases.
>
> Bspec: 55409,55316
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Clinton Taylor <clinton.a.taylor@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 69 ++++++++++++++-----
>   drivers/gpu/drm/i915/i915_reg.h               |  8 +++
>   2 files changed, 60 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index 18bfe8d09277..71ac57670043 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -149,6 +149,16 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
>   			pll->info->name, onoff(state), onoff(cur_state));
>   }
>   
> +static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
> +{
> +	return TC_PORT_1 + id - DPLL_ID_ICL_MGPLL1;
> +}
> +
> +enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
> +{
> +	return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;
> +}
> +
>   static i915_reg_t
>   intel_combo_pll_enable_reg(struct drm_i915_private *i915,
>   			   struct intel_shared_dpll *pll)
> @@ -161,6 +171,19 @@ intel_combo_pll_enable_reg(struct drm_i915_private *i915,
>   	return CNL_DPLL_ENABLE(pll->info->id);
>   }
>   
> +static i915_reg_t
> +intel_tc_pll_enable_reg(struct drm_i915_private *i915,
> +			struct intel_shared_dpll *pll)
> +{
> +	const enum intel_dpll_id id = pll->info->id;
> +	enum tc_port tc_port = icl_pll_id_to_tc_port(id);
> +
> +	if (IS_ALDERLAKE_P(i915))
> +		return ADLP_PORTTC_PLL_ENABLE(tc_port);
> +
> +	return MG_PLL_ENABLE(tc_port);
> +}
> +
>   /**
>    * intel_prepare_shared_dpll - call a dpll's prepare hook
>    * @crtc_state: CRTC, and its state, which has a shared dpll
> @@ -3120,16 +3143,6 @@ static void icl_calc_dpll_state(struct drm_i915_private *i915,
>   		pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
>   }
>   
> -static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
> -{
> -	return id - DPLL_ID_ICL_MGPLL1;
> -}
> -
> -enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
> -{
> -	return tc_port + DPLL_ID_ICL_MGPLL1;
> -}
> -
>   static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
>   				     u32 *target_dco_khz,
>   				     struct intel_dpll_hw_state *state,
> @@ -3728,12 +3741,14 @@ static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
>   	bool ret = false;
>   	u32 val;
>   
> +	i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
> +
>   	wakeref = intel_display_power_get_if_enabled(dev_priv,
>   						     POWER_DOMAIN_DISPLAY_CORE);
>   	if (!wakeref)
>   		return false;
>   
> -	val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
> +	val = intel_de_read(dev_priv, enable_reg);
>   	if (!(val & PLL_ENABLE))
>   		goto out;
>   
> @@ -3797,7 +3812,7 @@ static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
>   	if (!wakeref)
>   		return false;
>   
> -	val = intel_de_read(dev_priv, MG_PLL_ENABLE(tc_port));
> +	val = intel_de_read(dev_priv, intel_tc_pll_enable_reg(dev_priv, pll));
>   	if (!(val & PLL_ENABLE))
>   		goto out;
>   
> @@ -4169,8 +4184,7 @@ static void tbt_pll_enable(struct drm_i915_private *dev_priv,
>   static void mg_pll_enable(struct drm_i915_private *dev_priv,
>   			  struct intel_shared_dpll *pll)
>   {
> -	i915_reg_t enable_reg =
> -		MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
> +	i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
>   
>   	icl_pll_power_enable(dev_priv, pll, enable_reg);
>   
> @@ -4249,8 +4263,7 @@ static void tbt_pll_disable(struct drm_i915_private *dev_priv,
>   static void mg_pll_disable(struct drm_i915_private *dev_priv,
>   			   struct intel_shared_dpll *pll)
>   {
> -	i915_reg_t enable_reg =
> -		MG_PLL_ENABLE(icl_pll_id_to_tc_port(pll->info->id));
> +	i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
>   
>   	icl_pll_disable(dev_priv, pll, enable_reg);
>   }
> @@ -4416,6 +4429,26 @@ static const struct intel_dpll_mgr adls_pll_mgr = {
>   	.dump_hw_state = icl_dump_hw_state,
>   };
>   
> +static const struct dpll_info adlp_plls[] = {
> +	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
> +	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
> +	{ "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
> +	{ "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
> +	{ "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
> +	{ "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
> +	{ "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
> +	{ },
> +};
> +
> +static const struct intel_dpll_mgr adlp_pll_mgr = {
> +	.dpll_info = adlp_plls,
> +	.get_dplls = icl_get_dplls,
> +	.put_dplls = icl_put_dplls,
> +	.update_active_dpll = icl_update_active_dpll,
> +	.update_ref_clks = icl_update_dpll_ref_clks,
> +	.dump_hw_state = icl_dump_hw_state,
> +};
> +
>   /**
>    * intel_shared_dpll_init - Initialize shared DPLLs
>    * @dev: drm device
> @@ -4429,7 +4462,9 @@ void intel_shared_dpll_init(struct drm_device *dev)
>   	const struct dpll_info *dpll_info;
>   	int i;
>   
> -	if (IS_ALDERLAKE_S(dev_priv))
> +	if (IS_ALDERLAKE_P(dev_priv))
> +		dpll_mgr = &adlp_pll_mgr;
> +	else if (IS_ALDERLAKE_S(dev_priv))
>   		dpll_mgr = &adls_pll_mgr;
>   	else if (IS_DG1(dev_priv))
>   		dpll_mgr = &dg1_pll_mgr;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2906dff26868..063f56a301fb 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10548,6 +10548,14 @@ enum skl_power_gate {
>   #define DG1_DPLL_ENABLE(pll)    _MMIO_PLL3(pll, DPLL0_ENABLE, DPLL1_ENABLE, \
>   					   _MG_PLL1_ENABLE, _MG_PLL2_ENABLE)
>   
> +/* ADL-P Type C PLL */
> +#define PORTTC1_PLL_ENABLE	0x46038
> +#define PORTTC2_PLL_ENABLE	0x46040
> +
> +#define ADLP_PORTTC_PLL_ENABLE(tc_port)		_MMIO_PORT((tc_port), \
> +							    PORTTC1_PLL_ENABLE, \
> +							    PORTTC2_PLL_ENABLE)
> +
>   #define _MG_REFCLKIN_CTL_PORT1				0x16892C
>   #define _MG_REFCLKIN_CTL_PORT2				0x16992C
>   #define _MG_REFCLKIN_CTL_PORT3				0x16A92C
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
@ 2021-05-17 23:02   ` Clint Taylor
  0 siblings, 0 replies; 57+ messages in thread
From: Clint Taylor @ 2021-05-17 23:02 UTC (permalink / raw)
  To: Matt Roper, intel-gfx

Values match current BSPEC.

Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>

-Clint


On 5/14/21 8:10 PM, Matt Roper wrote:
> From: Mika Kahola <mika.kahola@intel.com>
>
> Define and use DP voltage swing and pre-emphasis translation tables
> for ADL-P.
>
> v2:
>   - Update according to recent bspec updates; there are now separate
>     tables for RBR/HBR and HBR2/HBR3.  (Anusha)
>
> BSpec: 54956
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_ddi.c      |  7 ++-
>   .../drm/i915/display/intel_ddi_buf_trans.c    | 53 +++++++++++++++++++
>   .../drm/i915/display/intel_ddi_buf_trans.h    |  4 ++
>   3 files changed, 63 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 38a4f251b9c9..e0adb14ecd0d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -985,6 +985,8 @@ static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
>   	if (DISPLAY_VER(dev_priv) >= 12) {
>   		if (intel_phy_is_combo(dev_priv, phy))
>   			tgl_get_combo_buf_trans(encoder, crtc_state, &n_entries);
> +		else if (IS_ALDERLAKE_P(dev_priv))
> +			adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
>   		else
>   			tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
>   	} else if (DISPLAY_VER(dev_priv) == 11) {
> @@ -1431,7 +1433,10 @@ tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
>   	if (enc_to_dig_port(encoder)->tc_mode == TC_PORT_TBT_ALT)
>   		return;
>   
> -	ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
> +	if (IS_ALDERLAKE_P(dev_priv))
> +		ddi_translations = adlp_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
> +	else
> +		ddi_translations = tgl_get_dkl_buf_trans(encoder, crtc_state, &n_entries);
>   
>   	if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
>   		return;
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> index 7bcdd5c12028..b6388d93c3ea 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c
> @@ -735,6 +735,34 @@ static const struct cnl_ddi_buf_trans rkl_combo_phy_ddi_translations_dp_hbr2_hbr
>   	{ 0x6, 0x7F, 0x3F, 0x00, 0x00 },	/* 900   900      0.0   */
>   };
>   
> +static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr[] = {
> +				/* VS	pre-emp	Non-trans mV	Pre-emph dB */
> +	{ 0x7, 0x0, 0x01 },	/* 0	0	400mV		0 dB */
> +	{ 0x5, 0x0, 0x06 },	/* 0	1	400mV		3.5 dB */
> +	{ 0x2, 0x0, 0x0B },	/* 0	2	400mV		6 dB */
> +	{ 0x0, 0x0, 0x17 },	/* 0	3	400mV		9.5 dB */
> +	{ 0x5, 0x0, 0x00 },	/* 1	0	600mV		0 dB */
> +	{ 0x2, 0x0, 0x08 },	/* 1	1	600mV		3.5 dB */
> +	{ 0x0, 0x0, 0x14 },	/* 1	2	600mV		6 dB */
> +	{ 0x2, 0x0, 0x00 },	/* 2	0	800mV		0 dB */
> +	{ 0x0, 0x0, 0x0B },	/* 2	1	800mV		3.5 dB */
> +	{ 0x0, 0x0, 0x00 },	/* 3	0	1200mV		0 dB */
> +};
> +
> +static const struct tgl_dkl_phy_ddi_buf_trans adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3[] = {
> +				/* VS	pre-emp	Non-trans mV	Pre-emph dB */
> +	{ 0x7, 0x0, 0x00 },	/* 0	0	400mV		0 dB */
> +	{ 0x5, 0x0, 0x04 },	/* 0	1	400mV		3.5 dB */
> +	{ 0x2, 0x0, 0x0A },	/* 0	2	400mV		6 dB */
> +	{ 0x0, 0x0, 0x18 },	/* 0	3	400mV		9.5 dB */
> +	{ 0x5, 0x0, 0x00 },	/* 1	0	600mV		0 dB */
> +	{ 0x2, 0x0, 0x06 },	/* 1	1	600mV		3.5 dB */
> +	{ 0x0, 0x0, 0x14 },	/* 1	2	600mV		6 dB */
> +	{ 0x2, 0x0, 0x00 },	/* 2	0	800mV		0 dB */
> +	{ 0x0, 0x0, 0x09 },	/* 2	1	800mV		3.5 dB */
> +	{ 0x0, 0x0, 0x00 },	/* 3	0	1200mV		0 dB */
> +};
> +
>   bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
>   {
>   	return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
> @@ -1348,6 +1376,31 @@ tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
>   		return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
>   }
>   
> +static const struct tgl_dkl_phy_ddi_buf_trans *
> +adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
> +			  const struct intel_crtc_state *crtc_state,
> +			  int *n_entries)
> +{
> +	if (crtc_state->port_clock > 270000) {
> +		*n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr2_hbr3);
> +		return adlp_dkl_phy_dp_ddi_trans_hbr;
> +	} else {
> +		*n_entries = ARRAY_SIZE(adlp_dkl_phy_dp_ddi_trans_hbr);
> +		return adlp_dkl_phy_dp_ddi_trans_hbr;
> +	}
> +}
> +
> +const struct tgl_dkl_phy_ddi_buf_trans *
> +adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
> +		      const struct intel_crtc_state *crtc_state,
> +		      int *n_entries)
> +{
> +	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> +		return tgl_get_dkl_buf_trans_hdmi(encoder, crtc_state, n_entries);
> +	else
> +		return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
> +}
> +
>   int intel_ddi_hdmi_num_entries(struct intel_encoder *encoder,
>   			       const struct intel_crtc_state *crtc_state,
>   			       int *default_entry)
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> index f8f0ef87e977..4c2efab38642 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h
> @@ -67,6 +67,10 @@ bxt_get_buf_trans(struct intel_encoder *encoder,
>   		  const struct intel_crtc_state *crtc_state,
>   		  int *n_entries);
>   
> +const struct tgl_dkl_phy_ddi_buf_trans *
> +adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
> +		       const struct intel_crtc_state *crtc_state,
> +		       int *n_entries);
>   const struct cnl_ddi_buf_trans *
>   tgl_get_combo_buf_trans(struct intel_encoder *encoder,
>   			const struct intel_crtc_state *crtc_state,
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold
  2021-05-17 14:53   ` Imre Deak
@ 2021-05-17 23:15     ` Souza, Jose
  2021-05-17 23:22       ` Souza, Jose
  0 siblings, 1 reply; 57+ messages in thread
From: Souza, Jose @ 2021-05-17 23:15 UTC (permalink / raw)
  To: Deak, Imre; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 3451 bytes --]

On Mon, 2021-05-17 at 17:53 +0300, Imre Deak wrote:
> On Fri, May 14, 2021 at 08:10:20PM -0700, Matt Roper wrote:
> > From: José Roberto de Souza <jose.souza@intel.com>
> > 
> > On ADL-P TC cold is exited and blocked when legacy aux is powered,
> > that is exacly the same of what ICL need for static TC ports.
> > 
> > TODO: When a TBT hub or monitor is connected it will cause TBT and
> > legacy aux to be powered at the same time, hopefully this will not
> > cause any issues but if it do, some rework will be needed.
> > 
> > v2:
> >  - skip icl_tc_port_assert_ref_held() warn on, adl-p uses aux to
> >    block TC cold
> > 
> > BSpec: 55480
> > Cc: Imre Deak <imre.deak@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++-
> >  drivers/gpu/drm/i915/display/intel_tc.c            | 2 +-
> >  2 files changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 54c6d65011ee..29d2f1d0cffd 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -551,7 +551,8 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
> >  	if (drm_WARN_ON(&dev_priv->drm, !dig_port))
> >  		return;
> >  
> > -	if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
> > +	if (IS_ALDERLAKE_P(dev_priv) ||
> 
> A TC port reference is held whenever enabling the port's AUX power
> domain (so whenever blocking TC-cold for instance), so this shouldn't be
> needed.

I'm kinda of rusty in this area so I could be making a mistake but I don't see how tc_lock is held or tc_link_refcount is != 0 when enabling aux to do
a DPCD transaction when the port is no driving image to the sink.
Will do some experiments and update here.

> 
> OTOH, the !aux_powered check in intel_tc_port_reset_mode() needs this
> exception, since there TC-cold must be blocked and so AUX will be
> enabled as opposed to other platforms.
> 
> Also, in icl_tc_phy_aux_power_well_enable() we need to avoid the power
> well enabling timeout error message, since it won't get enabled unless
> something is actually plugged to the TC connector.

Agree with both above, planning to squash patch.txt to fix it and make sure we don't have similar issues with future platforms.

> 
> > +	    (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port))
> >  		return;
> >  
> >  	drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> > index e325463acddd..1b108dea5fed 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -28,7 +28,7 @@ tc_cold_get_power_domain(struct intel_digital_port *dig_port)
> >  {
> >  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> >  
> > -	if (DISPLAY_VER(i915) == 11)
> > +	if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) == 11)
> >  		return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> >  	else
> >  		return POWER_DOMAIN_TC_COLD_OFF;
> > -- 
> > 2.25.4
> > 


[-- Attachment #2: patch.txt --]
[-- Type: text/plain, Size: 3079 bytes --]

commit 2119a9417715932031fcf50e7c76f158febc6c7c
Author: José Roberto de Souza <jose.souza@intel.com>
Date:   Mon May 17 16:11:22 2021 -0700

    squash

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index feab8468d272..cf6488a33192 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -620,11 +620,9 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
 	 * or need to enable AUX on a legacy TypeC port as part of the TC-cold
 	 * exit sequence.
 	 */
-	timeout_expected = is_tbt;
-	if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port) {
+	timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);
+	if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
 		icl_tc_cold_exit(dev_priv);
-		timeout_expected = true;
-	}
 
 	hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
 
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 2af4d8d5a983..3c23346aeef3 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -26,9 +26,7 @@ static const char *tc_port_mode_name(enum tc_port_mode mode)
 static enum intel_display_power_domain
 tc_cold_get_power_domain(struct intel_digital_port *dig_port)
 {
-	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
-
-	if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) == 11)
+	if (intel_tc_cold_requires_aux_pw(dig_port))
 		return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
 	else
 		return POWER_DOMAIN_TC_COLD_OFF;
@@ -454,7 +452,7 @@ static void intel_tc_port_reset_mode(struct intel_digital_port *dig_port,
 	enum tc_port_mode old_tc_mode = dig_port->tc_mode;
 
 	intel_display_power_flush_work(i915);
-	if (DISPLAY_VER(i915) != 11 || !dig_port->tc_legacy_port) {
+	if (!intel_tc_cold_requires_aux_pw(dig_port)) {
 		enum intel_display_power_domain aux_domain;
 		bool aux_powered;
 
@@ -669,3 +667,15 @@ void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy)
 	dig_port->tc_link_refcount = 0;
 	tc_port_load_fia_params(i915, dig_port);
 }
+
+bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
+{
+	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+	enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
+
+	if (!intel_phy_is_tc(i915, phy))
+		return false;
+
+	return (DISPLAY_VER(i915) == 11 && dig_port->tc_legacy_port) ||
+		IS_ALDERLAKE_P(i915);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
index b619e4736f85..0eacbd76ec15 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.h
+++ b/drivers/gpu/drm/i915/display/intel_tc.h
@@ -29,4 +29,6 @@ bool intel_tc_port_ref_held(struct intel_digital_port *dig_port);
 
 void intel_tc_port_init(struct intel_digital_port *dig_port, bool is_legacy);
 
+bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port);
+
 #endif /* __INTEL_TC_H__ */

[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold
  2021-05-17 23:15     ` Souza, Jose
@ 2021-05-17 23:22       ` Souza, Jose
  0 siblings, 0 replies; 57+ messages in thread
From: Souza, Jose @ 2021-05-17 23:22 UTC (permalink / raw)
  To: Deak, Imre; +Cc: intel-gfx

On Mon, 2021-05-17 at 16:18 -0700, José Roberto de Souza wrote:
> On Mon, 2021-05-17 at 17:53 +0300, Imre Deak wrote:
> > On Fri, May 14, 2021 at 08:10:20PM -0700, Matt Roper wrote:
> > > From: José Roberto de Souza <jose.souza@intel.com>
> > > 
> > > On ADL-P TC cold is exited and blocked when legacy aux is powered,
> > > that is exacly the same of what ICL need for static TC ports.
> > > 
> > > TODO: When a TBT hub or monitor is connected it will cause TBT and
> > > legacy aux to be powered at the same time, hopefully this will not
> > > cause any issues but if it do, some rework will be needed.
> > > 
> > > v2:
> > >  - skip icl_tc_port_assert_ref_held() warn on, adl-p uses aux to
> > >    block TC cold
> > > 
> > > BSpec: 55480
> > > Cc: Imre Deak <imre.deak@intel.com>
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display_power.c | 3 ++-
> > >  drivers/gpu/drm/i915/display/intel_tc.c            | 2 +-
> > >  2 files changed, 3 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > index 54c6d65011ee..29d2f1d0cffd 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > > @@ -551,7 +551,8 @@ static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
> > >  	if (drm_WARN_ON(&dev_priv->drm, !dig_port))
> > >  		return;
> > >  
> > > -	if (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port)
> > > +	if (IS_ALDERLAKE_P(dev_priv) ||
> > 
> > A TC port reference is held whenever enabling the port's AUX power
> > domain (so whenever blocking TC-cold for instance), so this shouldn't be
> > needed.
> 
> I'm kinda of rusty in this area so I could be making a mistake but I don't see how tc_lock is held or tc_link_refcount is != 0 when enabling aux to do
> a DPCD transaction when the port is no driving image to the sink.
> Will do some experiments and update here.

Ops please ignore the above.
Yep we don't need it, when coming from tc_cold_block() the mutex is held and when doing a DPCD transaction intel_tc_port_lock() is called before get
the aux power well.

So will drop it, thanks for pointing it out.

> 
> > 
> > OTOH, the !aux_powered check in intel_tc_port_reset_mode() needs this
> > exception, since there TC-cold must be blocked and so AUX will be
> > enabled as opposed to other platforms.
> > 
> > Also, in icl_tc_phy_aux_power_well_enable() we need to avoid the power
> > well enabling timeout error message, since it won't get enabled unless
> > something is actually plugged to the TC connector.
> 
> Agree with both above, planning to squash patch.txt to fix it and make sure we don't have similar issues with future platforms.
> 
> > 
> > > +	    (DISPLAY_VER(dev_priv) == 11 && dig_port->tc_legacy_port))
> > >  		return;
> > >  
> > >  	drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
> > > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> > > index e325463acddd..1b108dea5fed 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > > @@ -28,7 +28,7 @@ tc_cold_get_power_domain(struct intel_digital_port *dig_port)
> > >  {
> > >  	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> > >  
> > > -	if (DISPLAY_VER(i915) == 11)
> > > +	if (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) == 11)
> > >  		return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
> > >  	else
> > >  		return POWER_DOMAIN_TC_COLD_OFF;
> > > -- 
> > > 2.25.4
> > > 
> 

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BUILD: failure for Alder Lake-P Support (rev4)
  2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
                   ` (25 preceding siblings ...)
  2021-05-15  5:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2021-05-17 23:41 ` Patchwork
  26 siblings, 0 replies; 57+ messages in thread
From: Patchwork @ 2021-05-17 23:41 UTC (permalink / raw)
  To: Souza, Jose; +Cc: intel-gfx

== Series Details ==

Series: Alder Lake-P Support (rev4)
URL   : https://patchwork.freedesktop.org/series/89899/
State : failure

== Summary ==

Applying: drm/i915/xelpd: Enhanced pipe underrun reporting
Applying: drm/i915/xelpd: Support DP1.4 compression BPPs
Applying: drm/i915/xelpd: Calculate VDSC RC parameters
Applying: drm/i915/xelpd: Add rc_qp_table for rcparams calculation
Applying: drm/i915/xelpd: Add VRR guardband for VRR CTL
Applying: drm/i915/adl_p: Add dedicated SAGV watermarks
Applying: drm/i915/adl_p: Setup ports/phys
Applying: drm/i915/adl_p: Handle TC cold
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_display_power.c).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0008 drm/i915/adl_p: Handle TC cold
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".


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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4 compression BPPs
  2021-05-17 15:18   ` Jani Nikula
@ 2021-05-18  6:33     ` Kulkarni, Vandita
  0 siblings, 0 replies; 57+ messages in thread
From: Kulkarni, Vandita @ 2021-05-18  6:33 UTC (permalink / raw)
  To: Jani Nikula, Roper, Matthew D, intel-gfx

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Jani
> Nikula
> Sent: Monday, May 17, 2021 8:49 PM
> To: Roper, Matthew D <matthew.d.roper@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4
> compression BPPs
> 
> On Fri, 14 May 2021, Matt Roper <matthew.d.roper@intel.com> wrote:
> > From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >
> > Support compression BPPs from bpc to uncompressed BPP -1.
> > So far we have 8,10,12 as valid compressed BPPS now the support is
> > extended.
> >
> > Cc: Manasi Navare <manasi.d.navare@intel.com>
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dp.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 5c9222283044..16cdec9a4aa3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -521,6 +521,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct
> drm_i915_private *i915,
> >  	drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
> >  		    max_bpp_small_joiner_ram);
> >
> > +
> >  	/*
> >  	 * Greatest allowed DSC BPP = MIN (output BPP from available Link
> BW
> >  	 * check, output bpp from small joiner RAM check)
> 
> What happened here? This is the full patch?
I see that the rest of the patch is merged.

Thanks
Vandita
> 
> 
> --
> Jani Nikula, Intel Open Source Graphics Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function
  2021-05-17 16:58   ` Souza, Jose
@ 2021-05-18  9:33     ` Mun, Gwan-gyeong
  2021-05-18 11:06       ` Ville Syrjälä
  0 siblings, 1 reply; 57+ messages in thread
From: Mun, Gwan-gyeong @ 2021-05-18  9:33 UTC (permalink / raw)
  To: ville.syrjala, Roper, Matthew D, intel-gfx, Souza, Jose

Hi Ville, 
initially, intel_psr_pause() called intel_psr_disable_locked() instead
of intel_psr_exit().
In intel_psr_resume(), _intel_psr_enable_locked() was called instead of
intel_psr_activate().
Can you share what problem the initial code caused when calling
intel_psr_pause() / intel_psr_resume()?

In addition, intel_psr_exit() /intel_psr_activate() function  disable /
enable only the PSR source.
So, if disable/enable for PSR Sink Device is not called together, there
will be a problem that the PSR state machine of sink and source is
different.
What do you think?

On Mon, 2021-05-17 at 09:58 -0700, Souza, Jose wrote:
> On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> > From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > 
> > This introduces the following function that can enable and disable
> > psr
> > without intel_crtc_state/drm_connector_state when intel_psr is
> > already
> > enabled with current intel_crtc_state and drm_connector_state
> > information.
> > 
> > - intel_psr_pause(): Pause current PSR. it deactivates current psr
> > state.
> > - intel_psr_resume(): Resume paused PSR without intel_crtc_state and
> >                       drm_connector_state. It activates paused psr
> > state.
> > 
> > Cc: José Roberto de Souza <jose.souza@intel.com>
> > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > ---
> >  .../drm/i915/display/intel_display_types.h    |  1 +
> >  drivers/gpu/drm/i915/display/intel_psr.c      | 93 ++++++++++++++++-
> > --
> >  drivers/gpu/drm/i915/display/intel_psr.h      |  2 +
> >  3 files changed, 82 insertions(+), 14 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index b8d1f702d808..ee7cbdd7db87 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1482,6 +1482,7 @@ struct intel_psr {
> >         bool sink_support;
> >         bool source_support;
> >         bool enabled;
> > +       bool paused;
> >         enum pipe pipe;
> >         enum transcoder transcoder;
> >         bool active;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 4a63d10876ce..d4df3f5e7918 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -1060,34 +1060,23 @@ static bool psr_interrupt_error_check(struct
> > intel_dp *intel_dp)
> >         return true;
> >  }
> >  
> > -static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > -                                   const struct intel_crtc_state
> > *crtc_state,
> > -                                   const struct drm_connector_state
> > *conn_state)
> > +static void _intel_psr_enable_locked(struct intel_dp *intel_dp,
> > +                                    const struct intel_crtc_state
> > *crtc_state)
> >  {
> >         struct intel_digital_port *dig_port =
> > dp_to_dig_port(intel_dp);
> >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> >         struct intel_encoder *encoder = &dig_port->base;
> > -       u32 val;
> >  
> >         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> >  
> > -       intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> >         intel_dp->psr.busy_frontbuffer_bits = 0;
> > -       intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> > >pipe;
> > -       intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> > -       /* DC5/DC6 requires at least 6 idle frames */
> > -       val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > 6);
> > -       intel_dp->psr.dc3co_exit_delay = val;
> > -       intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> > -       intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > >enable_psr2_sel_fetch;
> >  
> >         if (!psr_interrupt_error_check(intel_dp))
> >                 return;
> >  
> >         drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> >                     intel_dp->psr.psr2_enabled ? "2" : "1");
> > -       intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state,
> > conn_state,
> > -                                    &intel_dp->psr.vsc);
> > +
> >         intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp-
> > >psr.vsc);
> >         intel_psr_enable_sink(intel_dp);
> >         intel_psr_enable_source(intel_dp);
> > @@ -1096,6 +1085,28 @@ static void intel_psr_enable_locked(struct
> > intel_dp *intel_dp,
> >         intel_psr_activate(intel_dp);
> >  }
> >  
> > +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > +                                   const struct intel_crtc_state
> > *crtc_state,
> > +                                   const struct drm_connector_state
> > *conn_state)
> > +{
> > +       u32 val;
> > +
> > +       intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > +       intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> > >pipe;
> > +       intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> > +       /* DC5/DC6 requires at least 6 idle frames */
> > +       val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > 6);
> > +       intel_dp->psr.dc3co_exit_delay = val;
> > +       intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > >enable_psr2_sel_fetch;
> > +       intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> > +       intel_dp->psr.paused = false;
> > +
> > +       intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state,
> > conn_state,
> > +                                    &intel_dp->psr.vsc);
> > +
> > +       _intel_psr_enable_locked(intel_dp, crtc_state);
> > +}
> > +
> >  /**
> >   * intel_psr_enable - Enable PSR
> >   * @intel_dp: Intel DP
> > @@ -1233,6 +1244,60 @@ void intel_psr_disable(struct intel_dp
> > *intel_dp,
> >         cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> >  }
> >  
> > +/**
> > + * intel_psr_pause - Pause PSR
> > + * @intel_dp: Intel DP
> > + *
> > + * This function need to be called after enabling psr.
> > + */
> > +void intel_psr_pause(struct intel_dp *intel_dp)
> > +{
> > +       struct intel_psr *psr = &intel_dp->psr;
> > +
> > +       if (!CAN_PSR(intel_dp))
> > +               return;
> > +
> > +       mutex_lock(&psr->lock);
> > +
> > +       if (!psr->active) {
> > +               mutex_unlock(&psr->lock);
> > +               return;
> > +       }
> > +
> > +       intel_psr_exit(intel_dp);
> > +       psr->paused = true;
> > +
> > +       mutex_unlock(&psr->lock);
> > +
> > +       cancel_work_sync(&psr->work);
> > +       cancel_delayed_work_sync(&psr->dc3co_work);
> > +}
> > +
> > +/**
> > + * intel_psr_resume - Resume PSR
> > + * @intel_dp: Intel DP
> > + *
> > + * This function need to be called after pausing psr.
> > + */
> > +void intel_psr_resume(struct intel_dp *intel_dp)
> > +{
> > +       struct intel_psr *psr = &intel_dp->psr;
> > +
> > +       if (!CAN_PSR(intel_dp))
> > +               return;
> > +
> > +       mutex_lock(&psr->lock);
> > +
> > +       if (!psr->paused)
> > +               goto unlock;
> > +
> > +       psr->paused = false;
> > +       intel_psr_activate(intel_dp);
> 
> This patch is doing a bunch of changes around the intel_psr_enable but
> then it is calling intel_psr_activate().
> 
> > +
> > +unlock:
> > +       mutex_unlock(&psr->lock);
> > +}
> > +
> >  static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
> >  {
> >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index e3db85e97f4c..641521b101c8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -51,5 +51,7 @@ void intel_psr2_program_plane_sel_fetch(struct
> > intel_plane *plane,
> >                                         const struct intel_crtc_state
> > *crtc_state,
> >                                         const struct
> > intel_plane_state *plane_state,
> >                                         int color_plane);
> > +void intel_psr_pause(struct intel_dp *intel_dp);
> > +void intel_psr_resume(struct intel_dp *intel_dp);
> >  
> >  #endif /* __INTEL_PSR_H__ */
> 

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function
  2021-05-18  9:33     ` Mun, Gwan-gyeong
@ 2021-05-18 11:06       ` Ville Syrjälä
  2021-05-21 10:58         ` Mun, Gwan-gyeong
  0 siblings, 1 reply; 57+ messages in thread
From: Ville Syrjälä @ 2021-05-18 11:06 UTC (permalink / raw)
  To: Mun, Gwan-gyeong; +Cc: intel-gfx

On Tue, May 18, 2021 at 09:33:09AM +0000, Mun, Gwan-gyeong wrote:
> Hi Ville, 
> initially, intel_psr_pause() called intel_psr_disable_locked() instead
> of intel_psr_exit().
> In intel_psr_resume(), _intel_psr_enable_locked() was called instead of
> intel_psr_activate().
> Can you share what problem the initial code caused when calling
> intel_psr_pause() / intel_psr_resume()?

It was doing illegal stuff with crtc->state/etc. That was oopsing.
The other problem was that IIRC it was going to do DPCD accesses
while the cdclk code was already holding the aux mutexes. I moved it
out from under the lock, but I think we might actually want it inside
the lock since we'll need that to prevent PSR during all AUX transfers
anyway. Putting it back inside the lock should also make it less racy
I guess.

> 
> In addition, intel_psr_exit() /intel_psr_activate() function  disable /
> enable only the PSR source.
> So, if disable/enable for PSR Sink Device is not called together, there
> will be a problem that the PSR state machine of sink and source is
> different.
> What do you think?

If possible I wouldn't want it touch the sink at all. It should
basically be no different to eg. enabling the vblank interrupt.

> 
> On Mon, 2021-05-17 at 09:58 -0700, Souza, Jose wrote:
> > On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> > > From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > 
> > > This introduces the following function that can enable and disable
> > > psr
> > > without intel_crtc_state/drm_connector_state when intel_psr is
> > > already
> > > enabled with current intel_crtc_state and drm_connector_state
> > > information.
> > > 
> > > - intel_psr_pause(): Pause current PSR. it deactivates current psr
> > > state.
> > > - intel_psr_resume(): Resume paused PSR without intel_crtc_state and
> > >                       drm_connector_state. It activates paused psr
> > > state.
> > > 
> > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > ---
> > >  .../drm/i915/display/intel_display_types.h    |  1 +
> > >  drivers/gpu/drm/i915/display/intel_psr.c      | 93 ++++++++++++++++-
> > > --
> > >  drivers/gpu/drm/i915/display/intel_psr.h      |  2 +
> > >  3 files changed, 82 insertions(+), 14 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index b8d1f702d808..ee7cbdd7db87 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -1482,6 +1482,7 @@ struct intel_psr {
> > >         bool sink_support;
> > >         bool source_support;
> > >         bool enabled;
> > > +       bool paused;
> > >         enum pipe pipe;
> > >         enum transcoder transcoder;
> > >         bool active;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 4a63d10876ce..d4df3f5e7918 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1060,34 +1060,23 @@ static bool psr_interrupt_error_check(struct
> > > intel_dp *intel_dp)
> > >         return true;
> > >  }
> > >  
> > > -static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > > -                                   const struct intel_crtc_state
> > > *crtc_state,
> > > -                                   const struct drm_connector_state
> > > *conn_state)
> > > +static void _intel_psr_enable_locked(struct intel_dp *intel_dp,
> > > +                                    const struct intel_crtc_state
> > > *crtc_state)
> > >  {
> > >         struct intel_digital_port *dig_port =
> > > dp_to_dig_port(intel_dp);
> > >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > >         struct intel_encoder *encoder = &dig_port->base;
> > > -       u32 val;
> > >  
> > >         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> > >  
> > > -       intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > >         intel_dp->psr.busy_frontbuffer_bits = 0;
> > > -       intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> > > >pipe;
> > > -       intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> > > -       /* DC5/DC6 requires at least 6 idle frames */
> > > -       val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > > 6);
> > > -       intel_dp->psr.dc3co_exit_delay = val;
> > > -       intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> > > -       intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > > >enable_psr2_sel_fetch;
> > >  
> > >         if (!psr_interrupt_error_check(intel_dp))
> > >                 return;
> > >  
> > >         drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> > >                     intel_dp->psr.psr2_enabled ? "2" : "1");
> > > -       intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state,
> > > conn_state,
> > > -                                    &intel_dp->psr.vsc);
> > > +
> > >         intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp-
> > > >psr.vsc);
> > >         intel_psr_enable_sink(intel_dp);
> > >         intel_psr_enable_source(intel_dp);
> > > @@ -1096,6 +1085,28 @@ static void intel_psr_enable_locked(struct
> > > intel_dp *intel_dp,
> > >         intel_psr_activate(intel_dp);
> > >  }
> > >  
> > > +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > > +                                   const struct intel_crtc_state
> > > *crtc_state,
> > > +                                   const struct drm_connector_state
> > > *conn_state)
> > > +{
> > > +       u32 val;
> > > +
> > > +       intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > > +       intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)-
> > > >pipe;
> > > +       intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> > > +       /* DC5/DC6 requires at least 6 idle frames */
> > > +       val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > > 6);
> > > +       intel_dp->psr.dc3co_exit_delay = val;
> > > +       intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > > >enable_psr2_sel_fetch;
> > > +       intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
> > > +       intel_dp->psr.paused = false;
> > > +
> > > +       intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state,
> > > conn_state,
> > > +                                    &intel_dp->psr.vsc);
> > > +
> > > +       _intel_psr_enable_locked(intel_dp, crtc_state);
> > > +}
> > > +
> > >  /**
> > >   * intel_psr_enable - Enable PSR
> > >   * @intel_dp: Intel DP
> > > @@ -1233,6 +1244,60 @@ void intel_psr_disable(struct intel_dp
> > > *intel_dp,
> > >         cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> > >  }
> > >  
> > > +/**
> > > + * intel_psr_pause - Pause PSR
> > > + * @intel_dp: Intel DP
> > > + *
> > > + * This function need to be called after enabling psr.
> > > + */
> > > +void intel_psr_pause(struct intel_dp *intel_dp)
> > > +{
> > > +       struct intel_psr *psr = &intel_dp->psr;
> > > +
> > > +       if (!CAN_PSR(intel_dp))
> > > +               return;
> > > +
> > > +       mutex_lock(&psr->lock);
> > > +
> > > +       if (!psr->active) {
> > > +               mutex_unlock(&psr->lock);
> > > +               return;
> > > +       }
> > > +
> > > +       intel_psr_exit(intel_dp);
> > > +       psr->paused = true;
> > > +
> > > +       mutex_unlock(&psr->lock);
> > > +
> > > +       cancel_work_sync(&psr->work);
> > > +       cancel_delayed_work_sync(&psr->dc3co_work);
> > > +}
> > > +
> > > +/**
> > > + * intel_psr_resume - Resume PSR
> > > + * @intel_dp: Intel DP
> > > + *
> > > + * This function need to be called after pausing psr.
> > > + */
> > > +void intel_psr_resume(struct intel_dp *intel_dp)
> > > +{
> > > +       struct intel_psr *psr = &intel_dp->psr;
> > > +
> > > +       if (!CAN_PSR(intel_dp))
> > > +               return;
> > > +
> > > +       mutex_lock(&psr->lock);
> > > +
> > > +       if (!psr->paused)
> > > +               goto unlock;
> > > +
> > > +       psr->paused = false;
> > > +       intel_psr_activate(intel_dp);
> > 
> > This patch is doing a bunch of changes around the intel_psr_enable but
> > then it is calling intel_psr_activate().
> > 
> > > +
> > > +unlock:
> > > +       mutex_unlock(&psr->lock);
> > > +}
> > > +
> > >  static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
> > >  {
> > >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > index e3db85e97f4c..641521b101c8 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > @@ -51,5 +51,7 @@ void intel_psr2_program_plane_sel_fetch(struct
> > > intel_plane *plane,
> > >                                         const struct intel_crtc_state
> > > *crtc_state,
> > >                                         const struct
> > > intel_plane_state *plane_state,
> > >                                         int color_plane);
> > > +void intel_psr_pause(struct intel_dp *intel_dp);
> > > +void intel_psr_resume(struct intel_dp *intel_dp);
> > >  
> > >  #endif /* __INTEL_PSR_H__ */
> > 
> 

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 10/23] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 10/23] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
@ 2021-05-18 11:58   ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 57+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-18 11:58 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Fri, May 14, 2021 at 08:10:22PM -0700, Matt Roper wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
> 
> Alderlake-P don't have programing sequences for MBUS or DBUF during
> display initializaiton, instead it requires programing to those
> registers during modeset because it to depend on the pipes left
> enabled.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> Bspec: 49213
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 29d2f1d0cffd..26d2eba87486 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -5246,6 +5246,9 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
>  {
>  	enum dbuf_slice slice;
>  
> +	if (IS_ALDERLAKE_P(dev_priv))
> +		return;
> +
>  	for_each_dbuf_slice(dev_priv, slice)
>  		intel_de_rmw(dev_priv, DBUF_CTL_S(slice),
>  			     DBUF_TRACKER_STATE_SERVICE_MASK,
> @@ -5257,6 +5260,9 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
>  	unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
>  	u32 mask, val, i;
>  
> +	if (IS_ALDERLAKE_P(dev_priv))
> +		return;
> +
>  	mask = MBUS_ABOX_BT_CREDIT_POOL1_MASK |
>  		MBUS_ABOX_BT_CREDIT_POOL2_MASK |
>  		MBUS_ABOX_B_CREDIT_MASK |
> -- 
> 2.25.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 11/23] drm/i915/adl_p: Add ddb allocation support
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 11/23] drm/i915/adl_p: Add ddb allocation support Matt Roper
@ 2021-05-18 12:22   ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 57+ messages in thread
From: Lisovskiy, Stanislav @ 2021-05-18 12:22 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On Fri, May 14, 2021 at 08:10:23PM -0700, Matt Roper wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> On adlp the two mbuses have two display pipes and
> two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on
> Mbus2. The Mbus can be joined and all the DBUFS can be
> used on Pipe A or B.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

> 
> Bspec: 49255
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  22 ++++--
>  drivers/gpu/drm/i915/intel_pm.c | 121 +++++++++++++++++++++++++++++++-
>  2 files changed, 138 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 65af0d84d75b..47be6054d480 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7308,7 +7308,7 @@ enum {
>  
>  #define _PLANE_BUF_CFG_1_B			0x7127c
>  #define _PLANE_BUF_CFG_2_B			0x7137c
> -#define  DDB_ENTRY_MASK				0x7FF /* skl+: 10 bits, icl+ 11 bits */
> +#define  DDB_ENTRY_MASK				0xFFF /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
>  #define  DDB_ENTRY_END_SHIFT			16
>  #define _PLANE_BUF_CFG_1(pipe)	\
>  	_PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B)
> @@ -8145,9 +8145,23 @@ enum {
>  #define  DISP_DATA_PARTITION_5_6	(1 << 6)
>  #define  DISP_IPC_ENABLE		(1 << 3)
>  
> -#define _DBUF_CTL_S1				0x45008
> -#define _DBUF_CTL_S2				0x44FE8
> -#define DBUF_CTL_S(slice)			_MMIO(_PICK_EVEN(slice, _DBUF_CTL_S1, _DBUF_CTL_S2))
> +/*
> + * The below are numbered starting from "S1" on gen11/gen12, but starting
> + * with gen13 display, the bspec switches to a 0-based numbering scheme
> + * (although the addresses stay the same so new S0 = old S1, new S1 = old S2).
> + * We'll just use the 0-based numbering here for all platforms since it's the
> + * way things will be named by the hardware team going forward, plus it's more
> + * consistent with how most of the rest of our registers are named.
> + */
> +#define _DBUF_CTL_S0				0x45008
> +#define _DBUF_CTL_S1				0x44FE8
> +#define _DBUF_CTL_S2				0x44300
> +#define _DBUF_CTL_S3				0x44304
> +#define DBUF_CTL_S(slice)			_MMIO(_PICK(slice, \
> +							    _DBUF_CTL_S0, \
> +							    _DBUF_CTL_S1, \
> +							    _DBUF_CTL_S2, \
> +							    _DBUF_CTL_S3))
>  #define  DBUF_POWER_REQUEST			REG_BIT(31)
>  #define  DBUF_POWER_STATE			REG_BIT(30)
>  #define  DBUF_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(23, 19)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 95fda20d5547..411ec468d02a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4558,6 +4558,118 @@ static const struct dbuf_slice_conf_entry tgl_allowed_dbufs[] =
>  	{}
>  };
>  
> +static const struct dbuf_slice_conf_entry adlp_allowed_dbufs[] = {
> +	{
> +		.active_pipes = BIT(PIPE_A),
> +		.dbuf_mask = {
> +			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_B),
> +		.dbuf_mask = {
> +			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B),
> +		.dbuf_mask = {
> +			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_C),
> +		.dbuf_mask = {
> +			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_A) | BIT(PIPE_C),
> +		.dbuf_mask = {
> +			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_B) | BIT(PIPE_C),
> +		.dbuf_mask = {
> +			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
> +		.dbuf_mask = {
> +			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_D),
> +		.dbuf_mask = {
> +			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_A) | BIT(PIPE_D),
> +		.dbuf_mask = {
> +			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_B) | BIT(PIPE_D),
> +		.dbuf_mask = {
> +			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
> +		.dbuf_mask = {
> +			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_C) | BIT(PIPE_D),
> +		.dbuf_mask = {
> +			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
> +		.dbuf_mask = {
> +			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> +		.dbuf_mask = {
> +			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +		},
> +	},
> +	{
> +		.active_pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
> +		.dbuf_mask = {
> +			[PIPE_A] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +			[PIPE_B] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +			[PIPE_C] = BIT(DBUF_S3) | BIT(DBUF_S4),
> +			[PIPE_D] = BIT(DBUF_S1) | BIT(DBUF_S2),
> +		},
> +	},
> +	{}
> +
> +};
> +
>  static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
>  			      const struct dbuf_slice_conf_entry *dbuf_slices)
>  {
> @@ -4597,12 +4709,19 @@ static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
>  	return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs);
>  }
>  
> +static u32 adlp_compute_dbuf_slices(enum pipe pipe, u32 active_pipes)
> +{
> +	return compute_dbuf_slices(pipe, active_pipes, adlp_allowed_dbufs);
> +}
> +
>  static u8 skl_compute_dbuf_slices(struct intel_crtc *crtc, u8 active_pipes)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  
> -	if (DISPLAY_VER(dev_priv) == 12)
> +	if (IS_ALDERLAKE_P(dev_priv))
> +		return adlp_compute_dbuf_slices(pipe, active_pipes);
> +	else if (DISPLAY_VER(dev_priv) == 12)
>  		return tgl_compute_dbuf_slices(pipe, active_pipes);
>  	else if (DISPLAY_VER(dev_priv) == 11)
>  		return icl_compute_dbuf_slices(pipe, active_pipes);
> -- 
> 2.25.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 03/23] drm/i915/xelpd: Calculate VDSC RC parameters
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 03/23] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
@ 2021-05-18 18:06   ` Navare, Manasi
  0 siblings, 0 replies; 57+ messages in thread
From: Navare, Manasi @ 2021-05-18 18:06 UTC (permalink / raw)
  To: Matt Roper; +Cc: Mohammed Khajapasha, intel-gfx, Juha-Pekka Heikkil

On Fri, May 14, 2021 at 08:10:15PM -0700, Matt Roper wrote:
> From: Vandita Kulkarni <vandita.kulkarni@intel.com>
> 
> Add methods to calculate rc parameters for all bpps, against the fixed
> arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444
> formats.  Our hw doesn't support YUV compression yet.  The calculations
> used here are from VESA C model for DSC 1.1
> 
> v2:
>  - Checkpatch fixes
> 
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Cc: Juha-Pekka Heikkil <juha-pekka.heikkila@intel.com>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> Signed-off-by: Mohammed Khajapasha <mohammed.khajapasha@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>

The new RC calculations look good to me and have been verified

Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>

Manasi

> ---
>  drivers/gpu/drm/i915/display/intel_vdsc.c | 97 ++++++++++++++++++++---
>  1 file changed, 87 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index efc3184d8315..02e86d2be395 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -5,7 +5,7 @@
>   * Author: Gaurav K Singh <gaurav.k.singh@intel.com>
>   *         Manasi Navare <manasi.d.navare@intel.com>
>   */
> -
> +#include <linux/limits.h>
>  #include "i915_drv.h"
>  #include "intel_de.h"
>  #include "intel_display_types.h"
> @@ -373,12 +373,74 @@ static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state)
>  	return true;
>  }
>  
> +static void
> +calculate_rc_params(struct rc_parameters *rc,
> +		    struct drm_dsc_config *vdsc_cfg)
> +{
> +	int bpc = vdsc_cfg->bits_per_component;
> +	int bpp = vdsc_cfg->bits_per_pixel >> 4;
> +	int ofs_und6[] = { 0, -2, -2, -4, -6, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 };
> +	int ofs_und8[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
> +	int ofs_und12[] = { 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -10, -12, -12, -12 };
> +	int ofs_und15[] = { 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -10, -12, -12, -12 };
> +	int qp_bpc_modifier = (bpc - 8) * 2;
> +	u32 res, buf_i;
> +
> +	if (vdsc_cfg->slice_height >= 8)
> +		rc->first_line_bpg_offset =
> +			12 + DIV_ROUND_UP((9 * min(34, vdsc_cfg->slice_height - 8)), 100);
> +	else
> +		rc->first_line_bpg_offset = 2 * (vdsc_cfg->slice_height - 1);
> +
> +	/* Our hw supports only 444 modes as of today */
> +	if (bpp >= 12)
> +		rc->initial_offset = 2048;
> +	else if (bpp >= 10)
> +		rc->initial_offset = 5632 - DIV_ROUND_UP(((bpp - 10) * 3584), 2);
> +	else if (bpp >= 8)
> +		rc->initial_offset = 6144 - DIV_ROUND_UP(((bpp - 8) * 512), 2);
> +	else
> +		rc->initial_offset = 6144;
> +
> +	/* initial_xmit_delay = rc_model_size/2/compression_bpp */
> +	rc->initial_xmit_delay = DIV_ROUND_UP(DSC_RC_MODEL_SIZE_CONST, 2 * bpp);
> +
> +	rc->flatness_min_qp = 3 + qp_bpc_modifier;
> +	rc->flatness_max_qp = 12 + qp_bpc_modifier;
> +
> +	rc->rc_quant_incr_limit0 = 11 + qp_bpc_modifier;
> +	rc->rc_quant_incr_limit1 = 11 + qp_bpc_modifier;
> +
> +	for (buf_i = 0; buf_i < DSC_NUM_BUF_RANGES; buf_i++) {
> +		/* Calculate range_bgp_offset */
> +		if (bpp <= 6) {
> +			rc->rc_range_params[buf_i].range_bpg_offset = ofs_und6[buf_i];
> +		} else if (bpp <= 8) {
> +			res = DIV_ROUND_UP(((bpp - 6) * (ofs_und8[buf_i] - ofs_und6[buf_i])), 2);
> +			rc->rc_range_params[buf_i].range_bpg_offset =
> +								ofs_und6[buf_i] + res;
> +		} else if (bpp <= 12) {
> +			rc->rc_range_params[buf_i].range_bpg_offset =
> +								ofs_und8[buf_i];
> +		} else if (bpp <= 15) {
> +			res = DIV_ROUND_UP(((bpp - 12) * (ofs_und15[buf_i] - ofs_und12[buf_i])), 3);
> +			rc->rc_range_params[buf_i].range_bpg_offset =
> +								ofs_und12[buf_i] + res;
> +		} else {
> +			rc->rc_range_params[buf_i].range_bpg_offset =
> +								ofs_und15[buf_i];
> +		}
> +	}
> +}
> +
>  int intel_dsc_compute_params(struct intel_encoder *encoder,
>  			     struct intel_crtc_state *pipe_config)
>  {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
>  	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
>  	const struct rc_parameters *rc_params;
> +	struct rc_parameters *rc = NULL;
>  	u8 i = 0;
>  
>  	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
> @@ -413,9 +475,24 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
>  		vdsc_cfg->rc_buf_thresh[13] = 0x7D;
>  	}
>  
> -	rc_params = get_rc_params(compressed_bpp, vdsc_cfg->bits_per_component);
> -	if (!rc_params)
> -		return -EINVAL;
> +	/*
> +	 * From XE_LPD onwards we supports compression bpps in steps of 1
> +	 * upto uncompressed bpp-1, hence add calculations for all the rc
> +	 * parameters
> +	 */
> +	if (DISPLAY_VER(dev_priv) >= 13) {
> +		rc = kmalloc(sizeof(*rc), GFP_KERNEL);
> +		if (!rc)
> +			return -ENOMEM;
> +
> +		calculate_rc_params(rc, vdsc_cfg);
> +		rc_params = rc;
> +	} else {
> +		rc_params = get_rc_params(compressed_bpp,
> +					  vdsc_cfg->bits_per_component);
> +		if (!rc_params)
> +			return -EINVAL;
> +	}
>  
>  	vdsc_cfg->first_line_bpg_offset = rc_params->first_line_bpg_offset;
>  	vdsc_cfg->initial_xmit_delay = rc_params->initial_xmit_delay;
> @@ -441,20 +518,20 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
>  
>  	/*
>  	 * BitsPerComponent value determines mux_word_size:
> -	 * When BitsPerComponent is 12bpc, muxWordSize will be equal to 64 bits
> -	 * When BitsPerComponent is 8 or 10bpc, muxWordSize will be equal to
> -	 * 48 bits
> +	 * When BitsPerComponent is less than or 10bpc, muxWordSize will be equal to
> +	 * 48 bits otherwise 64
>  	 */
> -	if (vdsc_cfg->bits_per_component == 8 ||
> -	    vdsc_cfg->bits_per_component == 10)
> +	if (vdsc_cfg->bits_per_component <= 10)
>  		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
> -	else if (vdsc_cfg->bits_per_component == 12)
> +	else
>  		vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC;
>  
>  	/* InitialScaleValue is a 6 bit value with 3 fractional bits (U3.3) */
>  	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
>  		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
>  
> +	kfree(rc);
> +
>  	return 0;
>  }
>  
> -- 
> 2.25.4
> 
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 16/23] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source()
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 16/23] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() Matt Roper
@ 2021-05-19  6:49   ` Anshuman Gupta
  0 siblings, 0 replies; 57+ messages in thread
From: Anshuman Gupta @ 2021-05-19  6:49 UTC (permalink / raw)
  To: Matt Roper; +Cc: intel-gfx

On 2021-05-15 at 08:40:28 +0530, Matt Roper wrote:
> From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> 
> It removes intel_crtc_state from function argument of
> intel_psr_enable_source() in order to use intel_psr_enable_source()
> without intel_crtc_state on other psr internal functions.
> And we can get cpu_trancoder from intel_psr, therefore we don't need to
> pass intel_crtc_state to this function.
> 
> Cc: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 7 +++----
>  1 file changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5bafd0de6ad9..cc85083dcd28 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -969,11 +969,10 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
>  	intel_dp->psr.active = true;
>  }
>  
> -static void intel_psr_enable_source(struct intel_dp *intel_dp,
> -				    const struct intel_crtc_state *crtc_state)
> +static void intel_psr_enable_source(struct intel_dp *intel_dp)
>  {
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> -	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> +	enum transcoder cpu_transcoder = intel_dp->psr.transcoder;
>  	u32 mask;
>  
>  	/* Only HSW and BDW have PSR AUX registers that need to be setup. SKL+
> @@ -1080,7 +1079,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
>  				     &intel_dp->psr.vsc);
>  	intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp->psr.vsc);
>  	intel_psr_enable_sink(intel_dp);
> -	intel_psr_enable_source(intel_dp, crtc_state);
> +	intel_psr_enable_source(intel_dp);
>  	intel_dp->psr.enabled = true;
>  
>  	intel_psr_activate(intel_dp);
> -- 
> 2.25.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function
  2021-05-18 11:06       ` Ville Syrjälä
@ 2021-05-21 10:58         ` Mun, Gwan-gyeong
  2021-05-21 21:52           ` Souza, Jose
  0 siblings, 1 reply; 57+ messages in thread
From: Mun, Gwan-gyeong @ 2021-05-21 10:58 UTC (permalink / raw)
  To: ville.syrjala, Lisovskiy, Stanislav; +Cc: intel-gfx

On Tue, 2021-05-18 at 14:06 +0300, Ville Syrjälä wrote:
> On Tue, May 18, 2021 at 09:33:09AM +0000, Mun, Gwan-gyeong wrote:
> > Hi Ville, 
> > initially, intel_psr_pause() called intel_psr_disable_locked()
> > instead
> > of intel_psr_exit().
> > In intel_psr_resume(), _intel_psr_enable_locked() was called instead
> > of
> > intel_psr_activate().
> > Can you share what problem the initial code caused when calling
> > intel_psr_pause() / intel_psr_resume()?
> 
> It was doing illegal stuff with crtc->state/etc. That was oopsing.
> The other problem was that IIRC it was going to do DPCD accesses
> while the cdclk code was already holding the aux mutexes. I moved it
> out from under the lock, but I think we might actually want it inside
> the lock since we'll need that to prevent PSR during all AUX transfers
> anyway. Putting it back inside the lock should also make it less racy
> I guess.
> 
> > 
> > In addition, intel_psr_exit() /intel_psr_activate() function  disable
> > /
> > enable only the PSR source.
> > So, if disable/enable for PSR Sink Device is not called together,
> > there
> > will be a problem that the PSR state machine of sink and source is
> > different.
> > What do you think?
> 
> If possible I wouldn't want it touch the sink at all. It should
> basically be no different to eg. enabling the vblank interrupt.
> 

Hi Ville and Stan, 
Thanks, Ville, for explaining.

intel_psr_pause() and intel_psr_resume() are an api added to use when
reactivating (disable and enable) the psr functionality without
intel_crtc_state and drm_connector_state, as described in the commit
log.
And in order to deactivate and activate psr normally, we must
deactivate the psr functionality of the sink as well, and at this time,
sink psr deactivate using dpcd.

And in the part explaining disabling psr in cdclk setting in bspec, the
following procedure is explained for disabling psr.
1. Temporarily disable PSR1, PSR2, and GTC.
2. Wait for disabling status from those functions.
3. Wait for any pending Aux transactions to complete, and do not start
any new Aux transaction.
...

So, in my opinion, when the cdclk setting is called from
intel_atomic_commit_tail() with functions such as
intel_set_cdclk_pre_plane_update() /
intel_set_cdclk_post_plane_update(),
if psr deactivation/activation is necessary, it seems that
intel_set_cdclk_pre_plane_update() /
intel_set_cdclk_post_plane_update() should be called with
intel_psr_enable() / intel_psr_disable() functions together. What do
you think?

Br,
G.G. 
> > 
> > On Mon, 2021-05-17 at 09:58 -0700, Souza, Jose wrote:
> > > On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> > > > From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > 
> > > > This introduces the following function that can enable and
> > > > disable
> > > > psr
> > > > without intel_crtc_state/drm_connector_state when intel_psr is
> > > > already
> > > > enabled with current intel_crtc_state and drm_connector_state
> > > > information.
> > > > 
> > > > - intel_psr_pause(): Pause current PSR. it deactivates current
> > > > psr
> > > > state.
> > > > - intel_psr_resume(): Resume paused PSR without intel_crtc_state
> > > > and
> > > >                       drm_connector_state. It activates paused
> > > > psr
> > > > state.
> > > > 
> > > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > ---
> > > >  .../drm/i915/display/intel_display_types.h    |  1 +
> > > >  drivers/gpu/drm/i915/display/intel_psr.c      | 93
> > > > ++++++++++++++++-
> > > > --
> > > >  drivers/gpu/drm/i915/display/intel_psr.h      |  2 +
> > > >  3 files changed, 82 insertions(+), 14 deletions(-)
> > > > 
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index b8d1f702d808..ee7cbdd7db87 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > @@ -1482,6 +1482,7 @@ struct intel_psr {
> > > >         bool sink_support;
> > > >         bool source_support;
> > > >         bool enabled;
> > > > +       bool paused;
> > > >         enum pipe pipe;
> > > >         enum transcoder transcoder;
> > > >         bool active;
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > index 4a63d10876ce..d4df3f5e7918 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > @@ -1060,34 +1060,23 @@ static bool
> > > > psr_interrupt_error_check(struct
> > > > intel_dp *intel_dp)
> > > >         return true;
> > > >  }
> > > >  
> > > > -static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > > > -                                   const struct intel_crtc_state
> > > > *crtc_state,
> > > > -                                   const struct
> > > > drm_connector_state
> > > > *conn_state)
> > > > +static void _intel_psr_enable_locked(struct intel_dp *intel_dp,
> > > > +                                    const struct
> > > > intel_crtc_state
> > > > *crtc_state)
> > > >  {
> > > >         struct intel_digital_port *dig_port =
> > > > dp_to_dig_port(intel_dp);
> > > >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > >         struct intel_encoder *encoder = &dig_port->base;
> > > > -       u32 val;
> > > >  
> > > >         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> > > >  
> > > > -       intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > > >         intel_dp->psr.busy_frontbuffer_bits = 0;
> > > > -       intel_dp->psr.pipe = to_intel_crtc(crtc_state-
> > > > >uapi.crtc)-
> > > > > pipe;
> > > > -       intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> > > > -       /* DC5/DC6 requires at least 6 idle frames */
> > > > -       val =
> > > > usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > > > 6);
> > > > -       intel_dp->psr.dc3co_exit_delay = val;
> > > > -       intel_dp->psr.dc3co_exitline = crtc_state-
> > > > >dc3co_exitline;
> > > > -       intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > > > > enable_psr2_sel_fetch;
> > > >  
> > > >         if (!psr_interrupt_error_check(intel_dp))
> > > >                 return;
> > > >  
> > > >         drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> > > >                     intel_dp->psr.psr2_enabled ? "2" : "1");
> > > > -       intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state,
> > > > conn_state,
> > > > -                                    &intel_dp->psr.vsc);
> > > > +
> > > >         intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp-
> > > > > psr.vsc);
> > > >         intel_psr_enable_sink(intel_dp);
> > > >         intel_psr_enable_source(intel_dp);
> > > > @@ -1096,6 +1085,28 @@ static void intel_psr_enable_locked(struct
> > > > intel_dp *intel_dp,
> > > >         intel_psr_activate(intel_dp);
> > > >  }
> > > >  
> > > > +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > > > +                                   const struct intel_crtc_state
> > > > *crtc_state,
> > > > +                                   const struct
> > > > drm_connector_state
> > > > *conn_state)
> > > > +{
> > > > +       u32 val;
> > > > +
> > > > +       intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > > > +       intel_dp->psr.pipe = to_intel_crtc(crtc_state-
> > > > >uapi.crtc)-
> > > > > pipe;
> > > > +       intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> > > > +       /* DC5/DC6 requires at least 6 idle frames */
> > > > +       val =
> > > > usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > > > 6);
> > > > +       intel_dp->psr.dc3co_exit_delay = val;
> > > > +       intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > > > > enable_psr2_sel_fetch;
> > > > +       intel_dp->psr.dc3co_exitline = crtc_state-
> > > > >dc3co_exitline;
> > > > +       intel_dp->psr.paused = false;
> > > > +
> > > > +       intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state,
> > > > conn_state,
> > > > +                                    &intel_dp->psr.vsc);
> > > > +
> > > > +       _intel_psr_enable_locked(intel_dp, crtc_state);
> > > > +}
> > > > +
> > > >  /**
> > > >   * intel_psr_enable - Enable PSR
> > > >   * @intel_dp: Intel DP
> > > > @@ -1233,6 +1244,60 @@ void intel_psr_disable(struct intel_dp
> > > > *intel_dp,
> > > >         cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> > > >  }
> > > >  
> > > > +/**
> > > > + * intel_psr_pause - Pause PSR
> > > > + * @intel_dp: Intel DP
> > > > + *
> > > > + * This function need to be called after enabling psr.
> > > > + */
> > > > +void intel_psr_pause(struct intel_dp *intel_dp)
> > > > +{
> > > > +       struct intel_psr *psr = &intel_dp->psr;
> > > > +
> > > > +       if (!CAN_PSR(intel_dp))
> > > > +               return;
> > > > +
> > > > +       mutex_lock(&psr->lock);
> > > > +
> > > > +       if (!psr->active) {
> > > > +               mutex_unlock(&psr->lock);
> > > > +               return;
> > > > +       }
> > > > +
> > > > +       intel_psr_exit(intel_dp);
> > > > +       psr->paused = true;
> > > > +
> > > > +       mutex_unlock(&psr->lock);
> > > > +
> > > > +       cancel_work_sync(&psr->work);
> > > > +       cancel_delayed_work_sync(&psr->dc3co_work);
> > > > +}
> > > > +
> > > > +/**
> > > > + * intel_psr_resume - Resume PSR
> > > > + * @intel_dp: Intel DP
> > > > + *
> > > > + * This function need to be called after pausing psr.
> > > > + */
> > > > +void intel_psr_resume(struct intel_dp *intel_dp)
> > > > +{
> > > > +       struct intel_psr *psr = &intel_dp->psr;
> > > > +
> > > > +       if (!CAN_PSR(intel_dp))
> > > > +               return;
> > > > +
> > > > +       mutex_lock(&psr->lock);
> > > > +
> > > > +       if (!psr->paused)
> > > > +               goto unlock;
> > > > +
> > > > +       psr->paused = false;
> > > > +       intel_psr_activate(intel_dp);
> > > 
> > > This patch is doing a bunch of changes around the intel_psr_enable
> > > but
> > > then it is calling intel_psr_activate().
> > > 
> > > > +
> > > > +unlock:
> > > > +       mutex_unlock(&psr->lock);
> > > > +}
> > > > +
> > > >  static void psr_force_hw_tracking_exit(struct intel_dp
> > > > *intel_dp)
> > > >  {
> > > >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > index e3db85e97f4c..641521b101c8 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > @@ -51,5 +51,7 @@ void intel_psr2_program_plane_sel_fetch(struct
> > > > intel_plane *plane,
> > > >                                         const struct
> > > > intel_crtc_state
> > > > *crtc_state,
> > > >                                         const struct
> > > > intel_plane_state *plane_state,
> > > >                                         int color_plane);
> > > > +void intel_psr_pause(struct intel_dp *intel_dp);
> > > > +void intel_psr_resume(struct intel_dp *intel_dp);
> > > >  
> > > >  #endif /* __INTEL_PSR_H__ */
> > > 
> > 
> 

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function
  2021-05-21 10:58         ` Mun, Gwan-gyeong
@ 2021-05-21 21:52           ` Souza, Jose
  2021-06-01 10:23             ` Mun, Gwan-gyeong
  0 siblings, 1 reply; 57+ messages in thread
From: Souza, Jose @ 2021-05-21 21:52 UTC (permalink / raw)
  To: ville.syrjala, Mun, Gwan-gyeong, Lisovskiy, Stanislav; +Cc: intel-gfx

On Fri, 2021-05-21 at 11:58 +0100, Mun, Gwan-gyeong wrote:
> On Tue, 2021-05-18 at 14:06 +0300, Ville Syrjälä wrote:
> > On Tue, May 18, 2021 at 09:33:09AM +0000, Mun, Gwan-gyeong wrote:
> > > Hi Ville, 
> > > initially, intel_psr_pause() called intel_psr_disable_locked()
> > > instead
> > > of intel_psr_exit().
> > > In intel_psr_resume(), _intel_psr_enable_locked() was called instead
> > > of
> > > intel_psr_activate().
> > > Can you share what problem the initial code caused when calling
> > > intel_psr_pause() / intel_psr_resume()?
> > 
> > It was doing illegal stuff with crtc->state/etc. That was oopsing.
> > The other problem was that IIRC it was going to do DPCD accesses
> > while the cdclk code was already holding the aux mutexes. I moved it
> > out from under the lock, but I think we might actually want it inside
> > the lock since we'll need that to prevent PSR during all AUX transfers
> > anyway. Putting it back inside the lock should also make it less racy
> > I guess.
> > 
> > > 
> > > In addition, intel_psr_exit() /intel_psr_activate() function  disable
> > > /
> > > enable only the PSR source.
> > > So, if disable/enable for PSR Sink Device is not called together,
> > > there
> > > will be a problem that the PSR state machine of sink and source is
> > > different.
> > > What do you think?
> > 
> > If possible I wouldn't want it touch the sink at all. It should
> > basically be no different to eg. enabling the vblank interrupt.
> > 
> 
> Hi Ville and Stan, 
> Thanks, Ville, for explaining.
> 
> intel_psr_pause() and intel_psr_resume() are an api added to use when
> reactivating (disable and enable) the psr functionality without
> intel_crtc_state and drm_connector_state, as described in the commit
> log.
> And in order to deactivate and activate psr normally, we must
> deactivate the psr functionality of the sink as well, and at this time,
> sink psr deactivate using dpcd.
> 
> And in the part explaining disabling psr in cdclk setting in bspec, the
> following procedure is explained for disabling psr.
> 1. Temporarily disable PSR1, PSR2, and GTC.
> 2. Wait for disabling status from those functions.
> 3. Wait for any pending Aux transactions to complete, and do not start
> any new Aux transaction.
> ...

I don't think we need to disable, psr_exit() + wait until PSR is idle is enough, all other stuff can be left as is.

> 
> So, in my opinion, when the cdclk setting is called from
> intel_atomic_commit_tail() with functions such as
> intel_set_cdclk_pre_plane_update() /
> intel_set_cdclk_post_plane_update(),
> if psr deactivation/activation is necessary, it seems that
> intel_set_cdclk_pre_plane_update() /
> intel_set_cdclk_post_plane_update() should be called with
> intel_psr_enable() / intel_psr_disable() functions together. What do
> you think?
> 
> Br,
> G.G. 
> > > 
> > > On Mon, 2021-05-17 at 09:58 -0700, Souza, Jose wrote:
> > > > On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> > > > > From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > > 
> > > > > This introduces the following function that can enable and
> > > > > disable
> > > > > psr
> > > > > without intel_crtc_state/drm_connector_state when intel_psr is
> > > > > already
> > > > > enabled with current intel_crtc_state and drm_connector_state
> > > > > information.
> > > > > 
> > > > > - intel_psr_pause(): Pause current PSR. it deactivates current
> > > > > psr
> > > > > state.
> > > > > - intel_psr_resume(): Resume paused PSR without intel_crtc_state
> > > > > and
> > > > >                       drm_connector_state. It activates paused
> > > > > psr
> > > > > state.
> > > > > 
> > > > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > ---
> > > > >  .../drm/i915/display/intel_display_types.h    |  1 +
> > > > >  drivers/gpu/drm/i915/display/intel_psr.c      | 93
> > > > > ++++++++++++++++-
> > > > > --
> > > > >  drivers/gpu/drm/i915/display/intel_psr.h      |  2 +
> > > > >  3 files changed, 82 insertions(+), 14 deletions(-)
> > > > > 
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > index b8d1f702d808..ee7cbdd7db87 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > @@ -1482,6 +1482,7 @@ struct intel_psr {
> > > > >         bool sink_support;
> > > > >         bool source_support;
> > > > >         bool enabled;
> > > > > +       bool paused;
> > > > >         enum pipe pipe;
> > > > >         enum transcoder transcoder;
> > > > >         bool active;
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > index 4a63d10876ce..d4df3f5e7918 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > @@ -1060,34 +1060,23 @@ static bool
> > > > > psr_interrupt_error_check(struct
> > > > > intel_dp *intel_dp)
> > > > >         return true;
> > > > >  }
> > > > >  
> > > > > -static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > > > > -                                   const struct intel_crtc_state
> > > > > *crtc_state,
> > > > > -                                   const struct
> > > > > drm_connector_state
> > > > > *conn_state)
> > > > > +static void _intel_psr_enable_locked(struct intel_dp *intel_dp,
> > > > > +                                    const struct
> > > > > intel_crtc_state
> > > > > *crtc_state)
> > > > >  {
> > > > >         struct intel_digital_port *dig_port =
> > > > > dp_to_dig_port(intel_dp);
> > > > >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > >         struct intel_encoder *encoder = &dig_port->base;
> > > > > -       u32 val;
> > > > >  
> > > > >         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> > > > >  
> > > > > -       intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > > > >         intel_dp->psr.busy_frontbuffer_bits = 0;
> > > > > -       intel_dp->psr.pipe = to_intel_crtc(crtc_state-
> > > > > > uapi.crtc)-
> > > > > > pipe;
> > > > > -       intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> > > > > -       /* DC5/DC6 requires at least 6 idle frames */
> > > > > -       val =
> > > > > usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > > > > 6);
> > > > > -       intel_dp->psr.dc3co_exit_delay = val;
> > > > > -       intel_dp->psr.dc3co_exitline = crtc_state-
> > > > > > dc3co_exitline;
> > > > > -       intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > > > > > enable_psr2_sel_fetch;
> > > > >  
> > > > >         if (!psr_interrupt_error_check(intel_dp))
> > > > >                 return;
> > > > >  
> > > > >         drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> > > > >                     intel_dp->psr.psr2_enabled ? "2" : "1");
> > > > > -       intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state,
> > > > > conn_state,
> > > > > -                                    &intel_dp->psr.vsc);
> > > > > +
> > > > >         intel_write_dp_vsc_sdp(encoder, crtc_state, &intel_dp-
> > > > > > psr.vsc);
> > > > >         intel_psr_enable_sink(intel_dp);
> > > > >         intel_psr_enable_source(intel_dp);
> > > > > @@ -1096,6 +1085,28 @@ static void intel_psr_enable_locked(struct
> > > > > intel_dp *intel_dp,
> > > > >         intel_psr_activate(intel_dp);
> > > > >  }
> > > > >  
> > > > > +static void intel_psr_enable_locked(struct intel_dp *intel_dp,
> > > > > +                                   const struct intel_crtc_state
> > > > > *crtc_state,
> > > > > +                                   const struct
> > > > > drm_connector_state
> > > > > *conn_state)
> > > > > +{
> > > > > +       u32 val;
> > > > > +
> > > > > +       intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > > > > +       intel_dp->psr.pipe = to_intel_crtc(crtc_state-
> > > > > > uapi.crtc)-
> > > > > > pipe;
> > > > > +       intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
> > > > > +       /* DC5/DC6 requires at least 6 idle frames */
> > > > > +       val =
> > > > > usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > > > > 6);
> > > > > +       intel_dp->psr.dc3co_exit_delay = val;
> > > > > +       intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > > > > > enable_psr2_sel_fetch;
> > > > > +       intel_dp->psr.dc3co_exitline = crtc_state-
> > > > > > dc3co_exitline;
> > > > > +       intel_dp->psr.paused = false;
> > > > > +
> > > > > +       intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state,
> > > > > conn_state,
> > > > > +                                    &intel_dp->psr.vsc);
> > > > > +
> > > > > +       _intel_psr_enable_locked(intel_dp, crtc_state);
> > > > > +}
> > > > > +
> > > > >  /**
> > > > >   * intel_psr_enable - Enable PSR
> > > > >   * @intel_dp: Intel DP
> > > > > @@ -1233,6 +1244,60 @@ void intel_psr_disable(struct intel_dp
> > > > > *intel_dp,
> > > > >         cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> > > > >  }
> > > > >  
> > > > > +/**
> > > > > + * intel_psr_pause - Pause PSR
> > > > > + * @intel_dp: Intel DP
> > > > > + *
> > > > > + * This function need to be called after enabling psr.
> > > > > + */
> > > > > +void intel_psr_pause(struct intel_dp *intel_dp)
> > > > > +{
> > > > > +       struct intel_psr *psr = &intel_dp->psr;
> > > > > +
> > > > > +       if (!CAN_PSR(intel_dp))
> > > > > +               return;
> > > > > +
> > > > > +       mutex_lock(&psr->lock);
> > > > > +
> > > > > +       if (!psr->active) {
> > > > > +               mutex_unlock(&psr->lock);
> > > > > +               return;
> > > > > +       }
> > > > > +
> > > > > +       intel_psr_exit(intel_dp);
> > > > > +       psr->paused = true;
> > > > > +
> > > > > +       mutex_unlock(&psr->lock);
> > > > > +
> > > > > +       cancel_work_sync(&psr->work);
> > > > > +       cancel_delayed_work_sync(&psr->dc3co_work);
> > > > > +}
> > > > > +
> > > > > +/**
> > > > > + * intel_psr_resume - Resume PSR
> > > > > + * @intel_dp: Intel DP
> > > > > + *
> > > > > + * This function need to be called after pausing psr.
> > > > > + */
> > > > > +void intel_psr_resume(struct intel_dp *intel_dp)
> > > > > +{
> > > > > +       struct intel_psr *psr = &intel_dp->psr;
> > > > > +
> > > > > +       if (!CAN_PSR(intel_dp))
> > > > > +               return;
> > > > > +
> > > > > +       mutex_lock(&psr->lock);
> > > > > +
> > > > > +       if (!psr->paused)
> > > > > +               goto unlock;
> > > > > +
> > > > > +       psr->paused = false;
> > > > > +       intel_psr_activate(intel_dp);
> > > > 
> > > > This patch is doing a bunch of changes around the intel_psr_enable
> > > > but
> > > > then it is calling intel_psr_activate().
> > > > 
> > > > > +
> > > > > +unlock:
> > > > > +       mutex_unlock(&psr->lock);
> > > > > +}
> > > > > +
> > > > >  static void psr_force_hw_tracking_exit(struct intel_dp
> > > > > *intel_dp)
> > > > >  {
> > > > >         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > index e3db85e97f4c..641521b101c8 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > @@ -51,5 +51,7 @@ void intel_psr2_program_plane_sel_fetch(struct
> > > > > intel_plane *plane,
> > > > >                                         const struct
> > > > > intel_crtc_state
> > > > > *crtc_state,
> > > > >                                         const struct
> > > > > intel_plane_state *plane_state,
> > > > >                                         int color_plane);
> > > > > +void intel_psr_pause(struct intel_dp *intel_dp);
> > > > > +void intel_psr_resume(struct intel_dp *intel_dp);
> > > > >  
> > > > >  #endif /* __INTEL_PSR_H__ */
> > > > 
> > > 
> > 
> 

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 05/23] drm/i915/xelpd: Add VRR guardband for VRR CTL
  2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 05/23] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
@ 2021-05-24 13:40   ` Aditya Swarup
  0 siblings, 0 replies; 57+ messages in thread
From: Aditya Swarup @ 2021-05-24 13:40 UTC (permalink / raw)
  To: Matt Roper, intel-gfx

On 5/14/21 8:10 PM, Matt Roper wrote:
> From: Manasi Navare <manasi.d.navare@intel.com>
> 
> On XE_LPD, VRR CTL register adds a new VRR Guardband bitfield
> replacing the pipeline full and deprecating the pipeline override
> bit.
> 
> This patch adds this corresponding bitfield in the register defs,
> crtc state vrr structure and populates this in vrr compute
> config and vrr enable functions. It also adds the corresponding
> HW state readout for this field.

LGTM. Can add Bspec: 50508 for reference.

Reviewed-by: Aditya Swarup <aditya.swarup@intel.com>
> 
> Cc: Aditya Swarup <aditya.swarup@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |  8 ++-
>  .../drm/i915/display/intel_display_types.h    |  2 +-
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 58 +++++++++++++------
>  drivers/gpu/drm/i915/i915_drv.h               |  3 +
>  drivers/gpu/drm/i915/i915_reg.h               |  2 +
>  5 files changed, 53 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 422b59ebf6dc..ce44f18340ee 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7631,10 +7631,11 @@ static void intel_dump_pipe_config(const struct intel_crtc_state *pipe_config,
>  	    intel_hdmi_infoframe_enable(DP_SDP_VSC))
>  		intel_dump_dp_vsc_sdp(dev_priv, &pipe_config->infoframes.vsc);
>  
> -	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
> +	drm_dbg_kms(&dev_priv->drm, "vrr: %s, vmin: %d, vmax: %d, pipeline full: %d, guardband: %d flipline: %d, vmin vblank: %d, vmax vblank: %d\n",
>  		    yesno(pipe_config->vrr.enable),
>  		    pipe_config->vrr.vmin, pipe_config->vrr.vmax,
> -		    pipe_config->vrr.pipeline_full, pipe_config->vrr.flipline,
> +		    pipe_config->vrr.pipeline_full, pipe_config->vrr.guardband,
> +		    pipe_config->vrr.flipline,
>  		    intel_vrr_vmin_vblank_start(pipe_config),
>  		    intel_vrr_vmax_vblank_start(pipe_config));
>  
> @@ -8640,6 +8641,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_I(vrr.vmax);
>  	PIPE_CONF_CHECK_I(vrr.flipline);
>  	PIPE_CONF_CHECK_I(vrr.pipeline_full);
> +	PIPE_CONF_CHECK_I(vrr.guardband);
>  
>  	PIPE_CONF_CHECK_BOOL(has_psr);
>  	PIPE_CONF_CHECK_BOOL(has_psr2);
> @@ -12200,6 +12202,8 @@ int intel_modeset_init_noirq(struct drm_i915_private *i915)
>  
>  	i915->framestart_delay = 1; /* 1-4 */
>  
> +	i915->window2_delay = 0; /* No DSB so no window2 delay */
> +
>  	intel_mode_config_init(i915);
>  
>  	ret = intel_cdclk_init(i915);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 9c0adfc60c6f..9e9f768e2d7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1202,7 +1202,7 @@ struct intel_crtc_state {
>  	struct {
>  		bool enable;
>  		u8 pipeline_full;
> -		u16 flipline, vmin, vmax;
> +		u16 flipline, vmin, vmax, guardband;
>  	} vrr;
>  
>  	/* Stream Splitter for eDP MSO */
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 046210ae1de0..c335b1dbafcf 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -68,7 +68,10 @@ static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_stat
>  	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  
>  	/* The hw imposes the extra scanline before frame start */
> -	return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
> +	if (DISPLAY_VER(i915) >= 13)
> +		return crtc_state->vrr.guardband + i915->framestart_delay + 1;
> +	else
> +		return crtc_state->vrr.pipeline_full + i915->framestart_delay + 1;
>  }
>  
>  int intel_vrr_vmin_vblank_start(const struct intel_crtc_state *crtc_state)
> @@ -86,6 +89,8 @@ void
>  intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  			 struct drm_connector_state *conn_state)
>  {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	struct intel_connector *connector =
>  		to_intel_connector(conn_state->connector);
>  	struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> @@ -124,17 +129,26 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  	crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1;
>  
>  	/*
> -	 * FIXME: s/4/framestart_delay+1/ to get consistent
> -	 * earliest/latest points for register latching regardless
> -	 * of the framestart_delay used?
> -	 *
> -	 * FIXME: this really needs the extra scanline to provide consistent
> -	 * behaviour for all framestart_delay values. Otherwise with
> -	 * framestart_delay==3 we will end up extending the min vblank by
> -	 * one extra line.
> +	 * For XE_LPD+, we use guardband and pipeline override
> +	 * is deprecated.
>  	 */
> -	crtc_state->vrr.pipeline_full =
> -		min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
> +	if (DISPLAY_VER(i915) >= 13)
> +		crtc_state->vrr.guardband =
> +			crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay -
> +			i915->window2_delay;
> +	else
> +		/*
> +		 * FIXME: s/4/framestart_delay+1/ to get consistent
> +		 * earliest/latest points for register latching regardless
> +		 * of the framestart_delay used?
> +		 *
> +		 * FIXME: this really needs the extra scanline to provide consistent
> +		 * behaviour for all framestart_delay values. Otherwise with
> +		 * framestart_delay==3 we will end up extending the min vblank by
> +		 * one extra line.
> +		 */
> +		crtc_state->vrr.pipeline_full =
> +			min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vdisplay - 4 - 1);
>  
>  	crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>  }
> @@ -149,10 +163,15 @@ void intel_vrr_enable(struct intel_encoder *encoder,
>  	if (!crtc_state->vrr.enable)
>  		return;
>  
> -	trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
> -		VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
> -		VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
> -		VRR_CTL_PIPELINE_FULL_OVERRIDE;
> +	if (DISPLAY_VER(dev_priv) >= 13)
> +		trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
> +			VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
> +			XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband);
> +	else
> +		trans_vrr_ctl = VRR_CTL_VRR_ENABLE |
> +			VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN |
> +			VRR_CTL_PIPELINE_FULL(crtc_state->vrr.pipeline_full) |
> +			VRR_CTL_PIPELINE_FULL_OVERRIDE;
>  
>  	intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1);
>  	intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1);
> @@ -199,8 +218,13 @@ void intel_vrr_get_config(struct intel_crtc *crtc,
>  	if (!crtc_state->vrr.enable)
>  		return;
>  
> -	if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
> -		crtc_state->vrr.pipeline_full = REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
> +	if (DISPLAY_VER(dev_priv) >= 13)
> +		crtc_state->vrr.guardband =
> +			REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
> +	else
> +		if (trans_vrr_ctl & VRR_CTL_PIPELINE_FULL_OVERRIDE)
> +			crtc_state->vrr.pipeline_full =
> +				REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl);
>  	if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN)
>  		crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1;
>  	crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1;
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 39b5e019c1a5..6eb6c6acd81e 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1139,6 +1139,9 @@ struct drm_i915_private {
>  
>  	u8 framestart_delay;
>  
> +	/* Window2 specifies time required to program DSB (Window2) in number of scan lines */
> +	u8 window2_delay;
> +
>  	u8 pch_ssc_use;
>  
>  	/* For i915gm/i945gm vblank irq workaround */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 506a5aa0646b..dbb75cd087d3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4376,6 +4376,8 @@ enum {
>  #define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
>  #define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
>  #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
> +#define	  XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
> +#define	  XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
>  
>  #define _TRANS_VRR_VMAX_A		0x60424
>  #define _TRANS_VRR_VMAX_B		0x61424
> 

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^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function
  2021-05-21 21:52           ` Souza, Jose
@ 2021-06-01 10:23             ` Mun, Gwan-gyeong
  0 siblings, 0 replies; 57+ messages in thread
From: Mun, Gwan-gyeong @ 2021-06-01 10:23 UTC (permalink / raw)
  To: ville.syrjala, Lisovskiy, Stanislav, Souza, Jose; +Cc: intel-gfx

The v2 patch which addressed Jose's comments was floated to
https://patchwork.freedesktop.org/series/90819/
On Fri, 2021-05-21 at 14:52 -0700, Souza, Jose wrote:
> On Fri, 2021-05-21 at 11:58 +0100, Mun, Gwan-gyeong wrote:
> > On Tue, 2021-05-18 at 14:06 +0300, Ville Syrjälä wrote:
> > > On Tue, May 18, 2021 at 09:33:09AM +0000, Mun, Gwan-gyeong wrote:
> > > > Hi Ville, 
> > > > initially, intel_psr_pause() called intel_psr_disable_locked()
> > > > instead
> > > > of intel_psr_exit().
> > > > In intel_psr_resume(), _intel_psr_enable_locked() was called
> > > > instead
> > > > of
> > > > intel_psr_activate().
> > > > Can you share what problem the initial code caused when calling
> > > > intel_psr_pause() / intel_psr_resume()?
> > > 
> > > It was doing illegal stuff with crtc->state/etc. That was oopsing.
> > > The other problem was that IIRC it was going to do DPCD accesses
> > > while the cdclk code was already holding the aux mutexes. I moved
> > > it
> > > out from under the lock, but I think we might actually want it
> > > inside
> > > the lock since we'll need that to prevent PSR during all AUX
> > > transfers
> > > anyway. Putting it back inside the lock should also make it less
> > > racy
> > > I guess.
> > > 
> > > > 
> > > > In addition, intel_psr_exit() /intel_psr_activate() function 
> > > > disable
> > > > /
> > > > enable only the PSR source.
> > > > So, if disable/enable for PSR Sink Device is not called together,
> > > > there
> > > > will be a problem that the PSR state machine of sink and source
> > > > is
> > > > different.
> > > > What do you think?
> > > 
> > > If possible I wouldn't want it touch the sink at all. It should
> > > basically be no different to eg. enabling the vblank interrupt.
> > > 
> > 
> > Hi Ville and Stan, 
> > Thanks, Ville, for explaining.
> > 
> > intel_psr_pause() and intel_psr_resume() are an api added to use when
> > reactivating (disable and enable) the psr functionality without
> > intel_crtc_state and drm_connector_state, as described in the commit
> > log.
> > And in order to deactivate and activate psr normally, we must
> > deactivate the psr functionality of the sink as well, and at this
> > time,
> > sink psr deactivate using dpcd.
> > 
> > And in the part explaining disabling psr in cdclk setting in bspec,
> > the
> > following procedure is explained for disabling psr.
> > 1. Temporarily disable PSR1, PSR2, and GTC.
> > 2. Wait for disabling status from those functions.
> > 3. Wait for any pending Aux transactions to complete, and do not
> > start
> > any new Aux transaction.
> > ...
> 
> I don't think we need to disable, psr_exit() + wait until PSR is idle
> is enough, all other stuff can be left as is.
> 
> > 
> > So, in my opinion, when the cdclk setting is called from
> > intel_atomic_commit_tail() with functions such as
> > intel_set_cdclk_pre_plane_update() /
> > intel_set_cdclk_post_plane_update(),
> > if psr deactivation/activation is necessary, it seems that
> > intel_set_cdclk_pre_plane_update() /
> > intel_set_cdclk_post_plane_update() should be called with
> > intel_psr_enable() / intel_psr_disable() functions together. What do
> > you think?
> > 
> > Br,
> > G.G. 
> > > > 
> > > > On Mon, 2021-05-17 at 09:58 -0700, Souza, Jose wrote:
> > > > > On Fri, 2021-05-14 at 20:10 -0700, Matt Roper wrote:
> > > > > > From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > > > 
> > > > > > This introduces the following function that can enable and
> > > > > > disable
> > > > > > psr
> > > > > > without intel_crtc_state/drm_connector_state when intel_psr
> > > > > > is
> > > > > > already
> > > > > > enabled with current intel_crtc_state and drm_connector_state
> > > > > > information.
> > > > > > 
> > > > > > - intel_psr_pause(): Pause current PSR. it deactivates
> > > > > > current
> > > > > > psr
> > > > > > state.
> > > > > > - intel_psr_resume(): Resume paused PSR without
> > > > > > intel_crtc_state
> > > > > > and
> > > > > >                       drm_connector_state. It activates
> > > > > > paused
> > > > > > psr
> > > > > > state.
> > > > > > 
> > > > > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > > > > Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > > > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > > > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > > > > > Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> > > > > > ---
> > > > > >  .../drm/i915/display/intel_display_types.h    |  1 +
> > > > > >  drivers/gpu/drm/i915/display/intel_psr.c      | 93
> > > > > > ++++++++++++++++-
> > > > > > --
> > > > > >  drivers/gpu/drm/i915/display/intel_psr.h      |  2 +
> > > > > >  3 files changed, 82 insertions(+), 14 deletions(-)
> > > > > > 
> > > > > > diff --git
> > > > > > a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > index b8d1f702d808..ee7cbdd7db87 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > > @@ -1482,6 +1482,7 @@ struct intel_psr {
> > > > > >         bool sink_support;
> > > > > >         bool source_support;
> > > > > >         bool enabled;
> > > > > > +       bool paused;
> > > > > >         enum pipe pipe;
> > > > > >         enum transcoder transcoder;
> > > > > >         bool active;
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > index 4a63d10876ce..d4df3f5e7918 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > > > > @@ -1060,34 +1060,23 @@ static bool
> > > > > > psr_interrupt_error_check(struct
> > > > > > intel_dp *intel_dp)
> > > > > >         return true;
> > > > > >  }
> > > > > >  
> > > > > > -static void intel_psr_enable_locked(struct intel_dp
> > > > > > *intel_dp,
> > > > > > -                                   const struct
> > > > > > intel_crtc_state
> > > > > > *crtc_state,
> > > > > > -                                   const struct
> > > > > > drm_connector_state
> > > > > > *conn_state)
> > > > > > +static void _intel_psr_enable_locked(struct intel_dp
> > > > > > *intel_dp,
> > > > > > +                                    const struct
> > > > > > intel_crtc_state
> > > > > > *crtc_state)
> > > > > >  {
> > > > > >         struct intel_digital_port *dig_port =
> > > > > > dp_to_dig_port(intel_dp);
> > > > > >         struct drm_i915_private *dev_priv =
> > > > > > dp_to_i915(intel_dp);
> > > > > >         struct intel_encoder *encoder = &dig_port->base;
> > > > > > -       u32 val;
> > > > > >  
> > > > > >         drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled);
> > > > > >  
> > > > > > -       intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > > > > >         intel_dp->psr.busy_frontbuffer_bits = 0;
> > > > > > -       intel_dp->psr.pipe = to_intel_crtc(crtc_state-
> > > > > > > uapi.crtc)-
> > > > > > > pipe;
> > > > > > -       intel_dp->psr.transcoder = crtc_state-
> > > > > > >cpu_transcoder;
> > > > > > -       /* DC5/DC6 requires at least 6 idle frames */
> > > > > > -       val =
> > > > > > usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > > > > > 6);
> > > > > > -       intel_dp->psr.dc3co_exit_delay = val;
> > > > > > -       intel_dp->psr.dc3co_exitline = crtc_state-
> > > > > > > dc3co_exitline;
> > > > > > -       intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > > > > > > enable_psr2_sel_fetch;
> > > > > >  
> > > > > >         if (!psr_interrupt_error_check(intel_dp))
> > > > > >                 return;
> > > > > >  
> > > > > >         drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n",
> > > > > >                     intel_dp->psr.psr2_enabled ? "2" : "1");
> > > > > > -       intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state,
> > > > > > conn_state,
> > > > > > -                                    &intel_dp->psr.vsc);
> > > > > > +
> > > > > >         intel_write_dp_vsc_sdp(encoder, crtc_state,
> > > > > > &intel_dp-
> > > > > > > psr.vsc);
> > > > > >         intel_psr_enable_sink(intel_dp);
> > > > > >         intel_psr_enable_source(intel_dp);
> > > > > > @@ -1096,6 +1085,28 @@ static void
> > > > > > intel_psr_enable_locked(struct
> > > > > > intel_dp *intel_dp,
> > > > > >         intel_psr_activate(intel_dp);
> > > > > >  }
> > > > > >  
> > > > > > +static void intel_psr_enable_locked(struct intel_dp
> > > > > > *intel_dp,
> > > > > > +                                   const struct
> > > > > > intel_crtc_state
> > > > > > *crtc_state,
> > > > > > +                                   const struct
> > > > > > drm_connector_state
> > > > > > *conn_state)
> > > > > > +{
> > > > > > +       u32 val;
> > > > > > +
> > > > > > +       intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
> > > > > > +       intel_dp->psr.pipe = to_intel_crtc(crtc_state-
> > > > > > > uapi.crtc)-
> > > > > > > pipe;
> > > > > > +       intel_dp->psr.transcoder = crtc_state-
> > > > > > >cpu_transcoder;
> > > > > > +       /* DC5/DC6 requires at least 6 idle frames */
> > > > > > +       val =
> > > > > > usecs_to_jiffies(intel_get_frame_time_us(crtc_state) *
> > > > > > 6);
> > > > > > +       intel_dp->psr.dc3co_exit_delay = val;
> > > > > > +       intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> > > > > > > enable_psr2_sel_fetch;
> > > > > > +       intel_dp->psr.dc3co_exitline = crtc_state-
> > > > > > > dc3co_exitline;
> > > > > > +       intel_dp->psr.paused = false;
> > > > > > +
> > > > > > +       intel_dp_compute_psr_vsc_sdp(intel_dp, crtc_state,
> > > > > > conn_state,
> > > > > > +                                    &intel_dp->psr.vsc);
> > > > > > +
> > > > > > +       _intel_psr_enable_locked(intel_dp, crtc_state);
> > > > > > +}
> > > > > > +
> > > > > >  /**
> > > > > >   * intel_psr_enable - Enable PSR
> > > > > >   * @intel_dp: Intel DP
> > > > > > @@ -1233,6 +1244,60 @@ void intel_psr_disable(struct intel_dp
> > > > > > *intel_dp,
> > > > > >         cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
> > > > > >  }
> > > > > >  
> > > > > > +/**
> > > > > > + * intel_psr_pause - Pause PSR
> > > > > > + * @intel_dp: Intel DP
> > > > > > + *
> > > > > > + * This function need to be called after enabling psr.
> > > > > > + */
> > > > > > +void intel_psr_pause(struct intel_dp *intel_dp)
> > > > > > +{
> > > > > > +       struct intel_psr *psr = &intel_dp->psr;
> > > > > > +
> > > > > > +       if (!CAN_PSR(intel_dp))
> > > > > > +               return;
> > > > > > +
> > > > > > +       mutex_lock(&psr->lock);
> > > > > > +
> > > > > > +       if (!psr->active) {
> > > > > > +               mutex_unlock(&psr->lock);
> > > > > > +               return;
> > > > > > +       }
> > > > > > +
> > > > > > +       intel_psr_exit(intel_dp);
> > > > > > +       psr->paused = true;
> > > > > > +
> > > > > > +       mutex_unlock(&psr->lock);
> > > > > > +
> > > > > > +       cancel_work_sync(&psr->work);
> > > > > > +       cancel_delayed_work_sync(&psr->dc3co_work);
> > > > > > +}
> > > > > > +
> > > > > > +/**
> > > > > > + * intel_psr_resume - Resume PSR
> > > > > > + * @intel_dp: Intel DP
> > > > > > + *
> > > > > > + * This function need to be called after pausing psr.
> > > > > > + */
> > > > > > +void intel_psr_resume(struct intel_dp *intel_dp)
> > > > > > +{
> > > > > > +       struct intel_psr *psr = &intel_dp->psr;
> > > > > > +
> > > > > > +       if (!CAN_PSR(intel_dp))
> > > > > > +               return;
> > > > > > +
> > > > > > +       mutex_lock(&psr->lock);
> > > > > > +
> > > > > > +       if (!psr->paused)
> > > > > > +               goto unlock;
> > > > > > +
> > > > > > +       psr->paused = false;
> > > > > > +       intel_psr_activate(intel_dp);
> > > > > 
> > > > > This patch is doing a bunch of changes around the
> > > > > intel_psr_enable
> > > > > but
> > > > > then it is calling intel_psr_activate().
> > > > > 
> > > > > > +
> > > > > > +unlock:
> > > > > > +       mutex_unlock(&psr->lock);
> > > > > > +}
> > > > > > +
> > > > > >  static void psr_force_hw_tracking_exit(struct intel_dp
> > > > > > *intel_dp)
> > > > > >  {
> > > > > >         struct drm_i915_private *dev_priv =
> > > > > > dp_to_i915(intel_dp);
> > > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > > b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > > index e3db85e97f4c..641521b101c8 100644
> > > > > > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > > > > > @@ -51,5 +51,7 @@ void
> > > > > > intel_psr2_program_plane_sel_fetch(struct
> > > > > > intel_plane *plane,
> > > > > >                                         const struct
> > > > > > intel_crtc_state
> > > > > > *crtc_state,
> > > > > >                                         const struct
> > > > > > intel_plane_state *plane_state,
> > > > > >                                         int color_plane);
> > > > > > +void intel_psr_pause(struct intel_dp *intel_dp);
> > > > > > +void intel_psr_resume(struct intel_dp *intel_dp);
> > > > > >  
> > > > > >  #endif /* __INTEL_PSR_H__ */
> > > > > 
> > > > 
> > > 
> > 
> 

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 57+ messages in thread

end of thread, other threads:[~2021-06-01 10:23 UTC | newest]

Thread overview: 57+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-15  3:10 [Intel-gfx] [PATCH v4 00/23] Alder Lake-P Support Matt Roper
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 01/23] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-05-17  6:52   ` Lisovskiy, Stanislav
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 02/23] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-05-17 15:18   ` Jani Nikula
2021-05-18  6:33     ` Kulkarni, Vandita
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 03/23] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-05-18 18:06   ` Navare, Manasi
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 04/23] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 05/23] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-05-24 13:40   ` Aditya Swarup
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 06/23] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
2021-05-17  6:49   ` Lisovskiy, Stanislav
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 07/23] drm/i915/adl_p: Setup ports/phys Matt Roper
2021-05-17 18:01   ` Imre Deak
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 08/23] drm/i915/adl_p: Handle TC cold Matt Roper
2021-05-17 14:53   ` Imre Deak
2021-05-17 23:15     ` Souza, Jose
2021-05-17 23:22       ` Souza, Jose
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 09/23] drm/i915/adl_p: Implement TC sequences Matt Roper
2021-05-17 15:12   ` Imre Deak
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 10/23] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
2021-05-18 11:58   ` Lisovskiy, Stanislav
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 11/23] drm/i915/adl_p: Add ddb allocation support Matt Roper
2021-05-18 12:22   ` Lisovskiy, Stanislav
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 12/23] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
2021-05-17  6:38   ` Lisovskiy, Stanislav
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 13/23] drm/i915/adl_p: MBUS programming Matt Roper
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 14/23] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
2021-05-17  7:36   ` Kulkarni, Vandita
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 15/23] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct Matt Roper
2021-05-17  6:39   ` Gupta, Anshuman
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 16/23] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source() Matt Roper
2021-05-19  6:49   ` Anshuman Gupta
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 17/23] drm/i915/display: Add PSR interrupt error check function Matt Roper
2021-05-17 17:03   ` Souza, Jose
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 18/23] drm/i915/display: Introduce new intel_psr_pause/resume function Matt Roper
2021-05-17 16:58   ` Souza, Jose
2021-05-18  9:33     ` Mun, Gwan-gyeong
2021-05-18 11:06       ` Ville Syrjälä
2021-05-21 10:58         ` Mun, Gwan-gyeong
2021-05-21 21:52           ` Souza, Jose
2021-06-01 10:23             ` Mun, Gwan-gyeong
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 19/23] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
2021-05-17 23:02   ` Clint Taylor
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 20/23] drm/i915/adl_p: Add PLL Support Matt Roper
2021-05-17 21:55   ` Clint Taylor
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 21/23] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Matt Roper
2021-05-17 17:01   ` Souza, Jose
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 22/23] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
2021-05-17 21:46   ` Clint Taylor
2021-05-15  3:10 ` [Intel-gfx] [PATCH v4 23/23] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
2021-05-17 17:02   ` Souza, Jose
2021-05-15  4:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Alder Lake-P Support (rev3) Patchwork
2021-05-15  4:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-15  5:22 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-05-17 23:41 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Alder Lake-P Support (rev4) Patchwork

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