From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paul Gortmaker Date: Sat, 15 May 2021 15:15:32 -0400 Subject: [PATCH 21/27] ppc: Remove sbc8641d board In-Reply-To: <20210515013432.12867-21-trini@konsulko.com> References: <20210515013432.12867-1-trini@konsulko.com> <20210515013432.12867-21-trini@konsulko.com> Message-ID: <20210515191532.GM258772@windriver.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de [[PATCH 21/27] ppc: Remove sbc8641d board] On 14/05/2021 (Fri 21:34) Tom Rini wrote: > This board has not been converted to CONFIG_DM_PCI by the deadline and is > also missing conversion to CONFIG_DM. Remove it. This is also the last > of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well. > > Cc: Paul Gortmaker Ack'd -- I'd sent the kernel removal several months ago, but that hasn't been merged yet... https://patchwork.ozlabs.org/project/linuxppc-dev/patch/20210111082823.99562-3-paul.gortmaker at windriver.com/ Thanks, Paul. -- > Cc: Priyanka Jain > Signed-off-by: Tom Rini > --- > .azure-pipelines.yml | 2 +- > MAINTAINERS | 6 - > README | 3 +- > arch/powerpc/Kconfig | 7 - > arch/powerpc/cpu/mpc86xx/Kconfig | 52 - > arch/powerpc/cpu/mpc86xx/Makefile | 24 - > arch/powerpc/cpu/mpc86xx/cache.S | 332 ------ > arch/powerpc/cpu/mpc86xx/config.mk | 6 - > arch/powerpc/cpu/mpc86xx/cpu.c | 207 ---- > arch/powerpc/cpu/mpc86xx/cpu_init.c | 104 -- > arch/powerpc/cpu/mpc86xx/fdt.c | 52 - > arch/powerpc/cpu/mpc86xx/interrupts.c | 116 -- > arch/powerpc/cpu/mpc86xx/mp.c | 130 --- > arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c | 87 -- > arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c | 96 -- > arch/powerpc/cpu/mpc86xx/release.S | 149 --- > arch/powerpc/cpu/mpc86xx/speed.c | 134 --- > arch/powerpc/cpu/mpc86xx/start.S | 982 ----------------- > arch/powerpc/cpu/mpc86xx/traps.c | 199 ---- > arch/powerpc/cpu/mpc86xx/u-boot.lds | 77 -- > arch/powerpc/include/asm/config.h | 4 - > arch/powerpc/include/asm/config_mpc86xx.h | 9 - > arch/powerpc/include/asm/fsl_law.h | 7 - > arch/powerpc/include/asm/fsl_pci.h | 2 +- > arch/powerpc/include/asm/immap_86xx.h | 1221 --------------------- > arch/powerpc/include/asm/ppc.h | 4 - > board/sbc8641d/Kconfig | 9 - > board/sbc8641d/MAINTAINERS | 6 - > board/sbc8641d/Makefile | 8 - > board/sbc8641d/README | 49 - > board/sbc8641d/ddr.c | 53 - > board/sbc8641d/law.c | 39 - > board/sbc8641d/sbc8641d.c | 268 ----- > configs/sbc8641d_defconfig | 39 - > doc/git-mailrc | 1 - > drivers/ddr/fsl/Kconfig | 12 +- > drivers/ddr/fsl/Makefile | 1 - > drivers/ddr/fsl/mpc86xx_ddr.c | 84 -- > env/Kconfig | 2 +- > include/configs/sbc8641d.h | 509 --------- > include/post.h | 5 - > 41 files changed, 6 insertions(+), 5091 deletions(-) > delete mode 100644 arch/powerpc/cpu/mpc86xx/Kconfig > delete mode 100644 arch/powerpc/cpu/mpc86xx/Makefile > delete mode 100644 arch/powerpc/cpu/mpc86xx/cache.S > delete mode 100644 arch/powerpc/cpu/mpc86xx/config.mk > delete mode 100644 arch/powerpc/cpu/mpc86xx/cpu.c > delete mode 100644 arch/powerpc/cpu/mpc86xx/cpu_init.c > delete mode 100644 arch/powerpc/cpu/mpc86xx/fdt.c > delete mode 100644 arch/powerpc/cpu/mpc86xx/interrupts.c > delete mode 100644 arch/powerpc/cpu/mpc86xx/mp.c > delete mode 100644 arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c > delete mode 100644 arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c > delete mode 100644 arch/powerpc/cpu/mpc86xx/release.S > delete mode 100644 arch/powerpc/cpu/mpc86xx/speed.c > delete mode 100644 arch/powerpc/cpu/mpc86xx/start.S > delete mode 100644 arch/powerpc/cpu/mpc86xx/traps.c > delete mode 100644 arch/powerpc/cpu/mpc86xx/u-boot.lds > delete mode 100644 arch/powerpc/include/asm/config_mpc86xx.h > delete mode 100644 arch/powerpc/include/asm/immap_86xx.h > delete mode 100644 board/sbc8641d/Kconfig > delete mode 100644 board/sbc8641d/MAINTAINERS > delete mode 100644 board/sbc8641d/Makefile > delete mode 100644 board/sbc8641d/README > delete mode 100644 board/sbc8641d/ddr.c > delete mode 100644 board/sbc8641d/law.c > delete mode 100644 board/sbc8641d/sbc8641d.c > delete mode 100644 configs/sbc8641d_defconfig > delete mode 100644 drivers/ddr/fsl/mpc86xx_ddr.c > delete mode 100644 include/configs/sbc8641d.h > > diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml > index 59e99b8894c5..8a567832ddac 100644 > --- a/.azure-pipelines.yml > +++ b/.azure-pipelines.yml > @@ -415,7 +415,7 @@ jobs: > t208xrdb_corenet_ds: > BUILDMAN: "t208xrdb corenet_ds" > fsl_ppc: > - BUILDMAN: "t4qds b4860qds mpc83xx&freescale mpc86xx&freescale" > + BUILDMAN: "t4qds b4860qds mpc83xx&freescale" > t102x: > BUILDMAN: "t102*" > p1_p2_rdb_pc: > diff --git a/MAINTAINERS b/MAINTAINERS > index 20092cb36740..7e36eb56a3af 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -973,12 +973,6 @@ S: Maintained > T: git https://source.denx.de/u-boot/custodians/u-boot-mpc85xx.git > F: arch/powerpc/cpu/mpc85xx/ > > -POWERPC MPC86XX > -M: Priyanka Jain > -S: Maintained > -T: git https://source.denx.de/u-boot/custodians/u-boot-mpc86xx.git > -F: arch/powerpc/cpu/mpc86xx/ > - > RISC-V > M: Rick Chen > S: Maintained > diff --git a/README b/README > index ad13092bbb7a..63568dc43c74 100644 > --- a/README > +++ b/README > @@ -423,8 +423,7 @@ The following options need to be configured: > > CONFIG_SYS_FSL_DDR > Freescale DDR driver in use. This type of DDR controller is > - found in mpc83xx, mpc85xx, mpc86xx as well as some ARM core > - SoCs. > + found in mpc83xx, mpc85xx as well as some ARM core SoCs. > > CONFIG_SYS_FSL_DDR_ADDR > Freescale DDR memory-mapped register base. > diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig > index 133447648cc6..737bdd8edb41 100644 > --- a/arch/powerpc/Kconfig > +++ b/arch/powerpc/Kconfig > @@ -25,12 +25,6 @@ config MPC85xx > imply CMD_IRQ > imply USB_EHCI_HCD if USB > > -config MPC86xx > - bool "MPC86xx" > - select SYS_FSL_DDR > - select SYS_FSL_DDR_BE > - imply CMD_REGINFO > - > config MPC8xx > bool "MPC8xx" > select BOARD_EARLY_INIT_F > @@ -47,7 +41,6 @@ config HIGH_BATS > > source "arch/powerpc/cpu/mpc83xx/Kconfig" > source "arch/powerpc/cpu/mpc85xx/Kconfig" > -source "arch/powerpc/cpu/mpc86xx/Kconfig" > source "arch/powerpc/cpu/mpc8xx/Kconfig" > source "arch/powerpc/lib/Kconfig" > > diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig > deleted file mode 100644 > index 1ee87038bed4..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/Kconfig > +++ /dev/null > @@ -1,52 +0,0 @@ > -menu "mpc86xx CPU" > - depends on MPC86xx > - > -config SYS_CPU > - default "mpc86xx" > - > -choice > - prompt "Target select" > - optional > - > -config TARGET_SBC8641D > - bool "Support sbc8641d" > - select ARCH_MPC8641 > - select BOARD_EARLY_INIT_F > - > -endchoice > - > -config ARCH_MPC8610 > - bool > - select FSL_LAW > - select SYS_FSL_HAS_DDR1 > - select SYS_FSL_HAS_DDR2 > - > -config ARCH_MPC8641 > - bool > - select FSL_LAW > - select SYS_FSL_HAS_DDR1 > - select SYS_FSL_HAS_DDR2 > - > -config FSL_LAW > - bool > - help > - Use Freescale common code for Local Access Window > - > -config SYS_CCSRBAR_DEFAULT > - hex "Default CCSRBAR address" > - default 0xff700000 if ARCH_MPC8610 || ARCH_MPC8641 > - help > - Default value of CCSRBAR comes from power-on-reset. It > - is fixed on each SoC. Some SoCs can have different value > - if changed by pre-boot regime. The value here must match > - the current value in SoC. If not sure, do not change. > -config SYS_FSL_NUM_LAWS > - int "Number of local access windows" > - default 10 if ARCH_MPC8610 || ARCH_MPC8641 > - help > - Number of local access windows. This is fixed per SoC. > - If not sure, do not change. > - > -source "board/sbc8641d/Kconfig" > - > -endmenu > diff --git a/arch/powerpc/cpu/mpc86xx/Makefile b/arch/powerpc/cpu/mpc86xx/Makefile > deleted file mode 100644 > index 6e12be6a3f24..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/Makefile > +++ /dev/null > @@ -1,24 +0,0 @@ > -# SPDX-License-Identifier: GPL-2.0+ > -# > -# Copyright 2007 Freescale Semiconductor, Inc. > -# (C) Copyright 2002,2003 Motorola Inc. > -# Xianghua Xiao,X.Xiao at motorola.com > -# > -# (C) Copyright 2004 Freescale Semiconductor. (MC86xx Port) > -# Jeff Brown > -# > - > -extra-y = start.o > -extra-y += traps.o > - > -obj-y += cache.o > -obj-$(CONFIG_MP) += release.o > - > -obj-y += cpu.o > -obj-y += cpu_init.o > -obj-$(CONFIG_OF_LIBFDT) += fdt.o > -obj-y += interrupts.o > -obj-$(CONFIG_MP) += mp.o > -obj-$(CONFIG_ARCH_MPC8610) += mpc8610_serdes.o > -obj-$(CONFIG_ARCH_MPC8641) += mpc8641_serdes.o > -obj-y += speed.o > diff --git a/arch/powerpc/cpu/mpc86xx/cache.S b/arch/powerpc/cpu/mpc86xx/cache.S > deleted file mode 100644 > index 34968c604d7b..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/cache.S > +++ /dev/null > @@ -1,332 +0,0 @@ > -#include > -#include > - > -#include > -#include > - > -#include > -#include > - > -#ifndef CACHE_LINE_SIZE > -# define CACHE_LINE_SIZE L1_CACHE_BYTES > -#endif > - > -#if CACHE_LINE_SIZE == 128 > -#define LG_CACHE_LINE_SIZE 7 > -#elif CACHE_LINE_SIZE == 32 > -#define LG_CACHE_LINE_SIZE 5 > -#elif CACHE_LINE_SIZE == 16 > -#define LG_CACHE_LINE_SIZE 4 > -#elif CACHE_LINE_SIZE == 8 > -#define LG_CACHE_LINE_SIZE 3 > -#else > -# error "Invalid cache line size!" > -#endif > - > -/* > - * Most of this code is taken from 74xx_7xx/cache.S > - * and then cleaned up a bit > - */ > - > -/* > - * Invalidate L1 instruction cache. > - */ > -_GLOBAL(invalidate_l1_instruction_cache) > - /* use invalidate-all bit in HID0 */ > - mfspr r3,HID0 > - ori r3,r3,HID0_ICFI > - mtspr HID0,r3 > - isync > - blr > - > -/* > - * Invalidate L1 data cache. > - */ > -_GLOBAL(invalidate_l1_data_cache) > - mfspr r3,HID0 > - ori r3,r3,HID0_DCFI > - mtspr HID0,r3 > - isync > - blr > - > -/* > - * Flush data cache. > - */ > -_GLOBAL(flush_dcache) > - lis r3,0 > - lis r5,CACHE_LINE_SIZE > -flush: > - cmp 0,1,r3,r5 > - bge done > - lwz r5,0(r3) > - lis r5,CACHE_LINE_SIZE > - addi r3,r3,0x4 > - b flush > -done: > - blr > -/* > - * Write any modified data cache blocks out to memory > - * and invalidate the corresponding instruction cache blocks. > - * This is a no-op on the 601. > - * > - * flush_icache_range(unsigned long start, unsigned long stop) > - */ > -_GLOBAL(flush_icache_range) > - li r5,CACHE_LINE_SIZE-1 > - andc r3,r3,r5 > - subf r4,r3,r4 > - add r4,r4,r5 > - srwi. r4,r4,LG_CACHE_LINE_SIZE > - beqlr > - mtctr r4 > - mr r6,r3 > -1: dcbst 0,r3 > - addi r3,r3,CACHE_LINE_SIZE > - bdnz 1b > - sync /* wait for dcbst's to get to ram */ > - mtctr r4 > -2: icbi 0,r6 > - addi r6,r6,CACHE_LINE_SIZE > - bdnz 2b > - sync /* additional sync needed on g4 */ > - isync > - blr > -/* > - * Write any modified data cache blocks out to memory. > - * Does not invalidate the corresponding cache lines (especially for > - * any corresponding instruction cache). > - * > - * clean_dcache_range(unsigned long start, unsigned long stop) > - */ > -_GLOBAL(clean_dcache_range) > - li r5,CACHE_LINE_SIZE-1 > - andc r3,r3,r5 /* align r3 down to cache line */ > - subf r4,r3,r4 /* r4 = offset of stop from start of cache line */ > - add r4,r4,r5 /* r4 += cache_line_size-1 */ > - srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */ > - beqlr /* if r4 == 0 return */ > - mtctr r4 /* ctr = r4 */ > - > - sync > -1: dcbst 0,r3 > - addi r3,r3,CACHE_LINE_SIZE > - bdnz 1b > - sync /* wait for dcbst's to get to ram */ > - blr > - > -/* > - * Flush a particular page from the data cache to RAM. > - * Note: this is necessary because the instruction cache does *not* > - * snoop from the data cache. > - * > - * void __flush_page_to_ram(void *page) > - */ > -_GLOBAL(__flush_page_to_ram) > - rlwinm r3,r3,0,0,19 /* Get page base address */ > - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ > - mtctr r4 > - mr r6,r3 > -0: dcbst 0,r3 /* Write line to ram */ > - addi r3,r3,CACHE_LINE_SIZE > - bdnz 0b > - sync > - mtctr r4 > -1: icbi 0,r6 > - addi r6,r6,CACHE_LINE_SIZE > - bdnz 1b > - sync > - isync > - blr > - > -/* > - * Flush a particular page from the instruction cache. > - * Note: this is necessary because the instruction cache does *not* > - * snoop from the data cache. > - * > - * void __flush_icache_page(void *page) > - */ > -_GLOBAL(__flush_icache_page) > - li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */ > - mtctr r4 > -1: icbi 0,r3 > - addi r3,r3,CACHE_LINE_SIZE > - bdnz 1b > - sync > - isync > - blr > - > -/* > - * Clear a page using the dcbz instruction, which doesn't cause any > - * memory traffic (except to write out any cache lines which get > - * displaced). This only works on cacheable memory. > - */ > -_GLOBAL(clear_page) > - li r0,4096/CACHE_LINE_SIZE > - mtctr r0 > -1: dcbz 0,r3 > - addi r3,r3,CACHE_LINE_SIZE > - bdnz 1b > - blr > - > -/* > - * Enable L1 Instruction cache > - */ > -_GLOBAL(icache_enable) > - mfspr r3, HID0 > - li r5, HID0_ICFI|HID0_ILOCK > - andc r3, r3, r5 > - ori r3, r3, HID0_ICE > - ori r5, r3, HID0_ICFI > - mtspr HID0, r5 > - mtspr HID0, r3 > - isync > - blr > - > -/* > - * Disable L1 Instruction cache > - */ > -_GLOBAL(icache_disable) > - mflr r4 > - bl invalidate_l1_instruction_cache /* uses r3 */ > - sync > - mtlr r4 > - mfspr r3, HID0 > - li r5, 0 > - ori r5, r5, HID0_ICE > - andc r3, r3, r5 > - mtspr HID0, r3 > - isync > - blr > - > -/* > - * Is instruction cache enabled? > - */ > -_GLOBAL(icache_status) > - mfspr r3, HID0 > - andi. r3, r3, HID0_ICE > - blr > - > - > -_GLOBAL(l1dcache_enable) > - mfspr r3, HID0 > - li r5, HID0_DCFI|HID0_DLOCK > - andc r3, r3, r5 > - mtspr HID0, r3 /* no invalidate, unlock */ > - ori r3, r3, HID0_DCE > - ori r5, r3, HID0_DCFI > - mtspr HID0, r5 /* enable + invalidate */ > - mtspr HID0, r3 /* enable */ > - sync > - blr > - > -/* > - * Enable data cache(s) - L1 and optionally L2 > - * Calls l2cache_enable. LR saved in r5 > - */ > -_GLOBAL(dcache_enable) > - mfspr r3, HID0 > - li r5, HID0_DCFI|HID0_DLOCK > - andc r3, r3, r5 > - mtspr HID0, r3 /* no invalidate, unlock */ > - ori r3, r3, HID0_DCE > - ori r5, r3, HID0_DCFI > - mtspr HID0, r5 /* enable + invalidate */ > - mtspr HID0, r3 /* enable */ > - sync > -#ifdef CONFIG_SYS_L2 > - mflr r5 > - bl l2cache_enable /* uses r3 and r4 */ > - sync > - mtlr r5 > -#endif > - blr > - > - > -/* > - * Disable data cache(s) - L1 and optionally L2 > - * Calls flush_dcache and l2cache_disable_no_flush. > - * LR saved in r4 > - */ > -_GLOBAL(dcache_disable) > - mflr r4 /* save link register */ > - bl flush_dcache /* uses r3 and r5 */ > - sync > - mfspr r3, HID0 > - li r5, HID0_DCFI|HID0_DLOCK > - andc r3, r3, r5 > - mtspr HID0, r3 /* no invalidate, unlock */ > - li r5, HID0_DCE|HID0_DCFI > - andc r3, r3, r5 /* no enable, no invalidate */ > - mtspr HID0, r3 > - sync > -#ifdef CONFIG_SYS_L2 > - bl l2cache_disable_no_flush /* uses r3 */ > -#endif > - mtlr r4 /* restore link register */ > - blr > - > -/* > - * Is data cache enabled? > - */ > -_GLOBAL(dcache_status) > - mfspr r3, HID0 > - andi. r3, r3, HID0_DCE > - blr > - > -/* > - * Invalidate L2 cache using L2I, assume L2 is enabled > - */ > -_GLOBAL(l2cache_invalidate) > - mfspr r3, l2cr > - rlwinm. r3, r3, 0, 0, 0 > - beq 1f > - > - mfspr r3, l2cr > - rlwinm r3, r3, 0, 1, 31 > - > -#ifdef CONFIG_ALTIVEC > - dssall > -#endif > - sync > - mtspr l2cr, r3 > - sync > -1: mfspr r3, l2cr > - oris r3, r3, L2CR_L2I at h > - mtspr l2cr, r3 > - > -invl2: > - mfspr r3, l2cr > - andis. r3, r3, L2CR_L2I at h > - bne invl2 > - blr > - > -/* > - * Enable L2 cache > - * Calls l2cache_invalidate. LR is saved in r4 > - */ > -_GLOBAL(l2cache_enable) > - mflr r4 /* save link register */ > - bl l2cache_invalidate /* uses r3 */ > - sync > - lis r3, L2_ENABLE at h > - ori r3, r3, L2_ENABLE at l > - mtspr l2cr, r3 > - isync > - mtlr r4 /* restore link register */ > - blr > - > -/* > - * Disable L2 cache > - * Calls flush_dcache. LR is saved in r4 > - */ > -_GLOBAL(l2cache_disable) > - mflr r4 /* save link register */ > - bl flush_dcache /* uses r3 and r5 */ > - sync > - mtlr r4 /* restore link register */ > -l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */ > - lis r3, L2_INIT at h > - ori r3, r3, L2_INIT at l > - mtspr l2cr, r3 > - isync > - blr > diff --git a/arch/powerpc/cpu/mpc86xx/config.mk b/arch/powerpc/cpu/mpc86xx/config.mk > deleted file mode 100644 > index 5db5b0b4ed7e..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/config.mk > +++ /dev/null > @@ -1,6 +0,0 @@ > -# SPDX-License-Identifier: GPL-2.0+ > -# > -# (C) Copyright 2004 Freescale Semiconductor. > -# Jeff Brown > - > -PLATFORM_CPPFLAGS += -mcpu=7400 -mstring -maltivec -mabi=altivec -msoft-float > diff --git a/arch/powerpc/cpu/mpc86xx/cpu.c b/arch/powerpc/cpu/mpc86xx/cpu.c > deleted file mode 100644 > index 98b42bff7a3b..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/cpu.c > +++ /dev/null > @@ -1,207 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0+ > -/* > - * Copyright 2006,2009-2010 Freescale Semiconductor, Inc. > - * Jeff Brown > - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com) > - */ > - > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > - > -DECLARE_GLOBAL_DATA_PTR; > - > -/* > - * Default board reset function > - */ > -static void > -__board_reset(void) > -{ > - /* Do nothing */ > -} > -void board_reset(void) __attribute__((weak, alias("__board_reset"))); > - > - > -int > -checkcpu(void) > -{ > - sys_info_t sysinfo; > - uint pvr, svr; > - uint major, minor; > - char buf1[32], buf2[32]; > - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; > - volatile ccsr_gur_t *gur = &immap->im_gur; > - struct cpu_type *cpu; > - uint msscr0 = mfspr(MSSCR0); > - > - svr = get_svr(); > - major = SVR_MAJ(svr); > - minor = SVR_MIN(svr); > - > - if (cpu_numcores() > 1) { > -#ifndef CONFIG_MP > - puts("Unicore software on multiprocessor system!!\n" > - "To enable mutlticore build define CONFIG_MP\n"); > -#endif > - } > - puts("CPU: "); > - > - cpu = gd->arch.cpu; > - > - puts(cpu->name); > - > - printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); > - puts("Core: "); > - > - pvr = get_pvr(); > - major = PVR_E600_MAJ(pvr); > - minor = PVR_E600_MIN(pvr); > - > - printf("e600 Core %d", (msscr0 & 0x20) ? 1 : 0); > - if (gur->pordevsr & MPC86xx_PORDEVSR_CORE1TE) > - puts("\n Core1Translation Enabled"); > - debug(" (MSSCR0=%x, PORDEVSR=%x)", msscr0, gur->pordevsr); > - > - printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); > - > - get_sys_info(&sysinfo); > - > - puts("Clock Configuration:\n"); > - printf(" CPU:%-4s MHz, ", strmhz(buf1, sysinfo.freq_processor)); > - printf("MPX:%-4s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); > - printf(" DDR:%-4s MHz (%s MT/s data rate), ", > - strmhz(buf1, sysinfo.freq_systembus / 2), > - strmhz(buf2, sysinfo.freq_systembus)); > - > - if (sysinfo.freq_localbus > LCRR_CLKDIV) { > - printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); > - } else { > - printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", > - sysinfo.freq_localbus); > - } > - > - puts("L1: D-cache 32 KiB enabled\n"); > - puts(" I-cache 32 KiB enabled\n"); > - > - puts("L2: "); > - if (get_l2cr() & 0x80000000) { > -#if defined(CONFIG_ARCH_MPC8610) > - puts("256"); > -#elif defined(CONFIG_ARCH_MPC8641) > - puts("512"); > -#endif > - puts(" KiB enabled\n"); > - } else { > - puts("Disabled\n"); > - } > - > - return 0; > -} > - > - > -int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) > -{ > - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; > - volatile ccsr_gur_t *gur = &immap->im_gur; > - > - /* Attempt board-specific reset */ > - board_reset(); > - > - /* Next try asserting HRESET_REQ */ > - out_be32(&gur->rstcr, MPC86xx_RSTCR_HRST_REQ); > - > - while (1) > - ; > - > - return 1; > -} > - > - > -/* > - * Get timebase clock frequency > - */ > -unsigned long > -get_tbclk(void) > -{ > - sys_info_t sys_info; > - > - get_sys_info(&sys_info); > - return (sys_info.freq_systembus + 3L) / 4L; > -} > - > - > -#if defined(CONFIG_WATCHDOG) > -void > -watchdog_reset(void) > -{ > -#if defined(CONFIG_ARCH_MPC8610) > - /* > - * This actually feed the hard enabled watchdog. > - */ > - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; > - volatile ccsr_wdt_t *wdt = &immap->im_wdt; > - volatile ccsr_gur_t *gur = &immap->im_gur; > - u32 tmp = gur->pordevsr; > - > - if (tmp & 0x4000) { > - wdt->swsrr = 0x556c; > - wdt->swsrr = 0xaa39; > - } > -#endif > -} > -#endif /* CONFIG_WATCHDOG */ > - > -/* > - * Print out the state of various machine registers. > - * Currently prints out LAWs, BR0/OR0, and BATs > - */ > -void print_reginfo(void) > -{ > - print_bats(); > - print_laws(); > - print_lbc_regs(); > -} > - > -/* > - * Set the DDR BATs to reflect the actual size of DDR. > - * > - * dram_size is the actual size of DDR, in bytes > - * > - * Note: we assume that CONFIG_MAX_MEM_MAPPED is 2G or smaller as we only > - * are using a single BAT to cover DDR. > - * > - * If this is not true, (e.g. CONFIG_MAX_MEM_MAPPED is 2GB but HID0_XBSEN > - * is not defined) then we might have a situation where U-Boot will attempt > - * to relocated itself outside of the region mapped by DBAT0. > - * This will cause a machine check. > - * > - * Currently we are limited to power of two sized DDR since we only use a > - * single bat. If a non-power of two size is used that is less than > - * CONFIG_MAX_MEM_MAPPED u-boot will crash. > - * > - */ > -void setup_ddr_bat(phys_addr_t dram_size) > -{ > - unsigned long batu, bl; > - > - bl = TO_BATU_BL(min(dram_size, CONFIG_MAX_MEM_MAPPED)); > - > - if (BATU_SIZE(bl) != dram_size) { > - u64 sz = (u64)dram_size - BATU_SIZE(bl); > - print_size(sz, " left unmapped\n"); > - } > - > - batu = bl | BATU_VS | BATU_VP; > - write_bat(DBAT0, batu, CONFIG_SYS_DBAT0L); > - write_bat(IBAT0, batu, CONFIG_SYS_IBAT0L); > -} > diff --git a/arch/powerpc/cpu/mpc86xx/cpu_init.c b/arch/powerpc/cpu/mpc86xx/cpu_init.c > deleted file mode 100644 > index 73779f862c2a..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/cpu_init.c > +++ /dev/null > @@ -1,104 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0+ > -/* > - * Copyright 2004,2009-2011 Freescale Semiconductor, Inc. > - * Jeff Brown > - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com) > - */ > - > -/* > - * cpu_init.c - low level cpu init > - */ > - > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > - > -extern void srio_init(void); > - > -DECLARE_GLOBAL_DATA_PTR; > - > -/* > - * Breathe some life into the CPU... > - * > - * Set up the memory map > - * initialize a bunch of registers > - */ > - > -void cpu_init_f(void) > -{ > - /* Pointer is writable since we allocated a register for it */ > - gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); > - > - /* Clear initial global data */ > - memset ((void *) gd, 0, sizeof (gd_t)); > - > -#ifdef CONFIG_FSL_LAW > - init_laws(); > -#endif > - > - setup_bats(); > - > - init_early_memctl_regs(); > - > -#if defined(CONFIG_FSL_DMA) > - dma_init(); > -#endif > - > - /* enable the timebase bit in HID0 */ > - set_hid0(get_hid0() | 0x4000000); > - > - /* enable EMCP, SYNCBE | ABE bits in HID1 */ > - set_hid1(get_hid1() | 0x80000C00); > -} > - > -/* > - * initialize higher level parts of CPU like timers > - */ > -int cpu_init_r(void) > -{ > - /* needs to be in ram since code uses global static vars */ > - fsl_serdes_init(); > - > -#ifdef CONFIG_SYS_SRIO > - srio_init(); > -#endif > - > -#if defined(CONFIG_MP) > - setup_mp(); > -#endif > - return 0; > -} > - > -#ifdef CONFIG_ADDR_MAP > -/* Initialize address mapping array */ > -void init_addr_map(void) > -{ > - int i; > - ppc_bat_t bat = DBAT0; > - phys_size_t size; > - unsigned long upper, lower; > - > - for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) { > - if (read_bat(bat, &upper, &lower) != -1) { > - if (!BATU_VALID(upper)) > - size = 0; > - else > - size = BATU_SIZE(upper); > - addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower), > - size, i); > - } > -#ifdef CONFIG_HIGH_BATS > - /* High bats are not contiguous with low BAT numbers */ > - if (bat == DBAT3) > - bat = DBAT4 - 1; > -#endif > - } > -} > -#endif > diff --git a/arch/powerpc/cpu/mpc86xx/fdt.c b/arch/powerpc/cpu/mpc86xx/fdt.c > deleted file mode 100644 > index 1313d8adde66..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/fdt.c > +++ /dev/null > @@ -1,52 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0 > -/* > - * Copyright 2008, 2011 Freescale Semiconductor, Inc. > - */ > - > -#include > -#include > -#include > -#include > -#include > - > -DECLARE_GLOBAL_DATA_PTR; > - > -extern void ft_fixup_num_cores(void *blob); > -extern void ft_srio_setup(void *blob); > - > -void ft_cpu_setup(void *blob, struct bd_info *bd) > -{ > -#ifdef CONFIG_MP > - int off; > - u32 bootpg = determine_mp_bootpg(NULL); > -#endif > - > - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, > - "timebase-frequency", bd->bi_busfreq / 4, 1); > - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, > - "bus-frequency", bd->bi_busfreq, 1); > - do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, > - "clock-frequency", bd->bi_intfreq, 1); > - do_fixup_by_prop_u32(blob, "device_type", "soc", 4, > - "bus-frequency", bd->bi_busfreq, 1); > - > - fdt_fixup_memory(blob, (u64)gd->ram_base, (u64)gd->ram_size); > - > -#ifdef CONFIG_SYS_NS16550 > - do_fixup_by_compat_u32(blob, "ns16550", > - "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); > -#endif > - > -#ifdef CONFIG_MP > - /* Reserve the boot page so OSes dont use it */ > - off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); > - if (off < 0) > - printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); > - > - ft_fixup_num_cores(blob); > -#endif > - > -#ifdef CONFIG_SYS_SRIO > - ft_srio_setup(blob); > -#endif > -} > diff --git a/arch/powerpc/cpu/mpc86xx/interrupts.c b/arch/powerpc/cpu/mpc86xx/interrupts.c > deleted file mode 100644 > index 5a916600ed62..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/interrupts.c > +++ /dev/null > @@ -1,116 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0+ > -/* > - * (C) Copyright 2000-2002 > - * Wolfgang Denk, DENX Software Engineering, wd at denx.de. > - * > - * (C) Copyright 2002 (440 port) > - * Scott McNutt, Artesyn Communication Producs, smcnutt at artsyncp.com > - * > - * (C) Copyright 2003 Motorola Inc. (MPC85xx port) > - * Xianghua Xiao (X.Xiao at motorola.com) > - * > - * (C) Copyright 2004, 2007 Freescale Semiconductor. (MPC86xx Port) > - * Jeff Brown > - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com) > - */ > - > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#ifdef CONFIG_POST > -#include > -#endif > -#include > - > -void interrupt_init_cpu(unsigned *decrementer_count) > -{ > - volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; > - volatile ccsr_pic_t *pic = &immr->im_pic; > - > -#ifdef CONFIG_POST > - /* > - * The POST word is stored in the PIC's TFRR register which gets > - * cleared when the PIC is reset. Save it off so we can restore it > - * later. > - */ > - ulong post_word = post_word_load(); > -#endif > - > - pic->gcr = MPC86xx_PICGCR_RST; > - while (pic->gcr & MPC86xx_PICGCR_RST) > - ; > - pic->gcr = MPC86xx_PICGCR_MODE; > - > - *decrementer_count = get_tbclk() / CONFIG_SYS_HZ; > - debug("interrupt init: tbclk() = %ld MHz, decrementer_count = %d\n", > - (get_tbclk() / 1000000), > - *decrementer_count); > - > -#ifdef CONFIG_INTERRUPTS > - > - pic->iivpr1 = 0x810001; /* 50220 enable mcm interrupts */ > - debug("iivpr1@%p = %x\n", &pic->iivpr1, pic->iivpr1); > - > - pic->iivpr2 = 0x810002; /* 50240 enable ddr interrupts */ > - debug("iivpr2@%p = %x\n", &pic->iivpr2, pic->iivpr2); > - > - pic->iivpr3 = 0x810003; /* 50260 enable lbc interrupts */ > - debug("iivpr3@%p = %x\n", &pic->iivpr3, pic->iivpr3); > - > -#if defined(CONFIG_PCI1) || defined(CONFIG_PCIE1) > - pic->iivpr8 = 0x810008; /* enable pcie1 interrupts */ > - debug("iivpr8@%p = %x\n", &pic->iivpr8, pic->iivpr8); > -#endif > -#if defined(CONFIG_PCI2) || defined(CONFIG_PCIE2) > - pic->iivpr9 = 0x810009; /* enable pcie2 interrupts */ > - debug("iivpr9@%p = %x\n", &pic->iivpr9, pic->iivpr9); > -#endif > - > - pic->ctpr = 0; /* 40080 clear current task priority register */ > -#endif > - > -#ifdef CONFIG_POST > - post_word_store(post_word); > -#endif > -} > - > -/* > - * timer_interrupt - gets called when the decrementer overflows, > - * with interrupts disabled. > - * Trivial implementation - no need to be really accurate. > - */ > -void timer_interrupt_cpu(struct pt_regs *regs) > -{ > - /* nothing to do here */ > -} > - > -/* > - * Install and free a interrupt handler. Not implemented yet. > - */ > -void irq_install_handler(int vec, interrupt_handler_t *handler, void *arg) > -{ > -} > - > -void irq_free_handler(int vec) > -{ > -} > - > -/* > - * irqinfo - print information about PCI devices,not implemented. > - */ > -int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) > -{ > - return 0; > -} > - > -/* > - * Handle external interrupts > - */ > -void external_interrupt(struct pt_regs *regs) > -{ > - puts("external_interrupt(oops!)\n"); > -} > diff --git a/arch/powerpc/cpu/mpc86xx/mp.c b/arch/powerpc/cpu/mpc86xx/mp.c > deleted file mode 100644 > index e6795e06c98b..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/mp.c > +++ /dev/null > @@ -1,130 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0+ > -/* > - * Copyright 2008-2010 Freescale Semiconductor, Inc. > - */ > - > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > - > -DECLARE_GLOBAL_DATA_PTR; > - > -int cpu_reset(u32 nr) > -{ > - /* dummy function so common/cmd_mp.c will build > - * should be implemented in the future, when cpu_release() > - * is supported. Be aware there may be a similiar bug > - * as exists on MPC85xx w/its PIC having a timing window > - * associated to resetting the core */ > - return 1; > -} > - > -int cpu_status(u32 nr) > -{ > - /* dummy function so common/cmd_mp.c will build */ > - return 0; > -} > - > -int cpu_disable(u32 nr) > -{ > - volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; > - volatile ccsr_gur_t *gur = &immap->im_gur; > - > - switch (nr) { > - case 0: > - setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU0); > - break; > - case 1: > - setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_CPU1); > - break; > - default: > - printf("Invalid cpu number for disable %d\n", nr); > - return 1; > - } > - > - return 0; > -} > - > -int is_core_disabled(int nr) { > - immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; > - ccsr_gur_t *gur = &immap->im_gur; > - u32 devdisr = in_be32(&gur->devdisr); > - > - switch (nr) { > - case 0: > - return (devdisr & MPC86xx_DEVDISR_CPU0); > - case 1: > - return (devdisr & MPC86xx_DEVDISR_CPU1); > - default: > - printf("Invalid cpu number for disable %d\n", nr); > - } > - > - return 0; > -} > - > -int cpu_release(u32 nr, int argc, char *const argv[]) > -{ > - /* dummy function so common/cmd_mp.c will build > - * should be implemented in the future */ > - return 1; > -} > - > -u32 determine_mp_bootpg(unsigned int *pagesize) > -{ > - if (pagesize) > - *pagesize = 4096; > - > - /* if we have 4G or more of memory, put the boot page at 4Gb-1M */ > - if ((u64)gd->ram_size > 0xfffff000) > - return (0xfff00000); > - > - return (gd->ram_size - (1024 * 1024)); > -} > - > -void cpu_mp_lmb_reserve(struct lmb *lmb) > -{ > - u32 bootpg = determine_mp_bootpg(NULL); > - > - /* tell u-boot we stole a page */ > - lmb_reserve(lmb, bootpg, 4096); > -} > - > -/* > - * Copy the code for other cpus to execute into an > - * aligned location accessible via BPTR > - */ > -void setup_mp(void) > -{ > - extern ulong __secondary_start_page; > - ulong fixup = (ulong)&__secondary_start_page; > - u32 bootpg = determine_mp_bootpg(NULL); > - u32 bootpg_va; > - > - if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) { > - /* We're not covered by the DDR mapping, set up BAT */ > - write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K | > - BATU_VS | BATU_VP, > - bootpg | BATL_PP_RW | BATL_MEMCOHERENCE); > - bootpg_va = CONFIG_SYS_SCRATCH_VA; > - } else { > - bootpg_va = bootpg; > - } > - > - memcpy((void *)bootpg_va, (void *)fixup, 4096); > - flush_cache(bootpg_va, 4096); > - > - /* remove the temporary BAT mapping */ > - if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) > - write_bat(DBAT7, 0, 0); > - > - /* If the physical location of bootpg is not at fff00000, set BPTR */ > - if (bootpg != 0xfff00000) > - out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 | > - (bootpg >> 12)); > -} > diff --git a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c > deleted file mode 100644 > index ecc88ba43746..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/mpc8610_serdes.c > +++ /dev/null > @@ -1,87 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0+ > -/* > - * Copyright 2010 Freescale Semiconductor, Inc. > - */ > - > -#include > -#include > -#include > -#include > -#include > -#include > - > -#define SRDS1_MAX_LANES 4 > -#define SRDS2_MAX_LANES 4 > - > -static u32 serdes1_prtcl_map, serdes2_prtcl_map; > - > -static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { > - [0x1] = {PCIE1, PCIE1, PCIE1, PCIE1}, > - [0x4] = {PCIE1, PCIE1, PCIE1, PCIE1}, > - [0x7] = {NONE, NONE, NONE, NONE}, > -}; > - > -static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { > - [0x0] = {PCIE2, PCIE2, PCIE2, PCIE2}, > - [0x4] = {PCIE2, PCIE2, PCIE2, PCIE2}, > - [0x7] = {NONE, NONE, NONE, NONE}, > -}; > - > -int is_serdes_configured(enum srds_prtcl device) > -{ > - int ret; > - > - if (!(serdes1_prtcl_map & (1 << NONE))) > - fsl_serdes_init(); > - > - ret = (1 << device) & serdes1_prtcl_map; > - > - if (ret) > - return ret; > - > - if (!(serdes2_prtcl_map & (1 << NONE))) > - fsl_serdes_init(); > - > - return (1 << device) & serdes2_prtcl_map; > -} > - > -void fsl_serdes_init(void) > -{ > - immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; > - ccsr_gur_t *gur = &immap->im_gur; > - u32 pordevsr = in_be32(&gur->pordevsr); > - u32 srds_cfg = (pordevsr & MPC8610_PORDEVSR_IO_SEL) >> > - MPC8610_PORDEVSR_IO_SEL_SHIFT; > - int lane; > - > - if (serdes1_prtcl_map & (1 << NONE) && > - serdes2_prtcl_map & (1 << NONE)) > - return; > - > - debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); > - > - if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { > - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); > - return; > - } > - for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { > - enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; > - serdes1_prtcl_map |= (1 << lane_prtcl); > - } > - > - /* Set the first bit to indicate serdes has been initialized */ > - serdes1_prtcl_map |= (1 << NONE); > - > - if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { > - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); > - return; > - } > - > - for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { > - enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; > - serdes2_prtcl_map |= (1 << lane_prtcl); > - } > - > - /* Set the first bit to indicate serdes has been initialized */ > - serdes2_prtcl_map |= (1 << NONE); > -} > diff --git a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c b/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c > deleted file mode 100644 > index 4df446618c09..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/mpc8641_serdes.c > +++ /dev/null > @@ -1,96 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0+ > -/* > - * Copyright 2010 Freescale Semiconductor, Inc. > - */ > - > -#include > -#include > -#include > -#include > -#include > -#include > - > -#define SRDS1_MAX_LANES 4 > -#define SRDS2_MAX_LANES 4 > - > -static u32 serdes1_prtcl_map, serdes2_prtcl_map; > - > -static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = { > - [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1}, > - [0x3] = {PCIE1, PCIE1, PCIE1, PCIE1}, > - [0x5] = {PCIE1, PCIE1, PCIE1, PCIE1}, > - [0x6] = {PCIE1, PCIE1, PCIE1, PCIE1}, > - [0x7] = {PCIE1, PCIE1, PCIE1, PCIE1}, > - [0xf] = {PCIE1, PCIE1, PCIE1, PCIE1}, > -}; > - > -static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = { > - [0x3] = {PCIE2, PCIE2, PCIE2, PCIE2}, > - [0x5] = {SRIO1, SRIO1, SRIO1, SRIO1}, > - [0x6] = {SRIO1, SRIO1, SRIO1, SRIO1}, > - [0x7] = {SRIO1, SRIO1, SRIO1, SRIO1}, > - [0x9] = {SRIO1, SRIO1, SRIO1, SRIO1}, > - [0xa] = {SRIO1, SRIO1, SRIO1, SRIO1}, > - [0xb] = {SRIO1, SRIO1, SRIO1, SRIO1}, > - [0xe] = {PCIE2, PCIE2, PCIE2, PCIE2}, > - [0xf] = {PCIE2, PCIE2, PCIE2, PCIE2}, > -}; > - > -int is_serdes_configured(enum srds_prtcl device) > -{ > - int ret; > - > - if (!(serdes1_prtcl_map & (1 << NONE))) > - fsl_serdes_init(); > - > - ret = (1 << device) & serdes1_prtcl_map; > - > - if (ret) > - return ret; > - > - if (!(serdes2_prtcl_map & (1 << NONE))) > - fsl_serdes_init(); > - > - return (1 << device) & serdes2_prtcl_map; > -} > - > -void fsl_serdes_init(void) > -{ > - immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; > - ccsr_gur_t *gur = &immap->im_gur; > - u32 pordevsr = in_be32(&gur->pordevsr); > - u32 srds_cfg = (pordevsr & MPC8641_PORDEVSR_IO_SEL) >> > - MPC8641_PORDEVSR_IO_SEL_SHIFT; > - int lane; > - > - if (serdes1_prtcl_map & (1 << NONE) && > - serdes2_prtcl_map & (1 << NONE)) > - return; > - > - debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); > - > - if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) { > - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); > - return; > - } > - for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { > - enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; > - serdes1_prtcl_map |= (1 << lane_prtcl); > - } > - > - /* Set the first bit to indicate serdes has been initialized */ > - serdes1_prtcl_map |= (1 << NONE); > - > - if (srds_cfg >= ARRAY_SIZE(serdes2_cfg_tbl)) { > - printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); > - return; > - } > - > - for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { > - enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; > - serdes2_prtcl_map |= (1 << lane_prtcl); > - } > - > - /* Set the first bit to indicate serdes has been initialized */ > - serdes2_prtcl_map |= (1 << NONE); > -} > diff --git a/arch/powerpc/cpu/mpc86xx/release.S b/arch/powerpc/cpu/mpc86xx/release.S > deleted file mode 100644 > index 72ad8834c979..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/release.S > +++ /dev/null > @@ -1,149 +0,0 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > -/* > - * Copyright 2004, 2007, 2008 Freescale Semiconductor. > - * Srikanth Srinivasan > - */ > -#include > -#include > - > -#include > -#include > - > -#include > -#include > - > -/* If this is a multi-cpu system then we need to handle the > - * 2nd cpu. The assumption is that the 2nd cpu is being > - * held in boot holdoff mode until the 1st cpu unlocks it > - * from Linux. We'll do some basic cpu init and then pass > - * it to the Linux Reset Vector. > - * Sri: Much of this initialization is not required. Linux > - * rewrites the bats, and the sprs and also enables the L1 cache. > - * > - * Core 0 must copy this to a 1M aligned region and set BPTR > - * to point to it. > - */ > - .align 12 > -.globl __secondary_start_page > -__secondary_start_page: > - .space 0x100 /* space over to reset vector loc */ > - mfspr r0, MSSCR0 > - andi. r0, r0, 0x0020 > - rlwinm r0,r0,27,31,31 > - mtspr PIR, r0 > - > - /* Invalidate BATs */ > - li r0, 0 > - mtspr IBAT0U, r0 > - mtspr IBAT1U, r0 > - mtspr IBAT2U, r0 > - mtspr IBAT3U, r0 > - mtspr IBAT4U, r0 > - mtspr IBAT5U, r0 > - mtspr IBAT6U, r0 > - mtspr IBAT7U, r0 > - isync > - mtspr DBAT0U, r0 > - mtspr DBAT1U, r0 > - mtspr DBAT2U, r0 > - mtspr DBAT3U, r0 > - mtspr DBAT4U, r0 > - mtspr DBAT5U, r0 > - mtspr DBAT6U, r0 > - mtspr DBAT7U, r0 > - isync > - sync > - > - /* enable extended addressing */ > - mfspr r0, HID0 > - lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h > - ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l > - mtspr HID0, r0 > - sync > - isync > - > -#ifdef CONFIG_SYS_L2 > - /* init the L2 cache */ > - addis r3, r0, L2_INIT at h > - ori r3, r3, L2_INIT at l > - sync > - mtspr l2cr, r3 > -#ifdef CONFIG_ALTIVEC > - dssall > -#endif > - /* invalidate the L2 cache */ > - mfspr r3, l2cr > - rlwinm. r3, r3, 0, 0, 0 > - beq 1f > - > - mfspr r3, l2cr > - rlwinm r3, r3, 0, 1, 31 > - > -#ifdef CONFIG_ALTIVEC > - dssall > -#endif > - sync > - mtspr l2cr, r3 > - sync > -1: mfspr r3, l2cr > - oris r3, r3, L2CR_L2I at h > - mtspr l2cr, r3 > - > -invl2: > - mfspr r3, l2cr > - andis. r3, r3, L2CR_L2I at h > - bne invl2 > - sync > -#endif > - > - /* enable and invalidate the data cache */ > - mfspr r3, HID0 > - li r5, HID0_DCFI|HID0_DLOCK > - andc r3, r3, r5 > - mtspr HID0, r3 /* no invalidate, unlock */ > - ori r3, r3, HID0_DCE > - ori r5, r3, HID0_DCFI > - mtspr HID0, r5 /* enable + invalidate */ > - mtspr HID0, r3 /* enable */ > - sync > -#ifdef CONFIG_SYS_L2 > - sync > - lis r3, L2_ENABLE at h > - ori r3, r3, L2_ENABLE at l > - mtspr l2cr, r3 > - isync > - sync > -#endif > - > - /* enable and invalidate the instruction cache*/ > - mfspr r3, HID0 > - li r5, HID0_ICFI|HID0_ILOCK > - andc r3, r3, r5 > - ori r3, r3, HID0_ICE > - ori r5, r3, HID0_ICFI > - mtspr HID0, r5 > - mtspr HID0, r3 > - isync > - sync > - > - /* TBEN in HID0 */ > - mfspr r4, HID0 > - oris r4, r4, 0x0400 > - mtspr HID0, r4 > - sync > - isync > - > - /* MCP|SYNCBE|ABE in HID1 */ > - mfspr r4, HID1 > - oris r4, r4, 0x8000 > - ori r4, r4, 0x0C00 > - mtspr HID1, r4 > - sync > - isync > - > - lis r3, CONFIG_LINUX_RESET_VEC at h > - ori r3, r3, CONFIG_LINUX_RESET_VEC at l > - mtlr r3 > - blr > - > - /* Never Returns, Running in Linux Now */ > diff --git a/arch/powerpc/cpu/mpc86xx/speed.c b/arch/powerpc/cpu/mpc86xx/speed.c > deleted file mode 100644 > index 86c1709c4ca2..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/speed.c > +++ /dev/null > @@ -1,134 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0+ > -/* > - * Copyright 2004 Freescale Semiconductor. > - * Jeff Brown > - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com) > - * > - * (C) Copyright 2000-2002 > - * Wolfgang Denk, DENX Software Engineering, wd at denx.de. > - */ > - > -#include > -#include > -#include > -#include > -#include > -#include > - > -DECLARE_GLOBAL_DATA_PTR; > - > -/* used in some defintiions of CONFIG_SYS_CLK_FREQ */ > -extern unsigned long get_board_sys_clk(unsigned long dummy); > - > -void get_sys_info(sys_info_t *sys_info) > -{ > - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; > - volatile ccsr_gur_t *gur = &immap->im_gur; > - uint plat_ratio, e600_ratio; > - > - plat_ratio = (gur->porpllsr) & 0x0000003e; > - plat_ratio >>= 1; > - > - switch (plat_ratio) { > - case 0x0: > - sys_info->freq_systembus = 16 * CONFIG_SYS_CLK_FREQ; > - break; > - case 0x02: > - case 0x03: > - case 0x04: > - case 0x05: > - case 0x06: > - case 0x08: > - case 0x09: > - case 0x0a: > - case 0x0c: > - case 0x10: > - sys_info->freq_systembus = plat_ratio * CONFIG_SYS_CLK_FREQ; > - break; > - default: > - sys_info->freq_systembus = 0; > - break; > - } > - > - e600_ratio = (gur->porpllsr) & 0x003f0000; > - e600_ratio >>= 16; > - > - switch (e600_ratio) { > - case 0x10: > - sys_info->freq_processor = 2 * sys_info->freq_systembus; > - break; > - case 0x19: > - sys_info->freq_processor = 5 * sys_info->freq_systembus / 2; > - break; > - case 0x20: > - sys_info->freq_processor = 3 * sys_info->freq_systembus; > - break; > - case 0x39: > - sys_info->freq_processor = 7 * sys_info->freq_systembus / 2; > - break; > - case 0x28: > - sys_info->freq_processor = 4 * sys_info->freq_systembus; > - break; > - case 0x1d: > - sys_info->freq_processor = 9 * sys_info->freq_systembus / 2; > - break; > - default: > - sys_info->freq_processor = e600_ratio + > - sys_info->freq_systembus; > - break; > - } > - > - sys_info->freq_localbus = sys_info->freq_systembus; > -} > - > - > -/* > - * Measure CPU clock speed (core clock GCLK1, GCLK2) > - * (Approx. GCLK frequency in Hz) > - */ > - > -int get_clocks(void) > -{ > - sys_info_t sys_info; > - > - get_sys_info(&sys_info); > - gd->cpu_clk = sys_info.freq_processor; > - gd->bus_clk = sys_info.freq_systembus; > - gd->arch.lbc_clk = sys_info.freq_localbus; > - > - /* > - * The base clock for I2C depends on the actual SOC. Unfortunately, > - * there is no pattern that can be used to determine the frequency, so > - * the only choice is to look up the actual SOC number and use the value > - * for that SOC. This information is taken from application note > - * AN2919. > - */ > -#ifdef CONFIG_ARCH_MPC8610 > - gd->arch.i2c1_clk = sys_info.freq_systembus; > -#else > - gd->arch.i2c1_clk = sys_info.freq_systembus / 2; > -#endif > - gd->arch.i2c2_clk = gd->arch.i2c1_clk; > - > - if (gd->cpu_clk != 0) > - return 0; > - else > - return 1; > -} > - > - > -/* > - * get_bus_freq > - * Return system bus freq in Hz > - */ > - > -ulong get_bus_freq(ulong dummy) > -{ > - ulong val; > - sys_info_t sys_info; > - > - get_sys_info(&sys_info); > - val = sys_info.freq_systembus; > - > - return val; > -} > diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S > deleted file mode 100644 > index f4651ce8d46f..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/start.S > +++ /dev/null > @@ -1,982 +0,0 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > -/* > - * Copyright 2004, 2007, 2011 Freescale Semiconductor. > - * Srikanth Srinivasan > - */ > - > -/* U-Boot - Startup Code for 86xx PowerPC based Embedded Boards > - * > - * > - * The processor starts at 0xfff00100 and the code is executed > - * from flash. The code is organized to be at an other address > - * in memory, but as long we don't jump around before relocating. > - * board_init lies at a quite high address and when the cpu has > - * jumped there, everything is ok. > - */ > -#include > -#include > -#include > -#include > - > -#include > -#include > - > -#include > -#include > -#include > - > -/* > - * Need MSR_DR | MSR_IR enabled to access I/O (printf) in exceptions > - */ > - > -/* > - * Set up GOT: Global Offset Table > - * > - * Use r12 to access the GOT > - */ > - START_GOT > - GOT_ENTRY(_GOT2_TABLE_) > - GOT_ENTRY(_FIXUP_TABLE_) > - > - GOT_ENTRY(_start) > - GOT_ENTRY(_start_of_vectors) > - GOT_ENTRY(_end_of_vectors) > - GOT_ENTRY(transfer_to_handler) > - > - GOT_ENTRY(__init_end) > - GOT_ENTRY(__bss_end) > - GOT_ENTRY(__bss_start) > - END_GOT > - > -/* > - * r3 - 1st arg to board_init(): IMMP pointer > - * r4 - 2nd arg to board_init(): boot flag > - */ > - .text > - .long 0x27051956 /* U-Boot Magic Number */ > - .globl version_string > -version_string: > - .ascii U_BOOT_VERSION_STRING, "\0" > - > - . = EXC_OFF_SYS_RESET > - .globl _start > -_start: > - b boot_cold > - > - /* the boot code is located below the exception table */ > - > - .globl _start_of_vectors > -_start_of_vectors: > - > -/* Machine check */ > - STD_EXCEPTION(0x200, MachineCheck, MachineCheckException) > - > -/* Data Storage exception. */ > - STD_EXCEPTION(0x300, DataStorage, UnknownException) > - > -/* Instruction Storage exception. */ > - STD_EXCEPTION(0x400, InstStorage, UnknownException) > - > -/* External Interrupt exception. */ > - STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) > - > -/* Alignment exception. */ > - . = 0x600 > -Alignment: > - EXCEPTION_PROLOG(SRR0, SRR1) > - mfspr r4,DAR > - stw r4,_DAR(r21) > - mfspr r5,DSISR > - stw r5,_DSISR(r21) > - addi r3,r1,STACK_FRAME_OVERHEAD > - EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) > - > -/* Program check exception */ > - . = 0x700 > -ProgramCheck: > - EXCEPTION_PROLOG(SRR0, SRR1) > - addi r3,r1,STACK_FRAME_OVERHEAD > - EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, > - MSR_KERNEL, COPY_EE) > - > - STD_EXCEPTION(0x800, FPUnavailable, UnknownException) > - > - /* I guess we could implement decrementer, and may have > - * to someday for timekeeping. > - */ > - STD_EXCEPTION(0x900, Decrementer, timer_interrupt) > - STD_EXCEPTION(0xa00, Trap_0a, UnknownException) > - STD_EXCEPTION(0xb00, Trap_0b, UnknownException) > - STD_EXCEPTION(0xc00, SystemCall, UnknownException) > - STD_EXCEPTION(0xd00, SingleStep, UnknownException) > - STD_EXCEPTION(0xe00, Trap_0e, UnknownException) > - STD_EXCEPTION(0xf00, Trap_0f, UnknownException) > - STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException) > - STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) > - STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) > - STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException) > - STD_EXCEPTION(0x1400, DataTLBError, UnknownException) > - STD_EXCEPTION(0x1500, Reserved5, UnknownException) > - STD_EXCEPTION(0x1600, Reserved6, UnknownException) > - STD_EXCEPTION(0x1700, Reserved7, UnknownException) > - STD_EXCEPTION(0x1800, Reserved8, UnknownException) > - STD_EXCEPTION(0x1900, Reserved9, UnknownException) > - STD_EXCEPTION(0x1a00, ReservedA, UnknownException) > - STD_EXCEPTION(0x1b00, ReservedB, UnknownException) > - STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException) > - STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException) > - STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException) > - STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException) > - > - .globl _end_of_vectors > -_end_of_vectors: > - > - . = 0x2000 > - > -boot_cold: > - /* > - * NOTE: Only Cpu 0 will ever come here. Other cores go to an > - * address specified by the BPTR > - */ > -1: > -#ifdef CONFIG_SYS_RAMBOOT > - /* disable everything */ > - li r0, 0 > - mtspr HID0, r0 > - sync > - mtmsr 0 > -#endif > - > - /* Invalidate BATs */ > - bl invalidate_bats > - sync > - /* Invalidate all of TLB before MMU turn on */ > - bl clear_tlbs > - sync > - > -#ifdef CONFIG_SYS_L2 > - /* init the L2 cache */ > - lis r3, L2_INIT at h > - ori r3, r3, L2_INIT at l > - mtspr l2cr, r3 > - /* invalidate the L2 cache */ > - bl l2cache_invalidate > - sync > -#endif > - > - /* > - * Calculate absolute address in FLASH and jump there > - *------------------------------------------------------*/ > - lis r3, CONFIG_SYS_MONITOR_BASE_EARLY at h > - ori r3, r3, CONFIG_SYS_MONITOR_BASE_EARLY at l > - addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET > - mtlr r3 > - blr > - > -in_flash: > - /* let the C-code set up the rest */ > - /* */ > - /* Be careful to keep code relocatable ! */ > - /*------------------------------------------------------*/ > - /* perform low-level init */ > - > - /* enable extended addressing */ > - bl enable_ext_addr > - > - /* setup the bats */ > - bl early_bats > - > - /* > - * Cache must be enabled here for stack-in-cache trick. > - * This means we need to enable the BATS. > - * Cache should be turned on after BATs, since by default > - * everything is write-through. > - */ > - > - /* enable address translation */ > - mfmsr r5 > - ori r5, r5, (MSR_IR | MSR_DR) > - lis r3,addr_trans_enabled at h > - ori r3, r3, addr_trans_enabled at l > - mtspr SPRN_SRR0,r3 > - mtspr SPRN_SRR1,r5 > - rfi > - > -addr_trans_enabled: > - /* enable and invalidate the data cache */ > -/* bl l1dcache_enable */ > - bl dcache_enable > - sync > - > -#if 1 > - bl icache_enable > -#endif > - > -#ifdef CONFIG_SYS_INIT_RAM_LOCK > - bl lock_ram_in_cache > - sync > -#endif > - > -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) > - bl setup_ccsrbar > -#endif > - > - /* set up the stack pointer in our newly created > - * cache-ram (r1) */ > - lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h > - ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l > - > - li r0, 0 /* Make room for stack frame header and */ > - stwu r0, -4(r1) /* clear final stack frame so that */ > - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ > - > - GET_GOT /* initialize GOT access */ > - > - /* run low-level CPU init code (from Flash) */ > - bl cpu_init_f > - sync > - > -#ifdef RUN_DIAG > - > - /* Load PX_AUX register address in r4 */ > - lis r4, PIXIS_BASE at h > - ori r4, r4, 0x6 > - /* Load contents of PX_AUX in r3 bits 24 to 31*/ > - lbz r3, 0(r4) > - > - /* Mask and obtain the bit in r3 */ > - rlwinm. r3, r3, 0, 24, 24 > - /* If not zero, jump and continue with u-boot */ > - bne diag_done > - > - /* Load back contents of PX_AUX in r3 bits 24 to 31 */ > - lbz r3, 0(r4) > - /* Set the MSB of the register value */ > - ori r3, r3, 0x80 > - /* Write value in r3 back to PX_AUX */ > - stb r3, 0(r4) > - > - /* Get the address to jump to in r3*/ > - lis r3, CONFIG_SYS_DIAG_ADDR at h > - ori r3, r3, CONFIG_SYS_DIAG_ADDR at l > - > - /* Load the LR with the branch address */ > - mtlr r3 > - > - /* Branch to diagnostic */ > - blr > - > -diag_done: > -#endif > - > -/* bl l2cache_enable */ > - > - /* run 1st part of board init code (from Flash) */ > - li r3, 0 /* clear boot_flag for calling board_init_f */ > - bl board_init_f > - sync > - > - /* NOTREACHED - board_init_f() does not return */ > - > - .globl invalidate_bats > -invalidate_bats: > - > - li r0, 0 > - /* invalidate BATs */ > - mtspr IBAT0U, r0 > - mtspr IBAT1U, r0 > - mtspr IBAT2U, r0 > - mtspr IBAT3U, r0 > - mtspr IBAT4U, r0 > - mtspr IBAT5U, r0 > - mtspr IBAT6U, r0 > - mtspr IBAT7U, r0 > - > - isync > - mtspr DBAT0U, r0 > - mtspr DBAT1U, r0 > - mtspr DBAT2U, r0 > - mtspr DBAT3U, r0 > - mtspr DBAT4U, r0 > - mtspr DBAT5U, r0 > - mtspr DBAT6U, r0 > - mtspr DBAT7U, r0 > - > - isync > - sync > - blr > - > -#define CONFIG_BAT_PAIR(n) \ > - lis r4, CONFIG_SYS_IBAT##n##L at h; \ > - ori r4, r4, CONFIG_SYS_IBAT##n##L at l; \ > - lis r3, CONFIG_SYS_IBAT##n##U at h; \ > - ori r3, r3, CONFIG_SYS_IBAT##n##U at l; \ > - mtspr IBAT##n##L, r4; \ > - mtspr IBAT##n##U, r3; \ > - lis r4, CONFIG_SYS_DBAT##n##L at h; \ > - ori r4, r4, CONFIG_SYS_DBAT##n##L at l; \ > - lis r3, CONFIG_SYS_DBAT##n##U at h; \ > - ori r3, r3, CONFIG_SYS_DBAT##n##U at l; \ > - mtspr DBAT##n##L, r4; \ > - mtspr DBAT##n##U, r3; > - > -/* > - * setup_bats: > - * > - * Set up the final BAT registers now that setup is done. > - * > - * Assumes that: > - * 1) Address translation is enabled upon entry > - * 2) The boot rom is still accessible via 1:1 translation > - */ > - .globl setup_bats > -setup_bats: > - mflr r5 > - sync > - > - /* > - * When we disable address translation, we will get 1:1 (VA==PA) > - * translation. The only place we know for sure is safe for that is > - * the bootrom where we originally started out. Pop back into there. > - */ > - lis r4, CONFIG_SYS_MONITOR_BASE_EARLY at h > - ori r4, r4, CONFIG_SYS_MONITOR_BASE_EARLY at l > - addi r4, r4, trans_disabled - _start + EXC_OFF_SYS_RESET > - > - /* disable address translation */ > - mfmsr r3 > - rlwinm r3, r3, 0, 28, 25 > - mtspr SRR0, r4 > - mtspr SRR1, r3 > - rfi > - > -trans_disabled: > -#if defined(CONFIG_SYS_DBAT0U) && defined(CONFIG_SYS_DBAT0L) \ > - && defined(CONFIG_SYS_IBAT0U) && defined(CONFIG_SYS_IBAT0L) > - CONFIG_BAT_PAIR(0) > -#endif > - CONFIG_BAT_PAIR(1) > - CONFIG_BAT_PAIR(2) > - CONFIG_BAT_PAIR(3) > - CONFIG_BAT_PAIR(4) > - CONFIG_BAT_PAIR(5) > - CONFIG_BAT_PAIR(6) > - CONFIG_BAT_PAIR(7) > - > - sync > - isync > - > - /* Turn translation back on and return */ > - mfmsr r3 > - ori r3, r3, (MSR_IR | MSR_DR) > - mtspr SPRN_SRR0,r5 > - mtspr SPRN_SRR1,r3 > - rfi > - > -/* > - * early_bats: > - * > - * Set up bats needed early on - this is usually the BAT for the > - * stack-in-cache, the Flash, and CCSR space > - */ > - .globl early_bats > -early_bats: > - /* IBAT 3 */ > - lis r4, CONFIG_SYS_IBAT3L at h > - ori r4, r4, CONFIG_SYS_IBAT3L at l > - lis r3, CONFIG_SYS_IBAT3U at h > - ori r3, r3, CONFIG_SYS_IBAT3U at l > - mtspr IBAT3L, r4 > - mtspr IBAT3U, r3 > - isync > - > - /* DBAT 3 */ > - lis r4, CONFIG_SYS_DBAT3L at h > - ori r4, r4, CONFIG_SYS_DBAT3L at l > - lis r3, CONFIG_SYS_DBAT3U at h > - ori r3, r3, CONFIG_SYS_DBAT3U at l > - mtspr DBAT3L, r4 > - mtspr DBAT3U, r3 > - isync > - > - /* IBAT 5 */ > - lis r4, CONFIG_SYS_IBAT5L at h > - ori r4, r4, CONFIG_SYS_IBAT5L at l > - lis r3, CONFIG_SYS_IBAT5U at h > - ori r3, r3, CONFIG_SYS_IBAT5U at l > - mtspr IBAT5L, r4 > - mtspr IBAT5U, r3 > - isync > - > - /* DBAT 5 */ > - lis r4, CONFIG_SYS_DBAT5L at h > - ori r4, r4, CONFIG_SYS_DBAT5L at l > - lis r3, CONFIG_SYS_DBAT5U at h > - ori r3, r3, CONFIG_SYS_DBAT5U at l > - mtspr DBAT5L, r4 > - mtspr DBAT5U, r3 > - isync > - > - /* IBAT 6 */ > - lis r4, CONFIG_SYS_IBAT6L_EARLY at h > - ori r4, r4, CONFIG_SYS_IBAT6L_EARLY at l > - lis r3, CONFIG_SYS_IBAT6U_EARLY at h > - ori r3, r3, CONFIG_SYS_IBAT6U_EARLY at l > - mtspr IBAT6L, r4 > - mtspr IBAT6U, r3 > - isync > - > - /* DBAT 6 */ > - lis r4, CONFIG_SYS_DBAT6L_EARLY at h > - ori r4, r4, CONFIG_SYS_DBAT6L_EARLY at l > - lis r3, CONFIG_SYS_DBAT6U_EARLY at h > - ori r3, r3, CONFIG_SYS_DBAT6U_EARLY at l > - mtspr DBAT6L, r4 > - mtspr DBAT6U, r3 > - isync > - > -#if(CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) > - /* IBAT 7 */ > - lis r4, CONFIG_SYS_CCSR_DEFAULT_IBATL at h > - ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_IBATL at l > - lis r3, CONFIG_SYS_CCSR_DEFAULT_IBATU at h > - ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_IBATU at l > - mtspr IBAT7L, r4 > - mtspr IBAT7U, r3 > - isync > - > - /* DBAT 7 */ > - lis r4, CONFIG_SYS_CCSR_DEFAULT_DBATL at h > - ori r4, r4, CONFIG_SYS_CCSR_DEFAULT_DBATL at l > - lis r3, CONFIG_SYS_CCSR_DEFAULT_DBATU at h > - ori r3, r3, CONFIG_SYS_CCSR_DEFAULT_DBATU at l > - mtspr DBAT7L, r4 > - mtspr DBAT7U, r3 > - isync > -#endif > - blr > - > - .globl clear_tlbs > -clear_tlbs: > - addis r3, 0, 0x0000 > - addis r5, 0, 0x4 > - isync > -tlblp: > - tlbie r3 > - sync > - addi r3, r3, 0x1000 > - cmp 0, 0, r3, r5 > - blt tlblp > - blr > - > - .globl disable_addr_trans > -disable_addr_trans: > - /* disable address translation */ > - mflr r4 > - mfmsr r3 > - andi. r0, r3, (MSR_IR | MSR_DR) > - beqlr > - andc r3, r3, r0 > - mtspr SRR0, r4 > - mtspr SRR1, r3 > - rfi > - > -/* > - * This code finishes saving the registers to the exception frame > - * and jumps to the appropriate handler for the exception. > - * Register r21 is pointer into trap frame, r1 has new stack pointer. > - */ > - .globl transfer_to_handler > -transfer_to_handler: > - stw r22,_NIP(r21) > - lis r22,MSR_POW at h > - andc r23,r23,r22 > - stw r23,_MSR(r21) > - SAVE_GPR(7, r21) > - SAVE_4GPRS(8, r21) > - SAVE_8GPRS(12, r21) > - SAVE_8GPRS(24, r21) > - mflr r23 > - andi. r24,r23,0x3f00 /* get vector offset */ > - stw r24,TRAP(r21) > - li r22,0 > - stw r22,RESULT(r21) > - mtspr SPRG2,r22 /* r1 is now kernel sp */ > - lwz r24,0(r23) /* virtual address of handler */ > - lwz r23,4(r23) /* where to go when done */ > - mtspr SRR0,r24 > - mtspr SRR1,r20 > - mtlr r23 > - SYNC > - rfi /* jump to handler, enable MMU */ > - > -int_return: > - mfmsr r28 /* Disable interrupts */ > - li r4,0 > - ori r4,r4,MSR_EE > - andc r28,r28,r4 > - SYNC /* Some chip revs need this... */ > - mtmsr r28 > - SYNC > - lwz r2,_CTR(r1) > - lwz r0,_LINK(r1) > - mtctr r2 > - mtlr r0 > - lwz r2,_XER(r1) > - lwz r0,_CCR(r1) > - mtspr XER,r2 > - mtcrf 0xFF,r0 > - REST_10GPRS(3, r1) > - REST_10GPRS(13, r1) > - REST_8GPRS(23, r1) > - REST_GPR(31, r1) > - lwz r2,_NIP(r1) /* Restore environment */ > - lwz r0,_MSR(r1) > - mtspr SRR0,r2 > - mtspr SRR1,r0 > - lwz r0,GPR0(r1) > - lwz r2,GPR2(r1) > - lwz r1,GPR1(r1) > - SYNC > - rfi > - > - .globl dc_read > -dc_read: > - blr > - > - > -/* > - * Function: in8 > - * Description: Input 8 bits > - */ > - .globl in8 > -in8: > - lbz r3,0x0000(r3) > - blr > - > -/* > - * Function: out8 > - * Description: Output 8 bits > - */ > - .globl out8 > -out8: > - stb r4,0x0000(r3) > - blr > - > -/* > - * Function: out16 > - * Description: Output 16 bits > - */ > - .globl out16 > -out16: > - sth r4,0x0000(r3) > - blr > - > -/* > - * Function: out16r > - * Description: Byte reverse and output 16 bits > - */ > - .globl out16r > -out16r: > - sthbrx r4,r0,r3 > - blr > - > -/* > - * Function: out32 > - * Description: Output 32 bits > - */ > - .globl out32 > -out32: > - stw r4,0x0000(r3) > - blr > - > -/* > - * Function: out32r > - * Description: Byte reverse and output 32 bits > - */ > - .globl out32r > -out32r: > - stwbrx r4,r0,r3 > - blr > - > -/* > - * Function: in16 > - * Description: Input 16 bits > - */ > - .globl in16 > -in16: > - lhz r3,0x0000(r3) > - blr > - > -/* > - * Function: in16r > - * Description: Input 16 bits and byte reverse > - */ > - .globl in16r > -in16r: > - lhbrx r3,r0,r3 > - blr > - > -/* > - * Function: in32 > - * Description: Input 32 bits > - */ > - .globl in32 > -in32: > - lwz 3,0x0000(3) > - blr > - > -/* > - * Function: in32r > - * Description: Input 32 bits and byte reverse > - */ > - .globl in32r > -in32r: > - lwbrx r3,r0,r3 > - blr > - > -/* > - * void relocate_code(addr_sp, gd, addr_moni) > - * > - * This "function" does not return, instead it continues in RAM > - * after relocating the monitor code. > - * > - * r3 = dest > - * r4 = src > - * r5 = length in bytes > - * r6 = cachelinesize > - */ > - .globl relocate_code > -relocate_code: > - > - mr r1, r3 /* Set new stack pointer */ > - mr r9, r4 /* Save copy of Global Data pointer */ > - mr r10, r5 /* Save copy of Destination Address */ > - > - GET_GOT > - mr r3, r5 /* Destination Address */ > - lis r4, CONFIG_SYS_MONITOR_BASE at h /* Source Address */ > - ori r4, r4, CONFIG_SYS_MONITOR_BASE at l > - lwz r5, GOT(__init_end) > - sub r5, r5, r4 > - li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */ > - > - /* > - * Fix GOT pointer: > - * > - * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address > - * > - * Offset: > - */ > - sub r15, r10, r4 > - > - /* First our own GOT */ > - add r12, r12, r15 > - /* then the one used by the C code */ > - add r30, r30, r15 > - > - /* > - * Now relocate code > - */ > - cmplw cr1,r3,r4 > - addi r0,r5,3 > - srwi. r0,r0,2 > - beq cr1,4f /* In place copy is not necessary */ > - beq 7f /* Protect against 0 count */ > - mtctr r0 > - bge cr1,2f > - > - la r8,-4(r4) > - la r7,-4(r3) > -1: lwzu r0,4(r8) > - stwu r0,4(r7) > - bdnz 1b > - b 4f > - > -2: slwi r0,r0,2 > - add r8,r4,r0 > - add r7,r3,r0 > -3: lwzu r0,-4(r8) > - stwu r0,-4(r7) > - bdnz 3b > -/* > - * Now flush the cache: note that we must start from a cache aligned > - * address. Otherwise we might miss one cache line. > - */ > -4: cmpwi r6,0 > - add r5,r3,r5 > - beq 7f /* Always flush prefetch queue in any case */ > - subi r0,r6,1 > - andc r3,r3,r0 > - mr r4,r3 > -5: dcbst 0,r4 > - add r4,r4,r6 > - cmplw r4,r5 > - blt 5b > - sync /* Wait for all dcbst to complete on bus */ > - mr r4,r3 > -6: icbi 0,r4 > - add r4,r4,r6 > - cmplw r4,r5 > - blt 6b > -7: sync /* Wait for all icbi to complete on bus */ > - isync > - > -/* > - * We are done. Do not return, instead branch to second part of board > - * initialization, now running from RAM. > - */ > - addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET > - mtlr r0 > - blr > - > -in_ram: > - /* > - * Relocation Function, r12 point to got2+0x8000 > - * > - * Adjust got2 pointers, no need to check for 0, this code > - * already puts a few entries in the table. > - */ > - li r0,__got2_entries at sectoff@l > - la r3,GOT(_GOT2_TABLE_) > - lwz r11,GOT(_GOT2_TABLE_) > - mtctr r0 > - sub r11,r3,r11 > - addi r3,r3,-4 > -1: lwzu r0,4(r3) > - cmpwi r0,0 > - beq- 2f > - add r0,r0,r11 > - stw r0,0(r3) > -2: bdnz 1b > - > - /* > - * Now adjust the fixups and the pointers to the fixups > - * in case we need to move ourselves again. > - */ > - li r0,__fixup_entries at sectoff@l > - lwz r3,GOT(_FIXUP_TABLE_) > - cmpwi r0,0 > - mtctr r0 > - addi r3,r3,-4 > - beq 4f > -3: lwzu r4,4(r3) > - lwzux r0,r4,r11 > - cmpwi r0,0 > - add r0,r0,r11 > - stw r4,0(r3) > - beq- 5f > - stw r0,0(r4) > -5: bdnz 3b > -4: > -/* clear_bss: */ > - /* > - * Now clear BSS segment > - */ > - lwz r3,GOT(__bss_start) > - lwz r4,GOT(__bss_end) > - > - cmplw 0, r3, r4 > - beq 6f > - > - li r0, 0 > -5: > - stw r0, 0(r3) > - addi r3, r3, 4 > - cmplw 0, r3, r4 > - bne 5b > -6: > - mr r3, r9 /* Init Date pointer */ > - mr r4, r10 /* Destination Address */ > - bl board_init_r > - > - /* not reached - end relocate_code */ > -/*-----------------------------------------------------------------------*/ > - > - /* > - * Copy exception vector code to low memory > - * > - * r3: dest_addr > - * r7: source address, r8: end address, r9: target address > - */ > - .globl trap_init > -trap_init: > - mflr r4 /* save link register */ > - GET_GOT > - lwz r7, GOT(_start) > - lwz r8, GOT(_end_of_vectors) > - > - li r9, 0x100 /* reset vector always at 0x100 */ > - > - cmplw 0, r7, r8 > - bgelr /* return if r7>=r8 - just in case */ > -1: > - lwz r0, 0(r7) > - stw r0, 0(r9) > - addi r7, r7, 4 > - addi r9, r9, 4 > - cmplw 0, r7, r8 > - bne 1b > - > - /* > - * relocate `hdlr' and `int_return' entries > - */ > - li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET > - li r8, Alignment - _start + EXC_OFF_SYS_RESET > -2: > - bl trap_reloc > - addi r7, r7, 0x100 /* next exception vector */ > - cmplw 0, r7, r8 > - blt 2b > - > - li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET > - bl trap_reloc > - > - li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET > - bl trap_reloc > - > - li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET > - li r8, SystemCall - _start + EXC_OFF_SYS_RESET > -3: > - bl trap_reloc > - addi r7, r7, 0x100 /* next exception vector */ > - cmplw 0, r7, r8 > - blt 3b > - > - li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET > - li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET > -4: > - bl trap_reloc > - addi r7, r7, 0x100 /* next exception vector */ > - cmplw 0, r7, r8 > - blt 4b > - > - /* enable execptions from RAM vectors */ > - mfmsr r7 > - li r8,MSR_IP > - andc r7,r7,r8 > - ori r7,r7,MSR_ME /* Enable Machine Check */ > - mtmsr r7 > - > - mtlr r4 /* restore link register */ > - blr > - > -.globl enable_ext_addr > -enable_ext_addr: > - mfspr r0, HID0 > - lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h > - ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l > - mtspr HID0, r0 > - sync > - isync > - blr > - > -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) > -.globl setup_ccsrbar > -setup_ccsrbar: > - /* Special sequence needed to update CCSRBAR itself */ > - lis r4, CONFIG_SYS_CCSRBAR_DEFAULT at h > - ori r4, r4, CONFIG_SYS_CCSRBAR_DEFAULT at l > - > - lis r5, CONFIG_SYS_CCSRBAR_PHYS_LOW at h > - ori r5, r5, CONFIG_SYS_CCSRBAR_PHYS_LOW at l > - srwi r5,r5,12 > - li r6, CONFIG_SYS_CCSRBAR_PHYS_HIGH at l > - rlwimi r5,r6,20,8,11 > - stw r5, 0(r4) /* Store physical value of CCSR */ > - isync > - > - lis r5, CONFIG_SYS_TEXT_BASE at h > - ori r5,r5,CONFIG_SYS_TEXT_BASE at l > - lwz r5, 0(r5) > - isync > - > - /* Use VA of CCSR to do read */ > - lis r3, CONFIG_SYS_CCSRBAR at h > - lwz r5, CONFIG_SYS_CCSRBAR at l(r3) > - isync > - > - blr > -#endif > - > -#ifdef CONFIG_SYS_INIT_RAM_LOCK > -lock_ram_in_cache: > - /* Allocate Initial RAM in data cache. > - */ > - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h > - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l > - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ > - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 > - mtctr r4 > -1: > - dcbz r0, r3 > - addi r3, r3, 32 > - bdnz 1b > -#if 1 > -/* Lock the data cache */ > - mfspr r0, HID0 > - ori r0, r0, 0x1000 > - sync > - mtspr HID0, r0 > - sync > - blr > -#endif > -#if 0 > - /* Lock the first way of the data cache */ > - mfspr r0, LDSTCR > - ori r0, r0, 0x0080 > -#if defined(CONFIG_ALTIVEC) > - dssall > -#endif > - sync > - mtspr LDSTCR, r0 > - sync > - isync > - blr > -#endif > - > -.globl unlock_ram_in_cache > -unlock_ram_in_cache: > - /* invalidate the INIT_RAM section */ > - lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h > - ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l > - li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \ > - (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32 > - mtctr r4 > -1: icbi r0, r3 > - addi r3, r3, 32 > - bdnz 1b > - sync /* Wait for all icbi to complete on bus */ > - isync > -#if 1 > -/* Unlock the data cache and invalidate it */ > - mfspr r0, HID0 > - li r3,0x1000 > - andc r0,r0,r3 > - li r3,0x0400 > - or r0,r0,r3 > - sync > - mtspr HID0, r0 > - sync > - blr > -#endif > -#if 0 > - /* Unlock the first way of the data cache */ > - mfspr r0, LDSTCR > - li r3,0x0080 > - andc r0,r0,r3 > -#ifdef CONFIG_ALTIVEC > - dssall > -#endif > - sync > - mtspr LDSTCR, r0 > - sync > - isync > - li r3,0x0400 > - or r0,r0,r3 > - sync > - mtspr HID0, r0 > - sync > - blr > -#endif > -#endif > diff --git a/arch/powerpc/cpu/mpc86xx/traps.c b/arch/powerpc/cpu/mpc86xx/traps.c > deleted file mode 100644 > index 46006ece4160..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/traps.c > +++ /dev/null > @@ -1,199 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0+ > -/* > - * Copyright (C) 1995-1996 Gary Thomas (gdt at linuxppc.org) > - * > - * Modified by Cort Dougan (cort at cs.nmt.edu) > - * and Paul Mackerras (paulus at cs.anu.edu.au) > - * > - * (C) Copyright 2000 > - * Wolfgang Denk, DENX Software Engineering, wd at denx.de. > - */ > - > -/* > - * This file handles the architecture-dependent parts of hardware exceptions > - */ > - > -#include > -#include > -#include > -#include > -#include > -#include > -#include > - > -DECLARE_GLOBAL_DATA_PTR; > - > -/* Returns 0 if exception not found and fixup otherwise. */ > -extern unsigned long search_exception_table(unsigned long); > - > -/* > - * End of addressable memory. This may be less than the actual > - * amount of memory on the system if we're unable to keep all > - * the memory mapped in. > - */ > -#define END_OF_MEM (gd->ram_base + get_effective_memsize()) > - > -/* > - * Trap & Exception support > - */ > - > -static void print_backtrace(unsigned long *sp) > -{ > - int cnt = 0; > - unsigned long i; > - > - printf("Call backtrace: "); > - while (sp) { > - if ((uint) sp > END_OF_MEM) > - break; > - > - i = sp[1]; > - if (cnt++ % 7 == 0) > - printf("\n"); > - printf("%08lX ", i); > - if (cnt > 32) > - break; > - sp = (unsigned long *)*sp; > - } > - printf("\n"); > -} > - > -void show_regs(struct pt_regs *regs) > -{ > - int i; > - > - printf("NIP: %08lX XER: %08lX LR: %08lX REGS:" > - " %p TRAP: %04lx DAR: %08lX\n", > - regs->nip, regs->xer, regs->link, regs, regs->trap, regs->dar); > - printf("MSR: %08lx EE: %01x PR: %01x FP:" > - " %01x ME: %01x IR/DR: %01x%01x\n", > - regs->msr, regs->msr & MSR_EE ? 1 : 0, > - regs->msr & MSR_PR ? 1 : 0, regs->msr & MSR_FP ? 1 : 0, > - regs->msr & MSR_ME ? 1 : 0, regs->msr & MSR_IR ? 1 : 0, > - regs->msr & MSR_DR ? 1 : 0); > - > - printf("\n"); > - for (i = 0; i < 32; i++) { > - if ((i % 8) == 0) { > - printf("GPR%02d: ", i); > - } > - > - printf("%08lX ", regs->gpr[i]); > - if ((i % 8) == 7) { > - printf("\n"); > - } > - } > -} > - > - > -static void _exception(int signr, struct pt_regs *regs) > -{ > - show_regs(regs); > - print_backtrace((unsigned long *)regs->gpr[1]); > - panic("Exception in kernel pc %lx signal %d", regs->nip, signr); > -} > - > -void MachineCheckException(struct pt_regs *regs) > -{ > - unsigned long fixup; > - > - /* Probing PCI using config cycles cause this exception > - * when a device is not present. Catch it and return to > - * the PCI exception handler. > - */ > - if ((fixup = search_exception_table(regs->nip)) != 0) { > - regs->nip = fixup; > - return; > - } > - > -#if defined(CONFIG_CMD_KGDB) > - if (debugger_exception_handler && (*debugger_exception_handler) (regs)) > - return; > -#endif > - > - printf("Machine check in kernel mode.\n"); > - printf("Caused by (from msr): "); > - printf("regs %p ", regs); > - switch ( regs->msr & 0x001F0000) { > - case (0x80000000>>11): > - printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0)); > - break; > - case (0x80000000>>12): > - printf("Machine check signal - probably due to mm fault\n" > - "with mmu off\n"); > - break; > - case (0x80000000 >> 13): > - printf("Transfer error ack signal\n"); > - break; > - case (0x80000000 >> 14): > - printf("Data parity signal\n"); > - break; > - case (0x80000000 >> 15): > - printf("Address parity signal\n"); > - break; > - default: > - printf("Unknown values in msr\n"); > - } > - show_regs(regs); > - print_backtrace((unsigned long *)regs->gpr[1]); > - panic("machine check"); > -} > - > -void AlignmentException(struct pt_regs *regs) > -{ > -#if defined(CONFIG_CMD_KGDB) > - if (debugger_exception_handler && (*debugger_exception_handler) (regs)) > - return; > -#endif > - show_regs(regs); > - print_backtrace((unsigned long *)regs->gpr[1]); > - panic("Alignment Exception"); > -} > - > -void ProgramCheckException(struct pt_regs *regs) > -{ > - unsigned char *p = regs ? (unsigned char *)(regs->nip) : NULL; > - int i, j; > - > -#if defined(CONFIG_CMD_KGDB) > - if (debugger_exception_handler && (*debugger_exception_handler) (regs)) > - return; > -#endif > - show_regs(regs); > - > - p = (unsigned char *)((unsigned long)p & 0xFFFFFFE0); > - p -= 32; > - for (i = 0; i < 256; i += 16) { > - printf("%08x: ", (unsigned int)p + i); > - for (j = 0; j < 16; j++) { > - printf("%02x ", p[i + j]); > - } > - printf("\n"); > - } > - > - print_backtrace((unsigned long *)regs->gpr[1]); > - panic("Program Check Exception"); > -} > - > -void SoftEmuException(struct pt_regs *regs) > -{ > -#if defined(CONFIG_CMD_KGDB) > - if (debugger_exception_handler && (*debugger_exception_handler) (regs)) > - return; > -#endif > - show_regs(regs); > - print_backtrace((unsigned long *)regs->gpr[1]); > - panic("Software Emulation Exception"); > -} > - > -void UnknownException(struct pt_regs *regs) > -{ > -#if defined(CONFIG_CMD_KGDB) > - if (debugger_exception_handler && (*debugger_exception_handler) (regs)) > - return; > -#endif > - printf("UnknownException regs@%lx\n", (ulong)regs); > - printf("Bad trap at PC: %lx, SR: %lx, vector=%lx\n", > - regs->nip, regs->msr, regs->trap); > - _exception(0, regs); > -} > diff --git a/arch/powerpc/cpu/mpc86xx/u-boot.lds b/arch/powerpc/cpu/mpc86xx/u-boot.lds > deleted file mode 100644 > index 94f07c6b7dd2..000000000000 > --- a/arch/powerpc/cpu/mpc86xx/u-boot.lds > +++ /dev/null > @@ -1,77 +0,0 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > -/* > - * Copyright 2006, 2007 Freescale Semiconductor, Inc. > - */ > - > -OUTPUT_ARCH(powerpc) > - > -SECTIONS > -{ > - > - /* Read-only sections, merged into text segment: */ > - .text : > - { > - arch/powerpc/cpu/mpc86xx/start.o (.text*) > - arch/powerpc/cpu/mpc86xx/traps.o (.text*) > - *(.text*) > - } > - _etext = .; > - PROVIDE (etext = .); > - .rodata : > - { > - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) > - } > - > - /* Read-write section, merged into data segment: */ > - . = (. + 0x00FF) & 0xFFFFFF00; > - _erotext = .; > - PROVIDE (erotext = .); > - .reloc : > - { > - _GOT2_TABLE_ = .; > - KEEP(*(.got2)) > - KEEP(*(.got)) > - _FIXUP_TABLE_ = .; > - KEEP(*(.fixup)) > - } > - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; > - __fixup_entries = (. - _FIXUP_TABLE_) >> 2; > - > - .data : > - { > - *(.data*) > - *(.sdata*) > - } > - _edata = .; > - PROVIDE (edata = .); > - > - . = .; > - > - . = ALIGN(4); > - .u_boot_list : { > - KEEP(*(SORT(.u_boot_list*))); > - } > - > - . = .; > - __start___ex_table = .; > - __ex_table : { *(__ex_table) } > - __stop___ex_table = .; > - > - . = ALIGN(256); > - __init_begin = .; > - .text.init : { *(.text.init) } > - .data.init : { *(.data.init) } > - . = ALIGN(256); > - __init_end = .; > - > - __bss_start = .; > - .bss (NOLOAD) : > - { > - *(.bss*) > - *(.sbss*) > - *(COMMON) > - . = ALIGN(4); > - } > - __bss_end = . ; > - PROVIDE (end = .); > -} > diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h > index 99b410dc9b09..2c96378efef8 100644 > --- a/arch/powerpc/include/asm/config.h > +++ b/arch/powerpc/include/asm/config.h > @@ -10,10 +10,6 @@ > #include > #endif > > -#ifdef CONFIG_MPC86xx > -#include > -#endif > - > #ifndef HWCONFIG_BUFFER_SIZE > #define HWCONFIG_BUFFER_SIZE 256 > #endif > diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h > deleted file mode 100644 > index f19ff7a6a128..000000000000 > --- a/arch/powerpc/include/asm/config_mpc86xx.h > +++ /dev/null > @@ -1,9 +0,0 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > -/* > - * Copyright 2011 Freescale Semiconductor, Inc. > - */ > - > -#ifndef _ASM_MPC86xx_CONFIG_H_ > -#define _ASM_MPC86xx_CONFIG_H_ > - > -#endif /* _ASM_MPC85xx_CONFIG_H_ */ > diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h > index 77cdc80fdcd0..39fbc04e4744 100644 > --- a/arch/powerpc/include/asm/fsl_law.h > +++ b/arch/powerpc/include/asm/fsl_law.h > @@ -78,9 +78,6 @@ enum law_trgt_if { > enum law_trgt_if { > LAW_TRGT_IF_PCI = 0x00, > LAW_TRGT_IF_PCI_2 = 0x01, > -#ifndef CONFIG_ARCH_MPC8641 > - LAW_TRGT_IF_PCIE_1 = 0x02, > -#endif > #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132) > LAW_TRGT_IF_OCN_DSP = 0x03, > #else > @@ -116,10 +113,6 @@ enum law_trgt_if { > #define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO > #define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC > > -#ifdef CONFIG_ARCH_MPC8641 > -#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI > -#endif > - > #if defined(CONFIG_ARCH_P2020) > #define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI > #endif > diff --git a/arch/powerpc/include/asm/fsl_pci.h b/arch/powerpc/include/asm/fsl_pci.h > index 508834829b95..06f9bfb8ac73 100644 > --- a/arch/powerpc/include/asm/fsl_pci.h > +++ b/arch/powerpc/include/asm/fsl_pci.h > @@ -30,7 +30,7 @@ void fsl_pci_config_unlock(struct pci_controller *hose); > void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr); > > /* > - * Common PCI/PCIE Register structure for mpc85xx and mpc86xx > + * Common PCI/PCIE Register structure for mpc85xx > */ > > /* > diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h > deleted file mode 100644 > index 1fbc63a5ceb8..000000000000 > --- a/arch/powerpc/include/asm/immap_86xx.h > +++ /dev/null > @@ -1,1221 +0,0 @@ > -/* > - * MPC86xx Internal Memory Map > - * > - * Copyright 2004, 2011 Freescale Semiconductor > - * Jeff Brown (Jeffrey at freescale.com) > - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com) > - * > - */ > - > -#ifndef __IMMAP_86xx__ > -#define __IMMAP_86xx__ > - > -#include > -#include > -#include > -#include > -#include > - > -/* Local-Access Registers and MCM Registers(0x0000-0x2000) */ > -typedef struct ccsr_local_mcm { > - uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ > - char res1[4]; > - uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */ > - char res2[4]; > - uint altcar; /* 0x10 - Alternate Configuration Attribute Register */ > - char res3[12]; > - uint bptr; /* 0x20 - Boot Page Translation Register */ > - char res4[3044]; > - uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */ > - char res5[4]; > - uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */ > - char res6[20]; > - uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */ > - char res7[4]; > - uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */ > - char res8[20]; > - uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */ > - char res9[4]; > - uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */ > - char res10[20]; > - uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */ > - char res11[4]; > - uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */ > - char res12[20]; > - uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */ > - char res13[4]; > - uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */ > - char res14[20]; > - uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */ > - char res15[4]; > - uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */ > - char res16[20]; > - uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */ > - char res17[4]; > - uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */ > - char res18[20]; > - uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ > - char res19[4]; > - uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ > - char res20[20]; > - uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ > - char res21[4]; > - uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ > - char res22[20]; > - uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ > - char res23[4]; > - uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ > - char res24[716]; > - uint abcr; /* 0x1000 - MCM CCB Address Configuration Register */ > - char res25[4]; > - uint dbcr; /* 0x1008 - MCM MPX data bus Configuration Register */ > - char res26[4]; > - uint pcr; /* 0x1010 - MCM CCB Port Configuration Register */ > - char res27[44]; > - uint hpmr0; /* 0x1040 - MCM HPM Threshold Count Register 0 */ > - uint hpmr1; /* 0x1044 - MCM HPM Threshold Count Register 1 */ > - uint hpmr2; /* 0x1048 - MCM HPM Threshold Count Register 2 */ > - uint hpmr3; /* 0x104c - MCM HPM Threshold Count Register 3 */ > - char res28[16]; > - uint hpmr4; /* 0x1060 - MCM HPM Threshold Count Register 4 */ > - uint hpmr5; /* 0x1064 - MCM HPM Threshold Count Register 5 */ > - uint hpmccr; /* 0x1068 - MCM HPM Cycle Count Register */ > - char res29[3476]; > - uint edr; /* 0x1e00 - MCM Error Detect Register */ > - char res30[4]; > - uint eer; /* 0x1e08 - MCM Error Enable Register */ > - uint eatr; /* 0x1e0c - MCM Error Attributes Capture Register */ > - uint eladr; /* 0x1e10 - MCM Error Low Address Capture Register */ > - uint ehadr; /* 0x1e14 - MCM Error High Address Capture Register */ > - char res31[488]; > -} ccsr_local_mcm_t; > - > -/* Daul I2C Registers(0x3000-0x4000) */ > -typedef struct ccsr_i2c { > - struct fsl_i2c_base i2c[2]; > - u8 res[4096 - 2 * sizeof(struct fsl_i2c_base)]; > -} ccsr_i2c_t; > - > -/* DUART Registers(0x4000-0x5000) */ > -typedef struct ccsr_duart { > - char res1[1280]; > - u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */ > - u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */ > - u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */ > - u_char ulcr1; /* 0x4503 - UART1 Line Control Register */ > - u_char umcr1; /* 0x4504 - UART1 Modem Control Register */ > - u_char ulsr1; /* 0x4505 - UART1 Line Status Register */ > - u_char umsr1; /* 0x4506 - UART1 Modem Status Register */ > - u_char uscr1; /* 0x4507 - UART1 Scratch Register */ > - char res2[8]; > - u_char udsr1; /* 0x4510 - UART1 DMA Status Register */ > - char res3[239]; > - u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */ > - u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */ > - u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */ > - u_char ulcr2; /* 0x4603 - UART2 Line Control Register */ > - u_char umcr2; /* 0x4604 - UART2 Modem Control Register */ > - u_char ulsr2; /* 0x4605 - UART2 Line Status Register */ > - u_char umsr2; /* 0x4606 - UART2 Modem Status Register */ > - u_char uscr2; /* 0x4607 - UART2 Scratch Register */ > - char res4[8]; > - u_char udsr2; /* 0x4610 - UART2 DMA Status Register */ > - char res5[2543]; > -} ccsr_duart_t; > - > -/* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */ > -typedef struct ccsr_pex { > - uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */ > - uint cfg_data; /* 0x8004 - PEX Configuration Data Register */ > - char res1[4]; > - uint out_comp_to; /* 0x800C - PEX Outbound Completion Timeout Register */ > - char res2[16]; > - uint pme_msg_det; /* 0x8020 - PEX PME & message detect register */ > - uint pme_msg_int_en; /* 0x8024 - PEX PME & message interrupt enable register */ > - uint pme_msg_dis; /* 0x8028 - PEX PME & message disable register */ > - uint pm_command; /* 0x802c - PEX PM Command register */ > - char res3[3016]; > - uint block_rev1; /* 0x8bf8 - PEX Block Revision register 1 */ > - uint block_rev2; /* 0x8bfc - PEX Block Revision register 2 */ > - uint potar0; /* 0x8c00 - PEX Outbound Transaction Address Register 0 */ > - uint potear0; /* 0x8c04 - PEX Outbound Translation Extended Address Register 0 */ > - char res4[8]; > - uint powar0; /* 0x8c10 - PEX Outbound Window Attributes Register 0 */ > - char res5[12]; > - uint potar1; /* 0x8c20 - PEX Outbound Transaction Address Register 1 */ > - uint potear1; /* 0x8c24 - PEX Outbound Translation Extended Address Register 1 */ > - uint powbar1; /* 0x8c28 - PEX Outbound Window Base Address Register 1 */ > - char res6[4]; > - uint powar1; /* 0x8c30 - PEX Outbound Window Attributes Register 1 */ > - char res7[12]; > - uint potar2; /* 0x8c40 - PEX Outbound Transaction Address Register 2 */ > - uint potear2; /* 0x8c44 - PEX Outbound Translation Extended Address Register 2 */ > - uint powbar2; /* 0x8c48 - PEX Outbound Window Base Address Register 2 */ > - char res8[4]; > - uint powar2; /* 0x8c50 - PEX Outbound Window Attributes Register 2 */ > - char res9[12]; > - uint potar3; /* 0x8c60 - PEX Outbound Transaction Address Register 3 */ > - uint potear3; /* 0x8c64 - PEX Outbound Translation Extended Address Register 3 */ > - uint powbar3; /* 0x8c68 - PEX Outbound Window Base Address Register 3 */ > - char res10[4]; > - uint powar3; /* 0x8c70 - PEX Outbound Window Attributes Register 3 */ > - char res11[12]; > - uint potar4; /* 0x8c80 - PEX Outbound Transaction Address Register 4 */ > - uint potear4; /* 0x8c84 - PEX Outbound Translation Extended Address Register 4 */ > - uint powbar4; /* 0x8c88 - PEX Outbound Window Base Address Register 4 */ > - char res12[4]; > - uint powar4; /* 0x8c90 - PEX Outbound Window Attributes Register 4 */ > - char res13[12]; > - char res14[256]; > - uint pitar3; /* 0x8da0 - PEX Inbound Translation Address Register 3 */ > - char res15[4]; > - uint piwbar3; /* 0x8da8 - PEX Inbound Window Base Address Register 3 */ > - uint piwbear3; /* 0x8dac - PEX Inbound Window Base Extended Address Register 3 */ > - uint piwar3; /* 0x8db0 - PEX Inbound Window Attributes Register 3 */ > - char res16[12]; > - uint pitar2; /* 0x8dc0 - PEX Inbound Translation Address Register 2 */ > - char res17[4]; > - uint piwbar2; /* 0x8dc8 - PEX Inbound Window Base Address Register 2 */ > - uint piwbear2; /* 0x8dcc - PEX Inbound Window Base Extended Address Register 2 */ > - uint piwar2; /* 0x8dd0 - PEX Inbound Window Attributes Register 2 */ > - char res18[12]; > - uint pitar1; /* 0x8de0 - PEX Inbound Translation Address Register 1 */ > - char res19[4]; > - uint piwbar1; /* 0x8de8 - PEX Inbound Window Base Address Register 1 */ > - uint piwbear1; > - uint piwar1; /* 0x8df0 - PEX Inbound Window Attributes Register 1 */ > - char res20[12]; > - uint pedr; /* 0x8e00 - PEX Error Detect Register */ > - char res21[4]; > - uint peer; /* 0x8e08 - PEX Error Interrupt Enable Register */ > - char res22[4]; > - uint pecdr; /* 0x8e10 - PEX Error Disable Register */ > - char res23[12]; > - uint peer_stat; /* 0x8e20 - PEX Error Capture Status Register */ > - char res24[4]; > - uint perr_cap0; /* 0x8e28 - PEX Error Capture Register 0 */ > - uint perr_cap1; /* 0x8e2c - PEX Error Capture Register 1 */ > - uint perr_cap2; /* 0x8e30 - PEX Error Capture Register 2 */ > - uint perr_cap3; /* 0x8e34 - PEX Error Capture Register 3 */ > - char res25[452]; > - char res26[4]; > -} ccsr_pex_t; > - > -/* Hyper Transport Register Block (0xA000-0xB000) */ > -typedef struct ccsr_ht { > - uint hcfg_addr; /* 0xa000 - HT Configuration Address register */ > - uint hcfg_data; /* 0xa004 - HT Configuration Data register */ > - char res1[3064]; > - uint howtar0; /* 0xac00 - HT Outbound Window 0 Translation register */ > - char res2[12]; > - uint howar0; /* 0xac10 - HT Outbound Window 0 Attributes register */ > - char res3[12]; > - uint howtar1; /* 0xac20 - HT Outbound Window 1 Translation register */ > - char res4[4]; > - uint howbar1; /* 0xac28 - HT Outbound Window 1 Base Address register */ > - char res5[4]; > - uint howar1; /* 0xac30 - HT Outbound Window 1 Attributes register */ > - char res6[12]; > - uint howtar2; /* 0xac40 - HT Outbound Window 2 Translation register */ > - char res7[4]; > - uint howbar2; /* 0xac48 - HT Outbound Window 2 Base Address register */ > - char res8[4]; > - uint howar2; /* 0xac50 - HT Outbound Window 2 Attributes register */ > - char res9[12]; > - uint howtar3; /* 0xac60 - HT Outbound Window 3 Translation register */ > - char res10[4]; > - uint howbar3; /* 0xac68 - HT Outbound Window 3 Base Address register */ > - char res11[4]; > - uint howar3; /* 0xac70 - HT Outbound Window 3 Attributes register */ > - char res12[12]; > - uint howtar4; /* 0xac80 - HT Outbound Window 4 Translation register */ > - char res13[4]; > - uint howbar4; /* 0xac88 - HT Outbound Window 4 Base Address register */ > - char res14[4]; > - uint howar4; /* 0xac90 - HT Outbound Window 4 Attributes register */ > - char res15[236]; > - uint hiwtar4; /* 0xad80 - HT Inbound Window 4 Translation register */ > - char res16[4]; > - uint hiwbar4; /* 0xad88 - HT Inbound Window 4 Base Address register */ > - char res17[4]; > - uint hiwar4; /* 0xad90 - HT Inbound Window 4 Attributes register */ > - char res18[12]; > - uint hiwtar3; /* 0xada0 - HT Inbound Window 3 Translation register */ > - char res19[4]; > - uint hiwbar3; /* 0xada8 - HT Inbound Window 3 Base Address register */ > - char res20[4]; > - uint hiwar3; /* 0xadb0 - HT Inbound Window 3 Attributes register */ > - char res21[12]; > - uint hiwtar2; /* 0xadc0 - HT Inbound Window 2 Translation register */ > - char res22[4]; > - uint hiwbar2; /* 0xadc8 - HT Inbound Window 2 Base Address register */ > - char res23[4]; > - uint hiwar2; /* 0xadd0 - HT Inbound Window 2 Attributes register */ > - char res24[12]; > - uint hiwtar1; /* 0xade0 - HT Inbound Window 1 Translation register */ > - char res25[4]; > - uint hiwbar1; /* 0xade8 - HT Inbound Window 1 Base Address register */ > - char res26[4]; > - uint hiwar1; /* 0xadf0 - HT Inbound Window 1 Attributes register */ > - char res27[12]; > - uint hedr; /* 0xae00 - HT Error Detect register */ > - char res28[4]; > - uint heier; /* 0xae08 - HT Error Interrupt Enable register */ > - char res29[4]; > - uint hecdr; /* 0xae10 - HT Error Capture Disbale register */ > - char res30[12]; > - uint hecsr; /* 0xae20 - HT Error Capture Status register */ > - char res31[4]; > - uint hec0; /* 0xae28 - HT Error Capture 0 register */ > - uint hec1; /* 0xae2c - HT Error Capture 1 register */ > - uint hec2; /* 0xae30 - HT Error Capture 2 register */ > - char res32[460]; > -} ccsr_ht_t; > - > -/* DMA Registers(0x2_1000-0x2_2000) */ > -typedef struct ccsr_dma { > - char res1[256]; > - struct fsl_dma dma[4]; > - uint dgsr; /* 0x21300 - DMA General Status Register */ > - char res2[3324]; > -} ccsr_dma_t; > - > -/* tsec1-4: 24000-28000 */ > -typedef struct ccsr_tsec { > - uint id; /* 0x24000 - Controller ID Register */ > - char res1[12]; > - uint ievent; /* 0x24010 - Interrupt Event Register */ > - uint imask; /* 0x24014 - Interrupt Mask Register */ > - uint edis; /* 0x24018 - Error Disabled Register */ > - char res2[4]; > - uint ecntrl; /* 0x24020 - Ethernet Control Register */ > - char res2_1[4]; > - uint ptv; /* 0x24028 - Pause Time Value Register */ > - uint dmactrl; /* 0x2402c - DMA Control Register */ > - uint tbipa; /* 0x24030 - TBI PHY Address Register */ > - char res3[88]; > - uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */ > - char res4[8]; > - uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ > - uint fifo_tx_starve_shutoff;/* 0x2409c - FIFO transmit starve shutoff register */ > - char res4_1[4]; > - uint fifo_rx_pause; /* 0x240a4 - FIFO receive pause threshold register */ > - uint fifo_rx_alarm; /* 0x240a8 - FIFO receive alarm threshold register */ > - char res5[84]; > - uint tctrl; /* 0x24100 - Transmit Control Register */ > - uint tstat; /* 0x24104 - Transmit Status Register */ > - uint dfvlan; /* 0x24108 - Default VLAN control word */ > - char res6[4]; > - uint txic; /* 0x24110 - Transmit interrupt coalescing Register */ > - uint tqueue; /* 0x24114 - Transmit Queue Control Register */ > - char res7[40]; > - uint tr03wt; /* 0x24140 - TxBD Rings 0-3 round-robin weightings */ > - uint tw47wt; /* 0x24144 - TxBD Rings 4-7 round-robin weightings */ > - char res8[52]; > - uint tbdbph; /* 0x2417c - Transmit Data Buffer Pointer High Register */ > - char res9[4]; > - uint tbptr0; /* 0x24184 - Transmit Buffer Descriptor Pointer for Ring 0 */ > - char res10[4]; > - uint tbptr1; /* 0x2418C - Transmit Buffer Descriptor Pointer for Ring 1 */ > - char res11[4]; > - uint tbptr2; /* 0x24194 - Transmit Buffer Descriptor Pointer for Ring 2 */ > - char res12[4]; > - uint tbptr3; /* 0x2419C - Transmit Buffer Descriptor Pointer for Ring 3 */ > - char res13[4]; > - uint tbptr4; /* 0x241A4 - Transmit Buffer Descriptor Pointer for Ring 4 */ > - char res14[4]; > - uint tbptr5; /* 0x241AC - Transmit Buffer Descriptor Pointer for Ring 5 */ > - char res15[4]; > - uint tbptr6; /* 0x241B4 - Transmit Buffer Descriptor Pointer for Ring 6 */ > - char res16[4]; > - uint tbptr7; /* 0x241BC - Transmit Buffer Descriptor Pointer for Ring 7 */ > - char res17[64]; > - uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ > - uint tbase0; /* 0x24204 - Transmit Descriptor Base Address Register of Ring 0 */ > - char res18[4]; > - uint tbase1; /* 0x2420C - Transmit Descriptor base address of Ring 1 */ > - char res19[4]; > - uint tbase2; /* 0x24214 - Transmit Descriptor base address of Ring 2 */ > - char res20[4]; > - uint tbase3; /* 0x2421C - Transmit Descriptor base address of Ring 3 */ > - char res21[4]; > - uint tbase4; /* 0x24224 - Transmit Descriptor base address of Ring 4 */ > - char res22[4]; > - uint tbase5; /* 0x2422C - Transmit Descriptor base address of Ring 5 */ > - char res23[4]; > - uint tbase6; /* 0x24234 - Transmit Descriptor base address of Ring 6 */ > - char res24[4]; > - uint tbase7; /* 0x2423C - Transmit Descriptor base address of Ring 7 */ > - char res25[192]; > - uint rctrl; /* 0x24300 - Receive Control Register */ > - uint rstat; /* 0x24304 - Receive Status Register */ > - char res26[8]; > - uint rxic; /* 0x24310 - Receive Interrupt Coalecing Register */ > - uint rqueue; /* 0x24314 - Receive queue control register */ > - char res27[24]; > - uint rbifx; /* 0x24330 - Receive bit field extract control Register */ > - uint rqfar; /* 0x24334 - Receive queue filing table address Register */ > - uint rqfcr; /* 0x24338 - Receive queue filing table control Register */ > - uint rqfpr; /* 0x2433c - Receive queue filing table property Register */ > - uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ > - char res28[56]; > - uint rbdbph; /* 0x2437C - Receive Data Buffer Pointer High */ > - char res29[4]; > - uint rbptr0; /* 0x24384 - Receive Buffer Descriptor Pointer for Ring 0 */ > - char res30[4]; > - uint rbptr1; /* 0x2438C - Receive Buffer Descriptor Pointer for Ring 1 */ > - char res31[4]; > - uint rbptr2; /* 0x24394 - Receive Buffer Descriptor Pointer for Ring 2 */ > - char res32[4]; > - uint rbptr3; /* 0x2439C - Receive Buffer Descriptor Pointer for Ring 3 */ > - char res33[4]; > - uint rbptr4; /* 0x243A4 - Receive Buffer Descriptor Pointer for Ring 4 */ > - char res34[4]; > - uint rbptr5; /* 0x243AC - Receive Buffer Descriptor Pointer for Ring 5 */ > - char res35[4]; > - uint rbptr6; /* 0x243B4 - Receive Buffer Descriptor Pointer for Ring 6 */ > - char res36[4]; > - uint rbptr7; /* 0x243BC - Receive Buffer Descriptor Pointer for Ring 7 */ > - char res37[64]; > - uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ > - uint rbase0; /* 0x24404 - Receive Descriptor Base Address of Ring 0 */ > - char res38[4]; > - uint rbase1; /* 0x2440C - Receive Descriptor Base Address of Ring 1 */ > - char res39[4]; > - uint rbase2; /* 0x24414 - Receive Descriptor Base Address of Ring 2 */ > - char res40[4]; > - uint rbase3; /* 0x2441C - Receive Descriptor Base Address of Ring 3 */ > - char res41[4]; > - uint rbase4; /* 0x24424 - Receive Descriptor Base Address of Ring 4 */ > - char res42[4]; > - uint rbase5; /* 0x2442C - Receive Descriptor Base Address of Ring 5 */ > - char res43[4]; > - uint rbase6; /* 0x24434 - Receive Descriptor Base Address of Ring 6 */ > - char res44[4]; > - uint rbase7; /* 0x2443C - Receive Descriptor Base Address of Ring 7 */ > - char res45[192]; > - uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ > - uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ > - uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ > - uint hafdup; /* 0x2450c - Half Duplex Register */ > - uint maxfrm; /* 0x24510 - Maximum Frame Length Register */ > - char res46[12]; > - uint miimcfg; /* 0x24520 - MII Management Configuration Register */ > - uint miimcom; /* 0x24524 - MII Management Command Register */ > - uint miimadd; /* 0x24528 - MII Management Address Register */ > - uint miimcon; /* 0x2452c - MII Management Control Register */ > - uint miimstat; /* 0x24530 - MII Management Status Register */ > - uint miimind; /* 0x24534 - MII Management Indicator Register */ > - uint ifctrl; /* 0x24538 - Interface Contrl Register */ > - uint ifstat; /* 0x2453c - Interface Status Register */ > - uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ > - uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ > - uint mac01addr1; /* 0x24548 - MAC exact match address 1, part 1 */ > - uint mac01addr2; /* 0x2454C - MAC exact match address 1, part 2 */ > - uint mac02addr1; /* 0x24550 - MAC exact match address 2, part 1 */ > - uint mac02addr2; /* 0x24554 - MAC exact match address 2, part 2 */ > - uint mac03addr1; /* 0x24558 - MAC exact match address 3, part 1 */ > - uint mac03addr2; /* 0x2455C - MAC exact match address 3, part 2 */ > - uint mac04addr1; /* 0x24560 - MAC exact match address 4, part 1 */ > - uint mac04addr2; /* 0x24564 - MAC exact match address 4, part 2 */ > - uint mac05addr1; /* 0x24568 - MAC exact match address 5, part 1 */ > - uint mac05addr2; /* 0x2456C - MAC exact match address 5, part 2 */ > - uint mac06addr1; /* 0x24570 - MAC exact match address 6, part 1 */ > - uint mac06addr2; /* 0x24574 - MAC exact match address 6, part 2 */ > - uint mac07addr1; /* 0x24578 - MAC exact match address 7, part 1 */ > - uint mac07addr2; /* 0x2457C - MAC exact match address 7, part 2 */ > - uint mac08addr1; /* 0x24580 - MAC exact match address 8, part 1 */ > - uint mac08addr2; /* 0x24584 - MAC exact match address 8, part 2 */ > - uint mac09addr1; /* 0x24588 - MAC exact match address 9, part 1 */ > - uint mac09addr2; /* 0x2458C - MAC exact match address 9, part 2 */ > - uint mac10addr1; /* 0x24590 - MAC exact match address 10, part 1 */ > - uint mac10addr2; /* 0x24594 - MAC exact match address 10, part 2 */ > - uint mac11addr1; /* 0x24598 - MAC exact match address 11, part 1 */ > - uint mac11addr2; /* 0x2459C - MAC exact match address 11, part 2 */ > - uint mac12addr1; /* 0x245A0 - MAC exact match address 12, part 1 */ > - uint mac12addr2; /* 0x245A4 - MAC exact match address 12, part 2 */ > - uint mac13addr1; /* 0x245A8 - MAC exact match address 13, part 1 */ > - uint mac13addr2; /* 0x245AC - MAC exact match address 13, part 2 */ > - uint mac14addr1; /* 0x245B0 - MAC exact match address 14, part 1 */ > - uint mac14addr2; /* 0x245B4 - MAC exact match address 14, part 2 */ > - uint mac15addr1; /* 0x245B8 - MAC exact match address 15, part 1 */ > - uint mac15addr2; /* 0x245BC - MAC exact match address 15, part 2 */ > - char res48[192]; > - uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ > - uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ > - uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */ > - uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */ > - uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */ > - uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */ > - uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ > - uint rbyt; /* 0x2469c - Receive Byte Counter */ > - uint rpkt; /* 0x246a0 - Receive Packet Counter */ > - uint rfcs; /* 0x246a4 - Receive FCS Error Counter */ > - uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */ > - uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */ > - uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */ > - uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */ > - uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */ > - uint raln; /* 0x246bc - Receive Alignment Error Counter */ > - uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */ > - uint rcde; /* 0x246c4 - Receive Code Error Counter */ > - uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */ > - uint rund; /* 0x246cc - Receive Undersize Packet Counter */ > - uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */ > - uint rfrg; /* 0x246d4 - Receive Fragments Counter */ > - uint rjbr; /* 0x246d8 - Receive Jabber Counter */ > - uint rdrp; /* 0x246dc - Receive Drop Counter */ > - uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */ > - uint tpkt; /* 0x246e4 - Transmit Packet Counter */ > - uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */ > - uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */ > - uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */ > - uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */ > - uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */ > - uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */ > - uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */ > - uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */ > - uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */ > - uint tncl; /* 0x2470c - Transmit Total Collision Counter */ > - char res49[4]; > - uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */ > - uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */ > - uint tfcs; /* 0x2471c - Transmit FCS Error Counter */ > - uint txcf; /* 0x24720 - Transmit Control Frame Counter */ > - uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */ > - uint tund; /* 0x24728 - Transmit Undersize Frame Counter */ > - uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */ > - uint car1; /* 0x24730 - Carry Register One */ > - uint car2; /* 0x24734 - Carry Register Two */ > - uint cam1; /* 0x24738 - Carry Mask Register One */ > - uint cam2; /* 0x2473c - Carry Mask Register Two */ > - uint rrej; /* 0x24740 - Receive filer rejected packet counter */ > - char res50[188]; > - uint iaddr0; /* 0x24800 - Indivdual address register 0 */ > - uint iaddr1; /* 0x24804 - Indivdual address register 1 */ > - uint iaddr2; /* 0x24808 - Indivdual address register 2 */ > - uint iaddr3; /* 0x2480c - Indivdual address register 3 */ > - uint iaddr4; /* 0x24810 - Indivdual address register 4 */ > - uint iaddr5; /* 0x24814 - Indivdual address register 5 */ > - uint iaddr6; /* 0x24818 - Indivdual address register 6 */ > - uint iaddr7; /* 0x2481c - Indivdual address register 7 */ > - char res51[96]; > - uint gaddr0; /* 0x24880 - Global address register 0 */ > - uint gaddr1; /* 0x24884 - Global address register 1 */ > - uint gaddr2; /* 0x24888 - Global address register 2 */ > - uint gaddr3; /* 0x2488c - Global address register 3 */ > - uint gaddr4; /* 0x24890 - Global address register 4 */ > - uint gaddr5; /* 0x24894 - Global address register 5 */ > - uint gaddr6; /* 0x24898 - Global address register 6 */ > - uint gaddr7; /* 0x2489c - Global address register 7 */ > - char res52[352]; > - uint fifocfg; /* 0x24A00 - FIFO interface configuration register */ > - char res53[500]; > - uint attr; /* 0x24BF8 - DMA Attribute register */ > - uint attreli; /* 0x24BFC - DMA Attribute extract length and index register */ > - char res54[1024]; > -} ccsr_tsec_t; > - > -/* PIC Registers(0x4_0000-0x6_1000) */ > - > -typedef struct ccsr_pic { > - char res1[64]; > - uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ > - char res2[12]; > - uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ > - char res3[12]; > - uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */ > - char res4[12]; > - uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */ > - char res5[12]; > - uint ctpr; /* 0x40080 - Current Task Priority Register */ > - char res6[12]; > - uint whoami; /* 0x40090 - Who Am I Register */ > - char res7[12]; > - uint iack; /* 0x400a0 - Interrupt Acknowledge Register */ > - char res8[12]; > - uint eoi; /* 0x400b0 - End Of Interrupt Register */ > - char res9[3916]; > - uint frr; /* 0x41000 - Feature Reporting Register */ > - char res10[28]; > - uint gcr; /* 0x41020 - Global Configuration Register */ > -#define MPC86xx_PICGCR_RST 0x80000000 > -#define MPC86xx_PICGCR_MODE 0x20000000 > - char res11[92]; > - uint vir; /* 0x41080 - Vendor Identification Register */ > - char res12[12]; > - uint pir; /* 0x41090 - Processor Initialization Register */ > - char res13[12]; > - uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */ > - char res14[12]; > - uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */ > - char res15[12]; > - uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */ > - char res16[12]; > - uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */ > - char res17[12]; > - uint svr; /* 0x410e0 - Spurious Vector Register */ > - char res18[12]; > - uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */ > - char res19[12]; > - uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */ > - char res20[12]; > - uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */ > - char res21[12]; > - uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */ > - char res22[12]; > - uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */ > - char res23[12]; > - uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */ > - char res24[12]; > - uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */ > - char res25[12]; > - uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */ > - char res26[12]; > - uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */ > - char res27[12]; > - uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */ > - char res28[12]; > - uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */ > - char res29[12]; > - uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */ > - char res30[12]; > - uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */ > - char res31[12]; > - uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */ > - char res32[12]; > - uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */ > - char res33[12]; > - uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */ > - char res34[12]; > - uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */ > - char res35[268]; > - uint tcr; /* 0x41300 - Timer Control Register */ > - char res36[12]; > - uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */ > - char res37[12]; > - uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */ > - char res38[12]; > - uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */ > - char res39[12]; > - uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */ > - char res40[12]; > - uint pm0mr0; /* 0x41350 - Performance monitor 0 mask register 0 */ > - char res41[12]; > - uint pm0mr1; /* 0x41360 - Performance monitor 0 mask register 1 */ > - char res42[12]; > - uint pm1mr0; /* 0x41370 - Performance monitor 1 mask register 0 */ > - char res43[12]; > - uint pm1mr1; /* 0x41380 - Performance monitor 1 mask register 1 */ > - char res44[12]; > - uint pm2mr0; /* 0x41390 - Performance monitor 2 mask register 0 */ > - char res45[12]; > - uint pm2mr1; /* 0x413A0 - Performance monitor 2 mask register 1 */ > - char res46[12]; > - uint pm3mr0; /* 0x413B0 - Performance monitor 3 mask register 0 */ > - char res47[12]; > - uint pm3mr1; /* 0x413C0 - Performance monitor 3 mask register 1 */ > - char res48[60]; > - uint msgr0; /* 0x41400 - Message Register 0 */ > - char res49[12]; > - uint msgr1; /* 0x41410 - Message Register 1 */ > - char res50[12]; > - uint msgr2; /* 0x41420 - Message Register 2 */ > - char res51[12]; > - uint msgr3; /* 0x41430 - Message Register 3 */ > - char res52[204]; > - uint mer; /* 0x41500 - Message Enable Register */ > - char res53[12]; > - uint msr; /* 0x41510 - Message Status Register */ > - char res54[60140]; > - uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */ > - char res55[12]; > - uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */ > - char res56[12]; > - uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */ > - char res57[12]; > - uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */ > - char res58[12]; > - uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */ > - char res59[12]; > - uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */ > - char res60[12]; > - uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */ > - char res61[12]; > - uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */ > - char res62[12]; > - uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */ > - char res63[12]; > - uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */ > - char res64[12]; > - uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */ > - char res65[12]; > - uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */ > - char res66[12]; > - uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */ > - char res67[12]; > - uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */ > - char res68[12]; > - uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */ > - char res69[12]; > - uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */ > - char res70[12]; > - uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */ > - char res71[12]; > - uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */ > - char res72[12]; > - uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */ > - char res73[12]; > - uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */ > - char res74[12]; > - uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */ > - char res75[12]; > - uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */ > - char res76[12]; > - uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */ > - char res77[12]; > - uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */ > - char res78[140]; > - uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */ > - char res79[12]; > - uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */ > - char res80[12]; > - uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */ > - char res81[12]; > - uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */ > - char res82[12]; > - uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */ > - char res83[12]; > - uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */ > - char res84[12]; > - uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */ > - char res85[12]; > - uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */ > - char res86[12]; > - uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */ > - char res87[12]; > - uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */ > - char res88[12]; > - uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */ > - char res89[12]; > - uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */ > - char res90[12]; > - uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */ > - char res91[12]; > - uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */ > - char res92[12]; > - uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */ > - char res93[12]; > - uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */ > - char res94[12]; > - uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */ > - char res95[12]; > - uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */ > - char res96[12]; > - uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */ > - char res97[12]; > - uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */ > - char res98[12]; > - uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */ > - char res99[12]; > - uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */ > - char res100[12]; > - uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */ > - char res101[12]; > - uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */ > - char res102[12]; > - uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */ > - char res103[12]; > - uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */ > - char res104[12]; > - uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */ > - char res105[12]; > - uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */ > - char res106[12]; > - uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */ > - char res107[12]; > - uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */ > - char res108[12]; > - uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */ > - char res109[12]; > - uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */ > - char res110[12]; > - uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */ > - char res111[12]; > - uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */ > - char res112[12]; > - uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */ > - char res113[12]; > - uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */ > - char res114[12]; > - uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */ > - char res115[12]; > - uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */ > - char res116[12]; > - uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */ > - char res117[12]; > - uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */ > - char res118[12]; > - uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */ > - char res119[12]; > - uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */ > - char res120[12]; > - uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */ > - char res121[12]; > - uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */ > - char res122[12]; > - uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */ > - char res123[12]; > - uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */ > - char res124[12]; > - uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */ > - char res125[12]; > - uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */ > - char res126[12]; > - uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */ > - char res127[12]; > - uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */ > - char res128[12]; > - uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */ > - char res129[12]; > - uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */ > - char res130[12]; > - uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */ > - char res131[12]; > - uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */ > - char res132[12]; > - uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */ > - char res133[12]; > - uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */ > - char res134[12]; > - uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */ > - char res135[12]; > - uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */ > - char res136[12]; > - uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */ > - char res137[12]; > - uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */ > - char res138[12]; > - uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */ > - char res139[12]; > - uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */ > - char res140[12]; > - uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ > - char res141[12]; > - uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ > - char res142[4108]; > - uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ > - char res143[12]; > - uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ > - char res144[12]; > - uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */ > - char res145[12]; > - uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */ > - char res146[12]; > - uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */ > - char res147[12]; > - uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */ > - char res148[12]; > - uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */ > - char res149[12]; > - uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */ > - char res150[59852]; > - uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */ > - char res151[12]; > - uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */ > - char res152[12]; > - uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */ > - char res153[12]; > - uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */ > - char res154[12]; > - uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */ > - char res155[12]; > - uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */ > - char res156[12]; > - uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */ > - char res157[12]; > - uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */ > - char res158[3916]; > -} ccsr_pic_t; > - > -/* RapidIO Registers(0xc_0000-0xe_0000) */ > - > -typedef struct ccsr_rio { > - uint didcar; /* 0xc0000 - Device Identity Capability Register */ > - uint dicar; /* 0xc0004 - Device Information Capability Register */ > - uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ > - uint aicar; /* 0xc000c - Assembly Information Capability Register */ > - uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ > - uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ > - uint socar; /* 0xc0018 - Source Operations Capability Register */ > - uint docar; /* 0xc001c - Destination Operations Capability Register */ > - char res1[32]; > - uint msr; /* 0xc0040 - Mailbox Command And Status Register */ > - uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ > - char res2[4]; > - uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ > - char res3[12]; > - uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ > - uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ > - char res4[4]; > - uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ > - uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ > - char res5[144]; > - uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ > - char res6[28]; > - uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ > - uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ > - char res7[20]; > - uint pgccsr; /* 0xc013c - Port General Command and Status Register */ > - uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ > - uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ > - uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ > - char res8[12]; > - uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ > - uint pccsr; /* 0xc015c - Port Control Command and Status Register */ > - char res9[1184]; > - uint erbh; /* 0xc0600 - Error Reporting Block Header Register */ > - char res10[4]; > - uint ltledcsr; /* 0xc0608 - Logical/Transport layer error detect status register */ > - uint ltleecsr; /* 0xc060c - Logical/Transport layer error enable register */ > - char res11[4]; > - uint ltlaccsr; /* 0xc0614 - Logical/Transport layer addresss capture register */ > - uint ltldidccsr; /* 0xc0618 - Logical/Transport layer device ID capture register */ > - uint ltlcccsr; /* 0xc061c - Logical/Transport layer control capture register */ > - char res12[32]; > - uint edcsr; /* 0xc0640 - Port 0 error detect status register */ > - uint erecsr; /* 0xc0644 - Port 0 error rate enable status register */ > - uint ecacsr; /* 0xc0648 - Port 0 error capture attributes register */ > - uint pcseccsr0; /* 0xc064c - Port 0 packet/control symbol error capture register 0 */ > - uint peccsr1; /* 0xc0650 - Port 0 error capture command and status register 1 */ > - uint peccsr2; /* 0xc0654 - Port 0 error capture command and status register 2 */ > - uint peccsr3; /* 0xc0658 - Port 0 error capture command and status register 3 */ > - char res13[12]; > - uint ercsr; /* 0xc0668 - Port 0 error rate command and status register */ > - uint ertcsr; /* 0xc066C - Port 0 error rate threshold status register*/ > - char res14[63892]; > - uint llcr; /* 0xd0004 - Logical Layer Configuration Register */ > - char res15[12]; > - uint epwisr; /* 0xd0010 - Error / Port-Write Interrupt Status Register */ > - char res16[12]; > - uint lretcr; /* 0xd0020 - Logical Retry Error Threshold Configuration Register */ > - char res17[92]; > - uint pretcr; /* 0xd0080 - Physical Retry Erorr Threshold Configuration Register */ > - char res18[124]; > - uint adidcsr; /* 0xd0100 - Port 0 Alt. Device ID Command and Status Register */ > - char res19[28]; > - uint ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All Configuration Register */ > - char res20[12]; > - uint iecsr; /* 0xd0130 - Port 0 Implementation Error Status Register */ > - char res21[12]; > - uint pcr; /* 0xd0140 - Port 0 Phsyical Configuration RegisterRegister */ > - char res22[20]; > - uint slcsr; /* 0xd0158 - Port 0 Serial Link Command and Status Register */ > - char res23[4]; > - uint sleir; /* 0xd0160 - Port 0 Serial Link Error Injection Register */ > - char res24[2716]; > - uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ > - uint rowtear0; /* 0xd0c04 - RapidIO Outbound Window Translation Ext. Address Register 0 */ > - char res25[8]; > - uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ > - char res26[12]; > - uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ > - uint rowtear1; /* 0xd0c24 - RapidIO Outbound Window Translation Ext. Address Register 1 */ > - uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ > - char res27[4]; > - uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ > - uint rows1r1; /* 0xd0c34 - RapidIO Outbound Window Segment 1 Register 1 */ > - uint rows2r1; /* 0xd0c38 - RapidIO Outbound Window Segment 2 Register 1 */ > - uint rows3r1; /* 0xd0c3c - RapidIO Outbound Window Segment 3 Register 1 */ > - uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ > - uint rowtear2; /* 0xd0c44 - RapidIO Outbound Window Translation Ext. Address Register 2 */ > - uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ > - char res28[4]; > - uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ > - uint rows1r2; /* 0xd0c54 - RapidIO Outbound Window Segment 1 Register 2 */ > - uint rows2r2; /* 0xd0c58 - RapidIO Outbound Window Segment 2 Register 2 */ > - uint rows3r2; /* 0xd0c5c - RapidIO Outbound Window Segment 3 Register 2 */ > - uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ > - uint rowtear3; /* 0xd0c64 - RapidIO Outbound Window Translation Ext. Address Register 3 */ > - uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ > - char res29[4]; > - uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ > - uint rows1r3; /* 0xd0c74 - RapidIO Outbound Window Segment 1 Register 3 */ > - uint rows2r3; /* 0xd0c78 - RapidIO Outbound Window Segment 2 Register 3 */ > - uint rows3r3; /* 0xd0c7c - RapidIO Outbound Window Segment 3 Register 3 */ > - uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ > - uint rowtear4; /* 0xd0c84 - RapidIO Outbound Window Translation Ext. Address Register 4 */ > - uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ > - char res30[4]; > - uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ > - uint rows1r4; /* 0xd0c94 - RapidIO Outbound Window Segment 1 Register 4 */ > - uint rows2r4; /* 0xd0c98 - RapidIO Outbound Window Segment 2 Register 4 */ > - uint rows3r4; /* 0xd0c9c - RapidIO Outbound Window Segment 3 Register 4 */ > - uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ > - uint rowtear5; /* 0xd0ca4 - RapidIO Outbound Window Translation Ext. Address Register 5 */ > - uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ > - char res31[4]; > - uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ > - uint rows1r5; /* 0xd0cb4 - RapidIO Outbound Window Segment 1 Register 5 */ > - uint rows2r5; /* 0xd0cb8 - RapidIO Outbound Window Segment 2 Register 5 */ > - uint rows3r5; /* 0xd0cbc - RapidIO Outbound Window Segment 3 Register 5 */ > - uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ > - uint rowtear6; /* 0xd0cc4 - RapidIO Outbound Window Translation Ext. Address Register 6 */ > - uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ > - char res32[4]; > - uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ > - uint rows1r6; /* 0xd0cd4 - RapidIO Outbound Window Segment 1 Register 6 */ > - uint rows2r6; /* 0xd0cd8 - RapidIO Outbound Window Segment 2 Register 6 */ > - uint rows3r6; /* 0xd0cdc - RapidIO Outbound Window Segment 3 Register 6 */ > - uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ > - uint rowtear7; /* 0xd0ce4 - RapidIO Outbound Window Translation Ext. Address Register 7 */ > - uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ > - char res33[4]; > - uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ > - uint rows1r7; /* 0xd0cf4 - RapidIO Outbound Window Segment 1 Register 7 */ > - uint rows2r7; /* 0xd0cf8 - RapidIO Outbound Window Segment 2 Register 7 */ > - uint rows3r7; /* 0xd0cfc - RapidIO Outbound Window Segment 3 Register 7 */ > - uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ > - uint rowtear8; /* 0xd0d04 - RapidIO Outbound Window Translation Ext. Address Register 8 */ > - uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ > - char res34[4]; > - uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ > - uint rows1r8; /* 0xd0d14 - RapidIO Outbound Window Segment 1 Register 8 */ > - uint rows2r8; /* 0xd0d18 - RapidIO Outbound Window Segment 2 Register 8 */ > - uint rows3r8; /* 0xd0d1c - RapidIO Outbound Window Segment 3 Register 8 */ > - char res35[64]; > - uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ > - uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ > - char res36[4]; > - uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ > - char res37[12]; > - uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ > - char res38[4]; > - uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ > - char res39[4]; > - uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ > - char res40[12]; > - uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ > - char res41[4]; > - uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ > - char res42[4]; > - uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ > - char res43[12]; > - uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ > - char res44[4]; > - uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ > - char res45[4]; > - uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ > - char res46[12]; > - uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ > - char res47[12]; > - uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ > - char res48[12]; > - uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ > - uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ > - uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ > - uint pecr; /* 0xd0e0c - Port Error Control Register */ > - uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ > - uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ > - uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ > - char res49[4]; > - uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ > - char res50[4]; > - uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ > - uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ > - char res51[8656]; > - uint omr; /* 0xd3000 - Outbound Mode Register */ > - uint osr; /* 0xd3004 - Outbound Status Register */ > - uint eodqtpar; /* 0xd3008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ > - uint odqtpar; /* 0xd300c - Outbound Descriptor Queue Tail Pointer Address Register */ > - uint eosar; /* 0xd3010 - Extended Outbound Unit Source Address Register */ > - uint osar; /* 0xd3014 - Outbound Unit Source Address Register */ > - uint odpr; /* 0xd3018 - Outbound Destination Port Register */ > - uint odatr; /* 0xd301c - Outbound Destination Attributes Register */ > - uint odcr; /* 0xd3020 - Outbound Doubleword Count Register */ > - uint eodqhpar; /* 0xd3024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ > - uint odqhpar; /* 0xd3028 - Outbound Descriptor Queue Head Pointer Address Register */ > - uint oretr; /* 0xd302C - Outbound Retry Error Threshold Register */ > - uint omgr; /* 0xd3030 - Outbound Multicast Group Register */ > - uint omlr; /* 0xd3034 - Outbound Multicast List Register */ > - char res52[40]; > - uint imr; /* 0xd3060 - Outbound Mode Register */ > - uint isr; /* 0xd3064 - Inbound Status Register */ > - uint eidqtpar; /* 0xd3068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ > - uint idqtpar; /* 0xd306c - Inbound Descriptor Queue Tail Pointer Address Register */ > - uint eifqhpar; /* 0xd3070 - Extended Inbound Frame Queue Head Pointer Address Register */ > - uint ifqhpar; /* 0xd3074 - Inbound Frame Queue Head Pointer Address Register */ > - uint imirir; /* 0xd3078 - Inbound Maximum Interrutp Report Interval Register */ > - char res53[900]; > - uint oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */ > - uint oddsr; /* 0xd3404 - Outbound Doorbell Status Register */ > - char res54[16]; > - uint oddpr; /* 0xd3418 - Outbound Doorbell Destination Port Register */ > - uint oddatr; /* 0xd341C - Outbound Doorbell Destination Attributes Register */ > - char res55[12]; > - uint oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold Configuration Register */ > - char res56[48]; > - uint idmr; /* 0xd3460 - Inbound Doorbell Mode Register */ > - uint idsr; /* 0xd3464 - Inbound Doorbell Status Register */ > - uint iedqtpar; /* 0xd3468 - Extended Inbound Doorbell Queue Tail Pointer Address Register */ > - uint iqtpar; /* 0xd346c - Inbound Doorbell Queue Tail Pointer Address Register */ > - uint iedqhpar; /* 0xd3470 - Extended Inbound Doorbell Queue Head Pointer Address Register */ > - uint idqhpar; /* 0xd3474 - Inbound Doorbell Queue Head Pointer Address Register */ > - uint idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt Report Interval Register */ > - char res57[100]; > - uint pwmr; /* 0xd34e0 - Port-Write Mode Register */ > - uint pwsr; /* 0xd34e4 - Port-Write Status Register */ > - uint epwqbar; /* 0xd34e8 - Extended Port-Write Queue Base Address Register */ > - uint pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ > - char res58[51984]; > -} ccsr_rio_t; > - > -/* Global Utilities Register Block(0xe_0000-0xf_ffff) */ > -typedef struct ccsr_gur { > - uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ > - uint porbmsr; /* 0xe0004 - POR boot mode status register */ > - uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ > - uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ > - uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ > - char res1[12]; > - uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ > - char res2[12]; > - uint gpiocr; /* 0xe0030 - GPIO control register */ > - char res3[12]; > - uint gpoutdr; /* 0xe0040 - General-purpose output data register */ > - char res4[12]; > - uint gpindr; /* 0xe0050 - General-purpose input data register */ > - char res5[12]; > - uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ > - char res6[12]; > - uint devdisr; /* 0xe0070 - Device disable control */ > - char res7[12]; > - uint powmgtcsr; /* 0xe0080 - Power management status and control register */ > - char res8[12]; > - uint mcpsumr; /* 0xe0090 - Machine check summary register */ > - uint rstrscr; /* 0xe0094 - Reset request status and control register */ > - char res9[8]; > - uint pvr; /* 0xe00a0 - Processor version register */ > - uint svr; /* 0xe00a4 - System version register */ > - char res10a[8]; > - uint rstcr; /* 0xe00b0 - Reset control register */ > - char res10b[1868]; > - uint clkdvdr; /* 0xe0800 - Clock Divide register */ > - char res10c[796]; > - uint ddr1clkdr; /* 0xe0b20 - DDRC1 Clock Disable register */ > - char res10d[4]; > - uint ddr2clkdr; /* 0xe0b28 - DDRC2 Clock Disable register */ > - char res10e[724]; > - uint clkocr; /* 0xe0e00 - Clock out select register */ > - char res11[12]; > - uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ > - char res12[12]; > - uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ > - char res13a[224]; > - uint srds1cr0; /* 0xe0f04 - SerDes1 control register 0 */ > - char res13b[4]; > - uint srds1cr1; /* 0xe0f08 - SerDes1 control register 1 */ > - char res14[24]; > - uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ > - char res15a[24]; > - uint srds2cr0; /* 0xe0f40 - SerDes2 control register 0 */ > - uint srds2cr1; /* 0xe0f44 - SerDes2 control register 1 */ > - char res16[184]; > -} ccsr_gur_t; > - > -#define MPC8610_PORBMSR_HA 0x00070000 > -#define MPC8610_PORBMSR_HA_SHIFT 16 > -#define MPC8641_PORBMSR_HA 0x00060000 > -#define MPC8641_PORBMSR_HA_SHIFT 17 > -#define MPC8610_PORDEVSR_IO_SEL 0x00380000 > -#define MPC8610_PORDEVSR_IO_SEL_SHIFT 19 > -#define MPC8641_PORDEVSR_IO_SEL 0x000F0000 > -#define MPC8641_PORDEVSR_IO_SEL_SHIFT 16 > -#define MPC86xx_PORDEVSR_CORE1TE 0x00000080 /* ASMP (Core1 addr trans) */ > -#define MPC86xx_DEVDISR_PCIEX1 0x80000000 > -#define MPC86xx_DEVDISR_PCIEX2 0x40000000 > -#define MPC86xx_DEVDISR_PCI1 0x80000000 > -#define MPC86xx_DEVDISR_PCIE1 0x40000000 > -#define MPC86xx_DEVDISR_PCIE2 0x20000000 > -#define MPC86xx_DEVDISR_SRIO 0x00080000 > -#define MPC86xx_DEVDISR_RMSG 0x00040000 > -#define MPC86xx_DEVDISR_CPU0 0x00008000 > -#define MPC86xx_DEVDISR_CPU1 0x00004000 > -#define MPC86xx_RSTCR_HRST_REQ 0x00000002 > - > -/* > - * Watchdog register block(0xe_4000-0xe_4fff) > - */ > -typedef struct ccsr_wdt { > - uint res0; > - uint swcrr; /* System watchdog control register */ > - uint swcnr; /* System watchdog count register */ > - char res1[2]; > - ushort swsrr; /* System watchdog service register */ > - char res2[4080]; > -} ccsr_wdt_t; > - > -typedef struct immap { > - ccsr_local_mcm_t im_local_mcm; > - struct ccsr_ddr im_ddr1; > - ccsr_i2c_t im_i2c; > - ccsr_duart_t im_duart; > - fsl_lbc_t im_lbc; > - struct ccsr_ddr im_ddr2; > - char res1[4096]; > - ccsr_pex_t im_pex1; > - ccsr_pex_t im_pex2; > - ccsr_ht_t im_ht; > - char res2[90112]; > - ccsr_dma_t im_dma; > - char res3[8192]; > - ccsr_tsec_t im_tsec1; > - ccsr_tsec_t im_tsec2; > - ccsr_tsec_t im_tsec3; > - ccsr_tsec_t im_tsec4; > - char res4[98304]; > - ccsr_pic_t im_pic; > - char res5[389120]; > - ccsr_rio_t im_rio; > - ccsr_gur_t im_gur; > - char res6[12288]; > - ccsr_wdt_t im_wdt; > -} immap_t; > - > -extern immap_t *immr; > - > -#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000 > -#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) > -#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000 > -#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) > -#define CONFIG_SYS_MPC86xx_DMA_OFFSET 0x21000 > -#define CONFIG_SYS_MPC86xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET) > -#define CONFIG_SYS_MPC86xx_PIC_OFFSET 0x40000 > -#define CONFIG_SYS_MPC8xxx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET) > - > - > -#define CONFIG_SYS_MPC86xx_PCI1_OFFSET 0x8000 > -#ifdef CONFIG_ARCH_MPC8610 > -#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0xa000 > -#else > -#define CONFIG_SYS_MPC86xx_PCIE1_OFFSET 0x8000 > -#endif > -#define CONFIG_SYS_MPC86xx_PCIE2_OFFSET 0x9000 > - > -#define CONFIG_SYS_PCI1_ADDR \ > - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI1_OFFSET) > -#define CONFIG_SYS_PCI2_ADDR \ > - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCI2_OFFSET) > -#define CONFIG_SYS_PCIE1_ADDR \ > - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE1_OFFSET) > -#define CONFIG_SYS_PCIE2_ADDR \ > - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PCIE2_OFFSET) > - > -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 > -#define CONFIG_SYS_MDIO1_OFFSET 0x24000 > -#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc) > - > -#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) > -#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) > - > -#endif /*__IMMAP_86xx__*/ > diff --git a/arch/powerpc/include/asm/ppc.h b/arch/powerpc/include/asm/ppc.h > index 055364c58fd9..2923350bd7b9 100644 > --- a/arch/powerpc/include/asm/ppc.h > +++ b/arch/powerpc/include/asm/ppc.h > @@ -15,10 +15,6 @@ > #if defined(CONFIG_MPC8xx) > #include > #endif > -#ifdef CONFIG_MPC86xx > -#include > -#include > -#endif > #ifdef CONFIG_MPC85xx > #include > #include > diff --git a/board/sbc8641d/Kconfig b/board/sbc8641d/Kconfig > deleted file mode 100644 > index 8dfc90cf8bc9..000000000000 > --- a/board/sbc8641d/Kconfig > +++ /dev/null > @@ -1,9 +0,0 @@ > -if TARGET_SBC8641D > - > -config SYS_BOARD > - default "sbc8641d" > - > -config SYS_CONFIG_NAME > - default "sbc8641d" > - > -endif > diff --git a/board/sbc8641d/MAINTAINERS b/board/sbc8641d/MAINTAINERS > deleted file mode 100644 > index a50b541ffe84..000000000000 > --- a/board/sbc8641d/MAINTAINERS > +++ /dev/null > @@ -1,6 +0,0 @@ > -SBC8641D BOARD > -M: Paul Gortmaker > -S: Maintained > -F: board/sbc8641d/ > -F: include/configs/sbc8641d.h > -F: configs/sbc8641d_defconfig > diff --git a/board/sbc8641d/Makefile b/board/sbc8641d/Makefile > deleted file mode 100644 > index c48f82d3d931..000000000000 > --- a/board/sbc8641d/Makefile > +++ /dev/null > @@ -1,8 +0,0 @@ > -# SPDX-License-Identifier: GPL-2.0+ > -# > -# (C) Copyright 2001 > -# Wolfgang Denk, DENX Software Engineering, wd at denx.de. > - > -obj-y += sbc8641d.o > -obj-y += law.o > -obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o > diff --git a/board/sbc8641d/README b/board/sbc8641d/README > deleted file mode 100644 > index 4999b7763c9c..000000000000 > --- a/board/sbc8641d/README > +++ /dev/null > @@ -1,49 +0,0 @@ > -Wind River SBC8641D reference board > -=========================== > - > -Created 06/14/2007 Joe Hamman > -Copyright 2007, Embedded Specialties, Inc. > -Copyright 2007 Wind River Systems, Inc. > ------------------------------ > - > -1. Building U-Boot > ------------------- > -The SBC8641D code is known to build using ELDK 4.1. > - > - $ make sbc8641d_config > - Configuring for sbc8641d board... > - > - $ make > - > - > -2. Switch and Jumper Settings > ------------------------------ > -All Jumpers & Switches are in their default positions. Please refer to > -the board documentation for details. Some settings control CPU voltages > -and settings may change with board revisions. > - > -3. Known limitations > --------------------- > -PCI: > - The PCI command may hang if no boards are present in either slot. > - > -4. Reflashing U-Boot > --------------------- > -The board has two independent flash devices which can be used for dual > -booting, or for U-Boot backup and recovery. A two pin jumper on the > -three pin JP10 determines which device is attached to /CS0 line. > - > -Assuming one device has a functional U-Boot, and the other device has > -a recently installed non-functional image, to perform a recovery from > -that non-functional image goes essentially as follows: > - > -a) power down the board and jumper JP10 to select the functional image. > -b) power on the board and let it get to U-Boot prompt. > -c) while on, using static precautions, move JP10 back to the failed image. > -d) use "md fff00000" to confirm you are looking at the failed image > -e) turn off write protect with "prot off all" > -f) get new image, i.e. "tftp 200000 /somepath/u-boot.bin" > -g) erase failed image: "erase FFF00000 FFF5FFFF" > -h) copy in new image: "cp.b 200000 FFF00000 60000" > -i) ensure new image is written: "md fff00000" > -k) power cycle the board and confirm new image works. > diff --git a/board/sbc8641d/ddr.c b/board/sbc8641d/ddr.c > deleted file mode 100644 > index b6c1847b141b..000000000000 > --- a/board/sbc8641d/ddr.c > +++ /dev/null > @@ -1,53 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0 > -/* > - * Copyright 2008 Freescale Semiconductor, Inc. > - */ > - > -#include > - > -#include > -#include > - > -void fsl_ddr_board_options(memctl_options_t *popts, > - dimm_params_t *pdimm, > - unsigned int ctrl_num) > -{ > - /* > - * Factors to consider for clock adjust: > - * - number of chips on bus > - * - position of slot > - * - DDR1 vs. DDR2? > - * - ??? > - * > - * This needs to be determined on a board-by-board basis. > - * 0110 3/4 cycle late > - * 0111 7/8 cycle late > - */ > - popts->clk_adjust = 7; > - > - /* > - * Factors to consider for CPO: > - * - frequency > - * - ddr1 vs. ddr2 > - */ > - popts->cpo_override = 10; > - > - /* > - * Factors to consider for write data delay: > - * - number of DIMMs > - * > - * 1 = 1/4 clock delay > - * 2 = 1/2 clock delay > - * 3 = 3/4 clock delay > - * 4 = 1 clock delay > - * 5 = 5/4 clock delay > - * 6 = 3/2 clock delay > - */ > - popts->write_data_delay = 3; > - > - /* > - * Factors to consider for half-strength driver enable: > - * - number of DIMMs installed > - */ > - popts->half_strength_driver_enable = 0; > -} > diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c > deleted file mode 100644 > index dc4696d123f4..000000000000 > --- a/board/sbc8641d/law.c > +++ /dev/null > @@ -1,39 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0+ > -/* > - * Copyright 2008 Freescale Semiconductor, Inc. > - * > - * (C) Copyright 2000 > - * Wolfgang Denk, DENX Software Engineering, wd at denx.de. > - */ > - > -#include > -#include > -#include > - > -/* > - * LAW (Local Access Window) configuration: > - * > - * 0x0000_0000 DDR 256M > - * 0x1000_0000 DDR2 256M > - * 0x8000_0000 PCIE1 MEM 512M > - * 0xa000_0000 PCIE2 MEM 512M > - * 0xc000_0000 RapidIO 512M > - * 0xe200_0000 PCIE1 IO 16M > - * 0xe300_0000 PCIE2 IO 16M > - * 0xf800_0000 CCSRBAR 2M > - * 0xfe00_0000 FLASH (boot bank) 32M > - * > - */ > - > - > -struct law_entry law_table[] = { > -#if !defined(CONFIG_SPD_EEPROM) > - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1), > - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, > - LAW_SIZE_256M, LAW_TRGT_IF_DDR_2), > -#endif > - SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC), > - SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC), > -}; > - > -int num_law_entries = ARRAY_SIZE(law_table); > diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c > deleted file mode 100644 > index a67092daf47f..000000000000 > --- a/board/sbc8641d/sbc8641d.c > +++ /dev/null > @@ -1,268 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0+ > -/* > - * Copyright 2007 Wind River Systemes, Inc. > - * Copyright 2007 Embedded Specialties, Inc. > - * Joe Hamman joe.hamman at embeddedspecialties.com > - * > - * Copyright 2004 Freescale Semiconductor. > - * Jeff Brown > - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com) > - * > - * (C) Copyright 2002 Scott McNutt > - */ > - > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > - > -DECLARE_GLOBAL_DATA_PTR; > - > -long int fixed_sdram (void); > - > -int board_early_init_f (void) > -{ > - return 0; > -} > - > -int checkboard (void) > -{ > - puts ("Board: Wind River SBC8641D\n"); > - > - return 0; > -} > - > -int dram_init(void) > -{ > - long dram_size = 0; > - > -#if defined(CONFIG_SPD_EEPROM) > - dram_size = fsl_ddr_sdram(); > -#else > - dram_size = fixed_sdram (); > -#endif > - > - debug(" DDR: "); > - gd->ram_size = dram_size; > - > - return 0; > -} > - > -#if defined(CONFIG_SYS_DRAM_TEST) > -int testdram(void) > -{ > - uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START; > - uint *pend = (uint *) CONFIG_SYS_MEMTEST_END; > - uint *p; > - > - puts ("SDRAM test phase 1:\n"); > - for (p = pstart; p < pend; p++) > - *p = 0xaaaaaaaa; > - > - for (p = pstart; p < pend; p++) { > - if (*p != 0xaaaaaaaa) { > - printf ("SDRAM test fails at: %08x\n", (uint) p); > - return 1; > - } > - } > - > - puts ("SDRAM test phase 2:\n"); > - for (p = pstart; p < pend; p++) > - *p = 0x55555555; > - > - for (p = pstart; p < pend; p++) { > - if (*p != 0x55555555) { > - printf ("SDRAM test fails at: %08x\n", (uint) p); > - return 1; > - } > - } > - > - puts ("SDRAM test passed.\n"); > - return 0; > -} > -#endif > - > -#if !defined(CONFIG_SPD_EEPROM) > -/* > - * Fixed sdram init -- doesn't use serial presence detect. > - */ > -long int fixed_sdram (void) > -{ > -#if !defined(CONFIG_SYS_RAMBOOT) > - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; > - volatile struct ccsr_ddr *ddr = &immap->im_ddr1; > - > - ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; > - ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS; > - ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS; > - ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS; > - ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; > - ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG; > - ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG; > - ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG; > - ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3; > - ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0; > - ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; > - ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; > - ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1A; > - ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2; > - ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1; > - ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2; > - ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTL; > - ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL; > - ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT; > - ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL; > - > - asm ("sync;isync"); > - > - udelay(500); > - > - ddr->sdram_cfg = CONFIG_SYS_DDR_CFG_1B; > - asm ("sync; isync"); > - > - udelay(500); > - ddr = &immap->im_ddr2; > - > - ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS; > - ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS; > - ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS; > - ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS; > - ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG; > - ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG; > - ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG; > - ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG; > - ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH; > - ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0; > - ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1; > - ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2; > - ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1A; > - ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2; > - ddr->sdram_mode = CONFIG_SYS_DDR2_MODE_1; > - ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2; > - ddr->sdram_md_cntl = CONFIG_SYS_DDR2_MODE_CTL; > - ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL; > - ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT; > - ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL; > - > - asm ("sync;isync"); > - > - udelay(500); > - > - ddr->sdram_cfg = CONFIG_SYS_DDR2_CFG_1B; > - asm ("sync; isync"); > - > - udelay(500); > -#endif > - return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; > -} > -#endif /* !defined(CONFIG_SPD_EEPROM) */ > - > -#if defined(CONFIG_PCI) > -/* > - * Initialize PCI Devices, report devices found. > - */ > - > -void pci_init_board(void) > -{ > - fsl_pcie_init_board(0); > -} > -#endif /* CONFIG_PCI */ > - > - > -#if defined(CONFIG_OF_BOARD_SETUP) > -int ft_board_setup(void *blob, struct bd_info *bd) > -{ > - ft_cpu_setup(blob, bd); > - > - FT_FSL_PCI_SETUP; > - > - return 0; > -} > -#endif > - > -void sbc8641d_reset_board (void) > -{ > - puts ("Resetting board....\n"); > -} > - > -/* > - * get_board_sys_clk > - * Clock is fixed at 1GHz on this board. Used for CONFIG_SYS_CLK_FREQ > - */ > - > -unsigned long get_board_sys_clk (ulong dummy) > -{ > - int i; > - ulong val = 0; > - > - i = 5; > - i &= 0x07; > - > - switch (i) { > - case 0: > - val = 33000000; > - break; > - case 1: > - val = 40000000; > - break; > - case 2: > - val = 50000000; > - break; > - case 3: > - val = 66000000; > - break; > - case 4: > - val = 83000000; > - break; > - case 5: > - val = 100000000; > - break; > - case 6: > - val = 134000000; > - break; > - case 7: > - val = 166000000; > - break; > - } > - > - return val; > -} > - > -void board_reset(void) > -{ > -#ifdef CONFIG_SYS_RESET_ADDRESS > - ulong addr = CONFIG_SYS_RESET_ADDRESS; > - > - /* flush and disable I/D cache */ > - __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3"); > - __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5"); > - __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4"); > - __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5"); > - __asm__ __volatile__ ("sync"); > - __asm__ __volatile__ ("mtspr 1008, 4"); > - __asm__ __volatile__ ("isync"); > - __asm__ __volatile__ ("sync"); > - __asm__ __volatile__ ("mtspr 1008, 5"); > - __asm__ __volatile__ ("isync"); > - __asm__ __volatile__ ("sync"); > - > - /* > - * SRR0 has system reset vector, SRR1 has default MSR value > - * rfi restores MSR from SRR1 and sets the PC to the SRR0 value > - */ > - __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr)); > - __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4"); > - __asm__ __volatile__ ("mtspr 27, 4"); > - __asm__ __volatile__ ("rfi"); > -#endif > -} > diff --git a/configs/sbc8641d_defconfig b/configs/sbc8641d_defconfig > deleted file mode 100644 > index ea601dea6f40..000000000000 > --- a/configs/sbc8641d_defconfig > +++ /dev/null > @@ -1,39 +0,0 @@ > -CONFIG_PPC=y > -CONFIG_SYS_TEXT_BASE=0xfff00000 > -CONFIG_ENV_SIZE=0x2000 > -CONFIG_ENV_SECT_SIZE=0x20000 > -CONFIG_MPC86xx=y > -CONFIG_HIGH_BATS=y > -CONFIG_TARGET_SBC8641D=y > -CONFIG_OF_BOARD_SETUP=y > -CONFIG_OF_STDOUT_VIA_ALIAS=y > -CONFIG_BOOTDELAY=10 > -# CONFIG_DISPLAY_BOARDINFO is not set > -CONFIG_HUSH_PARSER=y > -# CONFIG_AUTO_COMPLETE is not set > -CONFIG_CMD_IMLS=y > -CONFIG_CMD_I2C=y > -CONFIG_CMD_PCI=y > -# CONFIG_CMD_SETEXPR is not set > -CONFIG_CMD_PING=y > -CONFIG_MP=y > -CONFIG_DOS_PARTITION=y > -CONFIG_ENV_OVERWRITE=y > -CONFIG_ENV_ADDR=0xFFF60000 > -# CONFIG_MMC is not set > -CONFIG_MTD_NOR_FLASH=y > -CONFIG_FLASH_CFI_DRIVER=y > -CONFIG_SYS_FLASH_PROTECTION=y > -CONFIG_SYS_FLASH_CFI=y > -CONFIG_PHY_ATHEROS=y > -CONFIG_PHY_BROADCOM=y > -CONFIG_PHY_DAVICOM=y > -CONFIG_PHY_LXT=y > -CONFIG_PHY_MARVELL=y > -CONFIG_PHY_NATSEMI=y > -CONFIG_PHY_REALTEK=y > -CONFIG_PHY_SMSC=y > -CONFIG_PHY_VITESSE=y > -CONFIG_TSEC_ENET=y > -CONFIG_SYS_NS16550=y > -CONFIG_OF_LIBFDT=y > diff --git a/doc/git-mailrc b/doc/git-mailrc > index f520ff89b390..b8299a1a6c30 100644 > --- a/doc/git-mailrc > +++ b/doc/git-mailrc > @@ -99,7 +99,6 @@ alias ppc powerpc > alias mpc8xx uboot, wd, Christophe Leroy > alias mpc83xx uboot, mariosix > alias mpc85xx uboot, afleming, priyankajain > -alias mpc86xx uboot, afleming, priyankajain > > alias sandbox sjg > alias sb sandbox > diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig > index 890e62190b1a..e6a51f560978 100644 > --- a/drivers/ddr/fsl/Kconfig > +++ b/drivers/ddr/fsl/Kconfig > @@ -2,8 +2,8 @@ config SYS_FSL_DDR > bool > help > Select Freescale General DDR driver, shared between most Freescale > - PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM- > - based Layerscape SoCs (such as ls2080a). > + PowerPC- based SoCs (such as mpc83xx, mpc85xx and ARM- based > + Layerscape SoCs (such as ls2080a). > > config SYS_FSL_MMDC > bool > @@ -41,7 +41,6 @@ config SYS_NUM_DDR_CTLRS > ARCH_T4240 > default 2 if ARCH_B4860 || \ > ARCH_BSC9132 || \ > - ARCH_MPC8641 || \ > ARCH_P4080 || \ > ARCH_P5040 || \ > ARCH_LX2160A || \ > @@ -79,12 +78,6 @@ config SYS_FSL_DDRC_GEN2 > help > Enable Freescale DDR2 controller. > > -config SYS_FSL_DDRC_86XX_GEN2 > - bool > - depends on MPC86xx > - help > - Enable Freescale DDR2 controller for MPC86xx SoCs. > - > config SYS_FSL_DDRC_GEN3 > bool > depends on PPC > @@ -136,7 +129,6 @@ config SYS_FSL_DDR2 > bool "Freescale DDR2 controller" > depends on SYS_FSL_HAS_DDR2 > select SYS_FSL_DDRC_GEN2 if (!MPC86xx && !SYS_FSL_DDRC_GEN3) > - select SYS_FSL_DDRC_86XX_GEN2 if MPC86xx > > config SYS_FSL_DDR1 > bool "Freescale DDR1 controller" > diff --git a/drivers/ddr/fsl/Makefile b/drivers/ddr/fsl/Makefile > index c675f44ab00c..8081d0cd82f3 100644 > --- a/drivers/ddr/fsl/Makefile > +++ b/drivers/ddr/fsl/Makefile > @@ -28,7 +28,6 @@ obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o > obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o > obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o > obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o > -obj-$(CONFIG_SYS_FSL_DDRC_86XX_GEN2) += mpc86xx_ddr.o > obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o > obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o > obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o > diff --git a/drivers/ddr/fsl/mpc86xx_ddr.c b/drivers/ddr/fsl/mpc86xx_ddr.c > deleted file mode 100644 > index 43ed1ba432de..000000000000 > --- a/drivers/ddr/fsl/mpc86xx_ddr.c > +++ /dev/null > @@ -1,84 +0,0 @@ > -// SPDX-License-Identifier: GPL-2.0 > -/* > - * Copyright 2008 Freescale Semiconductor, Inc. > - */ > - > -#include > -#include > -#include > -#include > -#include > - > -#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4) > -#error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL > -#endif > - > -void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, > - unsigned int ctrl_num, int step) > -{ > - unsigned int i; > - struct ccsr_ddr __iomem *ddr; > - > - switch (ctrl_num) { > - case 0: > - ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; > - break; > - case 1: > - ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; > - break; > - default: > - printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); > - return; > - } > - > - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { > - if (i == 0) { > - out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); > - out_be32(&ddr->cs0_config, regs->cs[i].config); > - > - } else if (i == 1) { > - out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); > - out_be32(&ddr->cs1_config, regs->cs[i].config); > - > - } else if (i == 2) { > - out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); > - out_be32(&ddr->cs2_config, regs->cs[i].config); > - > - } else if (i == 3) { > - out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); > - out_be32(&ddr->cs3_config, regs->cs[i].config); > - } > - } > - > - out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3); > - out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0); > - out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); > - out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2); > - out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2); > - out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode); > - out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2); > - out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl); > - out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval); > - out_be32(&ddr->sdram_data_init, regs->ddr_data_init); > - out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl); > - out_be32(&ddr->init_addr, regs->ddr_init_addr); > - out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr); > - > - debug("before go\n"); > - > - /* > - * 200 painful micro-seconds must elapse between > - * the DDR clock setup and the DDR config enable. > - */ > - udelay(200); > - asm volatile("sync;isync"); > - > - out_be32(&ddr->sdram_cfg, regs->ddr_sdram_cfg); > - > - /* > - * Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done > - */ > - while (in_be32(&ddr->sdram_cfg_2) & 0x10) { > - udelay(10000); /* throttle polling rate */ > - } > -} > diff --git a/env/Kconfig b/env/Kconfig > index c06b8ba8cb7e..691f4d480cc4 100644 > --- a/env/Kconfig > +++ b/env/Kconfig > @@ -85,7 +85,7 @@ config ENV_IS_IN_FLASH > default y if M548x || M547x || M5282 > default y if MCF532x || MCF52x2 > default y if MPC86xx || MPC83xx > - default y if ARCH_MPC8548 || ARCH_MPC8641 > + default y if ARCH_MPC8548 > default y if SH && !CPU_SH4 > help > Define this if you have a flash device which you want to use for the > diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h > deleted file mode 100644 > index 3d5aee0dd58a..000000000000 > --- a/include/configs/sbc8641d.h > +++ /dev/null > @@ -1,509 +0,0 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > -/* > - * Copyright 2007 Wind River Systems > - * Copyright 2007 Embedded Specialties, Inc. > - * Joe Hamman > - * > - * Copyright 2006 Freescale Semiconductor. > - * > - * Srikanth Srinivasan (srikanth.srinivasan at freescale.com) > - */ > - > -/* > - * SBC8641D board configuration file > - * > - * Make sure you change the MAC address and other network params first, > - * search for CONFIG_SERVERIP, etc in this file. > - */ > - > -#ifndef __CONFIG_H > -#define __CONFIG_H > - > -/* High Level Configuration Options */ > -#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ > - > -#ifdef RUN_DIAG > -#define CONFIG_SYS_DIAG_ADDR 0xff800000 > -#endif > - > -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 > - > -/* > - * virtual address to be used for temporary mappings. There > - * should be 128k free at this VA. > - */ > -#define CONFIG_SYS_SCRATCH_VA 0xe8000000 > - > -#define CONFIG_SYS_SRIO > -#define CONFIG_SRIO1 /* SRIO port 1 */ > - > -#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ > -#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ > -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ > -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ > - > -#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ > - > -#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ > -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ > -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ > -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef > -#define CACHE_LINE_INTERLEAVING 0x20000000 > -#define PAGE_INTERLEAVING 0x21000000 > -#define BANK_INTERLEAVING 0x22000000 > -#define SUPER_BANK_INTERLEAVING 0x23000000 > - > -#define CONFIG_ALTIVEC 1 > - > -/* > - * L2CR setup -- make sure this is right for your board! > - */ > -#define CONFIG_SYS_L2 > -#define L2_INIT 0 > -#define L2_ENABLE (L2CR_L2E) > - > -#ifndef CONFIG_SYS_CLK_FREQ > -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) > -#endif > - > -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ > - > -/* > - * Base addresses -- Note these are effective addresses where the > - * actual resources get mapped (not physical addresses) > - */ > -#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ > -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ > - > -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR > -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 > -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW > - > -/* > - * DDR Setup > - */ > -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ > -#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ > -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE > -#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 > -#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ > -#define CONFIG_VERY_BIG_RAM > - > -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 > -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) > - > -#if defined(CONFIG_SPD_EEPROM) > - /* > - * Determine DDR configuration from I2C interface. > - */ > - #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ > - #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ > - #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ > - #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ > - > -#else > - /* > - * Manually set up DDR1 & DDR2 parameters > - */ > - > - #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ > - > - #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F > - #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 > - #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 > - #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 > - #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 > - #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 > - #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 > - #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 > - #define CONFIG_SYS_DDR_TIMING_3 0x00000000 > - #define CONFIG_SYS_DDR_TIMING_0 0x00220802 > - #define CONFIG_SYS_DDR_TIMING_1 0x38377322 > - #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 > - #define CONFIG_SYS_DDR_CFG_1A 0x43008008 > - #define CONFIG_SYS_DDR_CFG_2 0x24401000 > - #define CONFIG_SYS_DDR_MODE_1 0x23c00542 > - #define CONFIG_SYS_DDR_MODE_2 0x00000000 > - #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 > - #define CONFIG_SYS_DDR_INTERVAL 0x05080100 > - #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 > - #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 > - #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 > - > - #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F > - #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 > - #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 > - #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 > - #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 > - #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 > - #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 > - #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 > - #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 > - #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 > - #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 > - #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 > - #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 > - #define CONFIG_SYS_DDR2_CFG_2 0x24401000 > - #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 > - #define CONFIG_SYS_DDR2_MODE_2 0x00000000 > - #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 > - #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 > - #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 > - #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 > - #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 > - > -#endif > - > -/* #define CONFIG_ID_EEPROM 1 > -#define ID_EEPROM_ADDR 0x57 */ > - > -/* > - * The SBC8641D contains 16MB flash space at ff000000. > - */ > -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ > - > -/* Flash */ > -#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ > -#define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ > - > -/* 64KB EEPROM */ > -#define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ > -#define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ > - > -/* EPLD - User switches, board id, LEDs */ > -#define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ > -#define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ > - > -/* Local bus SDRAM 128MB */ > -#define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ > -#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ > -#define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ > -#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ > - > -/* Disk on Chip (DOC) 128MB */ > -#define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ > -#define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ > - > -/* LCD */ > -#define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ > -#define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ > - > -/* Control logic & misc peripherals */ > -#define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ > -#define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ > - > -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ > -#define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ > - > -#undef CONFIG_SYS_FLASH_CHECKSUM > -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ > -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ > -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ > -#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ > - > -#define CONFIG_SYS_WRITE_SWAPPED_DATA > -#define CONFIG_SYS_FLASH_EMPTY_INFO > - > -#define CONFIG_SYS_INIT_RAM_LOCK 1 > -#ifndef CONFIG_SYS_INIT_RAM_LOCK > -#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ > -#else > -#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ > -#endif > -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ > - > -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) > -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET > - > -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ > -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ > - > -/* Serial Port */ > -#define CONFIG_SYS_NS16550_SERIAL > -#define CONFIG_SYS_NS16550_REG_SIZE 1 > -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) > - > -#define CONFIG_SYS_BAUDRATE_TABLE \ > - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} > - > -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) > -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) > - > -/* > - * I2C > - */ > -#define CONFIG_SYS_I2C > -#define CONFIG_SYS_I2C_FSL > -#define CONFIG_SYS_FSL_I2C_SPEED 400000 > -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F > -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 > -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } > - > -/* > - * RapidIO MMU > - */ > -#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ > -#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE > -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ > - > -/* > - * General PCI > - * Addresses are mapped 1-1. > - */ > -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 > -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS > -#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS > -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ > -#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 > -#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS > -#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS > -#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ > - > -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 > -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS > -#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS > -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ > -#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 > -#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS > -#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS > -#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ > - > -#if defined(CONFIG_PCI) > - > -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ > - > - > -#if !defined(CONFIG_PCI_PNP) > - #define PCI_ENET0_IOADDR 0xe0000000 > - #define PCI_ENET0_MEMADDR 0xe0000000 > - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ > -#endif > - > -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ > - > -#ifdef CONFIG_SCSI_AHCI > -#define CONFIG_SATA_ULI5288 > -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 > -#define CONFIG_SYS_SCSI_MAX_LUN 1 > -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) > -#endif > - > -#endif /* CONFIG_PCI */ > - > -#if defined(CONFIG_TSEC_ENET) > -#define CONFIG_TSEC1 1 > -#define CONFIG_TSEC1_NAME "eTSEC1" > -#define CONFIG_TSEC2 1 > -#define CONFIG_TSEC2_NAME "eTSEC2" > -#define CONFIG_TSEC3 1 > -#define CONFIG_TSEC3_NAME "eTSEC3" > -#define CONFIG_TSEC4 1 > -#define CONFIG_TSEC4_NAME "eTSEC4" > - > -#define TSEC1_PHY_ADDR 0x1F > -#define TSEC2_PHY_ADDR 0x00 > -#define TSEC3_PHY_ADDR 0x01 > -#define TSEC4_PHY_ADDR 0x02 > -#define TSEC1_PHYIDX 0 > -#define TSEC2_PHYIDX 0 > -#define TSEC3_PHYIDX 0 > -#define TSEC4_PHYIDX 0 > -#define TSEC1_FLAGS TSEC_GIGABIT > -#define TSEC2_FLAGS TSEC_GIGABIT > -#define TSEC3_FLAGS TSEC_GIGABIT > -#define TSEC4_FLAGS TSEC_GIGABIT > - > -#define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ > - > -#define CONFIG_ETHPRIME "eTSEC1" > - > -#endif /* CONFIG_TSEC_ENET */ > - > -/* > - * BAT0 2G Cacheable, non-guarded > - * 0x0000_0000 2G DDR > - */ > -#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) > -#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) > -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) > -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U > - > -/* > - * BAT1 1G Cache-inhibited, guarded > - * 0x8000_0000 512M PCI-Express 1 Memory > - * 0xa000_0000 512M PCI-Express 2 Memory > - * Changed it for operating from 0xd0000000 > - */ > -#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ > - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) > -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) > -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) > -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U > - > -/* > - * BAT2 512M Cache-inhibited, guarded > - * 0xc000_0000 512M RapidIO Memory > - */ > -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ > - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) > -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) > -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) > -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U > - > -/* > - * BAT3 4M Cache-inhibited, guarded > - * 0xf800_0000 4M CCSR > - */ > -#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ > - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) > -#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) > -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) > -#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U > - > -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) > -#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ > - | BATL_PP_RW | BATL_CACHEINHIBIT \ > - | BATL_GUARDEDSTORAGE) > -#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ > - | BATU_BL_1M | BATU_VS | BATU_VP) > -#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ > - | BATL_PP_RW | BATL_CACHEINHIBIT) > -#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU > -#endif > - > -/* > - * BAT4 32M Cache-inhibited, guarded > - * 0xe200_0000 16M PCI-Express 1 I/O > - * 0xe300_0000 16M PCI-Express 2 I/0 > - * Note that this is at 0xe0000000 > - */ > -#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ > - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) > -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) > -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) > -#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U > - > -/* > - * BAT5 128K Cacheable, non-guarded > - * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) > - */ > -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) > -#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) > -#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L > -#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U > - > -/* > - * BAT6 32M Cache-inhibited, guarded > - * 0xfe00_0000 32M FLASH > - */ > -#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ > - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) > -#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) > -#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) > -#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U > - > -/* Map the last 1M of flash where we're running from reset */ > -#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ > - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) > -#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) > -#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ > - | BATL_MEMCOHERENCE) > -#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY > - > -#define CONFIG_SYS_DBAT7L 0x00000000 > -#define CONFIG_SYS_DBAT7U 0x00000000 > -#define CONFIG_SYS_IBAT7L 0x00000000 > -#define CONFIG_SYS_IBAT7U 0x00000000 > - > -/* > - * Environment > - */ > - > -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ > -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ > - > -#undef CONFIG_WATCHDOG /* watchdog disabled */ > - > -/* > - * Miscellaneous configurable options > - */ > -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ > - > -/* > - * For booting Linux, the board info and command line data > - * have to be in the first 8 MB of memory, since this is > - * the maximum mapped by the Linux kernel during initialization. > - */ > -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ > - > -/* Cache Configuration */ > -#define CONFIG_SYS_DCACHE_SIZE 32768 > -#define CONFIG_SYS_CACHELINE_SIZE 32 > -#if defined(CONFIG_CMD_KGDB) > -#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ > -#endif > - > -#if defined(CONFIG_CMD_KGDB) > -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ > -#endif > - > -/* > - * Environment Configuration > - */ > - > -#define CONFIG_HAS_ETH0 1 > -#define CONFIG_HAS_ETH1 1 > -#define CONFIG_HAS_ETH2 1 > -#define CONFIG_HAS_ETH3 1 > - > -#define CONFIG_IPADDR 192.168.0.50 > - > -#define CONFIG_HOSTNAME "sbc8641d" > -#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" > -#define CONFIG_BOOTFILE "uImage" > - > -#define CONFIG_SERVERIP 192.168.0.2 > -#define CONFIG_GATEWAYIP 192.168.0.1 > -#define CONFIG_NETMASK 255.255.255.0 > - > -/* default location for tftp and bootm */ > -#define CONFIG_LOADADDR 1000000 > - > -#define CONFIG_EXTRA_ENV_SETTINGS \ > - "netdev=eth0\0" \ > - "consoledev=ttyS0\0" \ > - "ramdiskaddr=2000000\0" \ > - "ramdiskfile=uRamdisk\0" \ > - "dtbaddr=400000\0" \ > - "dtbfile=sbc8641d.dtb\0" \ > - "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ > - "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ > - "maxcpus=1" > - > -#define CONFIG_NFSBOOTCOMMAND \ > - "setenv bootargs root=/dev/nfs rw " \ > - "nfsroot=$serverip:$rootpath " \ > - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ > - "console=$consoledev,$baudrate $othbootargs;" \ > - "tftp $loadaddr $bootfile;" \ > - "tftp $dtbaddr $dtbfile;" \ > - "bootm $loadaddr - $dtbaddr" > - > -#define CONFIG_RAMBOOTCOMMAND \ > - "setenv bootargs root=/dev/ram rw " \ > - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ > - "console=$consoledev,$baudrate $othbootargs;" \ > - "tftp $ramdiskaddr $ramdiskfile;" \ > - "tftp $loadaddr $bootfile;" \ > - "tftp $dtbaddr $dtbfile;" \ > - "bootm $loadaddr $ramdiskaddr $dtbaddr" > - > -#define CONFIG_FLASHBOOTCOMMAND \ > - "setenv bootargs root=/dev/ram rw " \ > - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ > - "console=$consoledev,$baudrate $othbootargs;" \ > - "bootm ffd00000 ffb00000 ffa00000" > - > -#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND > - > -#endif /* __CONFIG_H */ > diff --git a/include/post.h b/include/post.h > index 5695e2b5334f..a07a6bc5e252 100644 > --- a/include/post.h > +++ b/include/post.h > @@ -29,11 +29,6 @@ > #include > #define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \ > offsetof(ccsr_pic_t, tfrr)) > - > -#elif defined (CONFIG_MPC86xx) > -#include > -#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_PIC_OFFSET + \ > - offsetof(ccsr_pic_t, tfrr)) > #endif > > #ifndef _POST_WORD_ADDR > -- > 2.17.1 >