* [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov
@ 2021-05-17 14:39 Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 02/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10* Peng Ju Zhou
` (9 more replies)
0 siblings, 10 replies; 21+ messages in thread
From: Peng Ju Zhou @ 2021-05-17 14:39 UTC (permalink / raw)
To: amd-gfx
This patch series are used for GC/MMHUB(part)/IH_RB_CNTL
indirect access in the SRIOV environment.
There are 4 bits, controlled by host, to control
if GC/MMHUB(part)/IH_RB_CNTL indirect access enabled.
(one bit is master bit controls other 3 bits)
For GC registers, changing all the register access from MMIO to
RLC and use RLC as the default access method in the full access time.
For partial MMHUB registers, changing their access from MMIO to
RLC in the full access time, the remaining registers
keep the original access method.
For IH_RB_CNTL register, changing it's access from MMIO to PSP.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 4 +-
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 78 +++++++++----------
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 ++-
drivers/gpu/drm/amd/amdgpu/soc15_common.h | 87 +++++++++++++---------
6 files changed, 97 insertions(+), 84 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 3147c1c935c8..4e0c90e52ab6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1147,6 +1147,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
* Registers read & write functions.
*/
#define AMDGPU_REGS_NO_KIQ (1<<1)
+#define AMDGPU_REGS_RLC (1<<2)
#define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
#define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 7c6c435e5d02..a2392bbe1e21 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -490,7 +490,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
adev->gfx.rlc.funcs &&
adev->gfx.rlc.funcs->is_rlcg_access_range) {
if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
- return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0);
+ return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0, 0);
} else {
writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
index 4fc2ce8ce8ab..7a4775ab6804 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
@@ -127,8 +127,8 @@ struct amdgpu_rlc_funcs {
void (*reset)(struct amdgpu_device *adev);
void (*start)(struct amdgpu_device *adev);
void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid);
- void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag);
- u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 flag);
+ void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32 acc_flags, u32 hwip);
+ u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip);
bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 2a3427e5020f..7c5c1ff7d97e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1427,38 +1427,36 @@ static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
};
-static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset, uint32_t *flag, bool write)
-{
- /* always programed by rlcg, only for gc */
- if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
- offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
- offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
- offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
- offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
- offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
- if (!amdgpu_sriov_reg_indirect_gc(adev))
- *flag = GFX_RLCG_GC_WRITE_OLD;
- else
- *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
+static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip,
+ int write, u32 *rlcg_flag)
+{
+ switch (hwip) {
+ case GC_HWIP:
+ if (amdgpu_sriov_reg_indirect_gc(adev)) {
+ *rlcg_flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
- return true;
- }
+ return true;
+ /* only in new version, AMDGPU_REGS_NO_KIQ and AMDGPU_REGS_RLC enabled simultaneously */
+ } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags & AMDGPU_REGS_NO_KIQ)) {
+ *rlcg_flag = GFX_RLCG_GC_WRITE_OLD;
- /* currently support gc read/write, mmhub write */
- if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) &&
- offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) {
- if (amdgpu_sriov_reg_indirect_gc(adev))
- *flag = write ? GFX_RLCG_GC_WRITE : GFX_RLCG_GC_READ;
- else
- return false;
- } else {
- if (amdgpu_sriov_reg_indirect_mmhub(adev))
- *flag = GFX_RLCG_MMHUB_WRITE;
- else
- return false;
+ return true;
+ }
+
+ break;
+ case MMHUB_HWIP:
+ if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
+ (acc_flags & AMDGPU_REGS_RLC) && write) {
+ *rlcg_flag = GFX_RLCG_MMHUB_WRITE;
+ return true;
+ }
+
+ break;
+ default:
+ DRM_DEBUG("Not program register by RLCG\n");
}
- return true;
+ return false;
}
static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32_t flag)
@@ -1518,36 +1516,34 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, uint32
return ret;
}
-static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 flag)
+static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 value, u32 acc_flags, u32 hwip)
{
- uint32_t rlcg_flag;
+ u32 rlcg_flag;
- if (amdgpu_sriov_fullaccess(adev) &&
- gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 1)) {
+ if (!amdgpu_sriov_runtime(adev) &&
+ gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
-
return;
}
- if (flag & AMDGPU_REGS_NO_KIQ)
+
+ if (acc_flags & AMDGPU_REGS_NO_KIQ)
WREG32_NO_KIQ(offset, value);
else
WREG32(offset, value);
}
-static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 flag)
+static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32 acc_flags, u32 hwip)
{
- uint32_t rlcg_flag;
+ u32 rlcg_flag;
- if (amdgpu_sriov_fullaccess(adev) &&
- gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 0))
+ if (!amdgpu_sriov_runtime(adev) &&
+ gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
- if (flag & AMDGPU_REGS_NO_KIQ)
+ if (acc_flags & AMDGPU_REGS_NO_KIQ)
return RREG32_NO_KIQ(offset);
else
return RREG32(offset);
-
- return 0;
}
static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index feaa5e4a5538..fe5908f708cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -734,7 +734,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
};
-static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
+static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
{
static void *scratch_reg0;
static void *scratch_reg1;
@@ -787,15 +787,16 @@ static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32
}
-static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
+static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
+ u32 v, u32 acc_flags, u32 hwip)
{
if (amdgpu_sriov_fullaccess(adev)) {
- gfx_v9_0_rlcg_rw(adev, offset, v, flag);
+ gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
return;
}
- if (flag & AMDGPU_REGS_NO_KIQ)
+ if (acc_flags & AMDGPU_REGS_NO_KIQ)
WREG32_NO_KIQ(offset, v);
else
WREG32(offset, v);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index 14bd794bbea6..c781808e4dc3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -27,28 +27,51 @@
/* Register Access Macros */
#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
+#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
+ ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
+ adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
+ WREG32(reg, value))
+
+#define __RREG32_SOC15_RLC__(reg, flag, hwip) \
+ ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
+ adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
+ RREG32(reg))
+
#define WREG32_FIELD15(ip, idx, reg, field, val) \
- WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
- (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
- & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
+ __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
+ (__RREG32_SOC15_RLC__( \
+ adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
+ 0, ip##_HWIP) & \
+ ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
+ 0, ip##_HWIP)
#define RREG32_SOC15(ip, inst, reg) \
- RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
+ __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
+ 0, ip##_HWIP)
+
+#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP)
#define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
- RREG32_NO_KIQ(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
+ __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
+ AMDGPU_REGS_NO_KIQ, ip##_HWIP)
#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
- RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
+ __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_HWIP)
#define WREG32_SOC15(ip, inst, reg, value) \
- WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
+ __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
+ value, 0, ip##_HWIP)
+
+#define WREG32_SOC15_IP(ip, reg, value) \
+ __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
- WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
+ __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
+ value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
- WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
+ __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
+ value, 0, ip##_HWIP)
#define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
({ int ret = 0; \
@@ -77,12 +100,7 @@
})
#define WREG32_RLC(reg, value) \
- do { \
- if (adev->gfx.rlc.funcs->rlcg_wreg) \
- adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, 0); \
- else \
- WREG32(reg, value); \
- } while (0)
+ __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
#define WREG32_RLC_EX(prefix, reg, value) \
do { \
@@ -108,24 +126,19 @@
} \
} while (0)
+/* shadow the registers in the callback function */
#define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
- WREG32_RLC((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
+ __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP)
+/* for GC only */
#define RREG32_RLC(reg) \
- (adev->gfx.rlc.funcs->rlcg_rreg ? \
- adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, 0) : RREG32(reg))
-
-#define WREG32_RLC_NO_KIQ(reg, value) \
- do { \
- if (adev->gfx.rlc.funcs->rlcg_wreg) \
- adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, AMDGPU_REGS_NO_KIQ); \
- else \
- WREG32_NO_KIQ(reg, value); \
- } while (0)
+ __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
+
+#define WREG32_RLC_NO_KIQ(reg, value, hwip) \
+ __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
-#define RREG32_RLC_NO_KIQ(reg) \
- (adev->gfx.rlc.funcs->rlcg_rreg ? \
- adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, AMDGPU_REGS_NO_KIQ) : RREG32_NO_KIQ(reg))
+#define RREG32_RLC_NO_KIQ(reg, hwip) \
+ __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip)
#define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \
do { \
@@ -146,12 +159,12 @@
} while (0)
#define RREG32_SOC15_RLC(ip, inst, reg) \
- RREG32_RLC(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
+ __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP)
#define WREG32_SOC15_RLC(ip, inst, reg, value) \
do { \
uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
- WREG32_RLC(target_reg, value); \
+ __WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP); \
} while (0)
#define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \
@@ -161,14 +174,16 @@
} while (0)
#define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \
- WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
- (RREG32_RLC(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
- & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
+ __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
+ (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
+ AMDGPU_REGS_RLC, ip##_HWIP) & \
+ ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \
+ AMDGPU_REGS_RLC, ip##_HWIP)
#define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
- WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value)
+ __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP)
#define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \
- RREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset))
+ __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP)
#endif
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v5 02/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10*
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
@ 2021-05-17 14:39 ` Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 03/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10* Peng Ju Zhou
` (8 subsequent siblings)
9 siblings, 0 replies; 21+ messages in thread
From: Peng Ju Zhou @ 2021-05-17 14:39 UTC (permalink / raw)
To: amd-gfx
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 32 +++++++++++++-------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 7c5c1ff7d97e..952a2f0f2f4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -5178,10 +5178,10 @@ static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
uint32_t tmp;
/* enable Save Restore Machine */
- tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
+ tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
- WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
+ WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
}
static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
@@ -7876,12 +7876,12 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
{
u32 reg, data;
-
+ /* not for *_SOC15 */
reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
if (amdgpu_sriov_is_pp_one_vf(adev))
data = RREG32_NO_KIQ(reg);
else
- data = RREG32(reg);
+ data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
@@ -8621,16 +8621,16 @@ gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
- cp_int_cntl = RREG32(cp_int_cntl_reg);
+ cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
TIME_STAMP_INT_ENABLE, 0);
- WREG32(cp_int_cntl_reg, cp_int_cntl);
+ WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
break;
case AMDGPU_IRQ_STATE_ENABLE:
- cp_int_cntl = RREG32(cp_int_cntl_reg);
+ cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
TIME_STAMP_INT_ENABLE, 1);
- WREG32(cp_int_cntl_reg, cp_int_cntl);
+ WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
break;
default:
break;
@@ -8674,16 +8674,16 @@ static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev
switch (state) {
case AMDGPU_IRQ_STATE_DISABLE:
- mec_int_cntl = RREG32(mec_int_cntl_reg);
+ mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
TIME_STAMP_INT_ENABLE, 0);
- WREG32(mec_int_cntl_reg, mec_int_cntl);
+ WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
break;
case AMDGPU_IRQ_STATE_ENABLE:
- mec_int_cntl = RREG32(mec_int_cntl_reg);
+ mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
TIME_STAMP_INT_ENABLE, 1);
- WREG32(mec_int_cntl_reg, mec_int_cntl);
+ WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
break;
default:
break;
@@ -8879,20 +8879,20 @@ static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
GENERIC2_INT_ENABLE, 0);
WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
- tmp = RREG32(target);
+ tmp = RREG32_SOC15_IP(GC, target);
tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
GENERIC2_INT_ENABLE, 0);
- WREG32(target, tmp);
+ WREG32_SOC15_IP(GC, target, tmp);
} else {
tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
GENERIC2_INT_ENABLE, 1);
WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
- tmp = RREG32(target);
+ tmp = RREG32_SOC15_IP(GC, target);
tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
GENERIC2_INT_ENABLE, 1);
- WREG32(target, tmp);
+ WREG32_SOC15_IP(GC, target, tmp);
}
break;
default:
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v5 03/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10*
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 02/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10* Peng Ju Zhou
@ 2021-05-17 14:39 ` Peng Ju Zhou
2021-05-20 4:33 ` Felix Kuehling
2021-05-17 14:39 ` [PATCH v5 04/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c Peng Ju Zhou
` (7 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Peng Ju Zhou @ 2021-05-17 14:39 UTC (permalink / raw)
To: amd-gfx
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
.../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 42 +++++++++----------
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
index 62aa1a6f64ed..491acdf92f73 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
@@ -96,8 +96,8 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
lock_srbm(kgd, 0, 0, 0, vmid);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
+ WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
+ WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
/* APE1 no longer exists on GFX9 */
unlock_srbm(kgd);
@@ -161,7 +161,7 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
lock_srbm(kgd, mec, pipe, 0, 0);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
+ WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
@@ -239,13 +239,13 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
for (reg = hqd_base;
reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
- WREG32(reg, mqd_hqd[reg - hqd_base]);
+ WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
/* Activate doorbell logic before triggering WPTR poll. */
data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
if (wptr) {
/* Don't read wptr with get_user because the user
@@ -274,27 +274,27 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
lower_32_bits(guessed_wptr));
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
upper_32_bits(guessed_wptr));
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
lower_32_bits((uint64_t)wptr));
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
+ WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
upper_32_bits((uint64_t)wptr));
pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
(uint32_t)get_queue_mask(adev, pipe_id, queue_id));
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
+ WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
(uint32_t)get_queue_mask(adev, pipe_id, queue_id));
}
/* Start the EOP fetcher */
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
+ WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR,
REG_SET_FIELD(m->cp_hqd_eop_rptr,
CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
+ WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
release_queue(kgd);
@@ -365,7 +365,7 @@ static int kgd_hqd_dump(struct kgd_dev *kgd,
if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
break; \
(*dump)[i][0] = (addr) << 2; \
- (*dump)[i++][1] = RREG32(addr); \
+ (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \
} while (0)
*dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
@@ -497,13 +497,13 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
uint32_t low, high;
acquire_queue(kgd, pipe_id, queue_id);
- act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+ act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
if (act) {
low = lower_32_bits(queue_address >> 8);
high = upper_32_bits(queue_address >> 8);
- if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
- high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
+ if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
+ high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
retval = true;
}
release_queue(kgd);
@@ -621,11 +621,11 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
preempt_enable();
#endif
- WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
+ WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
end_jiffies = (utimeout * HZ / 1000) + jiffies;
while (true) {
- temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
+ temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
break;
if (time_after(jiffies, end_jiffies)) {
@@ -716,8 +716,8 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd,
mutex_lock(&adev->grbm_idx_mutex);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
+ WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
+ WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd);
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
INSTANCE_BROADCAST_WRITES, 1);
@@ -726,7 +726,7 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd,
data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
SE_BROADCAST_WRITES, 1);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
+ WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
mutex_unlock(&adev->grbm_idx_mutex);
return 0;
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v5 04/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 02/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10* Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 03/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10* Peng Ju Zhou
@ 2021-05-17 14:39 ` Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 05/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file sdma_v5* Peng Ju Zhou
` (6 subsequent siblings)
9 siblings, 0 replies; 21+ messages in thread
From: Peng Ju Zhou @ 2021-05-17 14:39 UTC (permalink / raw)
To: amd-gfx
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 080e715799d4..50f6574e1d35 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -632,7 +632,9 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
if (entry->and_mask == 0xffffffff) {
tmp = entry->or_mask;
} else {
- tmp = RREG32(reg);
+ tmp = (entry->hwip == GC_HWIP) ?
+ RREG32_SOC15_IP(GC, reg) : RREG32(reg);
+
tmp &= ~(entry->and_mask);
tmp |= (entry->or_mask & entry->and_mask);
}
@@ -643,7 +645,8 @@ void soc15_program_register_sequence(struct amdgpu_device *adev,
reg == SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG))
WREG32_RLC(reg, tmp);
else
- WREG32(reg, tmp);
+ (entry->hwip == GC_HWIP) ?
+ WREG32_SOC15_IP(GC, reg, tmp) : WREG32(reg, tmp);
}
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v5 05/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file sdma_v5*
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
` (2 preceding siblings ...)
2021-05-17 14:39 ` [PATCH v5 04/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c Peng Ju Zhou
@ 2021-05-17 14:39 ` Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 06/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c Peng Ju Zhou
` (5 subsequent siblings)
9 siblings, 0 replies; 21+ messages in thread
From: Peng Ju Zhou @ 2021-05-17 14:39 UTC (permalink / raw)
To: amd-gfx
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 78 ++++++++++++++------------
1 file changed, 42 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 04c68a79eca4..e5dded824afa 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -324,9 +324,9 @@ static uint64_t sdma_v5_0_ring_get_wptr(struct amdgpu_ring *ring)
wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs]));
DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
} else {
- wptr = RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
+ wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
wptr = wptr << 32;
- wptr |= RREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
+ wptr |= RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
}
@@ -367,9 +367,9 @@ static void sdma_v5_0_ring_set_wptr(struct amdgpu_ring *ring)
lower_32_bits(ring->wptr << 2),
ring->me,
upper_32_bits(ring->wptr << 2));
- WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
lower_32_bits(ring->wptr << 2));
- WREG32(sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
upper_32_bits(ring->wptr << 2));
}
}
@@ -545,12 +545,12 @@ static void sdma_v5_0_gfx_stop(struct amdgpu_device *adev)
amdgpu_ttm_set_buffer_funcs_status(adev, false);
for (i = 0; i < adev->sdma.num_instances; i++) {
- rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
+ rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
- ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+ ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
}
}
@@ -611,11 +611,11 @@ static void sdma_v5_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
}
if (enable && amdgpu_sdma_phase_quantum) {
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
phase_quantum);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
phase_quantum);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
phase_quantum);
}
if (!amdgpu_sriov_vf(adev))
@@ -682,58 +682,63 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
/* Set ring buffer size in dwords */
rb_bufsz = order_base_2(ring->ring_size / 4);
- rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
+ rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
#ifdef __BIG_ENDIAN
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
RPTR_WRITEBACK_SWAP_ENABLE, 1);
#endif
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
/* Initialize the ring buffer's read and write pointers */
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
/* setup the wptr shadow polling */
wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
lower_32_bits(wptr_gpu_addr));
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
upper_32_bits(wptr_gpu_addr));
- wptr_poll_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i,
+ wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
SDMA0_GFX_RB_WPTR_POLL_CNTL,
F32_POLL_ENABLE, 1);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
wptr_poll_cntl);
/* set the wb address whether it's enabled or not */
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE),
+ ring->gpu_addr >> 8);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
+ ring->gpu_addr >> 40);
ring->wptr = 0;
/* before programing wptr to a less value, need set minor_ptr_update first */
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
+ WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR),
+ lower_32_bits(ring->wptr) << 2);
+ WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
+ upper_32_bits(ring->wptr) << 2);
}
- doorbell = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
- doorbell_offset = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
+ doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
+ doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i,
+ mmSDMA0_GFX_DOORBELL_OFFSET));
if (ring->use_doorbell) {
doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
@@ -742,8 +747,9 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
} else {
doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
}
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET),
+ doorbell_offset);
adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
ring->doorbell_index, 20);
@@ -752,7 +758,7 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
sdma_v5_0_ring_set_wptr(ring);
/* set minor_ptr_update to 0 after wptr programed */
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
if (!amdgpu_sriov_vf(adev)) {
/* set utc l1 enable flag always to 1 */
@@ -786,15 +792,15 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev)
/* enable DMA RB */
rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
- ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
+ ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
#ifdef __BIG_ENDIAN
ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
#endif
/* enable DMA IBs */
- WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
+ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
ring->sched.ready = true;
--
2.17.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v5 06/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
` (3 preceding siblings ...)
2021-05-17 14:39 ` [PATCH v5 05/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file sdma_v5* Peng Ju Zhou
@ 2021-05-17 14:39 ` Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 07/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c Peng Ju Zhou
` (4 subsequent siblings)
9 siblings, 0 replies; 21+ messages in thread
From: Peng Ju Zhou @ 2021-05-17 14:39 UTC (permalink / raw)
To: amd-gfx
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 32c34470404c..a9ad28fb55b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -466,7 +466,7 @@ void nv_grbm_select(struct amdgpu_device *adev,
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
- WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
+ WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, grbm_gfx_cntl);
}
static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
--
2.17.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v5 07/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
` (4 preceding siblings ...)
2021-05-17 14:39 ` [PATCH v5 06/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c Peng Ju Zhou
@ 2021-05-17 14:39 ` Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 08/10] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2* Peng Ju Zhou
` (3 subsequent siblings)
9 siblings, 0 replies; 21+ messages in thread
From: Peng Ju Zhou @ 2021-05-17 14:39 UTC (permalink / raw)
To: amd-gfx
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 9 +++++++--
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 25 +++++++++++++++++--------
2 files changed, 24 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index a129ecc73869..3313d43bb94a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -629,13 +629,18 @@ void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type,
for (i = 0; i < 16; i++) {
reg = hub->vm_context0_cntl + hub->ctx_distance * i;
- tmp = RREG32(reg);
+ tmp = (hub_type == AMDGPU_GFXHUB_0) ?
+ RREG32_SOC15_IP(GC, reg) :
+ RREG32_SOC15_IP(MMHUB, reg);
+
if (enable)
tmp |= hub->vm_cntx_cntl_vm_fault;
else
tmp &= ~hub->vm_cntx_cntl_vm_fault;
- WREG32(reg, tmp);
+ (hub_type == AMDGPU_GFXHUB_0) ?
+ WREG32_SOC15_IP(GC, reg, tmp) :
+ WREG32_SOC15_IP(MMHUB, reg, tmp);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index c134af6b0ca0..52eba885289d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -229,6 +229,10 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
/* Use register 17 for GART */
const unsigned eng = 17;
unsigned int i;
+ unsigned char hub_ip = 0;
+
+ hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
+ GC_HWIP : MMHUB_HWIP;
spin_lock(&adev->gmc.invalidate_lock);
/*
@@ -242,8 +246,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
if (use_semaphore) {
for (i = 0; i < adev->usec_timeout; i++) {
/* a read return value of 1 means semaphore acuqire */
- tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
- hub->eng_distance * eng);
+ tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
+ hub->eng_distance * eng, hub_ip);
+
if (tmp & 0x1)
break;
udelay(1);
@@ -253,7 +258,9 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
}
- WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
+ WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
+ hub->eng_distance * eng,
+ inv_req, hub_ip);
/*
* Issue a dummy read to wait for the ACK register to be cleared
@@ -261,12 +268,14 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
*/
if ((vmhub == AMDGPU_GFXHUB_0) &&
(adev->asic_type < CHIP_SIENNA_CICHLID))
- RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng);
+ RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
+ hub->eng_distance * eng, hub_ip);
/* Wait for ACK with a delay.*/
for (i = 0; i < adev->usec_timeout; i++) {
- tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
- hub->eng_distance * eng);
+ tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
+ hub->eng_distance * eng, hub_ip);
+
tmp &= 1 << vmid;
if (tmp)
break;
@@ -280,8 +289,8 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
* add semaphore release after invalidation,
* write with 0 means semaphore release
*/
- WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
- hub->eng_distance * eng, 0);
+ WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
+ hub->eng_distance * eng, 0, hub_ip);
spin_unlock(&adev->gmc.invalidate_lock);
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v5 08/10] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2*
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
` (5 preceding siblings ...)
2021-05-17 14:39 ` [PATCH v5 07/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c Peng Ju Zhou
@ 2021-05-17 14:39 ` Peng Ju Zhou
2021-05-20 3:48 ` Alex Deucher
2021-05-17 14:39 ` [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers Peng Ju Zhou
` (2 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Peng Ju Zhou @ 2021-05-17 14:39 UTC (permalink / raw)
To: amd-gfx
From: pengzhou <PengJu.Zhou@amd.com>
In SRIOV environment, KMD should access GC registers
with RLCG if GC indirect access flag enabled.
Signed-off-by: pengzhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 37 +++++++++++++------------
1 file changed, 19 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index ac76081b91d5..e24225b3d42a 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -29,6 +29,7 @@
#include "mmhub/mmhub_2_0_0_default.h"
#include "navi10_enum.h"
+#include "gc/gc_10_1_0_offset.h"
#include "soc15_common.h"
#define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid 0x064d
@@ -165,11 +166,11 @@ static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmi
{
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
hub->ctx_addr_distance * vmid,
lower_32_bits(page_table_base));
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
hub->ctx_addr_distance * vmid,
upper_32_bits(page_table_base));
}
@@ -180,14 +181,14 @@ static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
- WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
(u32)(adev->gmc.gart_start >> 12));
- WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
(u32)(adev->gmc.gart_start >> 44));
- WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
(u32)(adev->gmc.gart_end >> 12));
- WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
(u32)(adev->gmc.gart_end >> 44));
}
@@ -197,9 +198,9 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
uint32_t tmp;
/* Program the AGP BAR */
- WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
- WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
- WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
if (!amdgpu_sriov_vf(adev)) {
/* Program the system aperture low logical page number. */
@@ -308,7 +309,7 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
- WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
}
static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
@@ -370,16 +371,16 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
!adev->gmc.noretry);
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
i * hub->ctx_distance, tmp);
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
i * hub->ctx_addr_distance, 0);
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
i * hub->ctx_addr_distance, 0);
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
i * hub->ctx_addr_distance,
lower_32_bits(adev->vm_manager.max_pfn - 1));
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
i * hub->ctx_addr_distance,
upper_32_bits(adev->vm_manager.max_pfn - 1));
}
@@ -391,9 +392,9 @@ static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
unsigned i;
for (i = 0; i < 18; ++i) {
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
i * hub->eng_addr_distance, 0xffffffff);
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
i * hub->eng_addr_distance, 0x1f);
}
}
@@ -422,7 +423,7 @@ static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
/* Disable all tables */
for (i = 0; i < AMDGPU_NUM_VMID; i++)
- WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
+ WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
i * hub->ctx_distance, 0);
/* Setup TLB control */
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
` (6 preceding siblings ...)
2021-05-17 14:39 ` [PATCH v5 08/10] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2* Peng Ju Zhou
@ 2021-05-17 14:39 ` Peng Ju Zhou
2021-05-20 3:46 ` Alex Deucher
2021-05-17 14:39 ` [PATCH v5 10/10] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV Peng Ju Zhou
2021-05-17 14:49 ` [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Zhou, Peng Ju
9 siblings, 1 reply; 21+ messages in thread
From: Peng Ju Zhou @ 2021-05-17 14:39 UTC (permalink / raw)
To: amd-gfx; +Cc: Victor
use psp to program IH_RB_CNTL* if indirect access
for ih enabled in SRIOV environment.
Signed-off-by: Victor <Victor.Zhao@amd.com>
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +++++++++++++++++--
drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index f4e4040bbd25..2e69cf8db072 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
/* enable_intr field is only valid in ring0 */
if (ih == &adev->irq.ih)
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
- WREG32(ih_regs->ih_rb_cntl, tmp);
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
+ DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+ WREG32(ih_regs->ih_rb_cntl, tmp);
+ }
if (enable) {
ih->enabled = true;
@@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
}
- WREG32(ih_regs->ih_rb_cntl, tmp);
+
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
+ DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+ WREG32(ih_regs->ih_rb_cntl, tmp);
+ }
if (ih == &adev->irq.ih) {
/* set the ih ring 0 writeback address whether it's enabled or not */
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index a9ad28fb55b3..b9c9c4d4606c 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_NAVI12:
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
- amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* [PATCH v5 10/10] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
` (7 preceding siblings ...)
2021-05-17 14:39 ` [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers Peng Ju Zhou
@ 2021-05-17 14:39 ` Peng Ju Zhou
2021-05-20 3:47 ` Alex Deucher
2021-05-17 14:49 ` [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Zhou, Peng Ju
9 siblings, 1 reply; 21+ messages in thread
From: Peng Ju Zhou @ 2021-05-17 14:39 UTC (permalink / raw)
To: amd-gfx
KMD should not program these registers, the value were
defined in the host, so skip them in the SRIOV environment.
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index e24225b3d42a..422d106a650b 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -197,12 +197,12 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
uint64_t value;
uint32_t tmp;
- /* Program the AGP BAR */
- WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
- WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
- WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
-
if (!amdgpu_sriov_vf(adev)) {
+ /* Program the AGP BAR */
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
+ WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
+
/* Program the system aperture low logical page number. */
WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
--
2.17.1
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^ permalink raw reply related [flat|nested] 21+ messages in thread
* RE: [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
` (8 preceding siblings ...)
2021-05-17 14:39 ` [PATCH v5 10/10] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV Peng Ju Zhou
@ 2021-05-17 14:49 ` Zhou, Peng Ju
2021-05-19 14:34 ` Zhou, Peng Ju
9 siblings, 1 reply; 21+ messages in thread
From: Zhou, Peng Ju @ 2021-05-17 14:49 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Deng, Emily, Ming, Davis, Chang, HaiJun
[AMD Official Use Only - Internal Distribution Only]
Hi Alex
About your comment:
"I think patches 1-4, 16 need to be squashed together to avoid breaking the build. Please also provide a description of how the new macros work in the patch description. Describe how the reworked macros properly handle sending GC and MMHUB accesses via the RLC rather than via some other mechanism. It's really hard to follow the macro logic."
I squashed patches 1-4, 16 and add more detail description in the patch description.
Can you help to review the patch series?
----------------------------------------------------------------------
BW
Pengju Zhou
> -----Original Message-----
> From: Peng Ju Zhou <PengJu.Zhou@amd.com>
> Sent: Monday, May 17, 2021 10:39 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Zhou, Peng Ju <PengJu.Zhou@amd.com>
> Subject: [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12
> sriov
>
> This patch series are used for GC/MMHUB(part)/IH_RB_CNTL indirect access
> in the SRIOV environment.
>
> There are 4 bits, controlled by host, to control if
> GC/MMHUB(part)/IH_RB_CNTL indirect access enabled.
> (one bit is master bit controls other 3 bits)
>
> For GC registers, changing all the register access from MMIO to RLC and use
> RLC as the default access method in the full access time.
>
> For partial MMHUB registers, changing their access from MMIO to RLC in the
> full access time, the remaining registers keep the original access method.
>
> For IH_RB_CNTL register, changing it's access from MMIO to PSP.
>
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 4 +-
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 78 +++++++++----------
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 ++-
> drivers/gpu/drm/amd/amdgpu/soc15_common.h | 87 +++++++++++++------
> ---
> 6 files changed, 97 insertions(+), 84 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 3147c1c935c8..4e0c90e52ab6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1147,6 +1147,7 @@ int emu_soc_asic_init(struct amdgpu_device
> *adev);
> * Registers read & write functions.
> */
> #define AMDGPU_REGS_NO_KIQ (1<<1)
> +#define AMDGPU_REGS_RLC (1<<2)
>
> #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg),
> AMDGPU_REGS_NO_KIQ) #define WREG32_NO_KIQ(reg, v)
> amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) diff --git
> a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 7c6c435e5d02..a2392bbe1e21 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -490,7 +490,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct
> amdgpu_device *adev,
> adev->gfx.rlc.funcs &&
> adev->gfx.rlc.funcs->is_rlcg_access_range) {
> if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
> - return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0);
> + return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0,
> 0);
> } else {
> writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> index 4fc2ce8ce8ab..7a4775ab6804 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> @@ -127,8 +127,8 @@ struct amdgpu_rlc_funcs {
> void (*reset)(struct amdgpu_device *adev);
> void (*start)(struct amdgpu_device *adev);
> void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned
> vmid);
> - void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32
> flag);
> - u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 flag);
> + void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32
> acc_flags, u32 hwip);
> + u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32
> +acc_flags, u32 hwip);
> bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t
> reg); };
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 2a3427e5020f..7c5c1ff7d97e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -1427,38 +1427,36 @@ static const struct soc15_reg_golden
> golden_settings_gc_10_1_2[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff,
> 0x00800000) };
>
> -static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset,
> uint32_t *flag, bool write) -{
> - /* always programed by rlcg, only for gc */
> - if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
> - offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
> - offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
> - offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
> - offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
> - offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
> - if (!amdgpu_sriov_reg_indirect_gc(adev))
> - *flag = GFX_RLCG_GC_WRITE_OLD;
> - else
> - *flag = write ? GFX_RLCG_GC_WRITE :
> GFX_RLCG_GC_READ;
> +static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32
> acc_flags, u32 hwip,
> + int write, u32 *rlcg_flag)
> +{
> + switch (hwip) {
> + case GC_HWIP:
> + if (amdgpu_sriov_reg_indirect_gc(adev)) {
> + *rlcg_flag = write ? GFX_RLCG_GC_WRITE :
> GFX_RLCG_GC_READ;
>
> - return true;
> - }
> + return true;
> + /* only in new version, AMDGPU_REGS_NO_KIQ and
> AMDGPU_REGS_RLC enabled simultaneously */
> + } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags &
> AMDGPU_REGS_NO_KIQ)) {
> + *rlcg_flag = GFX_RLCG_GC_WRITE_OLD;
>
> - /* currently support gc read/write, mmhub write */
> - if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) &&
> - offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) {
> - if (amdgpu_sriov_reg_indirect_gc(adev))
> - *flag = write ? GFX_RLCG_GC_WRITE :
> GFX_RLCG_GC_READ;
> - else
> - return false;
> - } else {
> - if (amdgpu_sriov_reg_indirect_mmhub(adev))
> - *flag = GFX_RLCG_MMHUB_WRITE;
> - else
> - return false;
> + return true;
> + }
> +
> + break;
> + case MMHUB_HWIP:
> + if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
> + (acc_flags & AMDGPU_REGS_RLC) && write) {
> + *rlcg_flag = GFX_RLCG_MMHUB_WRITE;
> + return true;
> + }
> +
> + break;
> + default:
> + DRM_DEBUG("Not program register by RLCG\n");
> }
>
> - return true;
> + return false;
> }
>
> static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v,
> uint32_t flag) @@ -1518,36 +1516,34 @@ static u32 gfx_v10_rlcg_rw(struct
> amdgpu_device *adev, u32 offset, u32 v, uint32
> return ret;
> }
>
> -static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32
> value, u32 flag)
> +static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
> +u32 value, u32 acc_flags, u32 hwip)
> {
> - uint32_t rlcg_flag;
> + u32 rlcg_flag;
>
> - if (amdgpu_sriov_fullaccess(adev) &&
> - gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 1)) {
> + if (!amdgpu_sriov_runtime(adev) &&
> + gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
> gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
> -
> return;
> }
> - if (flag & AMDGPU_REGS_NO_KIQ)
> +
> + if (acc_flags & AMDGPU_REGS_NO_KIQ)
> WREG32_NO_KIQ(offset, value);
> else
> WREG32(offset, value);
> }
>
> -static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32
> flag)
> +static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset,
> +u32 acc_flags, u32 hwip)
> {
> - uint32_t rlcg_flag;
> + u32 rlcg_flag;
>
> - if (amdgpu_sriov_fullaccess(adev) &&
> - gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 0))
> + if (!amdgpu_sriov_runtime(adev) &&
> + gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
> return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
>
> - if (flag & AMDGPU_REGS_NO_KIQ)
> + if (acc_flags & AMDGPU_REGS_NO_KIQ)
> return RREG32_NO_KIQ(offset);
> else
> return RREG32(offset);
> -
> - return 0;
> }
>
> static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = diff -
> -git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index feaa5e4a5538..fe5908f708cc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -734,7 +734,7 @@ static const u32
> GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
> mmRLC_SRM_INDEX_CNTL_DATA_7 -
> mmRLC_SRM_INDEX_CNTL_DATA_0, };
>
> -static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v,
> u32 flag)
> +static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32
> +v, u32 flag)
> {
> static void *scratch_reg0;
> static void *scratch_reg1;
> @@ -787,15 +787,16 @@ static void gfx_v9_0_rlcg_rw(struct amdgpu_device
> *adev, u32 offset, u32 v, u32
>
> }
>
> -static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32
> v, u32 flag)
> +static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
> + u32 v, u32 acc_flags, u32 hwip)
> {
> if (amdgpu_sriov_fullaccess(adev)) {
> - gfx_v9_0_rlcg_rw(adev, offset, v, flag);
> + gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
>
> return;
> }
>
> - if (flag & AMDGPU_REGS_NO_KIQ)
> + if (acc_flags & AMDGPU_REGS_NO_KIQ)
> WREG32_NO_KIQ(offset, v);
> else
> WREG32(offset, v);
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index 14bd794bbea6..c781808e4dc3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -27,28 +27,51 @@
> /* Register Access Macros */
> #define SOC15_REG_OFFSET(ip, inst, reg) (adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>
> +#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
> + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
> + adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
> + WREG32(reg, value))
> +
> +#define __RREG32_SOC15_RLC__(reg, flag, hwip) \
> + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
> + adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
> + RREG32(reg))
> +
> #define WREG32_FIELD15(ip, idx, reg, field, val) \
> - WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX]
> + mm##reg, \
> - (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX]
> + mm##reg) \
> - & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg,
> field))
> + __WREG32_SOC15_RLC__(adev-
> >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
> + (__RREG32_SOC15_RLC__( \
> + adev-
> >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
> + 0, ip##_HWIP) & \
> + ~REG_FIELD_MASK(reg, field)) | (val) <<
> REG_FIELD_SHIFT(reg, field), \
> + 0, ip##_HWIP)
>
> #define RREG32_SOC15(ip, inst, reg) \
> - RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> + __RREG32_SOC15_RLC__(adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
> + 0, ip##_HWIP)
> +
> +#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0,
> +ip##_HWIP)
>
> #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
> - RREG32_NO_KIQ(adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> + __RREG32_SOC15_RLC__(adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
> + AMDGPU_REGS_NO_KIQ, ip##_HWIP)
>
> #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
> - RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> + offset)
> +
> +__RREG32_SOC15_RLC__((adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> ++ reg) + offset, 0, ip##_HWIP)
>
> #define WREG32_SOC15(ip, inst, reg, value) \
> - WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg),
> value)
> + __WREG32_SOC15_RLC__((adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
> + value, 0, ip##_HWIP)
> +
> +#define WREG32_SOC15_IP(ip, reg, value) \
> + __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
>
> #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
> - WREG32_NO_KIQ((adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
> + __WREG32_SOC15_RLC__(adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
> + value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
>
> #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
> - WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> + offset, value)
> + __WREG32_SOC15_RLC__((adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
> + value, 0, ip##_HWIP)
>
> #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
> ({ int ret = 0; \
> @@ -77,12 +100,7 @@
> })
>
> #define WREG32_RLC(reg, value) \
> - do { \
> - if (adev->gfx.rlc.funcs->rlcg_wreg) \
> - adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, 0); \
> - else \
> - WREG32(reg, value); \
> - } while (0)
> + __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
>
> #define WREG32_RLC_EX(prefix, reg, value) \
> do { \
> @@ -108,24 +126,19 @@
> } \
> } while (0)
>
> +/* shadow the registers in the callback function */
> #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
> - WREG32_RLC((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> + reg), value)
> +
> +__WREG32_SOC15_RLC__((adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> ++ reg), value, AMDGPU_REGS_RLC, GC_HWIP)
>
> +/* for GC only */
> #define RREG32_RLC(reg) \
> - (adev->gfx.rlc.funcs->rlcg_rreg ? \
> - adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, 0) : RREG32(reg))
> -
> -#define WREG32_RLC_NO_KIQ(reg, value) \
> - do { \
> - if (adev->gfx.rlc.funcs->rlcg_wreg) \
> - adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value,
> AMDGPU_REGS_NO_KIQ); \
> - else \
> - WREG32_NO_KIQ(reg, value); \
> - } while (0)
> + __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
> +
> +#define WREG32_RLC_NO_KIQ(reg, value, hwip) \
> + __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ |
> AMDGPU_REGS_RLC,
> +hwip)
>
> -#define RREG32_RLC_NO_KIQ(reg) \
> - (adev->gfx.rlc.funcs->rlcg_rreg ? \
> - adev->gfx.rlc.funcs->rlcg_rreg(adev, reg,
> AMDGPU_REGS_NO_KIQ) : RREG32_NO_KIQ(reg))
> +#define RREG32_RLC_NO_KIQ(reg, hwip) \
> + __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ |
> AMDGPU_REGS_RLC, hwip)
>
> #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \
> do { \
> @@ -146,12 +159,12 @@
> } while (0)
>
> #define RREG32_SOC15_RLC(ip, inst, reg) \
> - RREG32_RLC(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] +
> reg)
> + __RREG32_SOC15_RLC__(adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> ++ reg, AMDGPU_REGS_RLC, ip##_HWIP)
>
> #define WREG32_SOC15_RLC(ip, inst, reg, value) \
> do { \
> uint32_t target_reg = adev-
> >reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
> - WREG32_RLC(target_reg, value); \
> + __WREG32_SOC15_RLC__(target_reg, value,
> AMDGPU_REGS_RLC, ip##_HWIP);
> +\
> } while (0)
>
> #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \ @@ -161,14
> +174,16 @@
> } while (0)
>
> #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \
> - WREG32_RLC((adev-
> >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
> - (RREG32_RLC(adev-
> >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
> - & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg,
> field))
> + __WREG32_SOC15_RLC__((adev-
> >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
> + (__RREG32_SOC15_RLC__(adev-
> >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
> + AMDGPU_REGS_RLC,
> ip##_HWIP) & \
> + ~REG_FIELD_MASK(reg, field)) | (val) <<
> REG_FIELD_SHIFT(reg, field), \
> + AMDGPU_REGS_RLC, ip##_HWIP)
>
> #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
> - WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> + reg) + offset), value)
> +
> +__WREG32_SOC15_RLC__((adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> ++ reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP)
>
> #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \
> - RREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] +
> reg) + offset))
> +
> +__RREG32_SOC15_RLC__((adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> ++ reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP)
>
> #endif
> --
> 2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov
2021-05-17 14:49 ` [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Zhou, Peng Ju
@ 2021-05-19 14:34 ` Zhou, Peng Ju
2021-05-25 15:18 ` Ming, Davis
0 siblings, 1 reply; 21+ messages in thread
From: Zhou, Peng Ju @ 2021-05-19 14:34 UTC (permalink / raw)
To: Zhou, Peng Ju, Alex Deucher, amd-gfx
Cc: Deng, Emily, Ming, Davis, Chang, HaiJun
[AMD Official Use Only - Internal Distribution Only]
Ping on this series.
----------------------------------------------------------------------
BW
Pengju Zhou
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhou,
> Peng Ju
> Sent: Monday, May 17, 2021 10:50 PM
> To: Alex Deucher <alexdeucher@gmail.com>; amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily <Emily.Deng@amd.com>; Ming, Davis
> <Davis.Ming@amd.com>; Chang, HaiJun <HaiJun.Chang@amd.com>
> Subject: RE: [PATCH v5 01/10] drm/amdgpu: Indirect register access for
> Navi12 sriov
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex
> About your comment:
> "I think patches 1-4, 16 need to be squashed together to avoid breaking the
> build. Please also provide a description of how the new macros work in the
> patch description. Describe how the reworked macros properly handle
> sending GC and MMHUB accesses via the RLC rather than via some other
> mechanism. It's really hard to follow the macro logic."
>
> I squashed patches 1-4, 16 and add more detail description in the patch
> description.
> Can you help to review the patch series?
>
>
> ----------------------------------------------------------------------
> BW
> Pengju Zhou
>
>
>
> > -----Original Message-----
> > From: Peng Ju Zhou <PengJu.Zhou@amd.com>
> > Sent: Monday, May 17, 2021 10:39 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Zhou, Peng Ju <PengJu.Zhou@amd.com>
> > Subject: [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12
> > sriov
> >
> > This patch series are used for GC/MMHUB(part)/IH_RB_CNTL indirect
> access
> > in the SRIOV environment.
> >
> > There are 4 bits, controlled by host, to control if
> > GC/MMHUB(part)/IH_RB_CNTL indirect access enabled.
> > (one bit is master bit controls other 3 bits)
> >
> > For GC registers, changing all the register access from MMIO to RLC and use
> > RLC as the default access method in the full access time.
> >
> > For partial MMHUB registers, changing their access from MMIO to RLC in
> the
> > full access time, the remaining registers keep the original access method.
> >
> > For IH_RB_CNTL register, changing it's access from MMIO to PSP.
> >
> > Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 4 +-
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 78 +++++++++----------
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 ++-
> > drivers/gpu/drm/amd/amdgpu/soc15_common.h | 87 +++++++++++++----
> --
> > ---
> > 6 files changed, 97 insertions(+), 84 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 3147c1c935c8..4e0c90e52ab6 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -1147,6 +1147,7 @@ int emu_soc_asic_init(struct amdgpu_device
> > *adev);
> > * Registers read & write functions.
> > */
> > #define AMDGPU_REGS_NO_KIQ (1<<1)
> > +#define AMDGPU_REGS_RLC (1<<2)
> >
> > #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg),
> > AMDGPU_REGS_NO_KIQ) #define WREG32_NO_KIQ(reg, v)
> > amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) diff --git
> > a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 7c6c435e5d02..a2392bbe1e21 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -490,7 +490,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct
> > amdgpu_device *adev,
> > adev->gfx.rlc.funcs &&
> > adev->gfx.rlc.funcs->is_rlcg_access_range) {
> > if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
> > - return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0);
> > + return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0,
> > 0);
> > } else {
> > writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
> > }
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> > index 4fc2ce8ce8ab..7a4775ab6804 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> > @@ -127,8 +127,8 @@ struct amdgpu_rlc_funcs {
> > void (*reset)(struct amdgpu_device *adev);
> > void (*start)(struct amdgpu_device *adev);
> > void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned
> > vmid);
> > - void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32
> > flag);
> > - u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 flag);
> > + void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32
> > acc_flags, u32 hwip);
> > + u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32
> > +acc_flags, u32 hwip);
> > bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t
> > reg); };
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index 2a3427e5020f..7c5c1ff7d97e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -1427,38 +1427,36 @@ static const struct soc15_reg_golden
> > golden_settings_gc_10_1_2[] =
> > SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff,
> > 0x00800000) };
> >
> > -static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset,
> > uint32_t *flag, bool write) -{
> > - /* always programed by rlcg, only for gc */
> > - if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
> > - offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
> > - offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
> > - offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
> > - offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
> > - offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
> > - if (!amdgpu_sriov_reg_indirect_gc(adev))
> > - *flag = GFX_RLCG_GC_WRITE_OLD;
> > - else
> > - *flag = write ? GFX_RLCG_GC_WRITE :
> > GFX_RLCG_GC_READ;
> > +static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32
> > acc_flags, u32 hwip,
> > + int write, u32 *rlcg_flag)
> > +{
> > + switch (hwip) {
> > + case GC_HWIP:
> > + if (amdgpu_sriov_reg_indirect_gc(adev)) {
> > + *rlcg_flag = write ? GFX_RLCG_GC_WRITE :
> > GFX_RLCG_GC_READ;
> >
> > - return true;
> > - }
> > + return true;
> > + /* only in new version, AMDGPU_REGS_NO_KIQ and
> > AMDGPU_REGS_RLC enabled simultaneously */
> > + } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags &
> > AMDGPU_REGS_NO_KIQ)) {
> > + *rlcg_flag = GFX_RLCG_GC_WRITE_OLD;
> >
> > - /* currently support gc read/write, mmhub write */
> > - if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) &&
> > - offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) {
> > - if (amdgpu_sriov_reg_indirect_gc(adev))
> > - *flag = write ? GFX_RLCG_GC_WRITE :
> > GFX_RLCG_GC_READ;
> > - else
> > - return false;
> > - } else {
> > - if (amdgpu_sriov_reg_indirect_mmhub(adev))
> > - *flag = GFX_RLCG_MMHUB_WRITE;
> > - else
> > - return false;
> > + return true;
> > + }
> > +
> > + break;
> > + case MMHUB_HWIP:
> > + if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
> > + (acc_flags & AMDGPU_REGS_RLC) && write) {
> > + *rlcg_flag = GFX_RLCG_MMHUB_WRITE;
> > + return true;
> > + }
> > +
> > + break;
> > + default:
> > + DRM_DEBUG("Not program register by RLCG\n");
> > }
> >
> > - return true;
> > + return false;
> > }
> >
> > static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v,
> > uint32_t flag) @@ -1518,36 +1516,34 @@ static u32 gfx_v10_rlcg_rw(struct
> > amdgpu_device *adev, u32 offset, u32 v, uint32
> > return ret;
> > }
> >
> > -static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32
> > value, u32 flag)
> > +static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
> > +u32 value, u32 acc_flags, u32 hwip)
> > {
> > - uint32_t rlcg_flag;
> > + u32 rlcg_flag;
> >
> > - if (amdgpu_sriov_fullaccess(adev) &&
> > - gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 1)) {
> > + if (!amdgpu_sriov_runtime(adev) &&
> > + gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
> > gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
> > -
> > return;
> > }
> > - if (flag & AMDGPU_REGS_NO_KIQ)
> > +
> > + if (acc_flags & AMDGPU_REGS_NO_KIQ)
> > WREG32_NO_KIQ(offset, value);
> > else
> > WREG32(offset, value);
> > }
> >
> > -static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32
> > flag)
> > +static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset,
> > +u32 acc_flags, u32 hwip)
> > {
> > - uint32_t rlcg_flag;
> > + u32 rlcg_flag;
> >
> > - if (amdgpu_sriov_fullaccess(adev) &&
> > - gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 0))
> > + if (!amdgpu_sriov_runtime(adev) &&
> > + gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
> > return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
> >
> > - if (flag & AMDGPU_REGS_NO_KIQ)
> > + if (acc_flags & AMDGPU_REGS_NO_KIQ)
> > return RREG32_NO_KIQ(offset);
> > else
> > return RREG32(offset);
> > -
> > - return 0;
> > }
> >
> > static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = diff
> -
> > -git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index feaa5e4a5538..fe5908f708cc 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -734,7 +734,7 @@ static const u32
> > GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
> > mmRLC_SRM_INDEX_CNTL_DATA_7 -
> > mmRLC_SRM_INDEX_CNTL_DATA_0, };
> >
> > -static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32
> v,
> > u32 flag)
> > +static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32
> > +v, u32 flag)
> > {
> > static void *scratch_reg0;
> > static void *scratch_reg1;
> > @@ -787,15 +787,16 @@ static void gfx_v9_0_rlcg_rw(struct
> amdgpu_device
> > *adev, u32 offset, u32 v, u32
> >
> > }
> >
> > -static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
> u32
> > v, u32 flag)
> > +static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
> > + u32 v, u32 acc_flags, u32 hwip)
> > {
> > if (amdgpu_sriov_fullaccess(adev)) {
> > - gfx_v9_0_rlcg_rw(adev, offset, v, flag);
> > + gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
> >
> > return;
> > }
> >
> > - if (flag & AMDGPU_REGS_NO_KIQ)
> > + if (acc_flags & AMDGPU_REGS_NO_KIQ)
> > WREG32_NO_KIQ(offset, v);
> > else
> > WREG32(offset, v);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> > b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> > index 14bd794bbea6..c781808e4dc3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> > @@ -27,28 +27,51 @@
> > /* Register Access Macros */
> > #define SOC15_REG_OFFSET(ip, inst, reg) (adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> >
> > +#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
> > + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
> > + adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
> > + WREG32(reg, value))
> > +
> > +#define __RREG32_SOC15_RLC__(reg, flag, hwip) \
> > + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
> > + adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
> > + RREG32(reg))
> > +
> > #define WREG32_FIELD15(ip, idx, reg, field, val) \
> > - WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX]
> > + mm##reg, \
> > - (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX]
> > + mm##reg) \
> > - & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg,
> > field))
> > + __WREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
> > + (__RREG32_SOC15_RLC__( \
> > + adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
> > + 0, ip##_HWIP) & \
> > + ~REG_FIELD_MASK(reg, field)) | (val) <<
> > REG_FIELD_SHIFT(reg, field), \
> > + 0, ip##_HWIP)
> >
> > #define RREG32_SOC15(ip, inst, reg) \
> > - RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> > + __RREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
> > + 0, ip##_HWIP)
> > +
> > +#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0,
> > +ip##_HWIP)
> >
> > #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
> > - RREG32_NO_KIQ(adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> > + __RREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
> > + AMDGPU_REGS_NO_KIQ, ip##_HWIP)
> >
> > #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
> > - RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> > + offset)
> > +
> > +__RREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > ++ reg) + offset, 0, ip##_HWIP)
> >
> > #define WREG32_SOC15(ip, inst, reg, value) \
> > - WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg),
> > value)
> > + __WREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
> > + value, 0, ip##_HWIP)
> > +
> > +#define WREG32_SOC15_IP(ip, reg, value) \
> > + __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
> >
> > #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
> > - WREG32_NO_KIQ((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
> > + __WREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
> > + value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
> >
> > #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
> > - WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> > + offset, value)
> > + __WREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
> > + value, 0, ip##_HWIP)
> >
> > #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
> > ({ int ret = 0; \
> > @@ -77,12 +100,7 @@
> > })
> >
> > #define WREG32_RLC(reg, value) \
> > - do { \
> > - if (adev->gfx.rlc.funcs->rlcg_wreg) \
> > - adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, 0); \
> > - else \
> > - WREG32(reg, value); \
> > - } while (0)
> > + __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
> >
> > #define WREG32_RLC_EX(prefix, reg, value) \
> > do { \
> > @@ -108,24 +126,19 @@
> > } \
> > } while (0)
> >
> > +/* shadow the registers in the callback function */
> > #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
> > - WREG32_RLC((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > + reg), value)
> > +
> > +__WREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > ++ reg), value, AMDGPU_REGS_RLC, GC_HWIP)
> >
> > +/* for GC only */
> > #define RREG32_RLC(reg) \
> > - (adev->gfx.rlc.funcs->rlcg_rreg ? \
> > - adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, 0) : RREG32(reg))
> > -
> > -#define WREG32_RLC_NO_KIQ(reg, value) \
> > - do { \
> > - if (adev->gfx.rlc.funcs->rlcg_wreg) \
> > - adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value,
> > AMDGPU_REGS_NO_KIQ); \
> > - else \
> > - WREG32_NO_KIQ(reg, value); \
> > - } while (0)
> > + __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
> > +
> > +#define WREG32_RLC_NO_KIQ(reg, value, hwip) \
> > + __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ |
> > AMDGPU_REGS_RLC,
> > +hwip)
> >
> > -#define RREG32_RLC_NO_KIQ(reg) \
> > - (adev->gfx.rlc.funcs->rlcg_rreg ? \
> > - adev->gfx.rlc.funcs->rlcg_rreg(adev, reg,
> > AMDGPU_REGS_NO_KIQ) : RREG32_NO_KIQ(reg))
> > +#define RREG32_RLC_NO_KIQ(reg, hwip) \
> > + __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ |
> > AMDGPU_REGS_RLC, hwip)
> >
> > #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \
> > do { \
> > @@ -146,12 +159,12 @@
> > } while (0)
> >
> > #define RREG32_SOC15_RLC(ip, inst, reg) \
> > - RREG32_RLC(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] +
> > reg)
> > + __RREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > ++ reg, AMDGPU_REGS_RLC, ip##_HWIP)
> >
> > #define WREG32_SOC15_RLC(ip, inst, reg, value) \
> > do { \
> > uint32_t target_reg = adev-
> > >reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
> > - WREG32_RLC(target_reg, value); \
> > + __WREG32_SOC15_RLC__(target_reg, value,
> > AMDGPU_REGS_RLC, ip##_HWIP);
> > +\
> > } while (0)
> >
> > #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \ @@ -161,14
> > +174,16 @@
> > } while (0)
> >
> > #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \
> > - WREG32_RLC((adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
> > - (RREG32_RLC(adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
> > - & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg,
> > field))
> > + __WREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
> > + (__RREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
> > + AMDGPU_REGS_RLC,
> > ip##_HWIP) & \
> > + ~REG_FIELD_MASK(reg, field)) | (val) <<
> > REG_FIELD_SHIFT(reg, field), \
> > + AMDGPU_REGS_RLC, ip##_HWIP)
> >
> > #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
> > - WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > + reg) + offset), value)
> > +
> > +__WREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > ++ reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP)
> >
> > #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \
> > - RREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] +
> > reg) + offset))
> > +
> > +__RREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > ++ reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP)
> >
> > #endif
> > --
> > 2.17.1
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.f
> reedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfx&data=04%7C01%7CPengju.Zhou%40amd.com%7C5593a422cc7e48b
> 80f6c08d9194308ae%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7
> C637568597973904052%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAw
> MDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sd
> ata=a4brqHQ43K6fkF%2BAgWWclhZdgEs2SpThk%2BFYcmaInTM%3D&r
> eserved=0
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers
2021-05-17 14:39 ` [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers Peng Ju Zhou
@ 2021-05-20 3:46 ` Alex Deucher
2021-05-21 9:58 ` Zhou, Peng Ju
0 siblings, 1 reply; 21+ messages in thread
From: Alex Deucher @ 2021-05-20 3:46 UTC (permalink / raw)
To: Peng Ju Zhou; +Cc: Victor, amd-gfx list
On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou <PengJu.Zhou@amd.com> wrote:
>
> use psp to program IH_RB_CNTL* if indirect access
> for ih enabled in SRIOV environment.
>
> Signed-off-by: Victor <Victor.Zhao@amd.com>
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +++++++++++++++++--
> drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
> 2 files changed, 18 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> index f4e4040bbd25..2e69cf8db072 100644
> --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> @@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
> /* enable_intr field is only valid in ring0 */
> if (ih == &adev->irq.ih)
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
> - WREG32(ih_regs->ih_rb_cntl, tmp);
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> + return -ETIMEDOUT;
> + }
> + } else {
> + WREG32(ih_regs->ih_rb_cntl, tmp);
> + }
>
> if (enable) {
> ih->enabled = true;
> @@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev,
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
> tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
> }
> - WREG32(ih_regs->ih_rb_cntl, tmp);
> +
> + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> + return -ETIMEDOUT;
> + }
> + } else {
> + WREG32(ih_regs->ih_rb_cntl, tmp);
> + }
>
> if (ih == &adev->irq.ih) {
> /* set the ih ring 0 writeback address whether it's enabled or not */
> diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
> index a9ad28fb55b3..b9c9c4d4606c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> case CHIP_NAVI12:
> amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
> + amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
Is it safe to change the order like this on bare metal? Please look
at what was done for vega and sienna cichlid. Something like that is
probably a better bet.
Alex
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
> amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v5 10/10] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV
2021-05-17 14:39 ` [PATCH v5 10/10] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV Peng Ju Zhou
@ 2021-05-20 3:47 ` Alex Deucher
0 siblings, 0 replies; 21+ messages in thread
From: Alex Deucher @ 2021-05-20 3:47 UTC (permalink / raw)
To: Peng Ju Zhou; +Cc: amd-gfx list
On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou <PengJu.Zhou@amd.com> wrote:
>
> KMD should not program these registers, the value were
> defined in the host, so skip them in the SRIOV environment.
>
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> index e24225b3d42a..422d106a650b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> @@ -197,12 +197,12 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
> uint64_t value;
> uint32_t tmp;
>
> - /* Program the AGP BAR */
> - WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
> - WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
> - WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
> -
> if (!amdgpu_sriov_vf(adev)) {
> + /* Program the AGP BAR */
> + WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
> + WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
> + WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
> +
> /* Program the system aperture low logical page number. */
> WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
> min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v5 08/10] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2*
2021-05-17 14:39 ` [PATCH v5 08/10] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2* Peng Ju Zhou
@ 2021-05-20 3:48 ` Alex Deucher
0 siblings, 0 replies; 21+ messages in thread
From: Alex Deucher @ 2021-05-20 3:48 UTC (permalink / raw)
To: Peng Ju Zhou; +Cc: amd-gfx list
On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou <PengJu.Zhou@amd.com> wrote:
>
> From: pengzhou <PengJu.Zhou@amd.com>
>
> In SRIOV environment, KMD should access GC registers
> with RLCG if GC indirect access flag enabled.
>
> Signed-off-by: pengzhou <PengJu.Zhou@amd.com>
Patches 1-8 are:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
See my comments on patch 9.
Alex
> ---
> drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c | 37 +++++++++++++------------
> 1 file changed, 19 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> index ac76081b91d5..e24225b3d42a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
> @@ -29,6 +29,7 @@
> #include "mmhub/mmhub_2_0_0_default.h"
> #include "navi10_enum.h"
>
> +#include "gc/gc_10_1_0_offset.h"
> #include "soc15_common.h"
>
> #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid 0x064d
> @@ -165,11 +166,11 @@ static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmi
> {
> struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
>
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
> + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
> hub->ctx_addr_distance * vmid,
> lower_32_bits(page_table_base));
>
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
> + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
> hub->ctx_addr_distance * vmid,
> upper_32_bits(page_table_base));
> }
> @@ -180,14 +181,14 @@ static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
>
> mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
>
> - WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
> + WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
> (u32)(adev->gmc.gart_start >> 12));
> - WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
> + WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
> (u32)(adev->gmc.gart_start >> 44));
>
> - WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
> + WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
> (u32)(adev->gmc.gart_end >> 12));
> - WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
> + WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
> (u32)(adev->gmc.gart_end >> 44));
> }
>
> @@ -197,9 +198,9 @@ static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
> uint32_t tmp;
>
> /* Program the AGP BAR */
> - WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
> - WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
> - WREG32_SOC15(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
> + WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
> + WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
> + WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
>
> if (!amdgpu_sriov_vf(adev)) {
> /* Program the system aperture low logical page number. */
> @@ -308,7 +309,7 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
> RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
> - WREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
> + WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
> }
>
> static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
> @@ -370,16 +371,16 @@ static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
> tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
> RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
> !adev->gmc.noretry);
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
> + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
> i * hub->ctx_distance, tmp);
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
> + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
> i * hub->ctx_addr_distance, 0);
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
> + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
> i * hub->ctx_addr_distance, 0);
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
> + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
> i * hub->ctx_addr_distance,
> lower_32_bits(adev->vm_manager.max_pfn - 1));
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
> i * hub->ctx_addr_distance,
> upper_32_bits(adev->vm_manager.max_pfn - 1));
> }
> @@ -391,9 +392,9 @@ static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
> unsigned i;
>
> for (i = 0; i < 18; ++i) {
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
> + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
> i * hub->eng_addr_distance, 0xffffffff);
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
> + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
> i * hub->eng_addr_distance, 0x1f);
> }
> }
> @@ -422,7 +423,7 @@ static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
>
> /* Disable all tables */
> for (i = 0; i < AMDGPU_NUM_VMID; i++)
> - WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
> + WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
> i * hub->ctx_distance, 0);
>
> /* Setup TLB control */
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v5 03/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10*
2021-05-17 14:39 ` [PATCH v5 03/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10* Peng Ju Zhou
@ 2021-05-20 4:33 ` Felix Kuehling
0 siblings, 0 replies; 21+ messages in thread
From: Felix Kuehling @ 2021-05-20 4:33 UTC (permalink / raw)
To: Peng Ju Zhou, amd-gfx
Am 2021-05-17 um 10:39 a.m. schrieb Peng Ju Zhou:
> In SRIOV environment, KMD should access GC registers
> with RLCG if GC indirect access flag enabled.
>
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
This patch is
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
> ---
> .../drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c | 42 +++++++++----------
> 1 file changed, 21 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> index 62aa1a6f64ed..491acdf92f73 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c
> @@ -96,8 +96,8 @@ static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
>
> lock_srbm(kgd, 0, 0, 0, vmid);
>
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_CONFIG), sh_mem_config);
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmSH_MEM_BASES), sh_mem_bases);
> + WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
> + WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
> /* APE1 no longer exists on GFX9 */
>
> unlock_srbm(kgd);
> @@ -161,7 +161,7 @@ static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
>
> lock_srbm(kgd, mec, pipe, 0, 0);
>
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmCPC_INT_CNTL),
> + WREG32_SOC15(GC, 0, mmCPC_INT_CNTL,
> CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
> CP_INT_CNTL_RING0__OPCODE_ERROR_INT_ENABLE_MASK);
>
> @@ -239,13 +239,13 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
>
> for (reg = hqd_base;
> reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++)
> - WREG32(reg, mqd_hqd[reg - hqd_base]);
> + WREG32_SOC15_IP(GC, reg, mqd_hqd[reg - hqd_base]);
>
>
> /* Activate doorbell logic before triggering WPTR poll. */
> data = REG_SET_FIELD(m->cp_hqd_pq_doorbell_control,
> CP_HQD_PQ_DOORBELL_CONTROL, DOORBELL_EN, 1);
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL), data);
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, data);
>
> if (wptr) {
> /* Don't read wptr with get_user because the user
> @@ -274,27 +274,27 @@ static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
> guessed_wptr += m->cp_hqd_pq_wptr_lo & ~(queue_size - 1);
> guessed_wptr += (uint64_t)m->cp_hqd_pq_wptr_hi << 32;
>
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_LO),
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
> lower_32_bits(guessed_wptr));
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI),
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
> upper_32_bits(guessed_wptr));
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR),
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
> lower_32_bits((uint64_t)wptr));
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI),
> + WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
> upper_32_bits((uint64_t)wptr));
> pr_debug("%s setting CP_PQ_WPTR_POLL_CNTL1 to %x\n", __func__,
> (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1),
> + WREG32_SOC15(GC, 0, mmCP_PQ_WPTR_POLL_CNTL1,
> (uint32_t)get_queue_mask(adev, pipe_id, queue_id));
> }
>
> /* Start the EOP fetcher */
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_EOP_RPTR),
> + WREG32_SOC15(GC, 0, mmCP_HQD_EOP_RPTR,
> REG_SET_FIELD(m->cp_hqd_eop_rptr,
> CP_HQD_EOP_RPTR, INIT_FETCHER, 1));
>
> data = REG_SET_FIELD(m->cp_hqd_active, CP_HQD_ACTIVE, ACTIVE, 1);
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE), data);
> + WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data);
>
> release_queue(kgd);
>
> @@ -365,7 +365,7 @@ static int kgd_hqd_dump(struct kgd_dev *kgd,
> if (WARN_ON_ONCE(i >= HQD_N_REGS)) \
> break; \
> (*dump)[i][0] = (addr) << 2; \
> - (*dump)[i++][1] = RREG32(addr); \
> + (*dump)[i++][1] = RREG32_SOC15_IP(GC, addr); \
> } while (0)
>
> *dump = kmalloc(HQD_N_REGS*2*sizeof(uint32_t), GFP_KERNEL);
> @@ -497,13 +497,13 @@ static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
> uint32_t low, high;
>
> acquire_queue(kgd, pipe_id, queue_id);
> - act = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
> + act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
> if (act) {
> low = lower_32_bits(queue_address >> 8);
> high = upper_32_bits(queue_address >> 8);
>
> - if (low == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE)) &&
> - high == RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_BASE_HI)))
> + if (low == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE) &&
> + high == RREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI))
> retval = true;
> }
> release_queue(kgd);
> @@ -621,11 +621,11 @@ static int kgd_hqd_destroy(struct kgd_dev *kgd, void *mqd,
> preempt_enable();
> #endif
>
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_DEQUEUE_REQUEST), type);
> + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, type);
>
> end_jiffies = (utimeout * HZ / 1000) + jiffies;
> while (true) {
> - temp = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_HQD_ACTIVE));
> + temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE);
> if (!(temp & CP_HQD_ACTIVE__ACTIVE_MASK))
> break;
> if (time_after(jiffies, end_jiffies)) {
> @@ -716,8 +716,8 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd,
>
> mutex_lock(&adev->grbm_idx_mutex);
>
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), gfx_index_val);
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmSQ_CMD), sq_cmd);
> + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, gfx_index_val);
> + WREG32_SOC15(GC, 0, mmSQ_CMD, sq_cmd);
>
> data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
> INSTANCE_BROADCAST_WRITES, 1);
> @@ -726,7 +726,7 @@ static int kgd_wave_control_execute(struct kgd_dev *kgd,
> data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
> SE_BROADCAST_WRITES, 1);
>
> - WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data);
> + WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
> mutex_unlock(&adev->grbm_idx_mutex);
>
> return 0;
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers
2021-05-20 3:46 ` Alex Deucher
@ 2021-05-21 9:58 ` Zhou, Peng Ju
2021-05-21 10:07 ` Deng, Emily
0 siblings, 1 reply; 21+ messages in thread
From: Zhou, Peng Ju @ 2021-05-21 9:58 UTC (permalink / raw)
To: Alex Deucher, Zhao, Victor, Deng, Emily; +Cc: amd-gfx list
[AMD Official Use Only - Internal Distribution Only]
Hi @Zhao, Victor/@Deng, Emily
Can you help to answer Alex's question,?
Because this patch originally from @Zhao, Victor, it's hard for me to explain the question.
Alex's question:
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> > case CHIP_NAVI12:
> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> > - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> > amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
> > + amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
>
> Is it safe to change the order like this on bare metal? Please look at what was
> done for vega and sienna cichlid. Something like that is probably a better bet.
----------------------------------------------------------------------
BW
Pengju Zhou
> -----Original Message-----
> From: Alex Deucher <alexdeucher@gmail.com>
> Sent: Thursday, May 20, 2021 11:47 AM
> To: Zhou, Peng Ju <PengJu.Zhou@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhao, Victor
> <Victor.Zhao@amd.com>
> Subject: Re: [PATCH v5 09/10] drm/amdgpu: Use PSP to program
> IH_RB_CNTL* registers
>
> On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou <PengJu.Zhou@amd.com>
> wrote:
> >
> > use psp to program IH_RB_CNTL* if indirect access for ih enabled in
> > SRIOV environment.
> >
> > Signed-off-by: Victor <Victor.Zhao@amd.com>
> > Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +++++++++++++++++--
> > drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
> > 2 files changed, 18 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > index f4e4040bbd25..2e69cf8db072 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> > @@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct
> amdgpu_device *adev,
> > /* enable_intr field is only valid in ring0 */
> > if (ih == &adev->irq.ih)
> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ?
> 1 : 0));
> > - WREG32(ih_regs->ih_rb_cntl, tmp);
> > + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> > + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> > + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> > + return -ETIMEDOUT;
> > + }
> > + } else {
> > + WREG32(ih_regs->ih_rb_cntl, tmp);
> > + }
> >
> > if (enable) {
> > ih->enabled = true;
> > @@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct
> amdgpu_device *adev,
> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL,
> WPTR_OVERFLOW_ENABLE, 0);
> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE,
> 1);
> > }
> > - WREG32(ih_regs->ih_rb_cntl, tmp);
> > +
> > + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> > + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> > + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> > + return -ETIMEDOUT;
> > + }
> > + } else {
> > + WREG32(ih_regs->ih_rb_cntl, tmp);
> > + }
> >
> > if (ih == &adev->irq.ih) {
> > /* set the ih ring 0 writeback address whether it's
> > enabled or not */ diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
> > b/drivers/gpu/drm/amd/amdgpu/nv.c index a9ad28fb55b3..b9c9c4d4606c
> > 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> > case CHIP_NAVI12:
> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> > - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> > amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
> > + amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
>
> Is it safe to change the order like this on bare metal? Please look at what was
> done for vega and sienna cichlid. Something like that is probably a better bet.
>
> Alex
>
>
> > if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
> > amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> > if (adev->enable_virtual_display ||
> > amdgpu_sriov_vf(adev))
> > --
> > 2.17.1
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> gfx&data=04%7C01%7CPe
> >
> ngJu.Zhou%40amd.com%7Cabc8d955fb1f4deb9ce108d91b41ecbb%7C3dd89
> 61fe4884
> >
> e608e11a82d994e183d%7C0%7C0%7C637570792232990999%7CUnknown%7
> CTWFpbGZsb
> >
> 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
> %3D%
> >
> 7C1000&sdata=HyDcZjT3c6mY%2F%2FYdjMuW1T%2FRUIzqX5kK9vaYus
> mZJxI%3D&
> > amp;reserved=0
_______________________________________________
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^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers
2021-05-21 9:58 ` Zhou, Peng Ju
@ 2021-05-21 10:07 ` Deng, Emily
2021-05-21 14:25 ` Alex Deucher
2021-05-23 11:41 ` Zhou, Peng Ju
0 siblings, 2 replies; 21+ messages in thread
From: Deng, Emily @ 2021-05-21 10:07 UTC (permalink / raw)
To: Zhou, Peng Ju, Alex Deucher, Zhao, Victor; +Cc: amd-gfx list
Hi Pengju,
You'd better only switch for sriov.
Best wishes
Emily Deng
>-----Original Message-----
>From: Zhou, Peng Ju <PengJu.Zhou@amd.com>
>Sent: Friday, May 21, 2021 5:58 PM
>To: Alex Deucher <alexdeucher@gmail.com>; Zhao, Victor
><Victor.Zhao@amd.com>; Deng, Emily <Emily.Deng@amd.com>
>Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
>Subject: RE: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL*
>registers
>
>[AMD Official Use Only - Internal Distribution Only]
>
>Hi @Zhao, Victor/@Deng, Emily
>
>Can you help to answer Alex's question,?
>Because this patch originally from @Zhao, Victor, it's hard for me to explain the
>question.
>
>Alex's question:
>> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
>> > case CHIP_NAVI12:
>> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
>> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
>> > - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
>> > amdgpu_device_ip_block_add(adev,
>> > &psp_v11_0_ip_block);
>> > + amdgpu_device_ip_block_add(adev,
>> > + &navi10_ih_ip_block);
>>
>> Is it safe to change the order like this on bare metal? Please look
>> at what was done for vega and sienna cichlid. Something like that is probably
>a better bet.
>
>
>----------------------------------------------------------------------
>BW
>Pengju Zhou
>
>
>
>
>> -----Original Message-----
>> From: Alex Deucher <alexdeucher@gmail.com>
>> Sent: Thursday, May 20, 2021 11:47 AM
>> To: Zhou, Peng Ju <PengJu.Zhou@amd.com>
>> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhao, Victor
>> <Victor.Zhao@amd.com>
>> Subject: Re: [PATCH v5 09/10] drm/amdgpu: Use PSP to program
>> IH_RB_CNTL* registers
>>
>> On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou <PengJu.Zhou@amd.com>
>> wrote:
>> >
>> > use psp to program IH_RB_CNTL* if indirect access for ih enabled in
>> > SRIOV environment.
>> >
>> > Signed-off-by: Victor <Victor.Zhao@amd.com>
>> > Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
>> > ---
>> > drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +++++++++++++++++--
>> > drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
>> > 2 files changed, 18 insertions(+), 3 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> > b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> > index f4e4040bbd25..2e69cf8db072 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
>> > @@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct
>> amdgpu_device *adev,
>> > /* enable_intr field is only valid in ring0 */
>> > if (ih == &adev->irq.ih)
>> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ?
>> 1 : 0));
>> > - WREG32(ih_regs->ih_rb_cntl, tmp);
>> > + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>> > + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
>> > + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
>> > + return -ETIMEDOUT;
>> > + }
>> > + } else {
>> > + WREG32(ih_regs->ih_rb_cntl, tmp);
>> > + }
>> >
>> > if (enable) {
>> > ih->enabled = true;
>> > @@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct
>> amdgpu_device *adev,
>> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL,
>> WPTR_OVERFLOW_ENABLE, 0);
>> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE,
>> 1);
>> > }
>> > - WREG32(ih_regs->ih_rb_cntl, tmp);
>> > +
>> > + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
>> > + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
>> > + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
>> > + return -ETIMEDOUT;
>> > + }
>> > + } else {
>> > + WREG32(ih_regs->ih_rb_cntl, tmp);
>> > + }
>> >
>> > if (ih == &adev->irq.ih) {
>> > /* set the ih ring 0 writeback address whether it's
>> > enabled or not */ diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
>> > b/drivers/gpu/drm/amd/amdgpu/nv.c index a9ad28fb55b3..b9c9c4d4606c
>> > 100644
>> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
>> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
>> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
>> > case CHIP_NAVI12:
>> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
>> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
>> > - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
>> > amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
>> > + amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
>>
>> Is it safe to change the order like this on bare metal? Please look at what was
>> done for vega and sienna cichlid. Something like that is probably a better bet.
>>
>> Alex
>>
>>
>> > if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
>> > amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
>> > if (adev->enable_virtual_display ||
>> > amdgpu_sriov_vf(adev))
>> > --
>> > 2.17.1
>> >
>> > _______________________________________________
>> > amd-gfx mailing list
>> > amd-gfx@lists.freedesktop.org
>> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
>> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-
>> gfx&data=04%7C01%7CPe
>> >
>> ngJu.Zhou%40amd.com%7Cabc8d955fb1f4deb9ce108d91b41ecbb%7C3dd89
>> 61fe4884
>> >
>> e608e11a82d994e183d%7C0%7C0%7C637570792232990999%7CUnknown%7
>> CTWFpbGZsb
>> >
>> 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
>> %3D%
>> >
>> 7C1000&sdata=HyDcZjT3c6mY%2F%2FYdjMuW1T%2FRUIzqX5kK9vaYus
>> mZJxI%3D&
>> > amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers
2021-05-21 10:07 ` Deng, Emily
@ 2021-05-21 14:25 ` Alex Deucher
2021-05-23 11:41 ` Zhou, Peng Ju
1 sibling, 0 replies; 21+ messages in thread
From: Alex Deucher @ 2021-05-21 14:25 UTC (permalink / raw)
To: Deng, Emily; +Cc: Zhao, Victor, amd-gfx list
On Fri, May 21, 2021 at 6:07 AM Deng, Emily <Emily.Deng@amd.com> wrote:
>
> Hi Pengju,
> You'd better only switch for sriov.
Either verify that this doesn't break bare metal, or do something like
we do on sienna cichlid. E.g.,
if (!amdgpu_sriov_vf(adev)) {
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
if (likely(adev->firmware.load_type ==
AMDGPU_FW_LOAD_PSP))
amdgpu_device_ip_block_add(adev,
&psp_v11_0_ip_block);
} else {
if (likely(adev->firmware.load_type ==
AMDGPU_FW_LOAD_PSP))
amdgpu_device_ip_block_add(adev,
&psp_v11_0_ip_block);
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
}
Alex
>
> Best wishes
> Emily Deng
>
> >-----Original Message-----
> >From: Zhou, Peng Ju <PengJu.Zhou@amd.com>
> >Sent: Friday, May 21, 2021 5:58 PM
> >To: Alex Deucher <alexdeucher@gmail.com>; Zhao, Victor
> ><Victor.Zhao@amd.com>; Deng, Emily <Emily.Deng@amd.com>
> >Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> >Subject: RE: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL*
> >registers
> >
> >[AMD Official Use Only - Internal Distribution Only]
> >
> >Hi @Zhao, Victor/@Deng, Emily
> >
> >Can you help to answer Alex's question,?
> >Because this patch originally from @Zhao, Victor, it's hard for me to explain the
> >question.
> >
> >Alex's question:
> >> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> >> > case CHIP_NAVI12:
> >> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> >> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> >> > - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> >> > amdgpu_device_ip_block_add(adev,
> >> > &psp_v11_0_ip_block);
> >> > + amdgpu_device_ip_block_add(adev,
> >> > + &navi10_ih_ip_block);
> >>
> >> Is it safe to change the order like this on bare metal? Please look
> >> at what was done for vega and sienna cichlid. Something like that is probably
> >a better bet.
> >
> >
> >----------------------------------------------------------------------
> >BW
> >Pengju Zhou
> >
> >
> >
> >
> >> -----Original Message-----
> >> From: Alex Deucher <alexdeucher@gmail.com>
> >> Sent: Thursday, May 20, 2021 11:47 AM
> >> To: Zhou, Peng Ju <PengJu.Zhou@amd.com>
> >> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhao, Victor
> >> <Victor.Zhao@amd.com>
> >> Subject: Re: [PATCH v5 09/10] drm/amdgpu: Use PSP to program
> >> IH_RB_CNTL* registers
> >>
> >> On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou <PengJu.Zhou@amd.com>
> >> wrote:
> >> >
> >> > use psp to program IH_RB_CNTL* if indirect access for ih enabled in
> >> > SRIOV environment.
> >> >
> >> > Signed-off-by: Victor <Victor.Zhao@amd.com>
> >> > Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> >> > ---
> >> > drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +++++++++++++++++--
> >> > drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
> >> > 2 files changed, 18 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > index f4e4040bbd25..2e69cf8db072 100644
> >> > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > @@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct
> >> amdgpu_device *adev,
> >> > /* enable_intr field is only valid in ring0 */
> >> > if (ih == &adev->irq.ih)
> >> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ?
> >> 1 : 0));
> >> > - WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> >> > + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> >> > + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> >> > + return -ETIMEDOUT;
> >> > + }
> >> > + } else {
> >> > + WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > + }
> >> >
> >> > if (enable) {
> >> > ih->enabled = true;
> >> > @@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct
> >> amdgpu_device *adev,
> >> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL,
> >> WPTR_OVERFLOW_ENABLE, 0);
> >> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE,
> >> 1);
> >> > }
> >> > - WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > +
> >> > + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
> >> > + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> >> > + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> >> > + return -ETIMEDOUT;
> >> > + }
> >> > + } else {
> >> > + WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > + }
> >> >
> >> > if (ih == &adev->irq.ih) {
> >> > /* set the ih ring 0 writeback address whether it's
> >> > enabled or not */ diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > b/drivers/gpu/drm/amd/amdgpu/nv.c index a9ad28fb55b3..b9c9c4d4606c
> >> > 100644
> >> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
> >> > case CHIP_NAVI12:
> >> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> >> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> >> > - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> >> > amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
> >> > + amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> >>
> >> Is it safe to change the order like this on bare metal? Please look at what was
> >> done for vega and sienna cichlid. Something like that is probably a better bet.
> >>
> >> Alex
> >>
> >>
> >> > if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
> >> > amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
> >> > if (adev->enable_virtual_display ||
> >> > amdgpu_sriov_vf(adev))
> >> > --
> >> > 2.17.1
> >> >
> >> > _______________________________________________
> >> > amd-gfx mailing list
> >> > amd-gfx@lists.freedesktop.org
> >> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> >> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> >> gfx&data=04%7C01%7CPe
> >> >
> >> ngJu.Zhou%40amd.com%7Cabc8d955fb1f4deb9ce108d91b41ecbb%7C3dd89
> >> 61fe4884
> >> >
> >> e608e11a82d994e183d%7C0%7C0%7C637570792232990999%7CUnknown%7
> >> CTWFpbGZsb
> >> >
> >> 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
> >> %3D%
> >> >
> >> 7C1000&sdata=HyDcZjT3c6mY%2F%2FYdjMuW1T%2FRUIzqX5kK9vaYus
> >> mZJxI%3D&
> >> > amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers
2021-05-21 10:07 ` Deng, Emily
2021-05-21 14:25 ` Alex Deucher
@ 2021-05-23 11:41 ` Zhou, Peng Ju
1 sibling, 0 replies; 21+ messages in thread
From: Zhou, Peng Ju @ 2021-05-23 11:41 UTC (permalink / raw)
To: Deng, Emily, Alex Deucher, Zhao, Victor; +Cc: amd-gfx list
[AMD Official Use Only - Internal Distribution Only]
Hi Alex/Emily
I noticed our team member have merged this patch, so discard this one.
----------------------------------------------------------------------
BW
Pengju Zhou
> -----Original Message-----
> From: Deng, Emily <Emily.Deng@amd.com>
> Sent: Friday, May 21, 2021 6:08 PM
> To: Zhou, Peng Ju <PengJu.Zhou@amd.com>; Alex Deucher
> <alexdeucher@gmail.com>; Zhao, Victor <Victor.Zhao@amd.com>
> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> Subject: RE: [PATCH v5 09/10] drm/amdgpu: Use PSP to program
> IH_RB_CNTL* registers
>
> Hi Pengju,
> You'd better only switch for sriov.
>
> Best wishes
> Emily Deng
>
> >-----Original Message-----
> >From: Zhou, Peng Ju <PengJu.Zhou@amd.com>
> >Sent: Friday, May 21, 2021 5:58 PM
> >To: Alex Deucher <alexdeucher@gmail.com>; Zhao, Victor
> ><Victor.Zhao@amd.com>; Deng, Emily <Emily.Deng@amd.com>
> >Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
> >Subject: RE: [PATCH v5 09/10] drm/amdgpu: Use PSP to program
> >IH_RB_CNTL* registers
> >
> >[AMD Official Use Only - Internal Distribution Only]
> >
> >Hi @Zhao, Victor/@Deng, Emily
> >
> >Can you help to answer Alex's question,?
> >Because this patch originally from @Zhao, Victor, it's hard for me to
> >explain the question.
> >
> >Alex's question:
> >> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device
> *adev)
> >> > case CHIP_NAVI12:
> >> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> >> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> >> > - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> >> > amdgpu_device_ip_block_add(adev,
> >> > &psp_v11_0_ip_block);
> >> > + amdgpu_device_ip_block_add(adev,
> >> > + &navi10_ih_ip_block);
> >>
> >> Is it safe to change the order like this on bare metal? Please look
> >> at what was done for vega and sienna cichlid. Something like that is
> >> probably
> >a better bet.
> >
> >
> >----------------------------------------------------------------------
> >BW
> >Pengju Zhou
> >
> >
> >
> >
> >> -----Original Message-----
> >> From: Alex Deucher <alexdeucher@gmail.com>
> >> Sent: Thursday, May 20, 2021 11:47 AM
> >> To: Zhou, Peng Ju <PengJu.Zhou@amd.com>
> >> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Zhao, Victor
> >> <Victor.Zhao@amd.com>
> >> Subject: Re: [PATCH v5 09/10] drm/amdgpu: Use PSP to program
> >> IH_RB_CNTL* registers
> >>
> >> On Mon, May 17, 2021 at 10:39 AM Peng Ju Zhou
> <PengJu.Zhou@amd.com>
> >> wrote:
> >> >
> >> > use psp to program IH_RB_CNTL* if indirect access for ih enabled in
> >> > SRIOV environment.
> >> >
> >> > Signed-off-by: Victor <Victor.Zhao@amd.com>
> >> > Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> >> > ---
> >> > drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +++++++++++++++++--
> >> > drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
> >> > 2 files changed, 18 insertions(+), 3 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > index f4e4040bbd25..2e69cf8db072 100644
> >> > --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
> >> > @@ -151,7 +151,14 @@ static int
> >> > navi10_ih_toggle_ring_interrupts(struct
> >> amdgpu_device *adev,
> >> > /* enable_intr field is only valid in ring0 */
> >> > if (ih == &adev->irq.ih)
> >> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR,
> (enable ?
> >> 1 : 0));
> >> > - WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev))
> {
> >> > + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> >> > + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> >> > + return -ETIMEDOUT;
> >> > + }
> >> > + } else {
> >> > + WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > + }
> >> >
> >> > if (enable) {
> >> > ih->enabled = true; @@ -261,7 +268,15 @@ static int
> >> > navi10_ih_enable_ring(struct
> >> amdgpu_device *adev,
> >> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL,
> >> WPTR_OVERFLOW_ENABLE, 0);
> >> > tmp = REG_SET_FIELD(tmp, IH_RB_CNTL,
> >> > RB_FULL_DRAIN_ENABLE,
> >> 1);
> >> > }
> >> > - WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > +
> >> > + if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev))
> {
> >> > + if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
> >> > + DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
> >> > + return -ETIMEDOUT;
> >> > + }
> >> > + } else {
> >> > + WREG32(ih_regs->ih_rb_cntl, tmp);
> >> > + }
> >> >
> >> > if (ih == &adev->irq.ih) {
> >> > /* set the ih ring 0 writeback address whether it's
> >> > enabled or not */ diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > b/drivers/gpu/drm/amd/amdgpu/nv.c index
> a9ad28fb55b3..b9c9c4d4606c
> >> > 100644
> >> > --- a/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > +++ b/drivers/gpu/drm/amd/amdgpu/nv.c
> >> > @@ -845,8 +845,8 @@ int nv_set_ip_blocks(struct amdgpu_device
> *adev)
> >> > case CHIP_NAVI12:
> >> > amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
> >> > amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
> >> > - amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
> >> > amdgpu_device_ip_block_add(adev,
> >> > &psp_v11_0_ip_block);
> >> > + amdgpu_device_ip_block_add(adev,
> >> > + &navi10_ih_ip_block);
> >>
> >> Is it safe to change the order like this on bare metal? Please look
> >> at what was done for vega and sienna cichlid. Something like that is
> probably a better bet.
> >>
> >> Alex
> >>
> >>
> >> > if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
> >> > amdgpu_device_ip_block_add(adev,
> &smu_v11_0_ip_block);
> >> > if (adev->enable_virtual_display ||
> >> > amdgpu_sriov_vf(adev))
> >> > --
> >> > 2.17.1
> >> >
> >> > _______________________________________________
> >> > amd-gfx mailing list
> >> > amd-gfx@lists.freedesktop.org
> >> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fl
> >> > ist
> >> > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-
> >> gfx&data=04%7C01%7CPe
> >> >
> >>
> ngJu.Zhou%40amd.com%7Cabc8d955fb1f4deb9ce108d91b41ecbb%7C3dd89
> >> 61fe4884
> >> >
> >>
> e608e11a82d994e183d%7C0%7C0%7C637570792232990999%7CUnknown%7
> >> CTWFpbGZsb
> >> >
> >>
> 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0
> >> %3D%
> >> >
> >>
> 7C1000&sdata=HyDcZjT3c6mY%2F%2FYdjMuW1T%2FRUIzqX5kK9vaYus
> >> mZJxI%3D&
> >> > amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov
2021-05-19 14:34 ` Zhou, Peng Ju
@ 2021-05-25 15:18 ` Ming, Davis
0 siblings, 0 replies; 21+ messages in thread
From: Ming, Davis @ 2021-05-25 15:18 UTC (permalink / raw)
To: Zhou, Peng Ju, Alex Deucher, amd-gfx, Khaire, Rohit
Cc: Deng, Emily, Chang, HaiJun
+Rohit
-----Original Message-----
From: Zhou, Peng Ju <PengJu.Zhou@amd.com>
Sent: Wednesday, May 19, 2021 10:34 AM
To: Zhou, Peng Ju <PengJu.Zhou@amd.com>; Alex Deucher <alexdeucher@gmail.com>; amd-gfx@lists.freedesktop.org
Cc: Deng, Emily <Emily.Deng@amd.com>; Ming, Davis <Davis.Ming@amd.com>; Chang, HaiJun <HaiJun.Chang@amd.com>
Subject: RE: [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov
[AMD Official Use Only - Internal Distribution Only]
Ping on this series.
----------------------------------------------------------------------
BW
Pengju Zhou
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhou,
> Peng Ju
> Sent: Monday, May 17, 2021 10:50 PM
> To: Alex Deucher <alexdeucher@gmail.com>; amd-gfx@lists.freedesktop.org
> Cc: Deng, Emily <Emily.Deng@amd.com>; Ming, Davis
> <Davis.Ming@amd.com>; Chang, HaiJun <HaiJun.Chang@amd.com>
> Subject: RE: [PATCH v5 01/10] drm/amdgpu: Indirect register access for
> Navi12 sriov
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Alex
> About your comment:
> "I think patches 1-4, 16 need to be squashed together to avoid breaking the
> build. Please also provide a description of how the new macros work in the
> patch description. Describe how the reworked macros properly handle
> sending GC and MMHUB accesses via the RLC rather than via some other
> mechanism. It's really hard to follow the macro logic."
>
> I squashed patches 1-4, 16 and add more detail description in the patch
> description.
> Can you help to review the patch series?
>
>
> ----------------------------------------------------------------------
> BW
> Pengju Zhou
>
>
>
> > -----Original Message-----
> > From: Peng Ju Zhou <PengJu.Zhou@amd.com>
> > Sent: Monday, May 17, 2021 10:39 PM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Zhou, Peng Ju <PengJu.Zhou@amd.com>
> > Subject: [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12
> > sriov
> >
> > This patch series are used for GC/MMHUB(part)/IH_RB_CNTL indirect
> access
> > in the SRIOV environment.
> >
> > There are 4 bits, controlled by host, to control if
> > GC/MMHUB(part)/IH_RB_CNTL indirect access enabled.
> > (one bit is master bit controls other 3 bits)
> >
> > For GC registers, changing all the register access from MMIO to RLC and use
> > RLC as the default access method in the full access time.
> >
> > For partial MMHUB registers, changing their access from MMIO to RLC in
> the
> > full access time, the remaining registers keep the original access method.
> >
> > For IH_RB_CNTL register, changing it's access from MMIO to PSP.
> >
> > Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> > drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 4 +-
> > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 78 +++++++++----------
> > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 9 ++-
> > drivers/gpu/drm/amd/amdgpu/soc15_common.h | 87 +++++++++++++----
> --
> > ---
> > 6 files changed, 97 insertions(+), 84 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 3147c1c935c8..4e0c90e52ab6 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -1147,6 +1147,7 @@ int emu_soc_asic_init(struct amdgpu_device
> > *adev);
> > * Registers read & write functions.
> > */
> > #define AMDGPU_REGS_NO_KIQ (1<<1)
> > +#define AMDGPU_REGS_RLC (1<<2)
> >
> > #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg),
> > AMDGPU_REGS_NO_KIQ) #define WREG32_NO_KIQ(reg, v)
> > amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) diff --git
> > a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 7c6c435e5d02..a2392bbe1e21 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -490,7 +490,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct
> > amdgpu_device *adev,
> > adev->gfx.rlc.funcs &&
> > adev->gfx.rlc.funcs->is_rlcg_access_range) {
> > if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
> > - return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0);
> > + return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0,
> > 0);
> > } else {
> > writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
> > }
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> > b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> > index 4fc2ce8ce8ab..7a4775ab6804 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> > @@ -127,8 +127,8 @@ struct amdgpu_rlc_funcs {
> > void (*reset)(struct amdgpu_device *adev);
> > void (*start)(struct amdgpu_device *adev);
> > void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned
> > vmid);
> > - void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32
> > flag);
> > - u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 flag);
> > + void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32
> > acc_flags, u32 hwip);
> > + u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32
> > +acc_flags, u32 hwip);
> > bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t
> > reg); };
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > index 2a3427e5020f..7c5c1ff7d97e 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> > @@ -1427,38 +1427,36 @@ static const struct soc15_reg_golden
> > golden_settings_gc_10_1_2[] =
> > SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff,
> > 0x00800000) };
> >
> > -static bool gfx_v10_is_rlcg_rw(struct amdgpu_device *adev, u32 offset,
> > uint32_t *flag, bool write) -{
> > - /* always programed by rlcg, only for gc */
> > - if (offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI) ||
> > - offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO) ||
> > - offset == SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH) ||
> > - offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL) ||
> > - offset == SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX) ||
> > - offset == SOC15_REG_OFFSET(GC, 0, mmCP_ME_CNTL)) {
> > - if (!amdgpu_sriov_reg_indirect_gc(adev))
> > - *flag = GFX_RLCG_GC_WRITE_OLD;
> > - else
> > - *flag = write ? GFX_RLCG_GC_WRITE :
> > GFX_RLCG_GC_READ;
> > +static bool gfx_v10_get_rlcg_flag(struct amdgpu_device *adev, u32
> > acc_flags, u32 hwip,
> > + int write, u32 *rlcg_flag)
> > +{
> > + switch (hwip) {
> > + case GC_HWIP:
> > + if (amdgpu_sriov_reg_indirect_gc(adev)) {
> > + *rlcg_flag = write ? GFX_RLCG_GC_WRITE :
> > GFX_RLCG_GC_READ;
> >
> > - return true;
> > - }
> > + return true;
> > + /* only in new version, AMDGPU_REGS_NO_KIQ and
> > AMDGPU_REGS_RLC enabled simultaneously */
> > + } else if ((acc_flags & AMDGPU_REGS_RLC) && !(acc_flags &
> > AMDGPU_REGS_NO_KIQ)) {
> > + *rlcg_flag = GFX_RLCG_GC_WRITE_OLD;
> >
> > - /* currently support gc read/write, mmhub write */
> > - if (offset >= SOC15_REG_OFFSET(GC, 0, mmSDMA0_DEC_START) &&
> > - offset <= SOC15_REG_OFFSET(GC, 0, mmRLC_GTS_OFFSET_MSB)) {
> > - if (amdgpu_sriov_reg_indirect_gc(adev))
> > - *flag = write ? GFX_RLCG_GC_WRITE :
> > GFX_RLCG_GC_READ;
> > - else
> > - return false;
> > - } else {
> > - if (amdgpu_sriov_reg_indirect_mmhub(adev))
> > - *flag = GFX_RLCG_MMHUB_WRITE;
> > - else
> > - return false;
> > + return true;
> > + }
> > +
> > + break;
> > + case MMHUB_HWIP:
> > + if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
> > + (acc_flags & AMDGPU_REGS_RLC) && write) {
> > + *rlcg_flag = GFX_RLCG_MMHUB_WRITE;
> > + return true;
> > + }
> > +
> > + break;
> > + default:
> > + DRM_DEBUG("Not program register by RLCG\n");
> > }
> >
> > - return true;
> > + return false;
> > }
> >
> > static u32 gfx_v10_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v,
> > uint32_t flag) @@ -1518,36 +1516,34 @@ static u32 gfx_v10_rlcg_rw(struct
> > amdgpu_device *adev, u32 offset, u32 v, uint32
> > return ret;
> > }
> >
> > -static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32
> > value, u32 flag)
> > +static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
> > +u32 value, u32 acc_flags, u32 hwip)
> > {
> > - uint32_t rlcg_flag;
> > + u32 rlcg_flag;
> >
> > - if (amdgpu_sriov_fullaccess(adev) &&
> > - gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 1)) {
> > + if (!amdgpu_sriov_runtime(adev) &&
> > + gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 1, &rlcg_flag)) {
> > gfx_v10_rlcg_rw(adev, offset, value, rlcg_flag);
> > -
> > return;
> > }
> > - if (flag & AMDGPU_REGS_NO_KIQ)
> > +
> > + if (acc_flags & AMDGPU_REGS_NO_KIQ)
> > WREG32_NO_KIQ(offset, value);
> > else
> > WREG32(offset, value);
> > }
> >
> > -static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32
> > flag)
> > +static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset,
> > +u32 acc_flags, u32 hwip)
> > {
> > - uint32_t rlcg_flag;
> > + u32 rlcg_flag;
> >
> > - if (amdgpu_sriov_fullaccess(adev) &&
> > - gfx_v10_is_rlcg_rw(adev, offset, &rlcg_flag, 0))
> > + if (!amdgpu_sriov_runtime(adev) &&
> > + gfx_v10_get_rlcg_flag(adev, acc_flags, hwip, 0, &rlcg_flag))
> > return gfx_v10_rlcg_rw(adev, offset, 0, rlcg_flag);
> >
> > - if (flag & AMDGPU_REGS_NO_KIQ)
> > + if (acc_flags & AMDGPU_REGS_NO_KIQ)
> > return RREG32_NO_KIQ(offset);
> > else
> > return RREG32(offset);
> > -
> > - return 0;
> > }
> >
> > static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] = diff
> -
> > -git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index feaa5e4a5538..fe5908f708cc 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -734,7 +734,7 @@ static const u32
> > GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
> > mmRLC_SRM_INDEX_CNTL_DATA_7 -
> > mmRLC_SRM_INDEX_CNTL_DATA_0, };
> >
> > -static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32
> v,
> > u32 flag)
> > +static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32
> > +v, u32 flag)
> > {
> > static void *scratch_reg0;
> > static void *scratch_reg1;
> > @@ -787,15 +787,16 @@ static void gfx_v9_0_rlcg_rw(struct
> amdgpu_device
> > *adev, u32 offset, u32 v, u32
> >
> > }
> >
> > -static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
> u32
> > v, u32 flag)
> > +static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
> > + u32 v, u32 acc_flags, u32 hwip)
> > {
> > if (amdgpu_sriov_fullaccess(adev)) {
> > - gfx_v9_0_rlcg_rw(adev, offset, v, flag);
> > + gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
> >
> > return;
> > }
> >
> > - if (flag & AMDGPU_REGS_NO_KIQ)
> > + if (acc_flags & AMDGPU_REGS_NO_KIQ)
> > WREG32_NO_KIQ(offset, v);
> > else
> > WREG32(offset, v);
> > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> > b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> > index 14bd794bbea6..c781808e4dc3 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> > @@ -27,28 +27,51 @@
> > /* Register Access Macros */
> > #define SOC15_REG_OFFSET(ip, inst, reg) (adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> >
> > +#define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
> > + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_wreg) ? \
> > + adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
> > + WREG32(reg, value))
> > +
> > +#define __RREG32_SOC15_RLC__(reg, flag, hwip) \
> > + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs->rlcg_rreg) ? \
> > + adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
> > + RREG32(reg))
> > +
> > #define WREG32_FIELD15(ip, idx, reg, field, val) \
> > - WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX]
> > + mm##reg, \
> > - (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX]
> > + mm##reg) \
> > - & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg,
> > field))
> > + __WREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
> > + (__RREG32_SOC15_RLC__( \
> > + adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
> > + 0, ip##_HWIP) & \
> > + ~REG_FIELD_MASK(reg, field)) | (val) <<
> > REG_FIELD_SHIFT(reg, field), \
> > + 0, ip##_HWIP)
> >
> > #define RREG32_SOC15(ip, inst, reg) \
> > - RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> > + __RREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
> > + 0, ip##_HWIP)
> > +
> > +#define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0,
> > +ip##_HWIP)
> >
> > #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
> > - RREG32_NO_KIQ(adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> > + __RREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
> > + AMDGPU_REGS_NO_KIQ, ip##_HWIP)
> >
> > #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
> > - RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> > + offset)
> > +
> > +__RREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > ++ reg) + offset, 0, ip##_HWIP)
> >
> > #define WREG32_SOC15(ip, inst, reg, value) \
> > - WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg),
> > value)
> > + __WREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \
> > + value, 0, ip##_HWIP)
> > +
> > +#define WREG32_SOC15_IP(ip, reg, value) \
> > + __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP)
> >
> > #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
> > - WREG32_NO_KIQ((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
> > + __WREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \
> > + value, AMDGPU_REGS_NO_KIQ, ip##_HWIP)
> >
> > #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
> > - WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
> > + offset, value)
> > + __WREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \
> > + value, 0, ip##_HWIP)
> >
> > #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \
> > ({ int ret = 0; \
> > @@ -77,12 +100,7 @@
> > })
> >
> > #define WREG32_RLC(reg, value) \
> > - do { \
> > - if (adev->gfx.rlc.funcs->rlcg_wreg) \
> > - adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, 0); \
> > - else \
> > - WREG32(reg, value); \
> > - } while (0)
> > + __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP)
> >
> > #define WREG32_RLC_EX(prefix, reg, value) \
> > do { \
> > @@ -108,24 +126,19 @@
> > } \
> > } while (0)
> >
> > +/* shadow the registers in the callback function */
> > #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \
> > - WREG32_RLC((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > + reg), value)
> > +
> > +__WREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > ++ reg), value, AMDGPU_REGS_RLC, GC_HWIP)
> >
> > +/* for GC only */
> > #define RREG32_RLC(reg) \
> > - (adev->gfx.rlc.funcs->rlcg_rreg ? \
> > - adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, 0) : RREG32(reg))
> > -
> > -#define WREG32_RLC_NO_KIQ(reg, value) \
> > - do { \
> > - if (adev->gfx.rlc.funcs->rlcg_wreg) \
> > - adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value,
> > AMDGPU_REGS_NO_KIQ); \
> > - else \
> > - WREG32_NO_KIQ(reg, value); \
> > - } while (0)
> > + __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP)
> > +
> > +#define WREG32_RLC_NO_KIQ(reg, value, hwip) \
> > + __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ |
> > AMDGPU_REGS_RLC,
> > +hwip)
> >
> > -#define RREG32_RLC_NO_KIQ(reg) \
> > - (adev->gfx.rlc.funcs->rlcg_rreg ? \
> > - adev->gfx.rlc.funcs->rlcg_rreg(adev, reg,
> > AMDGPU_REGS_NO_KIQ) : RREG32_NO_KIQ(reg))
> > +#define RREG32_RLC_NO_KIQ(reg, hwip) \
> > + __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ |
> > AMDGPU_REGS_RLC, hwip)
> >
> > #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \
> > do { \
> > @@ -146,12 +159,12 @@
> > } while (0)
> >
> > #define RREG32_SOC15_RLC(ip, inst, reg) \
> > - RREG32_RLC(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] +
> > reg)
> > + __RREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > ++ reg, AMDGPU_REGS_RLC, ip##_HWIP)
> >
> > #define WREG32_SOC15_RLC(ip, inst, reg, value) \
> > do { \
> > uint32_t target_reg = adev-
> > >reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\
> > - WREG32_RLC(target_reg, value); \
> > + __WREG32_SOC15_RLC__(target_reg, value,
> > AMDGPU_REGS_RLC, ip##_HWIP);
> > +\
> > } while (0)
> >
> > #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \ @@ -161,14
> > +174,16 @@
> > } while (0)
> >
> > #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \
> > - WREG32_RLC((adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
> > - (RREG32_RLC(adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
> > - & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg,
> > field))
> > + __WREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
> > + (__RREG32_SOC15_RLC__(adev-
> > >reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
> > + AMDGPU_REGS_RLC,
> > ip##_HWIP) & \
> > + ~REG_FIELD_MASK(reg, field)) | (val) <<
> > REG_FIELD_SHIFT(reg, field), \
> > + AMDGPU_REGS_RLC, ip##_HWIP)
> >
> > #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \
> > - WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > + reg) + offset), value)
> > +
> > +__WREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > ++ reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP)
> >
> > #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \
> > - RREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] +
> > reg) + offset))
> > +
> > +__RREG32_SOC15_RLC__((adev-
> > >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
> > ++ reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP)
> >
> > #endif
> > --
> > 2.17.1
> _______________________________________________
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^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2021-05-25 15:18 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-17 14:39 [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 02/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10* Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 03/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10* Peng Ju Zhou
2021-05-20 4:33 ` Felix Kuehling
2021-05-17 14:39 ` [PATCH v5 04/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 05/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file sdma_v5* Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 06/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 07/10] drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c Peng Ju Zhou
2021-05-17 14:39 ` [PATCH v5 08/10] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2* Peng Ju Zhou
2021-05-20 3:48 ` Alex Deucher
2021-05-17 14:39 ` [PATCH v5 09/10] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers Peng Ju Zhou
2021-05-20 3:46 ` Alex Deucher
2021-05-21 9:58 ` Zhou, Peng Ju
2021-05-21 10:07 ` Deng, Emily
2021-05-21 14:25 ` Alex Deucher
2021-05-23 11:41 ` Zhou, Peng Ju
2021-05-17 14:39 ` [PATCH v5 10/10] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV Peng Ju Zhou
2021-05-20 3:47 ` Alex Deucher
2021-05-17 14:49 ` [PATCH v5 01/10] drm/amdgpu: Indirect register access for Navi12 sriov Zhou, Peng Ju
2021-05-19 14:34 ` Zhou, Peng Ju
2021-05-25 15:18 ` Ming, Davis
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