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* [PATCH 0/7] arm64: dts: freescale: Add i.MX8DXL support
@ 2021-05-17 17:11 ` abelvesa
  0 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:11 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Abel Vesa <abel.vesa@nxp.com>

This work is taken from NXP's internal tree. In order to fast track
the upstreaming, I took the latest versions of the files, trying to
keep the original author where possible.

With this patchset, i.MX8DXL boots to prompt with SD rootfs.

Abel Vesa (2):
  arm64: dts: imx8-ss-lsio: Add mu5a mailbox
  arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl

Jacky Bai (5):
  arm64: dts: freescale: Add the top level dtsi support for imx8dxl
  arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi
  arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
  arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl
  arm64: dts: imx8dxl: Add i.MX8DXL evk board support

 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../boot/dts/freescale/imx8-ss-lsio.dtsi      |   9 +
 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 429 ++++++++++++++++++
 .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   |  53 +++
 .../boot/dts/freescale/imx8dxl-ss-conn.dtsi   | 133 ++++++
 .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi    |  34 ++
 .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi   |  68 +++
 arch/arm64/boot/dts/freescale/imx8dxl.dtsi    | 286 ++++++++++++
 8 files changed, 1013 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi

-- 
2.31.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 0/7] arm64: dts: freescale: Add i.MX8DXL support
@ 2021-05-17 17:11 ` abelvesa
  0 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:11 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Abel Vesa <abel.vesa@nxp.com>

This work is taken from NXP's internal tree. In order to fast track
the upstreaming, I took the latest versions of the files, trying to
keep the original author where possible.

With this patchset, i.MX8DXL boots to prompt with SD rootfs.

Abel Vesa (2):
  arm64: dts: imx8-ss-lsio: Add mu5a mailbox
  arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl

Jacky Bai (5):
  arm64: dts: freescale: Add the top level dtsi support for imx8dxl
  arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi
  arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
  arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl
  arm64: dts: imx8dxl: Add i.MX8DXL evk board support

 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../boot/dts/freescale/imx8-ss-lsio.dtsi      |   9 +
 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 429 ++++++++++++++++++
 .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   |  53 +++
 .../boot/dts/freescale/imx8dxl-ss-conn.dtsi   | 133 ++++++
 .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi    |  34 ++
 .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi   |  68 +++
 arch/arm64/boot/dts/freescale/imx8dxl.dtsi    | 286 ++++++++++++
 8 files changed, 1013 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi

-- 
2.31.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 1/7] arm64: dts: freescale: Add the top level dtsi support for imx8dxl
  2021-05-17 17:11 ` abelvesa
@ 2021-05-17 17:11   ` abelvesa
  -1 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:11 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Jacky Bai <ping.bai@nxp.com>

The i.MX8DXL is a device targeting the automotive and industrial
market segments. The flexibility of the architecture allows for
use in a wide variety of general embedded applications. The chip
is designed to achieve both high performance and low power consumption.
The chip relies on the power efficient dual (2x) Cortex-A35 cluster.

Add the reserved memory node property for dsp reserved memory,
the wakeup-irq property for SCU node, the imx ion, the rpmsg and the
cm4 rproc support.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 286 +++++++++++++++++++++
 1 file changed, 286 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
new file mode 100644
index 000000000000..43e0bcdc2469
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+#include <dt-bindings/clock/imx8-clock.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/pads-imx8dxl.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &fec1;
+		ethernet1 = &eqos;
+		gpio0 = &lsio_gpio0;
+		gpio1 = &lsio_gpio1;
+		gpio2 = &lsio_gpio2;
+		gpio3 = &lsio_gpio3;
+		gpio4 = &lsio_gpio4;
+		gpio5 = &lsio_gpio5;
+		gpio6 = &lsio_gpio6;
+		gpio7 = &lsio_gpio7;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mu1 = &lsio_mu1;
+		serial0 = &lpuart0;
+		serial1 = &lpuart1;
+		serial2 = &lpuart2;
+		serial3 = &lpuart3;
+	};
+
+	cpus: cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		/* We have 1 clusters with 2 Cortex-A35 cores */
+		A35_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&A35_L2>;
+			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+			#cooling-cells = <2>;
+			operating-points-v2 = <&a35_opp_table>;
+		};
+
+		A35_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			next-level-cache = <&A35_L2>;
+			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+			#cooling-cells = <2>;
+			operating-points-v2 = <&a35_opp_table>;
+		};
+
+		A35_L2: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	a35_opp_table: opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <150000>;
+		};
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		dsp_reserved: dsp@92400000 {
+			reg = <0 0x92400000 0 0x2000000>;
+			no-map;
+		};
+	};
+
+	rpmsg: rpmsg{
+		compatible = "fsl,imx8qxp-rpmsg";
+		/* up to now, the following channels are used in imx rpmsg
+		 * - tx1/rx1: messages channel.
+		 * - general interrupt1: remote proc finish re-init rpmsg stack
+		 *   when A core is partition reset.
+		 */
+		mbox-names = "tx", "rx", "rxdb";
+		mboxes = <&lsio_mu5 0 1
+			  &lsio_mu5 1 1
+			  &lsio_mu5 3 1>;
+		mub-partition = <3>;
+		status = "disabled";
+	};
+
+	imx8dxl_cm4: imx8dxl_cm4@0 {
+		compatible = "fsl,imx8qxp-cm4";
+		rsc-da = <0x90000000>;
+		mbox-names = "tx", "rx", "rxdb";
+		mboxes = <&lsio_mu5 0 1
+			  &lsio_mu5 1 1
+			  &lsio_mu5 3 1>;
+		mub-partition = <3>;
+		core-index = <0>;
+		core-id = <IMX_SC_R_M4_0_PID0>;
+		status = "disabled";
+		power-domains = <&pd IMX_SC_R_M4_0_PID0>,
+				<&pd IMX_SC_R_M4_0_MU_1A>;
+	};
+
+	gic: interrupt-controller@51a00000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	scu {
+		compatible = "fsl,imx-scu";
+		mbox-names = "tx0",
+			     "rx0",
+			     "gip3";
+		mboxes = <&lsio_mu1 0 0
+			  &lsio_mu1 1 0
+			  &lsio_mu1 3 3>;
+
+		pd: imx8dxl-pd {
+			compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd";
+			#power-domain-cells = <1>;
+			wakeup-irq = <160 163 235 236 237 228 229 230 231 238
+				     239 240 166 169>;
+		};
+
+		clk: clock-controller {
+			compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
+			#clock-cells = <2>;
+			clocks = <&xtal32k &xtal24m>;
+			clock-names = "xtal_32KHz", "xtal_24Mhz";
+		};
+
+		iomuxc: pinctrl {
+			compatible = "fsl,imx8dxl-iomuxc";
+		};
+
+		ocotp: imx8qx-ocotp {
+			compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			fec_mac0: mac@2c4 {
+				reg = <0x2c4 6>;
+			};
+
+			fec_mac1: mac@2c6 {
+				reg = <0x2c6 6>;
+			};
+		};
+
+		rtc: rtc {
+			compatible = "fsl,imx8dxl-sc-rtc", "fsl,imx8qxp-sc-rtc";
+		};
+
+		watchdog {
+			compatible = "fsl,imx-sc-wdt";
+			timeout-sec = <60>;
+		};
+
+		tsens: thermal-sensor {
+			compatible = "fsl,imx-sc-thermal";
+			#thermal-sensor-cells = <1>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+	};
+
+	thermal_zones: thermal-zones {
+		cpu-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
+
+			trips {
+				cpu_alert0: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit0: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	clk_dummy: clock-dummy {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+		clock-output-names = "clk_dummy";
+	};
+
+	xtal32k: clock-xtal32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xtal_32KHz";
+	};
+
+	xtal24m: clock-xtal24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "xtal_24MHz";
+	};
+
+	imx_ion {
+		compatible = "fsl,mxc-ion";
+		fsl,heap-id = <0>;
+	};
+
+	sc_pwrkey: sc-powerkey {
+		compatible = "fsl,imx8-pwrkey";
+		linux,keycode = <KEY_POWER>;
+		wakeup-source;
+	};
+
+	/* sorted in register address */
+	#include "imx8-ss-adma.dtsi"
+	#include "imx8-ss-conn.dtsi"
+	#include "imx8-ss-ddr.dtsi"
+	#include "imx8-ss-lsio.dtsi"
+};
+
+#include "imx8dxl-ss-adma.dtsi"
+#include "imx8dxl-ss-conn.dtsi"
+#include "imx8dxl-ss-lsio.dtsi"
+#include "imx8dxl-ss-ddr.dtsi"
-- 
2.31.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 1/7] arm64: dts: freescale: Add the top level dtsi support for imx8dxl
@ 2021-05-17 17:11   ` abelvesa
  0 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:11 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Jacky Bai <ping.bai@nxp.com>

The i.MX8DXL is a device targeting the automotive and industrial
market segments. The flexibility of the architecture allows for
use in a wide variety of general embedded applications. The chip
is designed to achieve both high performance and low power consumption.
The chip relies on the power efficient dual (2x) Cortex-A35 cluster.

Add the reserved memory node property for dsp reserved memory,
the wakeup-irq property for SCU node, the imx ion, the rpmsg and the
cm4 rproc support.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 286 +++++++++++++++++++++
 1 file changed, 286 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
new file mode 100644
index 000000000000..43e0bcdc2469
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
@@ -0,0 +1,286 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+#include <dt-bindings/clock/imx8-clock.h>
+#include <dt-bindings/firmware/imx/rsrc.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/pads-imx8dxl.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	aliases {
+		ethernet0 = &fec1;
+		ethernet1 = &eqos;
+		gpio0 = &lsio_gpio0;
+		gpio1 = &lsio_gpio1;
+		gpio2 = &lsio_gpio2;
+		gpio3 = &lsio_gpio3;
+		gpio4 = &lsio_gpio4;
+		gpio5 = &lsio_gpio5;
+		gpio6 = &lsio_gpio6;
+		gpio7 = &lsio_gpio7;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		mu1 = &lsio_mu1;
+		serial0 = &lpuart0;
+		serial1 = &lpuart1;
+		serial2 = &lpuart2;
+		serial3 = &lpuart3;
+	};
+
+	cpus: cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		/* We have 1 clusters with 2 Cortex-A35 cores */
+		A35_0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+			next-level-cache = <&A35_L2>;
+			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+			#cooling-cells = <2>;
+			operating-points-v2 = <&a35_opp_table>;
+		};
+
+		A35_1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+			next-level-cache = <&A35_L2>;
+			clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
+			#cooling-cells = <2>;
+			operating-points-v2 = <&a35_opp_table>;
+		};
+
+		A35_L2: l2-cache0 {
+			compatible = "cache";
+		};
+	};
+
+	a35_opp_table: opp-table {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-900000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			opp-microvolt = <1000000>;
+			clock-latency-ns = <150000>;
+		};
+
+		opp-1200000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			opp-microvolt = <1100000>;
+			clock-latency-ns = <150000>;
+			opp-suspend;
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		dsp_reserved: dsp@92400000 {
+			reg = <0 0x92400000 0 0x2000000>;
+			no-map;
+		};
+	};
+
+	rpmsg: rpmsg{
+		compatible = "fsl,imx8qxp-rpmsg";
+		/* up to now, the following channels are used in imx rpmsg
+		 * - tx1/rx1: messages channel.
+		 * - general interrupt1: remote proc finish re-init rpmsg stack
+		 *   when A core is partition reset.
+		 */
+		mbox-names = "tx", "rx", "rxdb";
+		mboxes = <&lsio_mu5 0 1
+			  &lsio_mu5 1 1
+			  &lsio_mu5 3 1>;
+		mub-partition = <3>;
+		status = "disabled";
+	};
+
+	imx8dxl_cm4: imx8dxl_cm4@0 {
+		compatible = "fsl,imx8qxp-cm4";
+		rsc-da = <0x90000000>;
+		mbox-names = "tx", "rx", "rxdb";
+		mboxes = <&lsio_mu5 0 1
+			  &lsio_mu5 1 1
+			  &lsio_mu5 3 1>;
+		mub-partition = <3>;
+		core-index = <0>;
+		core-id = <IMX_SC_R_M4_0_PID0>;
+		status = "disabled";
+		power-domains = <&pd IMX_SC_R_M4_0_PID0>,
+				<&pd IMX_SC_R_M4_0_MU_1A>;
+	};
+
+	gic: interrupt-controller@51a00000 {
+		compatible = "arm,gic-v3";
+		reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
+		      <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	pmu {
+		compatible = "arm,armv8-pmuv3";
+		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	scu {
+		compatible = "fsl,imx-scu";
+		mbox-names = "tx0",
+			     "rx0",
+			     "gip3";
+		mboxes = <&lsio_mu1 0 0
+			  &lsio_mu1 1 0
+			  &lsio_mu1 3 3>;
+
+		pd: imx8dxl-pd {
+			compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd";
+			#power-domain-cells = <1>;
+			wakeup-irq = <160 163 235 236 237 228 229 230 231 238
+				     239 240 166 169>;
+		};
+
+		clk: clock-controller {
+			compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
+			#clock-cells = <2>;
+			clocks = <&xtal32k &xtal24m>;
+			clock-names = "xtal_32KHz", "xtal_24Mhz";
+		};
+
+		iomuxc: pinctrl {
+			compatible = "fsl,imx8dxl-iomuxc";
+		};
+
+		ocotp: imx8qx-ocotp {
+			compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			fec_mac0: mac@2c4 {
+				reg = <0x2c4 6>;
+			};
+
+			fec_mac1: mac@2c6 {
+				reg = <0x2c6 6>;
+			};
+		};
+
+		rtc: rtc {
+			compatible = "fsl,imx8dxl-sc-rtc", "fsl,imx8qxp-sc-rtc";
+		};
+
+		watchdog {
+			compatible = "fsl,imx-sc-wdt";
+			timeout-sec = <60>;
+		};
+
+		tsens: thermal-sensor {
+			compatible = "fsl,imx-sc-thermal";
+			#thermal-sensor-cells = <1>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
+	};
+
+	thermal_zones: thermal-zones {
+		cpu-thermal0 {
+			polling-delay-passive = <250>;
+			polling-delay = <2000>;
+			thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
+
+			trips {
+				cpu_alert0: trip0 {
+					temperature = <107000>;
+					hysteresis = <2000>;
+					type = "passive";
+				};
+				cpu_crit0: trip1 {
+					temperature = <127000>;
+					hysteresis = <2000>;
+					type = "critical";
+				};
+			};
+			cooling-maps {
+				map0 {
+					trip = <&cpu_alert0>;
+					cooling-device =
+					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				};
+			};
+		};
+	};
+
+	clk_dummy: clock-dummy {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+		clock-output-names = "clk_dummy";
+	};
+
+	xtal32k: clock-xtal32k {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+		clock-output-names = "xtal_32KHz";
+	};
+
+	xtal24m: clock-xtal24m {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <24000000>;
+		clock-output-names = "xtal_24MHz";
+	};
+
+	imx_ion {
+		compatible = "fsl,mxc-ion";
+		fsl,heap-id = <0>;
+	};
+
+	sc_pwrkey: sc-powerkey {
+		compatible = "fsl,imx8-pwrkey";
+		linux,keycode = <KEY_POWER>;
+		wakeup-source;
+	};
+
+	/* sorted in register address */
+	#include "imx8-ss-adma.dtsi"
+	#include "imx8-ss-conn.dtsi"
+	#include "imx8-ss-ddr.dtsi"
+	#include "imx8-ss-lsio.dtsi"
+};
+
+#include "imx8dxl-ss-adma.dtsi"
+#include "imx8dxl-ss-conn.dtsi"
+#include "imx8dxl-ss-lsio.dtsi"
+#include "imx8dxl-ss-ddr.dtsi"
-- 
2.31.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 2/7] arm64: dts: imx8-ss-lsio: Add mu5a mailbox
  2021-05-17 17:11 ` abelvesa
@ 2021-05-17 17:12   ` abelvesa
  -1 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Abel Vesa <abel.vesa@nxp.com>

The mailbox of the lsio mu5a is used by rpmsg on imx8qxp and
imx8dxl platforms.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index ee4e585a9c39..8e3c92c82fac 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -141,6 +141,15 @@ lsio_mu4: mailbox@5d1f0000 {
 		status = "disabled";
 	};
 
+	lsio_mu5: mailbox@5d200000 {
+		compatible = "fsl,imx6sx-mu";
+		reg = <0x5d200000 0x10000>;
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <2>;
+		power-domains = <&pd IMX_SC_R_MU_5A>;
+	};
+
+
 	lsio_mu13: mailbox@5d280000 {
 		reg = <0x5d280000 0x10000>;
 		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.31.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 2/7] arm64: dts: imx8-ss-lsio: Add mu5a mailbox
@ 2021-05-17 17:12   ` abelvesa
  0 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Abel Vesa <abel.vesa@nxp.com>

The mailbox of the lsio mu5a is used by rpmsg on imx8qxp and
imx8dxl platforms.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index ee4e585a9c39..8e3c92c82fac 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -141,6 +141,15 @@ lsio_mu4: mailbox@5d1f0000 {
 		status = "disabled";
 	};
 
+	lsio_mu5: mailbox@5d200000 {
+		compatible = "fsl,imx6sx-mu";
+		reg = <0x5d200000 0x10000>;
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+		#mbox-cells = <2>;
+		power-domains = <&pd IMX_SC_R_MU_5A>;
+	};
+
+
 	lsio_mu13: mailbox@5d280000 {
 		reg = <0x5d280000 0x10000>;
 		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.31.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 3/7] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl
  2021-05-17 17:11 ` abelvesa
@ 2021-05-17 17:12   ` abelvesa
  -1 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa, Clark Wang

From: Abel Vesa <abel.vesa@nxp.com>

Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with
the i.MX8DXL specific properties.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
new file mode 100644
index 000000000000..12ccbc6587ca
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+&audio_ipg_clk {
+	clock-frequency = <160000000>;
+};
+
+&dma_ipg_clk {
+	clock-frequency = <160000000>;
+};
+
+&i2c0 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c1 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c2 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c3 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart0 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart1 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart2 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart3 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+};
+
-- 
2.31.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 3/7] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl
@ 2021-05-17 17:12   ` abelvesa
  0 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa, Clark Wang

From: Abel Vesa <abel.vesa@nxp.com>

Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with
the i.MX8DXL specific properties.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   | 53 +++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
new file mode 100644
index 000000000000..12ccbc6587ca
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+&audio_ipg_clk {
+	clock-frequency = <160000000>;
+};
+
+&dma_ipg_clk {
+	clock-frequency = <160000000>;
+};
+
+&i2c0 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c1 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c2 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c3 {
+	compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+	interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart0 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart1 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart2 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lpuart3 {
+	compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
+	interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+};
+
-- 
2.31.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 4/7] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi
  2021-05-17 17:11 ` abelvesa
@ 2021-05-17 17:12   ` abelvesa
  -1 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Jacky Bai <ping.bai@nxp.com>

On i.MX8DXL, the Connectivity subsystem includes below peripherals:
1x ENET with AVB support, 1x ENET with TSN support, 2x USB OTG,
1x eMMC, 2x SD, 1x NAND.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 .../boot/dts/freescale/imx8dxl-ss-conn.dtsi   | 133 ++++++++++++++++++
 1 file changed, 133 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
new file mode 100644
index 000000000000..c10801926de3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+/delete-node/ &enet1_lpcg;
+/delete-node/ &fec2;
+
+&conn_subsys {
+	conn_enet0_root_clk: clock-conn-enet0-root {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <250000000>;
+		clock-output-names = "conn_enet0_root_clk";
+	};
+
+	eqos: ethernet@5b050000 {
+		compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
+		reg = <0x5b050000 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "eth_wake_irq", "macirq";
+		clocks = <&eqos_lpcg 2>,
+			 <&eqos_lpcg 4>,
+			 <&eqos_lpcg 0>,
+			 <&eqos_lpcg 3>,
+			 <&eqos_lpcg 1>;
+		clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
+		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <125000000>;
+		power-domains = <&pd IMX_SC_R_ENET_1>;
+		clk_csr = <0>;
+		status = "disabled";
+	};
+
+	usbotg2: usb@5b0e0000 {
+		compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
+		reg = <0x5b0e0000 0x200>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,usbphy = <&usbphy2>;
+		fsl,usbmisc = <&usbmisc2 0>;
+		/*
+		 * usbotg1 and usbotg2 share one clcok
+		 * scfw disable clock access and keep it always on
+		 * in case other core (M4) use one of these.
+		 */
+		clocks = <&clk_dummy>;
+		ahb-burst-config = <0x0>;
+		tx-burst-size-dword = <0x10>;
+		rx-burst-size-dword = <0x10>;
+		#stream-id-cells = <1>;
+		power-domains = <&pd IMX_SC_R_USB_1>;
+		status = "disabled";
+	};
+
+	usbmisc2: usbmisc@5b0e0200 {
+		#index-cells = <1>;
+		compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc";
+		reg = <0x5b0e0200 0x200>;
+	};
+
+	usbphy2: usbphy@0x5b110000 {
+		compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
+		reg = <0x5b110000 0x1000>;
+		clocks = <&usb2_2_lpcg 0>;
+		status = "disabled";
+	};
+
+	eqos_lpcg: clock-controller@5b240000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5b240000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&conn_enet0_root_clk>,
+			 <&conn_axi_clk>,
+			 <&conn_axi_clk>,
+			 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+			 <&conn_ipg_clk>;
+		bit-offset = <0 8 16 20 24>;
+		clock-output-names = "eqos_ptp",
+				     "eqos_mem_clk",
+				     "eqos_aclk",
+				     "eqos_clk",
+				     "eqos_csr_clk";
+		power-domains = <&pd IMX_SC_R_ENET_1>;
+	};
+
+	usb2_2_lpcg: clock-controller@5b280000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5b280000 0x10000>;
+		#clock-cells = <1>;
+
+		bit-offset = <28>;
+		clocks = <&conn_ipg_clk>;
+		clock-output-names = "usboh3_2_phy_ipg_clk";
+	};
+
+};
+
+&enet0_lpcg {
+	clocks = <&conn_enet0_root_clk>,
+		 <&conn_enet0_root_clk>,
+		 <&conn_axi_clk>,
+		 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
+		 <&conn_ipg_clk>,
+		 <&conn_ipg_clk>;
+};
+
+&fec1 {
+	compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec";
+	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+	assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
+	assigned-clock-rates = <125000000>;
+};
+
+&usdhc1 {
+	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usdhc2 {
+	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usdhc3 {
+	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+};
-- 
2.31.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 4/7] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi
@ 2021-05-17 17:12   ` abelvesa
  0 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Jacky Bai <ping.bai@nxp.com>

On i.MX8DXL, the Connectivity subsystem includes below peripherals:
1x ENET with AVB support, 1x ENET with TSN support, 2x USB OTG,
1x eMMC, 2x SD, 1x NAND.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 .../boot/dts/freescale/imx8dxl-ss-conn.dtsi   | 133 ++++++++++++++++++
 1 file changed, 133 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
new file mode 100644
index 000000000000..c10801926de3
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+/delete-node/ &enet1_lpcg;
+/delete-node/ &fec2;
+
+&conn_subsys {
+	conn_enet0_root_clk: clock-conn-enet0-root {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <250000000>;
+		clock-output-names = "conn_enet0_root_clk";
+	};
+
+	eqos: ethernet@5b050000 {
+		compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
+		reg = <0x5b050000 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "eth_wake_irq", "macirq";
+		clocks = <&eqos_lpcg 2>,
+			 <&eqos_lpcg 4>,
+			 <&eqos_lpcg 0>,
+			 <&eqos_lpcg 3>,
+			 <&eqos_lpcg 1>;
+		clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
+		assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <125000000>;
+		power-domains = <&pd IMX_SC_R_ENET_1>;
+		clk_csr = <0>;
+		status = "disabled";
+	};
+
+	usbotg2: usb@5b0e0000 {
+		compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
+		reg = <0x5b0e0000 0x200>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+		fsl,usbphy = <&usbphy2>;
+		fsl,usbmisc = <&usbmisc2 0>;
+		/*
+		 * usbotg1 and usbotg2 share one clcok
+		 * scfw disable clock access and keep it always on
+		 * in case other core (M4) use one of these.
+		 */
+		clocks = <&clk_dummy>;
+		ahb-burst-config = <0x0>;
+		tx-burst-size-dword = <0x10>;
+		rx-burst-size-dword = <0x10>;
+		#stream-id-cells = <1>;
+		power-domains = <&pd IMX_SC_R_USB_1>;
+		status = "disabled";
+	};
+
+	usbmisc2: usbmisc@5b0e0200 {
+		#index-cells = <1>;
+		compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc";
+		reg = <0x5b0e0200 0x200>;
+	};
+
+	usbphy2: usbphy@0x5b110000 {
+		compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
+		reg = <0x5b110000 0x1000>;
+		clocks = <&usb2_2_lpcg 0>;
+		status = "disabled";
+	};
+
+	eqos_lpcg: clock-controller@5b240000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5b240000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&conn_enet0_root_clk>,
+			 <&conn_axi_clk>,
+			 <&conn_axi_clk>,
+			 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
+			 <&conn_ipg_clk>;
+		bit-offset = <0 8 16 20 24>;
+		clock-output-names = "eqos_ptp",
+				     "eqos_mem_clk",
+				     "eqos_aclk",
+				     "eqos_clk",
+				     "eqos_csr_clk";
+		power-domains = <&pd IMX_SC_R_ENET_1>;
+	};
+
+	usb2_2_lpcg: clock-controller@5b280000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5b280000 0x10000>;
+		#clock-cells = <1>;
+
+		bit-offset = <28>;
+		clocks = <&conn_ipg_clk>;
+		clock-output-names = "usboh3_2_phy_ipg_clk";
+	};
+
+};
+
+&enet0_lpcg {
+	clocks = <&conn_enet0_root_clk>,
+		 <&conn_enet0_root_clk>,
+		 <&conn_axi_clk>,
+		 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
+		 <&conn_ipg_clk>,
+		 <&conn_ipg_clk>;
+};
+
+&fec1 {
+	compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec";
+	interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+	assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
+	assigned-clock-rates = <125000000>;
+};
+
+&usdhc1 {
+	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+	interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usdhc2 {
+	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+	interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usdhc3 {
+	compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
+	interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+};
-- 
2.31.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 5/7] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
  2021-05-17 17:11 ` abelvesa
@ 2021-05-17 17:12   ` abelvesa
  -1 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Jacky Bai <ping.bai@nxp.com>

Add the ddr subsys dtsi for i.MX8DXL. Additional db pmu is added
compared to i.MX8QXP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi    | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
new file mode 100644
index 000000000000..640b43f5ae97
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+&ddr_subsys {
+	db_ipg_clk: clock-db-ipg {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <456000000>;
+		clock-output-names = "db_ipg_clk";
+	};
+
+	db_pmu0: db-pmu@5ca40000 {
+		compatible = "fsl,imx8dxl-db-pmu";
+		reg = <0x5ca40000 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>;
+		clock-names = "ipg", "cnt";
+		power-domains = <&pd IMX_SC_R_PERF>;
+	};
+
+	db_pmu0_lpcg: clock-controller@5cae0000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5cae0000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&db_ipg_clk>, <&db_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "perf_lpcg_cnt_clk",
+				     "perf_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_PERF>;
+	};
+};
-- 
2.31.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 5/7] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
@ 2021-05-17 17:12   ` abelvesa
  0 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Jacky Bai <ping.bai@nxp.com>

Add the ddr subsys dtsi for i.MX8DXL. Additional db pmu is added
compared to i.MX8QXP.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi    | 34 +++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
new file mode 100644
index 000000000000..640b43f5ae97
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+&ddr_subsys {
+	db_ipg_clk: clock-db-ipg {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <456000000>;
+		clock-output-names = "db_ipg_clk";
+	};
+
+	db_pmu0: db-pmu@5ca40000 {
+		compatible = "fsl,imx8dxl-db-pmu";
+		reg = <0x5ca40000 0x10000>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>;
+		clock-names = "ipg", "cnt";
+		power-domains = <&pd IMX_SC_R_PERF>;
+	};
+
+	db_pmu0_lpcg: clock-controller@5cae0000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5cae0000 0x10000>;
+		#clock-cells = <1>;
+		clocks = <&db_ipg_clk>, <&db_ipg_clk>;
+		bit-offset = <0 16>;
+		clock-output-names = "perf_lpcg_cnt_clk",
+				     "perf_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_PERF>;
+	};
+};
-- 
2.31.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 6/7] arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl
  2021-05-17 17:11 ` abelvesa
@ 2021-05-17 17:12   ` abelvesa
  -1 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Jacky Bai <ping.bai@nxp.com>

On i.MX8DXL, the LSIO subsystem includes below devices:

1x Inline Encryption Engine (IEE)
1x FlexSPI
4x Pulse Width Modulator (PWM)
5x General Purpose Timer (GPT)
8x GPIO
14x Message Unit (MU)
256KB On-Chip Memory (OCRAM)

compared to the common imx8-ss-lsio dtsi, some nodes' interrupt
property need to be updated.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi   | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
new file mode 100644
index 000000000000..7496a38694df
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+&lsio_gpio0 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio1 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio2 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio3 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio4 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio5 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio6 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio7 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu0 {
+	compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu1 {
+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu2 {
+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu3 {
+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu4 {
+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+};
-- 
2.31.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 6/7] arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl
@ 2021-05-17 17:12   ` abelvesa
  0 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Jacky Bai <ping.bai@nxp.com>

On i.MX8DXL, the LSIO subsystem includes below devices:

1x Inline Encryption Engine (IEE)
1x FlexSPI
4x Pulse Width Modulator (PWM)
5x General Purpose Timer (GPT)
8x GPIO
14x Message Unit (MU)
256KB On-Chip Memory (OCRAM)

compared to the common imx8-ss-lsio dtsi, some nodes' interrupt
property need to be updated.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi   | 68 +++++++++++++++++++
 1 file changed, 68 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
new file mode 100644
index 000000000000..7496a38694df
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+&lsio_gpio0 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio1 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio2 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio3 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio4 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio5 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio6 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_gpio7 {
+	compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
+	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu0 {
+	compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+	interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu1 {
+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+	interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu2 {
+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu3 {
+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&lsio_mu4 {
+	compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+};
-- 
2.31.1


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^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 7/7] arm64: dts: imx8dxl: Add i.MX8DXL evk board support
  2021-05-17 17:11 ` abelvesa
@ 2021-05-17 17:12   ` abelvesa
  -1 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Jacky Bai <ping.bai@nxp.com>

Add i.MX8DXL EVK board support.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 429 ++++++++++++++++++
 2 files changed, 430 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 44890d56c194..feaa7b4054ce 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
new file mode 100644
index 000000000000..28ab4fd76aaa
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8dxl.dtsi"
+
+/ {
+	model = "Freescale i.MX8DXL EVK";
+	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
+
+	chosen {
+		stdout-path = &lpuart0;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/*
+		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
+		 * Shouldn't be used at A core and Linux side.
+		 *
+		 */
+		m4_reserved: m4@0x88000000 {
+			no-map;
+			reg = <0 0x88000000 0 0x8000000>;
+		};
+
+		rpmsg_reserved: rpmsg@0x90200000 {
+			no-map;
+			reg = <0 0x90200000 0 0x200000>;
+		};
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x14000000>;
+			alloc-ranges = <0 0x98000000 0 0x14000000>;
+			linux,cma-default;
+		};
+
+		vdev0vring0: vdev0vring0@90000000 {
+			reg = <0 0x90000000 0 0x8000>;
+			no-map;
+		};
+
+		vdev0vring1: vdev0vring1@90008000 {
+			reg = <0 0x90008000 0 0x8000>;
+			no-map;
+		};
+
+		vdev1vring0: vdev1vring0@90010000 {
+			reg = <0 0x90010000 0 0x8000>;
+			no-map;
+		};
+
+		vdev1vring1: vdev1vring1@90018000 {
+			reg = <0 0x90018000 0 0x8000>;
+			no-map;
+		};
+
+		vdevbuffer: vdevbuffer {
+			compatible = "shared-dma-pool";
+			reg = <0 0x90400000 0 0x100000>;
+			no-map;
+		};
+	};
+
+	modem_reset: modem-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&pca6416_2 0 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <2000>;
+		reset-post-delay-ms = <40>;
+		#reset-cells = <0>;
+	};
+
+	reg_usdhc2_vmmc: usdhc2-vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "SD1_SPWR";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		off-on-delay-us = <3480>;
+	};
+};
+
+&imx8dxl_cm4 {
+	memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>,
+			<&vdev1vring0>, <&vdev1vring1>;
+	status = "disabled";
+};
+
+&i2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	pca6416_1: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca6416_2: gpio@21 {
+		compatible = "ti,tca6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9548_1: pca9548@70 {
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			max7322: gpio@68 {
+				compatible = "maxim,max7322";
+				reg = <0x68>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+		};
+
+		i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4>;
+		};
+
+		i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x5>;
+		};
+
+		i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x6>;
+		};
+	};
+};
+
+&i2c3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	pca6416_3: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&lsio_gpio2>;
+		interrupts = <5 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pca9548_2: pca9548@70 {
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+		};
+
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x1>;
+		};
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+		};
+
+		i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4>;
+		};
+	};
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&lpuart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	resets = <&modem_reset>;
+	status = "okay";
+};
+
+&lsio_gpio4 {
+	status = "okay";
+};
+
+&lsio_gpio5 {
+	status = "okay";
+};
+
+&thermal_zones {
+	pmic-thermal0 {
+		polling-delay-passive = <250>;
+		polling-delay = <2000>;
+		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
+		trips {
+			pmic_alert0: trip0 {
+				temperature = <110000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+			pmic_crit0: trip1 {
+				temperature = <125000>;
+				hysteresis = <2000>;
+				type = "critical";
+			};
+		};
+		cooling-maps {
+			map0 {
+				trip = <&pmic_alert0>;
+				cooling-device =
+					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+};
+
+&usdhc1 {
+		pinctrl-names = "default", "state_100mhz", "state_200mhz";
+		pinctrl-0 = <&pinctrl_usdhc1>;
+		pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+		pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+		bus-width = <8>;
+		no-sd;
+		no-sdio;
+		non-removable;
+		status = "okay";
+};
+
+&usdhc2 {
+		pinctrl-names = "default", "state_100mhz", "state_200mhz";
+		pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+		pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+		pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+		bus-width = <4>;
+		vmmc-supply = <&reg_usdhc2_vmmc>;
+		cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
+		wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
+		max-frequency = <100000000>;
+		status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
+			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0
+			IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1		0x0600004c
+			IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN	0x0600004c
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA		0x06000021
+			IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL		0x06000021
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA		0x06000021
+			IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL		0x06000021
+		>;
+	};
+
+	pinctrl_lpuart0: lpuart0grp {
+		fsl,pins = <
+			IMX8DXL_UART0_RX_ADMA_UART0_RX		0x06000020
+			IMX8DXL_UART0_TX_ADMA_UART0_TX		0x06000020
+		>;
+	};
+
+	pinctrl_lpuart1: lpuart1grp {
+		fsl,pins = <
+			IMX8DXL_UART1_TX_ADMA_UART1_TX          0x06000020
+			IMX8DXL_UART1_RX_ADMA_UART1_RX          0x06000020
+			IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B    0x06000020
+			IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B    0x06000020
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
+			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
+			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		fsl,pins = <
+			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
+			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
+			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		fsl,pins = <
+			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
+			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
+			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000040 /* RESET_B */
+			IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x00000021 /* WP */
+			IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+		fsl,pins = <
+			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+		fsl,pins = <
+			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+		>;
+	};
+};
-- 
2.31.1


^ permalink raw reply	[flat|nested] 36+ messages in thread

* [PATCH 7/7] arm64: dts: imx8dxl: Add i.MX8DXL evk board support
@ 2021-05-17 17:12   ` abelvesa
  0 siblings, 0 replies; 36+ messages in thread
From: abelvesa @ 2021-05-17 17:12 UTC (permalink / raw)
  To: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng
  Cc: NXP Linux Team, devicetree, Linux Kernel Mailing List,
	linux-arm-kernel, Abel Vesa

From: Jacky Bai <ping.bai@nxp.com>

Add i.MX8DXL EVK board support.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
---
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 429 ++++++++++++++++++
 2 files changed, 430 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 44890d56c194..feaa7b4054ce 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
new file mode 100644
index 000000000000..28ab4fd76aaa
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
@@ -0,0 +1,429 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2021 NXP
+ */
+
+/dts-v1/;
+
+#include "imx8dxl.dtsi"
+
+/ {
+	model = "Freescale i.MX8DXL EVK";
+	compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
+
+	chosen {
+		stdout-path = &lpuart0;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000 0 0x40000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/*
+		 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
+		 * Shouldn't be used at A core and Linux side.
+		 *
+		 */
+		m4_reserved: m4@0x88000000 {
+			no-map;
+			reg = <0 0x88000000 0 0x8000000>;
+		};
+
+		rpmsg_reserved: rpmsg@0x90200000 {
+			no-map;
+			reg = <0 0x90200000 0 0x200000>;
+		};
+
+		/* global autoconfigured region for contiguous allocations */
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x14000000>;
+			alloc-ranges = <0 0x98000000 0 0x14000000>;
+			linux,cma-default;
+		};
+
+		vdev0vring0: vdev0vring0@90000000 {
+			reg = <0 0x90000000 0 0x8000>;
+			no-map;
+		};
+
+		vdev0vring1: vdev0vring1@90008000 {
+			reg = <0 0x90008000 0 0x8000>;
+			no-map;
+		};
+
+		vdev1vring0: vdev1vring0@90010000 {
+			reg = <0 0x90010000 0 0x8000>;
+			no-map;
+		};
+
+		vdev1vring1: vdev1vring1@90018000 {
+			reg = <0 0x90018000 0 0x8000>;
+			no-map;
+		};
+
+		vdevbuffer: vdevbuffer {
+			compatible = "shared-dma-pool";
+			reg = <0 0x90400000 0 0x100000>;
+			no-map;
+		};
+	};
+
+	modem_reset: modem-reset {
+		compatible = "gpio-reset";
+		reset-gpios = <&pca6416_2 0 GPIO_ACTIVE_LOW>;
+		reset-delay-us = <2000>;
+		reset-post-delay-ms = <40>;
+		#reset-cells = <0>;
+	};
+
+	reg_usdhc2_vmmc: usdhc2-vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "SD1_SPWR";
+		regulator-min-microvolt = <3000000>;
+		regulator-max-microvolt = <3000000>;
+		gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		off-on-delay-us = <3480>;
+	};
+};
+
+&imx8dxl_cm4 {
+	memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>,
+			<&vdev1vring0>, <&vdev1vring1>;
+	status = "disabled";
+};
+
+&i2c2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	status = "okay";
+
+	pca6416_1: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca6416_2: gpio@21 {
+		compatible = "ti,tca6416";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	pca9548_1: pca9548@70 {
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			max7322: gpio@68 {
+				compatible = "maxim,max7322";
+				reg = <0x68>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+		};
+
+		i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4>;
+		};
+
+		i2c@5 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x5>;
+		};
+
+		i2c@6 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x6>;
+		};
+	};
+};
+
+&i2c3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <100000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	status = "okay";
+
+	pca6416_3: gpio@20 {
+		compatible = "ti,tca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&lsio_gpio2>;
+		interrupts = <5 IRQ_TYPE_EDGE_RISING>;
+	};
+
+	pca9548_2: pca9548@70 {
+		compatible = "nxp,pca9548";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x70>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+		};
+
+		i2c@1 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x1>;
+		};
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+		};
+
+		i2c@4 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4>;
+		};
+	};
+};
+
+&lpuart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart0>;
+	status = "okay";
+};
+
+&lpuart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	resets = <&modem_reset>;
+	status = "okay";
+};
+
+&lsio_gpio4 {
+	status = "okay";
+};
+
+&lsio_gpio5 {
+	status = "okay";
+};
+
+&thermal_zones {
+	pmic-thermal0 {
+		polling-delay-passive = <250>;
+		polling-delay = <2000>;
+		thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
+		trips {
+			pmic_alert0: trip0 {
+				temperature = <110000>;
+				hysteresis = <2000>;
+				type = "passive";
+			};
+			pmic_crit0: trip1 {
+				temperature = <125000>;
+				hysteresis = <2000>;
+				type = "critical";
+			};
+		};
+		cooling-maps {
+			map0 {
+				trip = <&pmic_alert0>;
+				cooling-device =
+					<&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+					<&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			};
+		};
+	};
+};
+
+&usdhc1 {
+		pinctrl-names = "default", "state_100mhz", "state_200mhz";
+		pinctrl-0 = <&pinctrl_usdhc1>;
+		pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+		pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+		bus-width = <8>;
+		no-sd;
+		no-sdio;
+		non-removable;
+		status = "okay";
+};
+
+&usdhc2 {
+		pinctrl-names = "default", "state_100mhz", "state_200mhz";
+		pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+		pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+		pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+		bus-width = <4>;
+		vmmc-supply = <&reg_usdhc2_vmmc>;
+		cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
+		wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
+		max-frequency = <100000000>;
+		status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD	0x000514a0
+			IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD	0x000014a0
+			IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1		0x0600004c
+			IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN	0x0600004c
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA		0x06000021
+			IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL		0x06000021
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA		0x06000021
+			IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL		0x06000021
+		>;
+	};
+
+	pinctrl_lpuart0: lpuart0grp {
+		fsl,pins = <
+			IMX8DXL_UART0_RX_ADMA_UART0_RX		0x06000020
+			IMX8DXL_UART0_TX_ADMA_UART0_TX		0x06000020
+		>;
+	};
+
+	pinctrl_lpuart1: lpuart1grp {
+		fsl,pins = <
+			IMX8DXL_UART1_TX_ADMA_UART1_TX          0x06000020
+			IMX8DXL_UART1_RX_ADMA_UART1_RX          0x06000020
+			IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B    0x06000020
+			IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B    0x06000020
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
+			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
+			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+		fsl,pins = <
+			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
+			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
+			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+		fsl,pins = <
+			IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK	0x06000041
+			IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD	0x00000021
+			IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
+			IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
+			IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
+			IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
+			IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
+			IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
+			IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
+			IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
+			IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE	0x00000041
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30	0x00000040 /* RESET_B */
+			IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00	0x00000021 /* WP */
+			IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01	0x00000021 /* CD */
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+		fsl,pins = <
+			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+		fsl,pins = <
+			IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK		0x06000041
+			IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2	0x00000021
+			IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3	0x00000021
+			IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT	0x00000021
+		>;
+	};
+};
-- 
2.31.1


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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 1/7] arm64: dts: freescale: Add the top level dtsi support for imx8dxl
  2021-05-17 17:11   ` abelvesa
@ 2021-05-18  7:35     ` Dong Aisheng
  -1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:35 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:14 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> The i.MX8DXL is a device targeting the automotive and industrial
> market segments. The flexibility of the architecture allows for
> use in a wide variety of general embedded applications. The chip
> is designed to achieve both high performance and low power consumption.
> The chip relies on the power efficient dual (2x) Cortex-A35 cluster.
>
> Add the reserved memory node property for dsp reserved memory,
> the wakeup-irq property for SCU node, the imx ion, the rpmsg and the
> cm4 rproc support.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

FIrst of all, did you run make dt_binding_check?
I wonder there're dt binding missing for a few nodes

> ---
>  arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 286 +++++++++++++++++++++
>  1 file changed, 286 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> new file mode 100644
> index 000000000000..43e0bcdc2469
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +
> +#include <dt-bindings/clock/imx8-clock.h>
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/pads-imx8dxl.h>

this depends on pinctrl driver. Is that upstreamed already?

> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> +       interrupt-parent = <&gic>;
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       aliases {
> +               ethernet0 = &fec1;
> +               ethernet1 = &eqos;
> +               gpio0 = &lsio_gpio0;
> +               gpio1 = &lsio_gpio1;
> +               gpio2 = &lsio_gpio2;
> +               gpio3 = &lsio_gpio3;
> +               gpio4 = &lsio_gpio4;
> +               gpio5 = &lsio_gpio5;
> +               gpio6 = &lsio_gpio6;
> +               gpio7 = &lsio_gpio7;
> +               i2c2 = &i2c2;
> +               i2c3 = &i2c3;
> +               mmc0 = &usdhc1;
> +               mmc1 = &usdhc2;
> +               mu1 = &lsio_mu1;
> +               serial0 = &lpuart0;
> +               serial1 = &lpuart1;
> +               serial2 = &lpuart2;
> +               serial3 = &lpuart3;
> +       };
> +
> +       cpus: cpus {
> +               #address-cells = <2>;
> +               #size-cells = <0>;
> +
> +               /* We have 1 clusters with 2 Cortex-A35 cores */
> +               A35_0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a35";
> +                       reg = <0x0 0x0>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&A35_L2>;
> +                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
> +                       #cooling-cells = <2>;
> +                       operating-points-v2 = <&a35_opp_table>;
> +               };
> +
> +               A35_1: cpu@1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a35";
> +                       reg = <0x0 0x1>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&A35_L2>;
> +                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
> +                       #cooling-cells = <2>;
> +                       operating-points-v2 = <&a35_opp_table>;
> +               };
> +
> +               A35_L2: l2-cache0 {
> +                       compatible = "cache";
> +               };
> +       };
> +
> +       a35_opp_table: opp-table {
> +               compatible = "operating-points-v2";
> +               opp-shared;
> +
> +               opp-900000000 {
> +                       opp-hz = /bits/ 64 <900000000>;
> +                       opp-microvolt = <1000000>;
> +                       clock-latency-ns = <150000>;
> +               };
> +
> +               opp-1200000000 {
> +                       opp-hz = /bits/ 64 <1200000000>;
> +                       opp-microvolt = <1100000>;
> +                       clock-latency-ns = <150000>;
> +                       opp-suspend;
> +               };
> +       };
> +
> +       reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               dsp_reserved: dsp@92400000 {
> +                       reg = <0 0x92400000 0 0x2000000>;
> +                       no-map;
> +               };
> +       };

this could be added when enabling DSP in case any changes required in upstream

> +
> +       rpmsg: rpmsg{
> +               compatible = "fsl,imx8qxp-rpmsg";

I belive this is still not supported in upstream
so drop it first

> +               /* up to now, the following channels are used in imx rpmsg
> +                * - tx1/rx1: messages channel.
> +                * - general interrupt1: remote proc finish re-init rpmsg stack
> +                *   when A core is partition reset.
> +                */
> +               mbox-names = "tx", "rx", "rxdb";
> +               mboxes = <&lsio_mu5 0 1
> +                         &lsio_mu5 1 1
> +                         &lsio_mu5 3 1>;
> +               mub-partition = <3>;
> +               status = "disabled";
> +       };
> +
> +       imx8dxl_cm4: imx8dxl_cm4@0 {
> +               compatible = "fsl,imx8qxp-cm4";

i'd suggest drop it first and add in separate patch
as it's still not supported

> +               rsc-da = <0x90000000>;
> +               mbox-names = "tx", "rx", "rxdb";
> +               mboxes = <&lsio_mu5 0 1
> +                         &lsio_mu5 1 1
> +                         &lsio_mu5 3 1>;
> +               mub-partition = <3>;
> +               core-index = <0>;
> +               core-id = <IMX_SC_R_M4_0_PID0>;
> +               status = "disabled";
> +               power-domains = <&pd IMX_SC_R_M4_0_PID0>,
> +                               <&pd IMX_SC_R_M4_0_MU_1A>;
> +       };
> +
> +       gic: interrupt-controller@51a00000 {
> +               compatible = "arm,gic-v3";
> +               reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
> +                     <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
> +               #interrupt-cells = <3>;
> +               interrupt-controller;
> +               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       pmu {
> +               compatible = "arm,armv8-pmuv3";
> +               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-1.0";
> +               method = "smc";
> +       };
> +
> +       scu {
> +               compatible = "fsl,imx-scu";
> +               mbox-names = "tx0",
> +                            "rx0",
> +                            "gip3";
> +               mboxes = <&lsio_mu1 0 0
> +                         &lsio_mu1 1 0
> +                         &lsio_mu1 3 3>;
> +
> +               pd: imx8dxl-pd {
> +                       compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd";
> +                       #power-domain-cells = <1>;
> +                       wakeup-irq = <160 163 235 236 237 228 229 230 231 238
> +                                    239 240 166 169>;

drop this property first which is still not supported

> +               };
> +
> +               clk: clock-controller {
> +                       compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
> +                       #clock-cells = <2>;
> +                       clocks = <&xtal32k &xtal24m>;
> +                       clock-names = "xtal_32KHz", "xtal_24Mhz";
> +               };
> +
> +               iomuxc: pinctrl {
> +                       compatible = "fsl,imx8dxl-iomuxc";

make sure pinctrl upstreamed

> +               };
> +
> +               ocotp: imx8qx-ocotp {
> +                       compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp";

need update binding doc as well

> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +
> +                       fec_mac0: mac@2c4 {
> +                               reg = <0x2c4 6>;
> +                       };
> +
> +                       fec_mac1: mac@2c6 {
> +                               reg = <0x2c6 6>;
> +                       };
> +               };
> +
> +               rtc: rtc {
> +                       compatible = "fsl,imx8dxl-sc-rtc", "fsl,imx8qxp-sc-rtc";

pls update dt binding as well

> +               };
> +
> +               watchdog {
> +                       compatible = "fsl,imx-sc-wdt";
> +                       timeout-sec = <60>;
> +               };
> +
> +               tsens: thermal-sensor {
> +                       compatible = "fsl,imx-sc-thermal";
> +                       #thermal-sensor-cells = <1>;
> +               };
> +       };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
> +                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
> +                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
> +                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
> +       };
> +
> +       thermal_zones: thermal-zones {
> +               cpu-thermal0 {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <2000>;
> +                       thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
> +
> +                       trips {
> +                               cpu_alert0: trip0 {
> +                                       temperature = <107000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu_crit0: trip1 {
> +                                       temperature = <127000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu_alert0>;
> +                                       cooling-device =
> +                                       <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                       <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +       };
> +
> +       clk_dummy: clock-dummy {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <0>;
> +               clock-output-names = "clk_dummy";
> +       };
> +
> +       xtal32k: clock-xtal32k {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <32768>;
> +               clock-output-names = "xtal_32KHz";
> +       };
> +
> +       xtal24m: clock-xtal24m {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <24000000>;
> +               clock-output-names = "xtal_24MHz";
> +       };
> +
> +       imx_ion {
> +               compatible = "fsl,mxc-ion";

drop this unsupported node

Regards
Aisheng

> +               fsl,heap-id = <0>;
> +       };
> +
> +       sc_pwrkey: sc-powerkey {
> +               compatible = "fsl,imx8-pwrkey";
> +               linux,keycode = <KEY_POWER>;
> +               wakeup-source;
> +       };
> +
> +       /* sorted in register address */
> +       #include "imx8-ss-adma.dtsi"
> +       #include "imx8-ss-conn.dtsi"
> +       #include "imx8-ss-ddr.dtsi"
> +       #include "imx8-ss-lsio.dtsi"
> +};
> +
> +#include "imx8dxl-ss-adma.dtsi"
> +#include "imx8dxl-ss-conn.dtsi"
> +#include "imx8dxl-ss-lsio.dtsi"
> +#include "imx8dxl-ss-ddr.dtsi"
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 1/7] arm64: dts: freescale: Add the top level dtsi support for imx8dxl
@ 2021-05-18  7:35     ` Dong Aisheng
  0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:35 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:14 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> The i.MX8DXL is a device targeting the automotive and industrial
> market segments. The flexibility of the architecture allows for
> use in a wide variety of general embedded applications. The chip
> is designed to achieve both high performance and low power consumption.
> The chip relies on the power efficient dual (2x) Cortex-A35 cluster.
>
> Add the reserved memory node property for dsp reserved memory,
> the wakeup-irq property for SCU node, the imx ion, the rpmsg and the
> cm4 rproc support.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

FIrst of all, did you run make dt_binding_check?
I wonder there're dt binding missing for a few nodes

> ---
>  arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 286 +++++++++++++++++++++
>  1 file changed, 286 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> new file mode 100644
> index 000000000000..43e0bcdc2469
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +
> +#include <dt-bindings/clock/imx8-clock.h>
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/pads-imx8dxl.h>

this depends on pinctrl driver. Is that upstreamed already?

> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> +       interrupt-parent = <&gic>;
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       aliases {
> +               ethernet0 = &fec1;
> +               ethernet1 = &eqos;
> +               gpio0 = &lsio_gpio0;
> +               gpio1 = &lsio_gpio1;
> +               gpio2 = &lsio_gpio2;
> +               gpio3 = &lsio_gpio3;
> +               gpio4 = &lsio_gpio4;
> +               gpio5 = &lsio_gpio5;
> +               gpio6 = &lsio_gpio6;
> +               gpio7 = &lsio_gpio7;
> +               i2c2 = &i2c2;
> +               i2c3 = &i2c3;
> +               mmc0 = &usdhc1;
> +               mmc1 = &usdhc2;
> +               mu1 = &lsio_mu1;
> +               serial0 = &lpuart0;
> +               serial1 = &lpuart1;
> +               serial2 = &lpuart2;
> +               serial3 = &lpuart3;
> +       };
> +
> +       cpus: cpus {
> +               #address-cells = <2>;
> +               #size-cells = <0>;
> +
> +               /* We have 1 clusters with 2 Cortex-A35 cores */
> +               A35_0: cpu@0 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a35";
> +                       reg = <0x0 0x0>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&A35_L2>;
> +                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
> +                       #cooling-cells = <2>;
> +                       operating-points-v2 = <&a35_opp_table>;
> +               };
> +
> +               A35_1: cpu@1 {
> +                       device_type = "cpu";
> +                       compatible = "arm,cortex-a35";
> +                       reg = <0x0 0x1>;
> +                       enable-method = "psci";
> +                       next-level-cache = <&A35_L2>;
> +                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
> +                       #cooling-cells = <2>;
> +                       operating-points-v2 = <&a35_opp_table>;
> +               };
> +
> +               A35_L2: l2-cache0 {
> +                       compatible = "cache";
> +               };
> +       };
> +
> +       a35_opp_table: opp-table {
> +               compatible = "operating-points-v2";
> +               opp-shared;
> +
> +               opp-900000000 {
> +                       opp-hz = /bits/ 64 <900000000>;
> +                       opp-microvolt = <1000000>;
> +                       clock-latency-ns = <150000>;
> +               };
> +
> +               opp-1200000000 {
> +                       opp-hz = /bits/ 64 <1200000000>;
> +                       opp-microvolt = <1100000>;
> +                       clock-latency-ns = <150000>;
> +                       opp-suspend;
> +               };
> +       };
> +
> +       reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               dsp_reserved: dsp@92400000 {
> +                       reg = <0 0x92400000 0 0x2000000>;
> +                       no-map;
> +               };
> +       };

this could be added when enabling DSP in case any changes required in upstream

> +
> +       rpmsg: rpmsg{
> +               compatible = "fsl,imx8qxp-rpmsg";

I belive this is still not supported in upstream
so drop it first

> +               /* up to now, the following channels are used in imx rpmsg
> +                * - tx1/rx1: messages channel.
> +                * - general interrupt1: remote proc finish re-init rpmsg stack
> +                *   when A core is partition reset.
> +                */
> +               mbox-names = "tx", "rx", "rxdb";
> +               mboxes = <&lsio_mu5 0 1
> +                         &lsio_mu5 1 1
> +                         &lsio_mu5 3 1>;
> +               mub-partition = <3>;
> +               status = "disabled";
> +       };
> +
> +       imx8dxl_cm4: imx8dxl_cm4@0 {
> +               compatible = "fsl,imx8qxp-cm4";

i'd suggest drop it first and add in separate patch
as it's still not supported

> +               rsc-da = <0x90000000>;
> +               mbox-names = "tx", "rx", "rxdb";
> +               mboxes = <&lsio_mu5 0 1
> +                         &lsio_mu5 1 1
> +                         &lsio_mu5 3 1>;
> +               mub-partition = <3>;
> +               core-index = <0>;
> +               core-id = <IMX_SC_R_M4_0_PID0>;
> +               status = "disabled";
> +               power-domains = <&pd IMX_SC_R_M4_0_PID0>,
> +                               <&pd IMX_SC_R_M4_0_MU_1A>;
> +       };
> +
> +       gic: interrupt-controller@51a00000 {
> +               compatible = "arm,gic-v3";
> +               reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
> +                     <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
> +               #interrupt-cells = <3>;
> +               interrupt-controller;
> +               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       pmu {
> +               compatible = "arm,armv8-pmuv3";
> +               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +       };
> +
> +       psci {
> +               compatible = "arm,psci-1.0";
> +               method = "smc";
> +       };
> +
> +       scu {
> +               compatible = "fsl,imx-scu";
> +               mbox-names = "tx0",
> +                            "rx0",
> +                            "gip3";
> +               mboxes = <&lsio_mu1 0 0
> +                         &lsio_mu1 1 0
> +                         &lsio_mu1 3 3>;
> +
> +               pd: imx8dxl-pd {
> +                       compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd";
> +                       #power-domain-cells = <1>;
> +                       wakeup-irq = <160 163 235 236 237 228 229 230 231 238
> +                                    239 240 166 169>;

drop this property first which is still not supported

> +               };
> +
> +               clk: clock-controller {
> +                       compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
> +                       #clock-cells = <2>;
> +                       clocks = <&xtal32k &xtal24m>;
> +                       clock-names = "xtal_32KHz", "xtal_24Mhz";
> +               };
> +
> +               iomuxc: pinctrl {
> +                       compatible = "fsl,imx8dxl-iomuxc";

make sure pinctrl upstreamed

> +               };
> +
> +               ocotp: imx8qx-ocotp {
> +                       compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp";

need update binding doc as well

> +                       #address-cells = <1>;
> +                       #size-cells = <1>;
> +
> +                       fec_mac0: mac@2c4 {
> +                               reg = <0x2c4 6>;
> +                       };
> +
> +                       fec_mac1: mac@2c6 {
> +                               reg = <0x2c6 6>;
> +                       };
> +               };
> +
> +               rtc: rtc {
> +                       compatible = "fsl,imx8dxl-sc-rtc", "fsl,imx8qxp-sc-rtc";

pls update dt binding as well

> +               };
> +
> +               watchdog {
> +                       compatible = "fsl,imx-sc-wdt";
> +                       timeout-sec = <60>;
> +               };
> +
> +               tsens: thermal-sensor {
> +                       compatible = "fsl,imx-sc-thermal";
> +                       #thermal-sensor-cells = <1>;
> +               };
> +       };
> +
> +       timer {
> +               compatible = "arm,armv8-timer";
> +               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
> +                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
> +                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
> +                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
> +       };
> +
> +       thermal_zones: thermal-zones {
> +               cpu-thermal0 {
> +                       polling-delay-passive = <250>;
> +                       polling-delay = <2000>;
> +                       thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
> +
> +                       trips {
> +                               cpu_alert0: trip0 {
> +                                       temperature = <107000>;
> +                                       hysteresis = <2000>;
> +                                       type = "passive";
> +                               };
> +                               cpu_crit0: trip1 {
> +                                       temperature = <127000>;
> +                                       hysteresis = <2000>;
> +                                       type = "critical";
> +                               };
> +                       };
> +                       cooling-maps {
> +                               map0 {
> +                                       trip = <&cpu_alert0>;
> +                                       cooling-device =
> +                                       <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                       <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                               };
> +                       };
> +               };
> +       };
> +
> +       clk_dummy: clock-dummy {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <0>;
> +               clock-output-names = "clk_dummy";
> +       };
> +
> +       xtal32k: clock-xtal32k {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <32768>;
> +               clock-output-names = "xtal_32KHz";
> +       };
> +
> +       xtal24m: clock-xtal24m {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <24000000>;
> +               clock-output-names = "xtal_24MHz";
> +       };
> +
> +       imx_ion {
> +               compatible = "fsl,mxc-ion";

drop this unsupported node

Regards
Aisheng

> +               fsl,heap-id = <0>;
> +       };
> +
> +       sc_pwrkey: sc-powerkey {
> +               compatible = "fsl,imx8-pwrkey";
> +               linux,keycode = <KEY_POWER>;
> +               wakeup-source;
> +       };
> +
> +       /* sorted in register address */
> +       #include "imx8-ss-adma.dtsi"
> +       #include "imx8-ss-conn.dtsi"
> +       #include "imx8-ss-ddr.dtsi"
> +       #include "imx8-ss-lsio.dtsi"
> +};
> +
> +#include "imx8dxl-ss-adma.dtsi"
> +#include "imx8dxl-ss-conn.dtsi"
> +#include "imx8dxl-ss-lsio.dtsi"
> +#include "imx8dxl-ss-ddr.dtsi"
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 2/7] arm64: dts: imx8-ss-lsio: Add mu5a mailbox
  2021-05-17 17:12   ` abelvesa
@ 2021-05-18  7:50     ` Dong Aisheng
  -1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:50 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:14 AM <abelvesa@kernel.org> wrote:
>
> From: Abel Vesa <abel.vesa@nxp.com>
>
> The mailbox of the lsio mu5a is used by rpmsg on imx8qxp and
> imx8dxl platforms.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> index ee4e585a9c39..8e3c92c82fac 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> @@ -141,6 +141,15 @@ lsio_mu4: mailbox@5d1f0000 {
>                 status = "disabled";
>         };
>
> +       lsio_mu5: mailbox@5d200000 {
> +               compatible = "fsl,imx6sx-mu";

For normal devices node, the compatible string are prefered to be
defined in soc-ss-xxx.dtsi
in case to handle HW minus difference. e.g. mu13


> +               reg = <0x5d200000 0x10000>;
> +               interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> +               #mbox-cells = <2>;
> +               power-domains = <&pd IMX_SC_R_MU_5A>;
> +       };
> +
> +
>         lsio_mu13: mailbox@5d280000 {
>                 reg = <0x5d280000 0x10000>;
>                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 2/7] arm64: dts: imx8-ss-lsio: Add mu5a mailbox
@ 2021-05-18  7:50     ` Dong Aisheng
  0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:50 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:14 AM <abelvesa@kernel.org> wrote:
>
> From: Abel Vesa <abel.vesa@nxp.com>
>
> The mailbox of the lsio mu5a is used by rpmsg on imx8qxp and
> imx8dxl platforms.
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> index ee4e585a9c39..8e3c92c82fac 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> @@ -141,6 +141,15 @@ lsio_mu4: mailbox@5d1f0000 {
>                 status = "disabled";
>         };
>
> +       lsio_mu5: mailbox@5d200000 {
> +               compatible = "fsl,imx6sx-mu";

For normal devices node, the compatible string are prefered to be
defined in soc-ss-xxx.dtsi
in case to handle HW minus difference. e.g. mu13


> +               reg = <0x5d200000 0x10000>;
> +               interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> +               #mbox-cells = <2>;
> +               power-domains = <&pd IMX_SC_R_MU_5A>;
> +       };
> +
> +
>         lsio_mu13: mailbox@5d280000 {
>                 reg = <0x5d280000 0x10000>;
>                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 3/7] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl
  2021-05-17 17:12   ` abelvesa
@ 2021-05-18  7:52     ` Dong Aisheng
  -1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:52 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa, Clark Wang

On Tue, May 18, 2021 at 1:15 AM <abelvesa@kernel.org> wrote:
>
> From: Abel Vesa <abel.vesa@nxp.com>
>
> Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with
> the i.MX8DXL specific properties.
>
> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Please add dt-binding update as well.
Better along with this patch series

> ---
>  .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   | 53 +++++++++++++++++++
>  1 file changed, 53 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> new file mode 100644
> index 000000000000..12ccbc6587ca
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +
> +&audio_ipg_clk {
> +       clock-frequency = <160000000>;
> +};
> +
> +&dma_ipg_clk {
> +       clock-frequency = <160000000>;
> +};
> +
> +&i2c0 {
> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +       interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c1 {
> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +       interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c2 {
> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +       interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c3 {
> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart0 {
> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +       interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart1 {
> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart2 {
> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +       interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart3 {
> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +       interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 3/7] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl
@ 2021-05-18  7:52     ` Dong Aisheng
  0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:52 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa, Clark Wang

On Tue, May 18, 2021 at 1:15 AM <abelvesa@kernel.org> wrote:
>
> From: Abel Vesa <abel.vesa@nxp.com>
>
> Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with
> the i.MX8DXL specific properties.
>
> Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>

Please add dt-binding update as well.
Better along with this patch series

> ---
>  .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   | 53 +++++++++++++++++++
>  1 file changed, 53 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> new file mode 100644
> index 000000000000..12ccbc6587ca
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +
> +&audio_ipg_clk {
> +       clock-frequency = <160000000>;
> +};
> +
> +&dma_ipg_clk {
> +       clock-frequency = <160000000>;
> +};
> +
> +&i2c0 {
> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +       interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c1 {
> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +       interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c2 {
> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +       interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&i2c3 {
> +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart0 {
> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +       interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart1 {
> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart2 {
> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +       interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lpuart3 {
> +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> +       interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 4/7] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi
  2021-05-17 17:12   ` abelvesa
@ 2021-05-18  7:53     ` Dong Aisheng
  -1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:53 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:15 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> On i.MX8DXL, the Connectivity subsystem includes below peripherals:
> 1x ENET with AVB support, 1x ENET with TSN support, 2x USB OTG,
> 1x eMMC, 2x SD, 1x NAND.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  .../boot/dts/freescale/imx8dxl-ss-conn.dtsi   | 133 ++++++++++++++++++
>  1 file changed, 133 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
> new file mode 100644
> index 000000000000..c10801926de3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
> @@ -0,0 +1,133 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +
> +/delete-node/ &enet1_lpcg;
> +/delete-node/ &fec2;
> +
> +&conn_subsys {
> +       conn_enet0_root_clk: clock-conn-enet0-root {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <250000000>;
> +               clock-output-names = "conn_enet0_root_clk";
> +       };
> +
> +       eqos: ethernet@5b050000 {
> +               compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
> +               reg = <0x5b050000 0x10000>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> +               interrupt-names = "eth_wake_irq", "macirq";
> +               clocks = <&eqos_lpcg 2>,
> +                        <&eqos_lpcg 4>,
> +                        <&eqos_lpcg 0>,
> +                        <&eqos_lpcg 3>,
> +                        <&eqos_lpcg 1>;

need fix LPCG index
pls refer to binding doc

> +               clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
> +               assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
> +               assigned-clock-rates = <125000000>;
> +               power-domains = <&pd IMX_SC_R_ENET_1>;
> +               clk_csr = <0>;
> +               status = "disabled";
> +       };
> +
> +       usbotg2: usb@5b0e0000 {
> +               compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
> +               reg = <0x5b0e0000 0x200>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
> +               fsl,usbphy = <&usbphy2>;
> +               fsl,usbmisc = <&usbmisc2 0>;
> +               /*
> +                * usbotg1 and usbotg2 share one clcok
> +                * scfw disable clock access and keep it always on
> +                * in case other core (M4) use one of these.
> +                */
> +               clocks = <&clk_dummy>;
> +               ahb-burst-config = <0x0>;
> +               tx-burst-size-dword = <0x10>;
> +               rx-burst-size-dword = <0x10>;
> +               #stream-id-cells = <1>;
> +               power-domains = <&pd IMX_SC_R_USB_1>;
> +               status = "disabled";
> +       };
> +
> +       usbmisc2: usbmisc@5b0e0200 {
> +               #index-cells = <1>;
> +               compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc";
> +               reg = <0x5b0e0200 0x200>;
> +       };
> +
> +       usbphy2: usbphy@0x5b110000 {
> +               compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
> +               reg = <0x5b110000 0x1000>;
> +               clocks = <&usb2_2_lpcg 0>;
> +               status = "disabled";
> +       };
> +
> +       eqos_lpcg: clock-controller@5b240000 {
> +               compatible = "fsl,imx8qxp-lpcg";
> +               reg = <0x5b240000 0x10000>;
> +               #clock-cells = <1>;
> +               clocks = <&conn_enet0_root_clk>,
> +                        <&conn_axi_clk>,
> +                        <&conn_axi_clk>,
> +                        <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
> +                        <&conn_ipg_clk>;
> +               bit-offset = <0 8 16 20 24>;
> +               clock-output-names = "eqos_ptp",
> +                                    "eqos_mem_clk",
> +                                    "eqos_aclk",
> +                                    "eqos_clk",
> +                                    "eqos_csr_clk";
> +               power-domains = <&pd IMX_SC_R_ENET_1>;
> +       };
> +
> +       usb2_2_lpcg: clock-controller@5b280000 {
> +               compatible = "fsl,imx8qxp-lpcg";
> +               reg = <0x5b280000 0x10000>;
> +               #clock-cells = <1>;
> +
> +               bit-offset = <28>;
> +               clocks = <&conn_ipg_clk>;
> +               clock-output-names = "usboh3_2_phy_ipg_clk";
> +       };
> +
> +};
> +
> +&enet0_lpcg {
> +       clocks = <&conn_enet0_root_clk>,
> +                <&conn_enet0_root_clk>,
> +                <&conn_axi_clk>,
> +                <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
> +                <&conn_ipg_clk>,
> +                <&conn_ipg_clk>;
> +};
> +
> +&fec1 {
> +       compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec";
> +       interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> +                    <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +                    <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
> +                    <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
> +       assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
> +       assigned-clock-rates = <125000000>;
> +};
> +
> +&usdhc1 {
> +       compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
> +       interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&usdhc2 {
> +       compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
> +       interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&usdhc3 {
> +       compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
> +       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> +};
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 4/7] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi
@ 2021-05-18  7:53     ` Dong Aisheng
  0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:53 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:15 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> On i.MX8DXL, the Connectivity subsystem includes below peripherals:
> 1x ENET with AVB support, 1x ENET with TSN support, 2x USB OTG,
> 1x eMMC, 2x SD, 1x NAND.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  .../boot/dts/freescale/imx8dxl-ss-conn.dtsi   | 133 ++++++++++++++++++
>  1 file changed, 133 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
> new file mode 100644
> index 000000000000..c10801926de3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
> @@ -0,0 +1,133 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +
> +/delete-node/ &enet1_lpcg;
> +/delete-node/ &fec2;
> +
> +&conn_subsys {
> +       conn_enet0_root_clk: clock-conn-enet0-root {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <250000000>;
> +               clock-output-names = "conn_enet0_root_clk";
> +       };
> +
> +       eqos: ethernet@5b050000 {
> +               compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a";
> +               reg = <0x5b050000 0x10000>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
> +                            <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
> +               interrupt-names = "eth_wake_irq", "macirq";
> +               clocks = <&eqos_lpcg 2>,
> +                        <&eqos_lpcg 4>,
> +                        <&eqos_lpcg 0>,
> +                        <&eqos_lpcg 3>,
> +                        <&eqos_lpcg 1>;

need fix LPCG index
pls refer to binding doc

> +               clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
> +               assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>;
> +               assigned-clock-rates = <125000000>;
> +               power-domains = <&pd IMX_SC_R_ENET_1>;
> +               clk_csr = <0>;
> +               status = "disabled";
> +       };
> +
> +       usbotg2: usb@5b0e0000 {
> +               compatible = "fsl,imx8dxl-usb", "fsl,imx7ulp-usb";
> +               reg = <0x5b0e0000 0x200>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
> +               fsl,usbphy = <&usbphy2>;
> +               fsl,usbmisc = <&usbmisc2 0>;
> +               /*
> +                * usbotg1 and usbotg2 share one clcok
> +                * scfw disable clock access and keep it always on
> +                * in case other core (M4) use one of these.
> +                */
> +               clocks = <&clk_dummy>;
> +               ahb-burst-config = <0x0>;
> +               tx-burst-size-dword = <0x10>;
> +               rx-burst-size-dword = <0x10>;
> +               #stream-id-cells = <1>;
> +               power-domains = <&pd IMX_SC_R_USB_1>;
> +               status = "disabled";
> +       };
> +
> +       usbmisc2: usbmisc@5b0e0200 {
> +               #index-cells = <1>;
> +               compatible = "fsl,imx8dxl-usbmisc", "fsl,imx7ulp-usbmisc";
> +               reg = <0x5b0e0200 0x200>;
> +       };
> +
> +       usbphy2: usbphy@0x5b110000 {
> +               compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
> +               reg = <0x5b110000 0x1000>;
> +               clocks = <&usb2_2_lpcg 0>;
> +               status = "disabled";
> +       };
> +
> +       eqos_lpcg: clock-controller@5b240000 {
> +               compatible = "fsl,imx8qxp-lpcg";
> +               reg = <0x5b240000 0x10000>;
> +               #clock-cells = <1>;
> +               clocks = <&conn_enet0_root_clk>,
> +                        <&conn_axi_clk>,
> +                        <&conn_axi_clk>,
> +                        <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
> +                        <&conn_ipg_clk>;
> +               bit-offset = <0 8 16 20 24>;
> +               clock-output-names = "eqos_ptp",
> +                                    "eqos_mem_clk",
> +                                    "eqos_aclk",
> +                                    "eqos_clk",
> +                                    "eqos_csr_clk";
> +               power-domains = <&pd IMX_SC_R_ENET_1>;
> +       };
> +
> +       usb2_2_lpcg: clock-controller@5b280000 {
> +               compatible = "fsl,imx8qxp-lpcg";
> +               reg = <0x5b280000 0x10000>;
> +               #clock-cells = <1>;
> +
> +               bit-offset = <28>;
> +               clocks = <&conn_ipg_clk>;
> +               clock-output-names = "usboh3_2_phy_ipg_clk";
> +       };
> +
> +};
> +
> +&enet0_lpcg {
> +       clocks = <&conn_enet0_root_clk>,
> +                <&conn_enet0_root_clk>,
> +                <&conn_axi_clk>,
> +                <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
> +                <&conn_ipg_clk>,
> +                <&conn_ipg_clk>;
> +};
> +
> +&fec1 {
> +       compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec";
> +       interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
> +                    <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> +                    <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
> +                    <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
> +       assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
> +       assigned-clock-rates = <125000000>;
> +};
> +
> +&usdhc1 {
> +       compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
> +       interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&usdhc2 {
> +       compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
> +       interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&usdhc3 {
> +       compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
> +       interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
> +};
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 5/7] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
  2021-05-17 17:12   ` abelvesa
@ 2021-05-18  7:54     ` Dong Aisheng
  -1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:54 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:16 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> Add the ddr subsys dtsi for i.MX8DXL. Additional db pmu is added
> compared to i.MX8QXP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi    | 34 +++++++++++++++++++
>  1 file changed, 34 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
> new file mode 100644
> index 000000000000..640b43f5ae97
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +&ddr_subsys {
> +       db_ipg_clk: clock-db-ipg {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <456000000>;
> +               clock-output-names = "db_ipg_clk";
> +       };
> +
> +       db_pmu0: db-pmu@5ca40000 {
> +               compatible = "fsl,imx8dxl-db-pmu";
> +               reg = <0x5ca40000 0x10000>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
> +               clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>;

fix lpcg index

> +               clock-names = "ipg", "cnt";
> +               power-domains = <&pd IMX_SC_R_PERF>;
> +       };
> +
> +       db_pmu0_lpcg: clock-controller@5cae0000 {
> +               compatible = "fsl,imx8qxp-lpcg";
> +               reg = <0x5cae0000 0x10000>;
> +               #clock-cells = <1>;
> +               clocks = <&db_ipg_clk>, <&db_ipg_clk>;
> +               bit-offset = <0 16>;

fix lpcg index by using macro

> +               clock-output-names = "perf_lpcg_cnt_clk",
> +                                    "perf_lpcg_ipg_clk";
> +               power-domains = <&pd IMX_SC_R_PERF>;
> +       };
> +};
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 5/7] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
@ 2021-05-18  7:54     ` Dong Aisheng
  0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:54 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:16 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> Add the ddr subsys dtsi for i.MX8DXL. Additional db pmu is added
> compared to i.MX8QXP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi    | 34 +++++++++++++++++++
>  1 file changed, 34 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
> new file mode 100644
> index 000000000000..640b43f5ae97
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +&ddr_subsys {
> +       db_ipg_clk: clock-db-ipg {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <456000000>;
> +               clock-output-names = "db_ipg_clk";
> +       };
> +
> +       db_pmu0: db-pmu@5ca40000 {
> +               compatible = "fsl,imx8dxl-db-pmu";
> +               reg = <0x5ca40000 0x10000>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
> +               clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>;

fix lpcg index

> +               clock-names = "ipg", "cnt";
> +               power-domains = <&pd IMX_SC_R_PERF>;
> +       };
> +
> +       db_pmu0_lpcg: clock-controller@5cae0000 {
> +               compatible = "fsl,imx8qxp-lpcg";
> +               reg = <0x5cae0000 0x10000>;
> +               #clock-cells = <1>;
> +               clocks = <&db_ipg_clk>, <&db_ipg_clk>;
> +               bit-offset = <0 16>;

fix lpcg index by using macro

> +               clock-output-names = "perf_lpcg_cnt_clk",
> +                                    "perf_lpcg_ipg_clk";
> +               power-domains = <&pd IMX_SC_R_PERF>;
> +       };
> +};
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 6/7] arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl
  2021-05-17 17:12   ` abelvesa
@ 2021-05-18  7:55     ` Dong Aisheng
  -1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:55 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:16 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> On i.MX8DXL, the LSIO subsystem includes below devices:
>
> 1x Inline Encryption Engine (IEE)
> 1x FlexSPI
> 4x Pulse Width Modulator (PWM)
> 5x General Purpose Timer (GPT)
> 8x GPIO
> 14x Message Unit (MU)
> 256KB On-Chip Memory (OCRAM)
>
> compared to the common imx8-ss-lsio dtsi, some nodes' interrupt
> property need to be updated.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi   | 68 +++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
> new file mode 100644
> index 000000000000..7496a38694df
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +&lsio_gpio0 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio1 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio2 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio3 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio4 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio5 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio6 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio7 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu0 {
> +       compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu1 {
> +       compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +       interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu2 {
> +       compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +       interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu3 {
> +       compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +       interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu4 {
> +       compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +       interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> +};

pls add the missing mu5/13

> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 6/7] arm64: dts: freescale: Add lsio subsys dtsi for imx8dxl
@ 2021-05-18  7:55     ` Dong Aisheng
  0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:55 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:16 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> On i.MX8DXL, the LSIO subsystem includes below devices:
>
> 1x Inline Encryption Engine (IEE)
> 1x FlexSPI
> 4x Pulse Width Modulator (PWM)
> 5x General Purpose Timer (GPT)
> 8x GPIO
> 14x Message Unit (MU)
> 256KB On-Chip Memory (OCRAM)
>
> compared to the common imx8-ss-lsio dtsi, some nodes' interrupt
> property need to be updated.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  .../boot/dts/freescale/imx8dxl-ss-lsio.dtsi   | 68 +++++++++++++++++++
>  1 file changed, 68 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
> new file mode 100644
> index 000000000000..7496a38694df
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-lsio.dtsi
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +&lsio_gpio0 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio1 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio2 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio3 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio4 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio5 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio6 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_gpio7 {
> +       compatible = "fsl,imx8dxl-gpio", "fsl,imx35-gpio";
> +       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu0 {
> +       compatible = "fsl,imx8dxl-mu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu1 {
> +       compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +       interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu2 {
> +       compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +       interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu3 {
> +       compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +       interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&lsio_mu4 {
> +       compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
> +       interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> +};

pls add the missing mu5/13

> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 7/7] arm64: dts: imx8dxl: Add i.MX8DXL evk board support
  2021-05-17 17:12   ` abelvesa
@ 2021-05-18  7:57     ` Dong Aisheng
  -1 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:57 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:16 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> Add i.MX8DXL EVK board support.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/Makefile        |   1 +
>  arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 429 ++++++++++++++++++
>  2 files changed, 430 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 44890d56c194..feaa7b4054ce 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> new file mode 100644
> index 000000000000..28ab4fd76aaa
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> @@ -0,0 +1,429 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8dxl.dtsi"
> +
> +/ {
> +       model = "Freescale i.MX8DXL EVK";
> +       compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
> +
> +       chosen {
> +               stdout-path = &lpuart0;
> +       };
> +
> +       memory@80000000 {
> +               device_type = "memory";
> +               reg = <0x00000000 0x80000000 0 0x40000000>;
> +       };
> +
> +       reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               /*
> +                * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
> +                * Shouldn't be used at A core and Linux side.
> +                *
> +                */
> +               m4_reserved: m4@0x88000000 {
> +                       no-map;
> +                       reg = <0 0x88000000 0 0x8000000>;
> +               };
> +
> +               rpmsg_reserved: rpmsg@0x90200000 {
> +                       no-map;
> +                       reg = <0 0x90200000 0 0x200000>;
> +               };

suggest adding reserve memory along with function enablement

> +
> +               /* global autoconfigured region for contiguous allocations */
> +               linux,cma {
> +                       compatible = "shared-dma-pool";
> +                       reusable;
> +                       size = <0 0x14000000>;
> +                       alloc-ranges = <0 0x98000000 0 0x14000000>;
> +                       linux,cma-default;
> +               };
> +
> +               vdev0vring0: vdev0vring0@90000000 {
> +                       reg = <0 0x90000000 0 0x8000>;
> +                       no-map;
> +               };
> +
> +               vdev0vring1: vdev0vring1@90008000 {
> +                       reg = <0 0x90008000 0 0x8000>;
> +                       no-map;
> +               };
> +
> +               vdev1vring0: vdev1vring0@90010000 {
> +                       reg = <0 0x90010000 0 0x8000>;
> +                       no-map;
> +               };
> +
> +               vdev1vring1: vdev1vring1@90018000 {
> +                       reg = <0 0x90018000 0 0x8000>;
> +                       no-map;
> +               };
> +
> +               vdevbuffer: vdevbuffer {
> +                       compatible = "shared-dma-pool";
> +                       reg = <0 0x90400000 0 0x100000>;
> +                       no-map;
> +               };

ditto

> +       };
> +
> +       modem_reset: modem-reset {
> +               compatible = "gpio-reset";
> +               reset-gpios = <&pca6416_2 0 GPIO_ACTIVE_LOW>;
> +               reset-delay-us = <2000>;
> +               reset-post-delay-ms = <40>;
> +               #reset-cells = <0>;
> +       };
> +
> +       reg_usdhc2_vmmc: usdhc2-vmmc {
> +               compatible = "regulator-fixed";
> +               regulator-name = "SD1_SPWR";
> +               regulator-min-microvolt = <3000000>;
> +               regulator-max-microvolt = <3000000>;
> +               gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
> +               enable-active-high;
> +               off-on-delay-us = <3480>;
> +       };
> +};
> +
> +&imx8dxl_cm4 {
> +       memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>,
> +                       <&vdev1vring0>, <&vdev1vring1>;
> +       status = "disabled";
> +};

drop first

> +
> +&i2c2 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       clock-frequency = <100000>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_i2c2>;
> +       status = "okay";
> +
> +       pca6416_1: gpio@20 {
> +               compatible = "ti,tca6416";
> +               reg = <0x20>;
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +       };
> +
> +       pca6416_2: gpio@21 {
> +               compatible = "ti,tca6416";
> +               reg = <0x21>;
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +       };
> +
> +       pca9548_1: pca9548@70 {
> +               compatible = "nxp,pca9548";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               reg = <0x70>;
> +
> +               i2c@0 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x0>;
> +
> +                       max7322: gpio@68 {
> +                               compatible = "maxim,max7322";
> +                               reg = <0x68>;
> +                               gpio-controller;
> +                               #gpio-cells = <2>;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               i2c@4 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x4>;
> +               };
> +
> +               i2c@5 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x5>;
> +               };
> +
> +               i2c@6 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x6>;
> +               };
> +       };
> +};
> +
> +&i2c3 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       clock-frequency = <100000>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_i2c3>;
> +       status = "okay";
> +
> +       pca6416_3: gpio@20 {
> +               compatible = "ti,tca6416";
> +               reg = <0x20>;
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-parent = <&lsio_gpio2>;
> +               interrupts = <5 IRQ_TYPE_EDGE_RISING>;
> +       };
> +
> +       pca9548_2: pca9548@70 {
> +               compatible = "nxp,pca9548";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               reg = <0x70>;
> +
> +               i2c@0 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x0>;
> +               };
> +
> +               i2c@1 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x1>;
> +               };
> +
> +               i2c@2 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x2>;
> +               };
> +
> +               i2c@3 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x3>;
> +               };
> +
> +               i2c@4 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x4>;
> +               };
> +       };
> +};
> +
> +&lpuart0 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_lpuart0>;
> +       status = "okay";
> +};
> +
> +&lpuart1 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_lpuart1>;
> +       resets = <&modem_reset>;
> +       status = "okay";
> +};
> +
> +&lsio_gpio4 {
> +       status = "okay";
> +};
> +
> +&lsio_gpio5 {
> +       status = "okay";
> +};
> +
> +&thermal_zones {
> +       pmic-thermal0 {
> +               polling-delay-passive = <250>;
> +               polling-delay = <2000>;
> +               thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
> +               trips {
> +                       pmic_alert0: trip0 {
> +                               temperature = <110000>;
> +                               hysteresis = <2000>;
> +                               type = "passive";
> +                       };
> +                       pmic_crit0: trip1 {
> +                               temperature = <125000>;
> +                               hysteresis = <2000>;
> +                               type = "critical";
> +                       };
> +               };
> +               cooling-maps {
> +                       map0 {
> +                               trip = <&pmic_alert0>;
> +                               cooling-device =
> +                                       <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                       <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                       };
> +               };
> +       };
> +};
> +
> +&usdhc1 {
> +               pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +               pinctrl-0 = <&pinctrl_usdhc1>;
> +               pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> +               pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> +               bus-width = <8>;
> +               no-sd;
> +               no-sdio;
> +               non-removable;
> +               status = "okay";
> +};
> +
> +&usdhc2 {
> +               pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +               pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +               pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> +               pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> +               bus-width = <4>;
> +               vmmc-supply = <&reg_usdhc2_vmmc>;
> +               cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
> +               wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
> +               max-frequency = <100000000>;
> +               status = "okay";
> +};
> +
> +&iomuxc {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_hog>;
> +
> +       pinctrl_hog: hoggrp {
> +               fsl,pins = <
> +                       IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD       0x000514a0
> +                       IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD       0x000014a0
> +                       IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1             0x0600004c
> +                       IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN     0x0600004c
> +               >;
> +       };
> +
> +       pinctrl_i2c2: i2c2grp {
> +               fsl,pins = <
> +                       IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA          0x06000021
> +                       IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL          0x06000021
> +               >;
> +       };
> +
> +       pinctrl_i2c3: i2c3grp {
> +               fsl,pins = <
> +                       IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA          0x06000021
> +                       IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL          0x06000021
> +               >;
> +       };
> +
> +       pinctrl_lpuart0: lpuart0grp {
> +               fsl,pins = <
> +                       IMX8DXL_UART0_RX_ADMA_UART0_RX          0x06000020
> +                       IMX8DXL_UART0_TX_ADMA_UART0_TX          0x06000020
> +               >;
> +       };
> +
> +       pinctrl_lpuart1: lpuart1grp {
> +               fsl,pins = <
> +                       IMX8DXL_UART1_TX_ADMA_UART1_TX          0x06000020
> +                       IMX8DXL_UART1_RX_ADMA_UART1_RX          0x06000020
> +                       IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B    0x06000020
> +                       IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B    0x06000020
> +               >;
> +       };
> +
> +       pinctrl_usdhc1: usdhc1grp {
> +               fsl,pins = <
> +                       IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK        0x06000041
> +                       IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD        0x00000021
> +                       IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0    0x00000021
> +                       IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1    0x00000021
> +                       IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2    0x00000021
> +                       IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3    0x00000021
> +                       IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4    0x00000021
> +                       IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5    0x00000021
> +                       IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6    0x00000021
> +                       IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7    0x00000021
> +                       IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE  0x00000041
> +               >;
> +       };
> +
> +       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> +               fsl,pins = <
> +                       IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK        0x06000041
> +                       IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD        0x00000021
> +                       IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0    0x00000021
> +                       IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1    0x00000021
> +                       IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2    0x00000021
> +                       IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3    0x00000021
> +                       IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4    0x00000021
> +                       IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5    0x00000021
> +                       IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6    0x00000021
> +                       IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7    0x00000021
> +                       IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE  0x00000041
> +               >;
> +       };
> +
> +       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> +               fsl,pins = <
> +                       IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK        0x06000041
> +                       IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD        0x00000021
> +                       IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0    0x00000021
> +                       IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1    0x00000021
> +                       IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2    0x00000021
> +                       IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3    0x00000021
> +                       IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4    0x00000021
> +                       IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5    0x00000021
> +                       IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6    0x00000021
> +                       IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7    0x00000021
> +                       IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE  0x00000041
> +               >;
> +       };
> +
> +       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> +               fsl,pins = <
> +                       IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30      0x00000040 /* RESET_B */
> +                       IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00        0x00000021 /* WP */
> +                       IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01        0x00000021 /* CD */
> +               >;
> +       };
> +
> +       pinctrl_usdhc2: usdhc2grp {
> +               fsl,pins = <
> +                       IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK         0x06000041
> +                       IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3      0x00000021
> +                       IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT    0x00000021
> +               >;
> +       };
> +
> +       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> +               fsl,pins = <
> +                       IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK         0x06000041
> +                       IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3      0x00000021
> +                       IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT    0x00000021
> +               >;
> +       };
> +
> +       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> +               fsl,pins = <
> +                       IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK         0x06000041
> +                       IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3      0x00000021
> +                       IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT    0x00000021
> +               >;
> +       };
> +};
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 7/7] arm64: dts: imx8dxl: Add i.MX8DXL evk board support
@ 2021-05-18  7:57     ` Dong Aisheng
  0 siblings, 0 replies; 36+ messages in thread
From: Dong Aisheng @ 2021-05-18  7:57 UTC (permalink / raw)
  To: Abel Vesa
  Cc: Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam, Jacky Bai,
	Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Abel Vesa

On Tue, May 18, 2021 at 1:16 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> Add i.MX8DXL EVK board support.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/Makefile        |   1 +
>  arch/arm64/boot/dts/freescale/imx8dxl-evk.dts | 429 ++++++++++++++++++
>  2 files changed, 430 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 44890d56c194..feaa7b4054ce 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> new file mode 100644
> index 000000000000..28ab4fd76aaa
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
> @@ -0,0 +1,429 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2019-2021 NXP
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8dxl.dtsi"
> +
> +/ {
> +       model = "Freescale i.MX8DXL EVK";
> +       compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
> +
> +       chosen {
> +               stdout-path = &lpuart0;
> +       };
> +
> +       memory@80000000 {
> +               device_type = "memory";
> +               reg = <0x00000000 0x80000000 0 0x40000000>;
> +       };
> +
> +       reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               /*
> +                * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
> +                * Shouldn't be used at A core and Linux side.
> +                *
> +                */
> +               m4_reserved: m4@0x88000000 {
> +                       no-map;
> +                       reg = <0 0x88000000 0 0x8000000>;
> +               };
> +
> +               rpmsg_reserved: rpmsg@0x90200000 {
> +                       no-map;
> +                       reg = <0 0x90200000 0 0x200000>;
> +               };

suggest adding reserve memory along with function enablement

> +
> +               /* global autoconfigured region for contiguous allocations */
> +               linux,cma {
> +                       compatible = "shared-dma-pool";
> +                       reusable;
> +                       size = <0 0x14000000>;
> +                       alloc-ranges = <0 0x98000000 0 0x14000000>;
> +                       linux,cma-default;
> +               };
> +
> +               vdev0vring0: vdev0vring0@90000000 {
> +                       reg = <0 0x90000000 0 0x8000>;
> +                       no-map;
> +               };
> +
> +               vdev0vring1: vdev0vring1@90008000 {
> +                       reg = <0 0x90008000 0 0x8000>;
> +                       no-map;
> +               };
> +
> +               vdev1vring0: vdev1vring0@90010000 {
> +                       reg = <0 0x90010000 0 0x8000>;
> +                       no-map;
> +               };
> +
> +               vdev1vring1: vdev1vring1@90018000 {
> +                       reg = <0 0x90018000 0 0x8000>;
> +                       no-map;
> +               };
> +
> +               vdevbuffer: vdevbuffer {
> +                       compatible = "shared-dma-pool";
> +                       reg = <0 0x90400000 0 0x100000>;
> +                       no-map;
> +               };

ditto

> +       };
> +
> +       modem_reset: modem-reset {
> +               compatible = "gpio-reset";
> +               reset-gpios = <&pca6416_2 0 GPIO_ACTIVE_LOW>;
> +               reset-delay-us = <2000>;
> +               reset-post-delay-ms = <40>;
> +               #reset-cells = <0>;
> +       };
> +
> +       reg_usdhc2_vmmc: usdhc2-vmmc {
> +               compatible = "regulator-fixed";
> +               regulator-name = "SD1_SPWR";
> +               regulator-min-microvolt = <3000000>;
> +               regulator-max-microvolt = <3000000>;
> +               gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
> +               enable-active-high;
> +               off-on-delay-us = <3480>;
> +       };
> +};
> +
> +&imx8dxl_cm4 {
> +       memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>,
> +                       <&vdev1vring0>, <&vdev1vring1>;
> +       status = "disabled";
> +};

drop first

> +
> +&i2c2 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       clock-frequency = <100000>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_i2c2>;
> +       status = "okay";
> +
> +       pca6416_1: gpio@20 {
> +               compatible = "ti,tca6416";
> +               reg = <0x20>;
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +       };
> +
> +       pca6416_2: gpio@21 {
> +               compatible = "ti,tca6416";
> +               reg = <0x21>;
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +       };
> +
> +       pca9548_1: pca9548@70 {
> +               compatible = "nxp,pca9548";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               reg = <0x70>;
> +
> +               i2c@0 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x0>;
> +
> +                       max7322: gpio@68 {
> +                               compatible = "maxim,max7322";
> +                               reg = <0x68>;
> +                               gpio-controller;
> +                               #gpio-cells = <2>;
> +                               status = "disabled";
> +                       };
> +               };
> +
> +               i2c@4 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x4>;
> +               };
> +
> +               i2c@5 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x5>;
> +               };
> +
> +               i2c@6 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x6>;
> +               };
> +       };
> +};
> +
> +&i2c3 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       clock-frequency = <100000>;
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_i2c3>;
> +       status = "okay";
> +
> +       pca6416_3: gpio@20 {
> +               compatible = "ti,tca6416";
> +               reg = <0x20>;
> +               gpio-controller;
> +               #gpio-cells = <2>;
> +               interrupt-parent = <&lsio_gpio2>;
> +               interrupts = <5 IRQ_TYPE_EDGE_RISING>;
> +       };
> +
> +       pca9548_2: pca9548@70 {
> +               compatible = "nxp,pca9548";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               reg = <0x70>;
> +
> +               i2c@0 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x0>;
> +               };
> +
> +               i2c@1 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x1>;
> +               };
> +
> +               i2c@2 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x2>;
> +               };
> +
> +               i2c@3 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x3>;
> +               };
> +
> +               i2c@4 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <0x4>;
> +               };
> +       };
> +};
> +
> +&lpuart0 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_lpuart0>;
> +       status = "okay";
> +};
> +
> +&lpuart1 {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_lpuart1>;
> +       resets = <&modem_reset>;
> +       status = "okay";
> +};
> +
> +&lsio_gpio4 {
> +       status = "okay";
> +};
> +
> +&lsio_gpio5 {
> +       status = "okay";
> +};
> +
> +&thermal_zones {
> +       pmic-thermal0 {
> +               polling-delay-passive = <250>;
> +               polling-delay = <2000>;
> +               thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
> +               trips {
> +                       pmic_alert0: trip0 {
> +                               temperature = <110000>;
> +                               hysteresis = <2000>;
> +                               type = "passive";
> +                       };
> +                       pmic_crit0: trip1 {
> +                               temperature = <125000>;
> +                               hysteresis = <2000>;
> +                               type = "critical";
> +                       };
> +               };
> +               cooling-maps {
> +                       map0 {
> +                               trip = <&pmic_alert0>;
> +                               cooling-device =
> +                                       <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> +                                       <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> +                       };
> +               };
> +       };
> +};
> +
> +&usdhc1 {
> +               pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +               pinctrl-0 = <&pinctrl_usdhc1>;
> +               pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> +               pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> +               bus-width = <8>;
> +               no-sd;
> +               no-sdio;
> +               non-removable;
> +               status = "okay";
> +};
> +
> +&usdhc2 {
> +               pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +               pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +               pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> +               pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> +               bus-width = <4>;
> +               vmmc-supply = <&reg_usdhc2_vmmc>;
> +               cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
> +               wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
> +               max-frequency = <100000000>;
> +               status = "okay";
> +};
> +
> +&iomuxc {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&pinctrl_hog>;
> +
> +       pinctrl_hog: hoggrp {
> +               fsl,pins = <
> +                       IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD       0x000514a0
> +                       IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD       0x000014a0
> +                       IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1             0x0600004c
> +                       IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN     0x0600004c
> +               >;
> +       };
> +
> +       pinctrl_i2c2: i2c2grp {
> +               fsl,pins = <
> +                       IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA          0x06000021
> +                       IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL          0x06000021
> +               >;
> +       };
> +
> +       pinctrl_i2c3: i2c3grp {
> +               fsl,pins = <
> +                       IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA          0x06000021
> +                       IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL          0x06000021
> +               >;
> +       };
> +
> +       pinctrl_lpuart0: lpuart0grp {
> +               fsl,pins = <
> +                       IMX8DXL_UART0_RX_ADMA_UART0_RX          0x06000020
> +                       IMX8DXL_UART0_TX_ADMA_UART0_TX          0x06000020
> +               >;
> +       };
> +
> +       pinctrl_lpuart1: lpuart1grp {
> +               fsl,pins = <
> +                       IMX8DXL_UART1_TX_ADMA_UART1_TX          0x06000020
> +                       IMX8DXL_UART1_RX_ADMA_UART1_RX          0x06000020
> +                       IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B    0x06000020
> +                       IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B    0x06000020
> +               >;
> +       };
> +
> +       pinctrl_usdhc1: usdhc1grp {
> +               fsl,pins = <
> +                       IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK        0x06000041
> +                       IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD        0x00000021
> +                       IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0    0x00000021
> +                       IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1    0x00000021
> +                       IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2    0x00000021
> +                       IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3    0x00000021
> +                       IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4    0x00000021
> +                       IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5    0x00000021
> +                       IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6    0x00000021
> +                       IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7    0x00000021
> +                       IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE  0x00000041
> +               >;
> +       };
> +
> +       pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> +               fsl,pins = <
> +                       IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK        0x06000041
> +                       IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD        0x00000021
> +                       IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0    0x00000021
> +                       IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1    0x00000021
> +                       IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2    0x00000021
> +                       IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3    0x00000021
> +                       IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4    0x00000021
> +                       IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5    0x00000021
> +                       IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6    0x00000021
> +                       IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7    0x00000021
> +                       IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE  0x00000041
> +               >;
> +       };
> +
> +       pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> +               fsl,pins = <
> +                       IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK        0x06000041
> +                       IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD        0x00000021
> +                       IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0    0x00000021
> +                       IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1    0x00000021
> +                       IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2    0x00000021
> +                       IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3    0x00000021
> +                       IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4    0x00000021
> +                       IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5    0x00000021
> +                       IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6    0x00000021
> +                       IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7    0x00000021
> +                       IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE  0x00000041
> +               >;
> +       };
> +
> +       pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> +               fsl,pins = <
> +                       IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30      0x00000040 /* RESET_B */
> +                       IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00        0x00000021 /* WP */
> +                       IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01        0x00000021 /* CD */
> +               >;
> +       };
> +
> +       pinctrl_usdhc2: usdhc2grp {
> +               fsl,pins = <
> +                       IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK         0x06000041
> +                       IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3      0x00000021
> +                       IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT    0x00000021
> +               >;
> +       };
> +
> +       pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> +               fsl,pins = <
> +                       IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK         0x06000041
> +                       IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3      0x00000021
> +                       IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT    0x00000021
> +               >;
> +       };
> +
> +       pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> +               fsl,pins = <
> +                       IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK         0x06000041
> +                       IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2      0x00000021
> +                       IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3      0x00000021
> +                       IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT    0x00000021
> +               >;
> +       };
> +};
> --
> 2.31.1
>
>
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^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 1/7] arm64: dts: freescale: Add the top level dtsi support for imx8dxl
  2021-05-18  7:35     ` Dong Aisheng
@ 2021-06-02  9:29       ` Abel Vesa
  -1 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2021-06-02  9:29 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: Abel Vesa, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam,
	Jacky Bai, Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On 21-05-18 15:35:41, Dong Aisheng wrote:
> On Tue, May 18, 2021 at 1:14 AM <abelvesa@kernel.org> wrote:
> >
> > From: Jacky Bai <ping.bai@nxp.com>
> >
> > The i.MX8DXL is a device targeting the automotive and industrial
> > market segments. The flexibility of the architecture allows for
> > use in a wide variety of general embedded applications. The chip
> > is designed to achieve both high performance and low power consumption.
> > The chip relies on the power efficient dual (2x) Cortex-A35 cluster.
> >
> > Add the reserved memory node property for dsp reserved memory,
> > the wakeup-irq property for SCU node, the imx ion, the rpmsg and the
> > cm4 rproc support.
> >
> > Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> 
> FIrst of all, did you run make dt_binding_check?
> I wonder there're dt binding missing for a few nodes
> 

Fixing those in the next version.

> > ---
> >  arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 286 +++++++++++++++++++++
> >  1 file changed, 286 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> > new file mode 100644
> > index 000000000000..43e0bcdc2469
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> > @@ -0,0 +1,286 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019-2021 NXP
> > + */
> > +
> > +#include <dt-bindings/clock/imx8-clock.h>
> > +#include <dt-bindings/firmware/imx/rsrc.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/input/input.h>
> > +#include <dt-bindings/pinctrl/pads-imx8dxl.h>
> 
> this depends on pinctrl driver. Is that upstreamed already?
> 

It is upstreamed.

> > +#include <dt-bindings/thermal/thermal.h>
> > +
> > +/ {
> > +       interrupt-parent = <&gic>;
> > +       #address-cells = <2>;
> > +       #size-cells = <2>;
> > +
> > +       aliases {
> > +               ethernet0 = &fec1;
> > +               ethernet1 = &eqos;
> > +               gpio0 = &lsio_gpio0;
> > +               gpio1 = &lsio_gpio1;
> > +               gpio2 = &lsio_gpio2;
> > +               gpio3 = &lsio_gpio3;
> > +               gpio4 = &lsio_gpio4;
> > +               gpio5 = &lsio_gpio5;
> > +               gpio6 = &lsio_gpio6;
> > +               gpio7 = &lsio_gpio7;
> > +               i2c2 = &i2c2;
> > +               i2c3 = &i2c3;
> > +               mmc0 = &usdhc1;
> > +               mmc1 = &usdhc2;
> > +               mu1 = &lsio_mu1;
> > +               serial0 = &lpuart0;
> > +               serial1 = &lpuart1;
> > +               serial2 = &lpuart2;
> > +               serial3 = &lpuart3;
> > +       };
> > +
> > +       cpus: cpus {
> > +               #address-cells = <2>;
> > +               #size-cells = <0>;
> > +
> > +               /* We have 1 clusters with 2 Cortex-A35 cores */
> > +               A35_0: cpu@0 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a35";
> > +                       reg = <0x0 0x0>;
> > +                       enable-method = "psci";
> > +                       next-level-cache = <&A35_L2>;
> > +                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
> > +                       #cooling-cells = <2>;
> > +                       operating-points-v2 = <&a35_opp_table>;
> > +               };
> > +
> > +               A35_1: cpu@1 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a35";
> > +                       reg = <0x0 0x1>;
> > +                       enable-method = "psci";
> > +                       next-level-cache = <&A35_L2>;
> > +                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
> > +                       #cooling-cells = <2>;
> > +                       operating-points-v2 = <&a35_opp_table>;
> > +               };
> > +
> > +               A35_L2: l2-cache0 {
> > +                       compatible = "cache";
> > +               };
> > +       };
> > +
> > +       a35_opp_table: opp-table {
> > +               compatible = "operating-points-v2";
> > +               opp-shared;
> > +
> > +               opp-900000000 {
> > +                       opp-hz = /bits/ 64 <900000000>;
> > +                       opp-microvolt = <1000000>;
> > +                       clock-latency-ns = <150000>;
> > +               };
> > +
> > +               opp-1200000000 {
> > +                       opp-hz = /bits/ 64 <1200000000>;
> > +                       opp-microvolt = <1100000>;
> > +                       clock-latency-ns = <150000>;
> > +                       opp-suspend;
> > +               };
> > +       };
> > +
> > +       reserved-memory {
> > +               #address-cells = <2>;
> > +               #size-cells = <2>;
> > +               ranges;
> > +
> > +               dsp_reserved: dsp@92400000 {
> > +                       reg = <0 0x92400000 0 0x2000000>;
> > +                       no-map;
> > +               };
> > +       };
> 
> this could be added when enabling DSP in case any changes required in upstream
>

Unfortunately, the imx8-ss-adma already depends on it. So it needs to go
in now, otherwise it won't build.

> > +
> > +       rpmsg: rpmsg{
> > +               compatible = "fsl,imx8qxp-rpmsg";
> 
> I belive this is still not supported in upstream
> so drop it first
> 

Removed in the next version.

> > +               /* up to now, the following channels are used in imx rpmsg
> > +                * - tx1/rx1: messages channel.
> > +                * - general interrupt1: remote proc finish re-init rpmsg stack
> > +                *   when A core is partition reset.
> > +                */
> > +               mbox-names = "tx", "rx", "rxdb";
> > +               mboxes = <&lsio_mu5 0 1
> > +                         &lsio_mu5 1 1
> > +                         &lsio_mu5 3 1>;
> > +               mub-partition = <3>;
> > +               status = "disabled";
> > +       };
> > +
> > +       imx8dxl_cm4: imx8dxl_cm4@0 {
> > +               compatible = "fsl,imx8qxp-cm4";
> 
> i'd suggest drop it first and add in separate patch
> as it's still not supported
> 

Removed in the next version.

> > +               rsc-da = <0x90000000>;
> > +               mbox-names = "tx", "rx", "rxdb";
> > +               mboxes = <&lsio_mu5 0 1
> > +                         &lsio_mu5 1 1
> > +                         &lsio_mu5 3 1>;
> > +               mub-partition = <3>;
> > +               core-index = <0>;
> > +               core-id = <IMX_SC_R_M4_0_PID0>;
> > +               status = "disabled";
> > +               power-domains = <&pd IMX_SC_R_M4_0_PID0>,
> > +                               <&pd IMX_SC_R_M4_0_MU_1A>;
> > +       };
> > +
> > +       gic: interrupt-controller@51a00000 {
> > +               compatible = "arm,gic-v3";
> > +               reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
> > +                     <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
> > +               #interrupt-cells = <3>;
> > +               interrupt-controller;
> > +               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       pmu {
> > +               compatible = "arm,armv8-pmuv3";
> > +               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       psci {
> > +               compatible = "arm,psci-1.0";
> > +               method = "smc";
> > +       };
> > +
> > +       scu {
> > +               compatible = "fsl,imx-scu";
> > +               mbox-names = "tx0",
> > +                            "rx0",
> > +                            "gip3";
> > +               mboxes = <&lsio_mu1 0 0
> > +                         &lsio_mu1 1 0
> > +                         &lsio_mu1 3 3>;
> > +
> > +               pd: imx8dxl-pd {
> > +                       compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd";
> > +                       #power-domain-cells = <1>;
> > +                       wakeup-irq = <160 163 235 236 237 228 229 230 231 238
> > +                                    239 240 166 169>;
> 
> drop this property first which is still not supported
> 

Removed in the next version.

> > +               };
> > +
> > +               clk: clock-controller {
> > +                       compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
> > +                       #clock-cells = <2>;
> > +                       clocks = <&xtal32k &xtal24m>;
> > +                       clock-names = "xtal_32KHz", "xtal_24Mhz";
> > +               };
> > +
> > +               iomuxc: pinctrl {
> > +                       compatible = "fsl,imx8dxl-iomuxc";
> 
> make sure pinctrl upstreamed
> 

It is upstreamed.

> > +               };
> > +
> > +               ocotp: imx8qx-ocotp {
> > +                       compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp";
> 
> need update binding doc as well
> 

Will do in the next version.

> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +
> > +                       fec_mac0: mac@2c4 {
> > +                               reg = <0x2c4 6>;
> > +                       };
> > +
> > +                       fec_mac1: mac@2c6 {
> > +                               reg = <0x2c6 6>;
> > +                       };
> > +               };
> > +
> > +               rtc: rtc {
> > +                       compatible = "fsl,imx8dxl-sc-rtc", "fsl,imx8qxp-sc-rtc";
> 
> pls update dt binding as well
> 

I'll actually remove this in the next version.

Will be sent later on as a separate patch.

> > +               };
> > +
> > +               watchdog {
> > +                       compatible = "fsl,imx-sc-wdt";
> > +                       timeout-sec = <60>;
> > +               };
> > +
> > +               tsens: thermal-sensor {
> > +                       compatible = "fsl,imx-sc-thermal";
> > +                       #thermal-sensor-cells = <1>;
> > +               };
> > +       };
> > +
> > +       timer {
> > +               compatible = "arm,armv8-timer";
> > +               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
> > +                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
> > +                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
> > +                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
> > +       };
> > +
> > +       thermal_zones: thermal-zones {
> > +               cpu-thermal0 {
> > +                       polling-delay-passive = <250>;
> > +                       polling-delay = <2000>;
> > +                       thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
> > +
> > +                       trips {
> > +                               cpu_alert0: trip0 {
> > +                                       temperature = <107000>;
> > +                                       hysteresis = <2000>;
> > +                                       type = "passive";
> > +                               };
> > +                               cpu_crit0: trip1 {
> > +                                       temperature = <127000>;
> > +                                       hysteresis = <2000>;
> > +                                       type = "critical";
> > +                               };
> > +                       };
> > +                       cooling-maps {
> > +                               map0 {
> > +                                       trip = <&cpu_alert0>;
> > +                                       cooling-device =
> > +                                       <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > +                                       <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > +                               };
> > +                       };
> > +               };
> > +       };
> > +
> > +       clk_dummy: clock-dummy {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <0>;
> > +               clock-output-names = "clk_dummy";
> > +       };
> > +
> > +       xtal32k: clock-xtal32k {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <32768>;
> > +               clock-output-names = "xtal_32KHz";
> > +       };
> > +
> > +       xtal24m: clock-xtal24m {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <24000000>;
> > +               clock-output-names = "xtal_24MHz";
> > +       };
> > +
> > +       imx_ion {
> > +               compatible = "fsl,mxc-ion";
> 
> drop this unsupported node
> 

Removed in the next version.

> Regards
> Aisheng
> 
> > +               fsl,heap-id = <0>;
> > +       };
> > +
> > +       sc_pwrkey: sc-powerkey {
> > +               compatible = "fsl,imx8-pwrkey";
> > +               linux,keycode = <KEY_POWER>;
> > +               wakeup-source;
> > +       };
> > +
> > +       /* sorted in register address */
> > +       #include "imx8-ss-adma.dtsi"
> > +       #include "imx8-ss-conn.dtsi"
> > +       #include "imx8-ss-ddr.dtsi"
> > +       #include "imx8-ss-lsio.dtsi"
> > +};
> > +
> > +#include "imx8dxl-ss-adma.dtsi"
> > +#include "imx8dxl-ss-conn.dtsi"
> > +#include "imx8dxl-ss-lsio.dtsi"
> > +#include "imx8dxl-ss-ddr.dtsi"
> > --
> > 2.31.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&amp;data=04%7C01%7Cabel.vesa%40nxp.com%7C843de7d5f11f49ba992408d919cfafdc%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637569202065001061%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=ZmB%2FXRdAz3Y0q2FFu2C2Y6cqYbfDQkk7Q1SNqESO2zc%3D&amp;reserved=0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 1/7] arm64: dts: freescale: Add the top level dtsi support for imx8dxl
@ 2021-06-02  9:29       ` Abel Vesa
  0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2021-06-02  9:29 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: Abel Vesa, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam,
	Jacky Bai, Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On 21-05-18 15:35:41, Dong Aisheng wrote:
> On Tue, May 18, 2021 at 1:14 AM <abelvesa@kernel.org> wrote:
> >
> > From: Jacky Bai <ping.bai@nxp.com>
> >
> > The i.MX8DXL is a device targeting the automotive and industrial
> > market segments. The flexibility of the architecture allows for
> > use in a wide variety of general embedded applications. The chip
> > is designed to achieve both high performance and low power consumption.
> > The chip relies on the power efficient dual (2x) Cortex-A35 cluster.
> >
> > Add the reserved memory node property for dsp reserved memory,
> > the wakeup-irq property for SCU node, the imx ion, the rpmsg and the
> > cm4 rproc support.
> >
> > Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> 
> FIrst of all, did you run make dt_binding_check?
> I wonder there're dt binding missing for a few nodes
> 

Fixing those in the next version.

> > ---
> >  arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 286 +++++++++++++++++++++
> >  1 file changed, 286 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> > new file mode 100644
> > index 000000000000..43e0bcdc2469
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi
> > @@ -0,0 +1,286 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019-2021 NXP
> > + */
> > +
> > +#include <dt-bindings/clock/imx8-clock.h>
> > +#include <dt-bindings/firmware/imx/rsrc.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/input/input.h>
> > +#include <dt-bindings/pinctrl/pads-imx8dxl.h>
> 
> this depends on pinctrl driver. Is that upstreamed already?
> 

It is upstreamed.

> > +#include <dt-bindings/thermal/thermal.h>
> > +
> > +/ {
> > +       interrupt-parent = <&gic>;
> > +       #address-cells = <2>;
> > +       #size-cells = <2>;
> > +
> > +       aliases {
> > +               ethernet0 = &fec1;
> > +               ethernet1 = &eqos;
> > +               gpio0 = &lsio_gpio0;
> > +               gpio1 = &lsio_gpio1;
> > +               gpio2 = &lsio_gpio2;
> > +               gpio3 = &lsio_gpio3;
> > +               gpio4 = &lsio_gpio4;
> > +               gpio5 = &lsio_gpio5;
> > +               gpio6 = &lsio_gpio6;
> > +               gpio7 = &lsio_gpio7;
> > +               i2c2 = &i2c2;
> > +               i2c3 = &i2c3;
> > +               mmc0 = &usdhc1;
> > +               mmc1 = &usdhc2;
> > +               mu1 = &lsio_mu1;
> > +               serial0 = &lpuart0;
> > +               serial1 = &lpuart1;
> > +               serial2 = &lpuart2;
> > +               serial3 = &lpuart3;
> > +       };
> > +
> > +       cpus: cpus {
> > +               #address-cells = <2>;
> > +               #size-cells = <0>;
> > +
> > +               /* We have 1 clusters with 2 Cortex-A35 cores */
> > +               A35_0: cpu@0 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a35";
> > +                       reg = <0x0 0x0>;
> > +                       enable-method = "psci";
> > +                       next-level-cache = <&A35_L2>;
> > +                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
> > +                       #cooling-cells = <2>;
> > +                       operating-points-v2 = <&a35_opp_table>;
> > +               };
> > +
> > +               A35_1: cpu@1 {
> > +                       device_type = "cpu";
> > +                       compatible = "arm,cortex-a35";
> > +                       reg = <0x0 0x1>;
> > +                       enable-method = "psci";
> > +                       next-level-cache = <&A35_L2>;
> > +                       clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>;
> > +                       #cooling-cells = <2>;
> > +                       operating-points-v2 = <&a35_opp_table>;
> > +               };
> > +
> > +               A35_L2: l2-cache0 {
> > +                       compatible = "cache";
> > +               };
> > +       };
> > +
> > +       a35_opp_table: opp-table {
> > +               compatible = "operating-points-v2";
> > +               opp-shared;
> > +
> > +               opp-900000000 {
> > +                       opp-hz = /bits/ 64 <900000000>;
> > +                       opp-microvolt = <1000000>;
> > +                       clock-latency-ns = <150000>;
> > +               };
> > +
> > +               opp-1200000000 {
> > +                       opp-hz = /bits/ 64 <1200000000>;
> > +                       opp-microvolt = <1100000>;
> > +                       clock-latency-ns = <150000>;
> > +                       opp-suspend;
> > +               };
> > +       };
> > +
> > +       reserved-memory {
> > +               #address-cells = <2>;
> > +               #size-cells = <2>;
> > +               ranges;
> > +
> > +               dsp_reserved: dsp@92400000 {
> > +                       reg = <0 0x92400000 0 0x2000000>;
> > +                       no-map;
> > +               };
> > +       };
> 
> this could be added when enabling DSP in case any changes required in upstream
>

Unfortunately, the imx8-ss-adma already depends on it. So it needs to go
in now, otherwise it won't build.

> > +
> > +       rpmsg: rpmsg{
> > +               compatible = "fsl,imx8qxp-rpmsg";
> 
> I belive this is still not supported in upstream
> so drop it first
> 

Removed in the next version.

> > +               /* up to now, the following channels are used in imx rpmsg
> > +                * - tx1/rx1: messages channel.
> > +                * - general interrupt1: remote proc finish re-init rpmsg stack
> > +                *   when A core is partition reset.
> > +                */
> > +               mbox-names = "tx", "rx", "rxdb";
> > +               mboxes = <&lsio_mu5 0 1
> > +                         &lsio_mu5 1 1
> > +                         &lsio_mu5 3 1>;
> > +               mub-partition = <3>;
> > +               status = "disabled";
> > +       };
> > +
> > +       imx8dxl_cm4: imx8dxl_cm4@0 {
> > +               compatible = "fsl,imx8qxp-cm4";
> 
> i'd suggest drop it first and add in separate patch
> as it's still not supported
> 

Removed in the next version.

> > +               rsc-da = <0x90000000>;
> > +               mbox-names = "tx", "rx", "rxdb";
> > +               mboxes = <&lsio_mu5 0 1
> > +                         &lsio_mu5 1 1
> > +                         &lsio_mu5 3 1>;
> > +               mub-partition = <3>;
> > +               core-index = <0>;
> > +               core-id = <IMX_SC_R_M4_0_PID0>;
> > +               status = "disabled";
> > +               power-domains = <&pd IMX_SC_R_M4_0_PID0>,
> > +                               <&pd IMX_SC_R_M4_0_MU_1A>;
> > +       };
> > +
> > +       gic: interrupt-controller@51a00000 {
> > +               compatible = "arm,gic-v3";
> > +               reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
> > +                     <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
> > +               #interrupt-cells = <3>;
> > +               interrupt-controller;
> > +               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       pmu {
> > +               compatible = "arm,armv8-pmuv3";
> > +               interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> > +       };
> > +
> > +       psci {
> > +               compatible = "arm,psci-1.0";
> > +               method = "smc";
> > +       };
> > +
> > +       scu {
> > +               compatible = "fsl,imx-scu";
> > +               mbox-names = "tx0",
> > +                            "rx0",
> > +                            "gip3";
> > +               mboxes = <&lsio_mu1 0 0
> > +                         &lsio_mu1 1 0
> > +                         &lsio_mu1 3 3>;
> > +
> > +               pd: imx8dxl-pd {
> > +                       compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd";
> > +                       #power-domain-cells = <1>;
> > +                       wakeup-irq = <160 163 235 236 237 228 229 230 231 238
> > +                                    239 240 166 169>;
> 
> drop this property first which is still not supported
> 

Removed in the next version.

> > +               };
> > +
> > +               clk: clock-controller {
> > +                       compatible = "fsl,imx8dxl-clk", "fsl,scu-clk";
> > +                       #clock-cells = <2>;
> > +                       clocks = <&xtal32k &xtal24m>;
> > +                       clock-names = "xtal_32KHz", "xtal_24Mhz";
> > +               };
> > +
> > +               iomuxc: pinctrl {
> > +                       compatible = "fsl,imx8dxl-iomuxc";
> 
> make sure pinctrl upstreamed
> 

It is upstreamed.

> > +               };
> > +
> > +               ocotp: imx8qx-ocotp {
> > +                       compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp";
> 
> need update binding doc as well
> 

Will do in the next version.

> > +                       #address-cells = <1>;
> > +                       #size-cells = <1>;
> > +
> > +                       fec_mac0: mac@2c4 {
> > +                               reg = <0x2c4 6>;
> > +                       };
> > +
> > +                       fec_mac1: mac@2c6 {
> > +                               reg = <0x2c6 6>;
> > +                       };
> > +               };
> > +
> > +               rtc: rtc {
> > +                       compatible = "fsl,imx8dxl-sc-rtc", "fsl,imx8qxp-sc-rtc";
> 
> pls update dt binding as well
> 

I'll actually remove this in the next version.

Will be sent later on as a separate patch.

> > +               };
> > +
> > +               watchdog {
> > +                       compatible = "fsl,imx-sc-wdt";
> > +                       timeout-sec = <60>;
> > +               };
> > +
> > +               tsens: thermal-sensor {
> > +                       compatible = "fsl,imx-sc-thermal";
> > +                       #thermal-sensor-cells = <1>;
> > +               };
> > +       };
> > +
> > +       timer {
> > +               compatible = "arm,armv8-timer";
> > +               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
> > +                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
> > +                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */
> > +                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */
> > +       };
> > +
> > +       thermal_zones: thermal-zones {
> > +               cpu-thermal0 {
> > +                       polling-delay-passive = <250>;
> > +                       polling-delay = <2000>;
> > +                       thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
> > +
> > +                       trips {
> > +                               cpu_alert0: trip0 {
> > +                                       temperature = <107000>;
> > +                                       hysteresis = <2000>;
> > +                                       type = "passive";
> > +                               };
> > +                               cpu_crit0: trip1 {
> > +                                       temperature = <127000>;
> > +                                       hysteresis = <2000>;
> > +                                       type = "critical";
> > +                               };
> > +                       };
> > +                       cooling-maps {
> > +                               map0 {
> > +                                       trip = <&cpu_alert0>;
> > +                                       cooling-device =
> > +                                       <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> > +                                       <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> > +                               };
> > +                       };
> > +               };
> > +       };
> > +
> > +       clk_dummy: clock-dummy {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <0>;
> > +               clock-output-names = "clk_dummy";
> > +       };
> > +
> > +       xtal32k: clock-xtal32k {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <32768>;
> > +               clock-output-names = "xtal_32KHz";
> > +       };
> > +
> > +       xtal24m: clock-xtal24m {
> > +               compatible = "fixed-clock";
> > +               #clock-cells = <0>;
> > +               clock-frequency = <24000000>;
> > +               clock-output-names = "xtal_24MHz";
> > +       };
> > +
> > +       imx_ion {
> > +               compatible = "fsl,mxc-ion";
> 
> drop this unsupported node
> 

Removed in the next version.

> Regards
> Aisheng
> 
> > +               fsl,heap-id = <0>;
> > +       };
> > +
> > +       sc_pwrkey: sc-powerkey {
> > +               compatible = "fsl,imx8-pwrkey";
> > +               linux,keycode = <KEY_POWER>;
> > +               wakeup-source;
> > +       };
> > +
> > +       /* sorted in register address */
> > +       #include "imx8-ss-adma.dtsi"
> > +       #include "imx8-ss-conn.dtsi"
> > +       #include "imx8-ss-ddr.dtsi"
> > +       #include "imx8-ss-lsio.dtsi"
> > +};
> > +
> > +#include "imx8dxl-ss-adma.dtsi"
> > +#include "imx8dxl-ss-conn.dtsi"
> > +#include "imx8dxl-ss-lsio.dtsi"
> > +#include "imx8dxl-ss-ddr.dtsi"
> > --
> > 2.31.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&amp;data=04%7C01%7Cabel.vesa%40nxp.com%7C843de7d5f11f49ba992408d919cfafdc%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637569202065001061%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=ZmB%2FXRdAz3Y0q2FFu2C2Y6cqYbfDQkk7Q1SNqESO2zc%3D&amp;reserved=0

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 2/7] arm64: dts: imx8-ss-lsio: Add mu5a mailbox
  2021-05-18  7:50     ` Dong Aisheng
@ 2021-06-02  9:48       ` Abel Vesa
  -1 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2021-06-02  9:48 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: Abel Vesa, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam,
	Jacky Bai, Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On 21-05-18 15:50:51, Dong Aisheng wrote:
> On Tue, May 18, 2021 at 1:14 AM <abelvesa@kernel.org> wrote:
> >
> > From: Abel Vesa <abel.vesa@nxp.com>
> >
> > The mailbox of the lsio mu5a is used by rpmsg on imx8qxp and
> > imx8dxl platforms.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> > index ee4e585a9c39..8e3c92c82fac 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> > @@ -141,6 +141,15 @@ lsio_mu4: mailbox@5d1f0000 {
> >                 status = "disabled";
> >         };
> >
> > +       lsio_mu5: mailbox@5d200000 {
> > +               compatible = "fsl,imx6sx-mu";
> 
> For normal devices node, the compatible string are prefered to be
> defined in soc-ss-xxx.dtsi
> in case to handle HW minus difference. e.g. mu13
> 

Moved it to imx8dxl-ss-lsio.dtsi.

> 
> > +               reg = <0x5d200000 0x10000>;
> > +               interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> > +               #mbox-cells = <2>;
> > +               power-domains = <&pd IMX_SC_R_MU_5A>;
> > +       };
> > +
> > +
> >         lsio_mu13: mailbox@5d280000 {
> >                 reg = <0x5d280000 0x10000>;
> >                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
> > --
> > 2.31.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&amp;data=04%7C01%7Cabel.vesa%40nxp.com%7C868b5c19cea64f7f3e4008d919d1ce23%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637569211161280172%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=z2cyzPRkkbHM8LgNIW97x5iPn%2BOjHlqSUvAaJ6%2BAOck%3D&amp;reserved=0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 2/7] arm64: dts: imx8-ss-lsio: Add mu5a mailbox
@ 2021-06-02  9:48       ` Abel Vesa
  0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2021-06-02  9:48 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: Abel Vesa, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam,
	Jacky Bai, Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE

On 21-05-18 15:50:51, Dong Aisheng wrote:
> On Tue, May 18, 2021 at 1:14 AM <abelvesa@kernel.org> wrote:
> >
> > From: Abel Vesa <abel.vesa@nxp.com>
> >
> > The mailbox of the lsio mu5a is used by rpmsg on imx8qxp and
> > imx8dxl platforms.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 9 +++++++++
> >  1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> > index ee4e585a9c39..8e3c92c82fac 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
> > @@ -141,6 +141,15 @@ lsio_mu4: mailbox@5d1f0000 {
> >                 status = "disabled";
> >         };
> >
> > +       lsio_mu5: mailbox@5d200000 {
> > +               compatible = "fsl,imx6sx-mu";
> 
> For normal devices node, the compatible string are prefered to be
> defined in soc-ss-xxx.dtsi
> in case to handle HW minus difference. e.g. mu13
> 

Moved it to imx8dxl-ss-lsio.dtsi.

> 
> > +               reg = <0x5d200000 0x10000>;
> > +               interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> > +               #mbox-cells = <2>;
> > +               power-domains = <&pd IMX_SC_R_MU_5A>;
> > +       };
> > +
> > +
> >         lsio_mu13: mailbox@5d280000 {
> >                 reg = <0x5d280000 0x10000>;
> >                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
> > --
> > 2.31.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&amp;data=04%7C01%7Cabel.vesa%40nxp.com%7C868b5c19cea64f7f3e4008d919d1ce23%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637569211161280172%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=z2cyzPRkkbHM8LgNIW97x5iPn%2BOjHlqSUvAaJ6%2BAOck%3D&amp;reserved=0

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 3/7] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl
  2021-05-18  7:52     ` Dong Aisheng
@ 2021-06-02 11:28       ` Abel Vesa
  -1 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2021-06-02 11:28 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: Abel Vesa, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam,
	Jacky Bai, Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Clark Wang

On 21-05-18 15:52:00, Dong Aisheng wrote:
> On Tue, May 18, 2021 at 1:15 AM <abelvesa@kernel.org> wrote:
> >
> > From: Abel Vesa <abel.vesa@nxp.com>
> >
> > Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with
> > the i.MX8DXL specific properties.
> >
> > Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
> > Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> 
> Please add dt-binding update as well.
> Better along with this patch series
> 

Will do in the next version.

> > ---
> >  .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   | 53 +++++++++++++++++++
> >  1 file changed, 53 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > new file mode 100644
> > index 000000000000..12ccbc6587ca
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > @@ -0,0 +1,53 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019-2021 NXP
> > + */
> > +
> > +&audio_ipg_clk {
> > +       clock-frequency = <160000000>;
> > +};
> > +
> > +&dma_ipg_clk {
> > +       clock-frequency = <160000000>;
> > +};
> > +
> > +&i2c0 {
> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +       interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&i2c1 {
> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +       interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&i2c2 {
> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +       interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&i2c3 {
> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart0 {
> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > +       interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart1 {
> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > +       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart2 {
> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > +       interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart3 {
> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > +       interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > --
> > 2.31.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Flists.infradead.org%2Fmailman%2Flistinfo%2Flinux-arm-kernel&amp;data=04%7C01%7Cabel.vesa%40nxp.com%7Cc94d080848a648df0ad708d919d1f75f%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C637569211861760914%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=J6uUG1sc6bXk2MNXKtBzH1AjIb%2FsmeXCw4Ww%2BqvrixQ%3D&amp;reserved=0

^ permalink raw reply	[flat|nested] 36+ messages in thread

* Re: [PATCH 3/7] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl
@ 2021-06-02 11:28       ` Abel Vesa
  0 siblings, 0 replies; 36+ messages in thread
From: Abel Vesa @ 2021-06-02 11:28 UTC (permalink / raw)
  To: Dong Aisheng
  Cc: Abel Vesa, Rob Herring, Shawn Guo, Sascha Hauer, Fabio Estevam,
	Jacky Bai, Dong Aisheng, NXP Linux Team, devicetree,
	Linux Kernel Mailing List,
	moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
	Clark Wang

On 21-05-18 15:52:00, Dong Aisheng wrote:
> On Tue, May 18, 2021 at 1:15 AM <abelvesa@kernel.org> wrote:
> >
> > From: Abel Vesa <abel.vesa@nxp.com>
> >
> > Override the I2Cs, LPUARTs, audio_ipg_clk and dma_ipg_clk with
> > the i.MX8DXL specific properties.
> >
> > Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
> > Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> 
> Please add dt-binding update as well.
> Better along with this patch series
> 

Will do in the next version.

> > ---
> >  .../boot/dts/freescale/imx8dxl-ss-adma.dtsi   | 53 +++++++++++++++++++
> >  1 file changed, 53 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > new file mode 100644
> > index 000000000000..12ccbc6587ca
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi
> > @@ -0,0 +1,53 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2019-2021 NXP
> > + */
> > +
> > +&audio_ipg_clk {
> > +       clock-frequency = <160000000>;
> > +};
> > +
> > +&dma_ipg_clk {
> > +       clock-frequency = <160000000>;
> > +};
> > +
> > +&i2c0 {
> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +       interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&i2c1 {
> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +       interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&i2c2 {
> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +       interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&i2c3 {
> > +       compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +       interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart0 {
> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > +       interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart1 {
> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > +       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart2 {
> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > +       interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > +&lpuart3 {
> > +       compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
> > +       interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
> > +};
> > +
> > --
> > 2.31.1
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
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^ permalink raw reply	[flat|nested] 36+ messages in thread

end of thread, other threads:[~2021-06-02 11:56 UTC | newest]

Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-17 17:11 [PATCH 0/7] arm64: dts: freescale: Add i.MX8DXL support abelvesa
2021-05-17 17:11 ` abelvesa
2021-05-17 17:11 ` [PATCH 1/7] arm64: dts: freescale: Add the top level dtsi support for imx8dxl abelvesa
2021-05-17 17:11   ` abelvesa
2021-05-18  7:35   ` Dong Aisheng
2021-05-18  7:35     ` Dong Aisheng
2021-06-02  9:29     ` Abel Vesa
2021-06-02  9:29       ` Abel Vesa
2021-05-17 17:12 ` [PATCH 2/7] arm64: dts: imx8-ss-lsio: Add mu5a mailbox abelvesa
2021-05-17 17:12   ` abelvesa
2021-05-18  7:50   ` Dong Aisheng
2021-05-18  7:50     ` Dong Aisheng
2021-06-02  9:48     ` Abel Vesa
2021-06-02  9:48       ` Abel Vesa
2021-05-17 17:12 ` [PATCH 3/7] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl abelvesa
2021-05-17 17:12   ` abelvesa
2021-05-18  7:52   ` Dong Aisheng
2021-05-18  7:52     ` Dong Aisheng
2021-06-02 11:28     ` Abel Vesa
2021-06-02 11:28       ` Abel Vesa
2021-05-17 17:12 ` [PATCH 4/7] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi abelvesa
2021-05-17 17:12   ` abelvesa
2021-05-18  7:53   ` Dong Aisheng
2021-05-18  7:53     ` Dong Aisheng
2021-05-17 17:12 ` [PATCH 5/7] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl abelvesa
2021-05-17 17:12   ` abelvesa
2021-05-18  7:54   ` Dong Aisheng
2021-05-18  7:54     ` Dong Aisheng
2021-05-17 17:12 ` [PATCH 6/7] arm64: dts: freescale: Add lsio " abelvesa
2021-05-17 17:12   ` abelvesa
2021-05-18  7:55   ` Dong Aisheng
2021-05-18  7:55     ` Dong Aisheng
2021-05-17 17:12 ` [PATCH 7/7] arm64: dts: imx8dxl: Add i.MX8DXL evk board support abelvesa
2021-05-17 17:12   ` abelvesa
2021-05-18  7:57   ` Dong Aisheng
2021-05-18  7:57     ` Dong Aisheng

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