From: Rob Herring <robh@kernel.org> To: Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Mark Rutland <mark.rutland@arm.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org>, Jiri Olsa <jolsa@redhat.com>, Kan Liang <kan.liang@linux.intel.com>, Ian Rogers <irogers@google.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, honnappa.nagarahalli@arm.com, Zachary.Leaf@arm.com, Raphael Gault <raphael.gault@arm.com>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Namhyung Kim <namhyung@kernel.org>, Itaru Kitayama <itaru.kitayama@gmail.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 0/5] arm64 userspace counter support Date: Mon, 17 May 2021 14:54:00 -0500 [thread overview] Message-ID: <20210517195405.3079458-1-robh@kernel.org> (raw) Another version of arm64 userspace counter access support. This is just the Arm bits as Arnaldo asked to send the tools separately. The bulk of the libperf changes landed in 5.13-rc1. This version departs from the x86 implementation by requiring the user to always explicitly request user access (via attr.config1) and only enables access for task bound events. Rather than trying to lock down the access as the x86 implementation has been doing, we can start with only a limited use case enabled and later expand it if needed. This originally resurrected Raphael's series[1] to enable userspace counter access on arm64. My previous versions are here[2][3][4][5][6][7][8]. A git branch is here[9]. Changes in v8: - Restrict user access to thread bound events which simplifies the implementation. A couple of perf core changes (patches 1 and 2) are needed to do this. - Always require the user to request userspace access. Changes in v7: - Handling of dirty counter leakage and reworking of context switch and user access enabling. The .sched_task hook and undef instruction handler are now utilized. (Patch 3) - Add a userspace disable switch like x86. (Patch 5) Changes in v6: - Reworking of the handling of 64-bit counters and user access. There's a new config1 flag to request user access. This takes priority over the 64-bit flag and the user will get the maximum size the h/w supports without chaining. - The libperf evsel mmap struct is stored in its own xyarray - New tests for user 64-bit and 32-bit counters - Rebase to v5.12-rc2 Changes in v5: - Limit enabling/disabling access to CPUs associated with the PMU (supported_cpus) and with the mm_struct matching current->active_mm. The x86 method of using mm_cpumask doesn't work for arm64 as it is not updated. - Only set cap_user_rdpmc if event is on current cpu. See patch 2. - Create an mmap for every event in an evsel. This results in some changes to the libperf mmap API from the last version. - Rebase to v5.11-rc2 Changes in v4: - Dropped 'arm64: pmu: Add hook to handle pmu-related undefined instructions'. The onus is on userspace to pin itself to a homogeneous subset of CPUs and avoid any aborts on heterogeneous systems, so the hook is not needed. - Make perf_evsel__mmap() take pages rather than bytes for size - Fix building arm64 heterogeneous test. Changes in v3: - Dropped removing x86 rdpmc test until libperf tests can run via 'perf test' - Added verbose prints for tests - Split adding perf_evsel__mmap() to separate patch The following changes to the arm64 support have been made compared to Raphael's last version: The major change is support for heterogeneous systems with some restrictions. Specifically, userspace must pin itself to like CPUs, open a specific PMU by type, and use h/w specific events. The tests have been reworked to demonstrate this. Chained events are not supported. The problem with supporting chained events was there's no way to distinguish between a chained event and a native 64-bit counter. We could add some flag, but do self monitoring processes really need that? Native 64-bit counters are supported if the PMU h/w has support. As there's already an explicit ABI to request 64-bit counters, userspace can request 64-bit counters and if user access is not enabled, then it must retry with 32-bit counters. Prior versions broke the build on arm32 (surprisingly never caught by 0-day). As a result, event_mapped and event_unmapped implementations have been moved into the arm64 code. There was a bug in that pmc_width was not set in the user page. The tests now check for this. The documentation has been converted to rST. I've added sections on chained events and heterogeneous. Rob [1] https://lore.kernel.org/r/20190822144220.27860-1-raphael.gault@arm.com/ [2] https://lore.kernel.org/r/20200707205333.624938-1-robh@kernel.org/ [3] https://lore.kernel.org/r/20200828205614.3391252-1-robh@kernel.org/ [4] https://lore.kernel.org/r/20200911215118.2887710-1-robh@kernel.org/ [5] https://lore.kernel.org/r/20201001140116.651970-1-robh@kernel.org/ [6] https://lore.kernel.org/r/20210114020605.3943992-1-robh@kernel.org/ [7] https://lore.kernel.org/r/20210311000837.3630499-1-robh@kernel.org/ [8] https://lore.kernel.org/r/20210420031511.2348977-1-robh@kernel.org/ [9] git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git arm64-user-perf-event-v8 Kan Liang (1): perf: Track per-PMU sched_task() callback users Raphael Gault (1): Documentation: arm64: Document PMU counters access from userspace Rob Herring (3): perf: Add a counter for number of user access events in context arm64: perf: Enable PMU counter userspace access for perf event arm64: perf: Add userspace counter access disable switch Documentation/arm64/perf.rst | 68 ++++++++++- arch/arm64/kernel/perf_event.c | 201 +++++++++++++++++++++++++++++++-- include/linux/perf/arm_pmu.h | 11 +- include/linux/perf_event.h | 4 + kernel/events/core.c | 8 +- 5 files changed, 279 insertions(+), 13 deletions(-) -- 2.27.0
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org> To: Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Mark Rutland <mark.rutland@arm.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org>, Jiri Olsa <jolsa@redhat.com>, Kan Liang <kan.liang@linux.intel.com>, Ian Rogers <irogers@google.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, honnappa.nagarahalli@arm.com, Zachary.Leaf@arm.com, Raphael Gault <raphael.gault@arm.com>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Namhyung Kim <namhyung@kernel.org>, Itaru Kitayama <itaru.kitayama@gmail.com>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 0/5] arm64 userspace counter support Date: Mon, 17 May 2021 14:54:00 -0500 [thread overview] Message-ID: <20210517195405.3079458-1-robh@kernel.org> (raw) Another version of arm64 userspace counter access support. This is just the Arm bits as Arnaldo asked to send the tools separately. The bulk of the libperf changes landed in 5.13-rc1. This version departs from the x86 implementation by requiring the user to always explicitly request user access (via attr.config1) and only enables access for task bound events. Rather than trying to lock down the access as the x86 implementation has been doing, we can start with only a limited use case enabled and later expand it if needed. This originally resurrected Raphael's series[1] to enable userspace counter access on arm64. My previous versions are here[2][3][4][5][6][7][8]. A git branch is here[9]. Changes in v8: - Restrict user access to thread bound events which simplifies the implementation. A couple of perf core changes (patches 1 and 2) are needed to do this. - Always require the user to request userspace access. Changes in v7: - Handling of dirty counter leakage and reworking of context switch and user access enabling. The .sched_task hook and undef instruction handler are now utilized. (Patch 3) - Add a userspace disable switch like x86. (Patch 5) Changes in v6: - Reworking of the handling of 64-bit counters and user access. There's a new config1 flag to request user access. This takes priority over the 64-bit flag and the user will get the maximum size the h/w supports without chaining. - The libperf evsel mmap struct is stored in its own xyarray - New tests for user 64-bit and 32-bit counters - Rebase to v5.12-rc2 Changes in v5: - Limit enabling/disabling access to CPUs associated with the PMU (supported_cpus) and with the mm_struct matching current->active_mm. The x86 method of using mm_cpumask doesn't work for arm64 as it is not updated. - Only set cap_user_rdpmc if event is on current cpu. See patch 2. - Create an mmap for every event in an evsel. This results in some changes to the libperf mmap API from the last version. - Rebase to v5.11-rc2 Changes in v4: - Dropped 'arm64: pmu: Add hook to handle pmu-related undefined instructions'. The onus is on userspace to pin itself to a homogeneous subset of CPUs and avoid any aborts on heterogeneous systems, so the hook is not needed. - Make perf_evsel__mmap() take pages rather than bytes for size - Fix building arm64 heterogeneous test. Changes in v3: - Dropped removing x86 rdpmc test until libperf tests can run via 'perf test' - Added verbose prints for tests - Split adding perf_evsel__mmap() to separate patch The following changes to the arm64 support have been made compared to Raphael's last version: The major change is support for heterogeneous systems with some restrictions. Specifically, userspace must pin itself to like CPUs, open a specific PMU by type, and use h/w specific events. The tests have been reworked to demonstrate this. Chained events are not supported. The problem with supporting chained events was there's no way to distinguish between a chained event and a native 64-bit counter. We could add some flag, but do self monitoring processes really need that? Native 64-bit counters are supported if the PMU h/w has support. As there's already an explicit ABI to request 64-bit counters, userspace can request 64-bit counters and if user access is not enabled, then it must retry with 32-bit counters. Prior versions broke the build on arm32 (surprisingly never caught by 0-day). As a result, event_mapped and event_unmapped implementations have been moved into the arm64 code. There was a bug in that pmc_width was not set in the user page. The tests now check for this. The documentation has been converted to rST. I've added sections on chained events and heterogeneous. Rob [1] https://lore.kernel.org/r/20190822144220.27860-1-raphael.gault@arm.com/ [2] https://lore.kernel.org/r/20200707205333.624938-1-robh@kernel.org/ [3] https://lore.kernel.org/r/20200828205614.3391252-1-robh@kernel.org/ [4] https://lore.kernel.org/r/20200911215118.2887710-1-robh@kernel.org/ [5] https://lore.kernel.org/r/20201001140116.651970-1-robh@kernel.org/ [6] https://lore.kernel.org/r/20210114020605.3943992-1-robh@kernel.org/ [7] https://lore.kernel.org/r/20210311000837.3630499-1-robh@kernel.org/ [8] https://lore.kernel.org/r/20210420031511.2348977-1-robh@kernel.org/ [9] git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git arm64-user-perf-event-v8 Kan Liang (1): perf: Track per-PMU sched_task() callback users Raphael Gault (1): Documentation: arm64: Document PMU counters access from userspace Rob Herring (3): perf: Add a counter for number of user access events in context arm64: perf: Enable PMU counter userspace access for perf event arm64: perf: Add userspace counter access disable switch Documentation/arm64/perf.rst | 68 ++++++++++- arch/arm64/kernel/perf_event.c | 201 +++++++++++++++++++++++++++++++-- include/linux/perf/arm_pmu.h | 11 +- include/linux/perf_event.h | 4 + kernel/events/core.c | 8 +- 5 files changed, 279 insertions(+), 13 deletions(-) -- 2.27.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next reply other threads:[~2021-05-17 19:54 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-17 19:54 Rob Herring [this message] 2021-05-17 19:54 ` [PATCH v8 0/5] arm64 userspace counter support Rob Herring 2021-05-17 19:54 ` [PATCH v8 1/5] perf: Add a counter for number of user access events in context Rob Herring 2021-05-17 19:54 ` Rob Herring 2021-05-17 19:54 ` [PATCH v8 2/5] perf: Track per-PMU sched_task() callback users Rob Herring 2021-05-17 19:54 ` Rob Herring 2021-05-17 19:54 ` [PATCH v8 3/5] arm64: perf: Enable PMU counter userspace access for perf event Rob Herring 2021-05-17 19:54 ` Rob Herring 2021-06-01 13:55 ` Mark Rutland 2021-06-01 13:55 ` Mark Rutland 2021-06-01 15:00 ` Rob Herring 2021-06-01 15:00 ` Rob Herring 2021-06-01 17:11 ` Mark Rutland 2021-06-01 17:11 ` Mark Rutland 2021-06-03 16:40 ` Rob Herring 2021-06-03 16:40 ` Rob Herring 2021-07-21 15:59 ` Rob Herring 2021-07-21 15:59 ` Rob Herring 2021-05-17 19:54 ` [PATCH v8 4/5] arm64: perf: Add userspace counter access disable switch Rob Herring 2021-05-17 19:54 ` Rob Herring 2021-06-01 12:57 ` Will Deacon 2021-06-01 12:57 ` Will Deacon 2021-05-17 19:54 ` [PATCH v8 5/5] Documentation: arm64: Document PMU counters access from userspace Rob Herring 2021-05-17 19:54 ` Rob Herring
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