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[83.51.215.31]) by smtp.gmail.com with ESMTPSA id i5sm6978293edt.11.2021.05.18.11.36.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 May 2021 11:36:57 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH 00/25] exec: Add load/store API for aligned pointers Date: Tue, 18 May 2021 20:36:30 +0200 Message-Id: <20210518183655.1711377-1-philmd@redhat.com> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=170.10.133.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.374, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , "Michael S. Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Huacai Chen , Richard Henderson , Peter Xu , Paolo Bonzini , Bibo Mao Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi,=0D =0D This series is the result of a chat with Stefan after looking at=0D Peter response to Bibo on a problem with unoptimized memcpy()=0D leading to atomic issues:=0D https://www.mail-archive.com/qemu-devel@nongnu.org/msg808209.html=0D =0D MIPS R6 (32/64-bit) does support unaligned accesses, but for the=0D older releases the compiler can't optimize the __builtin_memcpy().=0D =0D When a pointer is known to be aligned, we can skip the checks for=0D misalignment and directly access the data. The pair of virtio vring=0D fields happen to be aligned.=0D =0D To be able to call the aligned functions from the virtio layer, we=0D have to fill the gap in multiple API layers.=0D =0D The series is decomposed as:=0D - cleanups (1-6)=0D - clean ldst API using macros (7-13)=0D - add aligned ldst methods (14)=0D - add aligned memory methods (15-16)=0D - similar changes in virtio (17-24)=0D - use the new methods on vring aligned values (25)=0D =0D There are some checkpatch errors related to the macro used.=0D =0D Regards,=0D =0D Phil.=0D =0D Philippe Mathieu-Daud=C3=A9 (25):=0D exec/memory_ldst_cached: Sort declarations=0D exec/memory_ldst_phys: Sort declarations=0D exec/memory_ldst: Use correct type sizes=0D exec/memory_ldst_phys: Use correct type sizes=0D exec/memory_ldst_cached: Use correct type size=0D exec/memory: Use correct type size=0D qemu/bswap: Introduce ST_CONVERT() macro=0D qemu/bswap: Use ST_CONVERT() macro to emit 16-bit load/store functions=0D qemu/bswap: Introduce LD_CONVERT() macro=0D qemu/bswap: Use LD_CONVERT macro to emit 16-bit signed load/store code=0D qemu/bswap: Use LD_CONVERT macro to emit 16-bit unsigned load/store=0D code=0D qemu/bswap: Use LDST_CONVERT macro to emit 32-bit load/store functions=0D qemu/bswap: Use LDST_CONVERT macro to emit 64-bit load/store functions=0D qemu/bswap: Introduce load/store for aligned pointer=0D exec/memory: Add methods for aligned pointer access (address space)=0D exec/memory: Add methods for aligned pointer access (physical memory)=0D hw/virtio: Use correct type sizes=0D hw/virtio: Introduce VIRTIO_LD_CONVERT() macro=0D hw/virtio: Use LD_CONVERT macro to emit 16-bit unsigned load/store=0D code=0D hw/virtio: Introduce VIRTIO_ST_CONVERT() macro=0D hw/virtio: Use ST_CONVERT() macro to emit 16-bit load/store functions=0D hw/virtio: Use LDST_CONVERT macro to emit 32-bit load/store functions=0D hw/virtio: Use LDST_CONVERT macro to emit 64-bit load/store functions=0D hw/virtio: Add methods for aligned pointer access=0D hw/virtio: Optimize accesses on vring aligned pointers=0D =0D docs/devel/loads-stores.rst | 27 +--=0D include/exec/memory.h | 18 +-=0D include/hw/virtio/virtio-access.h | 239 +++++++++-----------------=0D include/qemu/bswap.h | 149 ++++++----------=0D include/exec/memory_ldst.h.inc | 16 +-=0D include/exec/memory_ldst_cached.h.inc | 66 ++++---=0D include/exec/memory_ldst_phys.h.inc | 72 ++++----=0D hw/virtio/virtio.c | 13 +-=0D memory_ldst.c.inc | 20 +--=0D 9 files changed, 270 insertions(+), 350 deletions(-)=0D =0D --=20=0D 2.26.3=0D =0D