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From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
	"Michael S. Tsirkin" <mst@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Huacai Chen" <chenhuacai@kernel.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Peter Xu" <peterx@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Bibo Mao" <maobibo@loongson.cn>
Subject: [RFC PATCH 04/25] exec/memory_ldst_phys: Use correct type sizes
Date: Tue, 18 May 2021 20:36:34 +0200	[thread overview]
Message-ID: <20210518183655.1711377-5-philmd@redhat.com> (raw)
In-Reply-To: <20210518183655.1711377-1-philmd@redhat.com>

Use uint8_t for (unsigned) byte, and uint16_t for (unsigned)
16-bit word.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
 include/exec/memory_ldst_phys.h.inc | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/include/exec/memory_ldst_phys.h.inc b/include/exec/memory_ldst_phys.h.inc
index 4033795add7..ecd678610d1 100644
--- a/include/exec/memory_ldst_phys.h.inc
+++ b/include/exec/memory_ldst_phys.h.inc
@@ -20,7 +20,7 @@
  */
 
 #ifdef TARGET_ENDIANNESS
-static inline uint32_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+static inline uint16_t glue(lduw_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
 {
     return glue(address_space_lduw, SUFFIX)(ARG1, addr,
                                             MEMTXATTRS_UNSPECIFIED, NULL);
@@ -38,7 +38,7 @@ static inline uint64_t glue(ldq_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
                                            MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
-static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
+static inline void glue(stw_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
 {
     glue(address_space_stw, SUFFIX)(ARG1, addr, val,
                                     MEMTXATTRS_UNSPECIFIED, NULL);
@@ -56,19 +56,19 @@ static inline void glue(stq_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
                                     MEMTXATTRS_UNSPECIFIED, NULL);
 }
 #else
-static inline uint32_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+static inline uint8_t glue(ldub_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
 {
     return glue(address_space_ldub, SUFFIX)(ARG1, addr,
                                             MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
-static inline uint32_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+static inline uint16_t glue(lduw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
 {
     return glue(address_space_lduw_le, SUFFIX)(ARG1, addr,
                                                MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
-static inline uint32_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
+static inline uint16_t glue(lduw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
 {
     return glue(address_space_lduw_be, SUFFIX)(ARG1, addr,
                                                MEMTXATTRS_UNSPECIFIED, NULL);
@@ -98,19 +98,19 @@ static inline uint64_t glue(ldq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr)
                                               MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
-static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
+static inline void glue(stb_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val)
 {
     glue(address_space_stb, SUFFIX)(ARG1, addr, val,
                                     MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
-static inline void glue(stw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
+static inline void glue(stw_le_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
 {
     glue(address_space_stw_le, SUFFIX)(ARG1, addr, val,
                                        MEMTXATTRS_UNSPECIFIED, NULL);
 }
 
-static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val)
+static inline void glue(stw_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val)
 {
     glue(address_space_stw_be, SUFFIX)(ARG1, addr, val,
                                        MEMTXATTRS_UNSPECIFIED, NULL);
-- 
2.26.3



  parent reply	other threads:[~2021-05-18 18:45 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-18 18:36 [RFC PATCH 00/25] exec: Add load/store API for aligned pointers Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 01/25] exec/memory_ldst_cached: Sort declarations Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 02/25] exec/memory_ldst_phys: " Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 03/25] exec/memory_ldst: Use correct type sizes Philippe Mathieu-Daudé
2021-05-18 18:36 ` Philippe Mathieu-Daudé [this message]
2021-05-18 18:36 ` [RFC PATCH 05/25] exec/memory_ldst_cached: Use correct type size Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 06/25] exec/memory: " Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 07/25] qemu/bswap: Introduce ST_CONVERT() macro Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 08/25] qemu/bswap: Use ST_CONVERT() macro to emit 16-bit load/store functions Philippe Mathieu-Daudé
2021-05-18 20:08   ` Peter Maydell
2021-05-19 17:30     ` Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 09/25] qemu/bswap: Introduce LD_CONVERT() macro Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 10/25] qemu/bswap: Use LD_CONVERT macro to emit 16-bit signed load/store code Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 11/25] qemu/bswap: Use LD_CONVERT macro to emit 16-bit unsigned " Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 12/25] qemu/bswap: Use LDST_CONVERT macro to emit 32-bit load/store functions Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 13/25] qemu/bswap: Use LDST_CONVERT macro to emit 64-bit " Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 14/25] qemu/bswap: Introduce load/store for aligned pointer Philippe Mathieu-Daudé
2021-05-18 20:15   ` Peter Maydell
2021-05-19  5:56     ` Philippe Mathieu-Daudé
2021-05-19  9:08       ` Stefan Hajnoczi
2021-05-18 18:36 ` [RFC PATCH 15/25] exec/memory: Add methods for aligned pointer access (address space) Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 16/25] exec/memory: Add methods for aligned pointer access (physical memory) Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 17/25] hw/virtio: Use correct type sizes Philippe Mathieu-Daudé
2021-05-20 16:27   ` Richard Henderson
2021-05-20 19:13     ` Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 18/25] hw/virtio: Introduce VIRTIO_LD_CONVERT() macro Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 19/25] hw/virtio: Use LD_CONVERT macro to emit 16-bit unsigned load/store code Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 20/25] hw/virtio: Introduce VIRTIO_ST_CONVERT() macro Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 21/25] hw/virtio: Use ST_CONVERT() macro to emit 16-bit load/store functions Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 22/25] hw/virtio: Use LDST_CONVERT macro to emit 32-bit " Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 23/25] hw/virtio: Use LDST_CONVERT macro to emit 64-bit " Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 24/25] hw/virtio: Add methods for aligned pointer access Philippe Mathieu-Daudé
2021-05-18 18:36 ` [RFC PATCH 25/25] hw/virtio: Optimize accesses on vring aligned pointers Philippe Mathieu-Daudé
2021-05-18 18:42 ` [RFC PATCH 00/25] exec: Add load/store API for " no-reply
2021-05-19 19:20 ` Richard Henderson
2021-05-19 19:40   ` Philippe Mathieu-Daudé
2021-05-20 16:28     ` Richard Henderson

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