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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [CI 11/17] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct
Date: Tue, 18 May 2021 17:06:19 -0700	[thread overview]
Message-ID: <20210519000625.3184321-12-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20210519000625.3184321-1-lucas.demarchi@intel.com>

From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>

It replaces dc3co_enabled with dc3co_exitline on intel_psr struct.  And
it saves dc3co_exitline, not dc3co_enabled, so we can use dc3co_exitline
without intel_crtc_state on other psr internal function like as
intel_psr_enable_source().

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h |  2 +-
 drivers/gpu/drm/i915/display/intel_psr.c           | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 9c0adfc60c6f..ce05475ad560 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1498,7 +1498,7 @@ struct intel_psr {
 	bool sink_not_reliable;
 	bool irq_aux_error;
 	u16 su_x_granularity;
-	bool dc3co_enabled;
+	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
 	struct delayed_work dc3co_work;
 	struct drm_dp_vsc_sdp vsc;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index acaf3d459821..5bafd0de6ad9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -638,7 +638,7 @@ static void tgl_dc3co_disable_work(struct work_struct *work)
 
 static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
 {
-	if (!intel_dp->psr.dc3co_enabled)
+	if (!intel_dp->psr.dc3co_exitline)
 		return;
 
 	cancel_delayed_work(&intel_dp->psr.dc3co_work);
@@ -1010,7 +1010,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 
 	psr_irq_control(intel_dp);
 
-	if (crtc_state->dc3co_exitline) {
+	if (intel_dp->psr.dc3co_exitline) {
 		u32 val;
 
 		/*
@@ -1019,7 +1019,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 		 */
 		val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
 		val &= ~EXITLINE_MASK;
-		val |= crtc_state->dc3co_exitline << EXITLINE_SHIFT;
+		val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
 		val |= EXITLINE_ENABLE;
 		intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
 	}
@@ -1044,11 +1044,11 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	intel_dp->psr.psr2_enabled = crtc_state->has_psr2;
 	intel_dp->psr.busy_frontbuffer_bits = 0;
 	intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
-	intel_dp->psr.dc3co_enabled = !!crtc_state->dc3co_exitline;
 	intel_dp->psr.transcoder = crtc_state->cpu_transcoder;
 	/* DC5/DC6 requires at least 6 idle frames */
 	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
 	intel_dp->psr.dc3co_exit_delay = val;
+	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
 	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
 
 	/*
@@ -1818,7 +1818,7 @@ tgl_dc3co_flush(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
 {
 	mutex_lock(&intel_dp->psr.lock);
 
-	if (!intel_dp->psr.dc3co_enabled)
+	if (!intel_dp->psr.dc3co_exitline)
 		goto unlock;
 
 	if (!intel_dp->psr.psr2_enabled || !intel_dp->psr.active)
-- 
2.31.1

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  parent reply	other threads:[~2021-05-19  0:07 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-19  0:06 [Intel-gfx] [CI 00/17] ADL-P: more reviewed patches Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 01/17] drm/i915/xelpd: Calculate VDSC RC parameters Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 02/17] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 03/17] drm/i915/adl_p: Add dedicated SAGV watermarks Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 04/17] drm/i915/adl_p: Setup ports/phys Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 05/17] drm/i915/adl_p: Implement TC sequences Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 06/17] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 07/17] drm/i915/adl_p: Add ddb allocation support Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 08/17] drm/i915: Introduce MBUS relative dbuf offsets Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 09/17] drm/i915/adl_p: MBUS programming Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 10/17] drm/i915/adl_p: Tx escape clock with DSI Lucas De Marchi
2021-05-19  0:06 ` Lucas De Marchi [this message]
2021-05-19  0:06 ` [Intel-gfx] [CI 12/17] drm/i915/display: Add PSR interrupt error check function Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 13/17] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 14/17] drm/i915/adl_p: Add PLL Support Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 15/17] drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTL Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 16/17] drm/i915/adlp: Add PIPE_MISC2 programming Lucas De Marchi
2021-05-19  0:06 ` [Intel-gfx] [CI 17/17] drm/i915/adl_p: Update memory bandwidth parameters Lucas De Marchi
2021-05-19  0:22 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for ADL-P: more reviewed patches Patchwork
2021-05-19  0:23 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-05-19  0:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-05-20  6:26 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-05-20  6:57   ` Lucas De Marchi
2021-05-20 10:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for ADL-P: more reviewed patches (rev2) Patchwork

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