* [PATCH 1/5] amdgpu/pm: reorder definition of swsmu_pm_funcs for readability
2021-05-20 3:57 [PATCH 0/5] Modify smu_get_power_limit to implement Powerplay API Darren Powell
@ 2021-05-20 3:57 ` Darren Powell
2021-05-20 3:57 ` [PATCH 2/5] amdgpu/pm: simplify logic of smu_get_power_level Darren Powell
` (3 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Darren Powell @ 2021-05-20 3:57 UTC (permalink / raw)
To: amd-gfx; +Cc: Darren Powell
Match the order of definition to the structure's declaration to
help with locating included and missing functions of the API
Signed-off-by: Darren Powell <darren.powell@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 48 +++++++++++------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 285849cef9f2..8aff67a667fa 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2962,6 +2962,8 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.get_fan_control_mode = smu_get_fan_control_mode,
.set_fan_speed_percent = smu_set_fan_speed_percent,
.get_fan_speed_percent = smu_get_fan_speed_percent,
+ .force_clock_level = smu_force_ppclk_levels,
+ .print_clock_levels = smu_print_ppclk_levels,
.force_performance_level = smu_force_performance_level,
.read_sensor = smu_read_sensor,
.get_performance_level = smu_get_performance_level,
@@ -2974,38 +2976,36 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.switch_power_profile = smu_switch_power_profile,
/* export to amdgpu */
.dispatch_tasks = smu_handle_dpm_task,
+ .load_firmware = smu_load_microcode,
.set_powergating_by_smu = smu_dpm_set_power_gate,
.set_power_limit = smu_set_power_limit,
+ .get_power_profile_mode = smu_get_power_profile_mode,
+ .set_power_profile_mode = smu_set_power_profile_mode,
.odn_edit_dpm_table = smu_od_edit_dpm_table,
.set_mp1_state = smu_set_mp1_state,
+ .gfx_state_change_set = smu_gfx_state_change_set,
/* export to DC */
- .get_sclk = smu_get_sclk,
- .get_mclk = smu_get_mclk,
- .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
- .get_asic_baco_capability = smu_get_baco_capability,
- .set_asic_baco_state = smu_baco_set_state,
- .get_ppfeature_status = smu_sys_get_pp_feature_mask,
- .set_ppfeature_status = smu_sys_set_pp_feature_mask,
- .asic_reset_mode_2 = smu_mode2_reset,
- .set_df_cstate = smu_set_df_cstate,
- .set_xgmi_pstate = smu_set_xgmi_pstate,
- .get_gpu_metrics = smu_sys_get_gpu_metrics,
- .set_power_profile_mode = smu_set_power_profile_mode,
- .get_power_profile_mode = smu_get_power_profile_mode,
- .force_clock_level = smu_force_ppclk_levels,
- .print_clock_levels = smu_print_ppclk_levels,
- .get_uclk_dpm_states = smu_get_uclk_dpm_states,
- .get_dpm_clock_table = smu_get_dpm_clock_table,
- .display_configuration_change = smu_display_configuration_change,
- .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
- .display_clock_voltage_request = smu_display_clock_voltage_request,
- .set_active_display_count = smu_set_display_count,
- .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
+ .get_sclk = smu_get_sclk,
+ .get_mclk = smu_get_mclk,
+ .display_configuration_change = smu_display_configuration_change,
+ .get_clock_by_type_with_latency = smu_get_clock_by_type_with_latency,
+ .display_clock_voltage_request = smu_display_clock_voltage_request,
+ .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
+ .set_active_display_count = smu_set_display_count,
+ .set_min_deep_sleep_dcefclk = smu_set_deep_sleep_dcefclk,
+ .get_asic_baco_capability = smu_get_baco_capability,
+ .set_asic_baco_state = smu_baco_set_state,
+ .get_ppfeature_status = smu_sys_get_pp_feature_mask,
+ .set_ppfeature_status = smu_sys_set_pp_feature_mask,
+ .asic_reset_mode_2 = smu_mode2_reset,
+ .set_df_cstate = smu_set_df_cstate,
+ .set_xgmi_pstate = smu_set_xgmi_pstate,
+ .get_gpu_metrics = smu_sys_get_gpu_metrics,
.set_watermarks_for_clock_ranges = smu_set_watermarks_for_clock_ranges,
.display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
.get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
- .load_firmware = smu_load_microcode,
- .gfx_state_change_set = smu_gfx_state_change_set,
+ .get_uclk_dpm_states = smu_get_uclk_dpm_states,
+ .get_dpm_clock_table = smu_get_dpm_clock_table,
.get_smu_prv_buf_details = smu_get_prv_buffer_details,
};
--
2.25.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/5] amdgpu/pm: simplify logic of smu_get_power_level
2021-05-20 3:57 [PATCH 0/5] Modify smu_get_power_limit to implement Powerplay API Darren Powell
2021-05-20 3:57 ` [PATCH 1/5] amdgpu/pm: reorder definition of swsmu_pm_funcs for readability Darren Powell
@ 2021-05-20 3:57 ` Darren Powell
2021-05-20 8:32 ` Lijo Lazar
2021-05-20 3:57 ` [PATCH 3/5] amdgpu/pm: modify Powerplay API get_power_limit to use pp_power_limit_level Darren Powell
` (2 subsequent siblings)
4 siblings, 1 reply; 7+ messages in thread
From: Darren Powell @ 2021-05-20 3:57 UTC (permalink / raw)
To: amd-gfx; +Cc: Darren Powell
new powerplay enumeration pp_power_limit_level
modify hwmon show_power functions to use pp_power_limit_level
remove insertion of byte field into smu_get_power_level output arg "limit"
modify smu_get_power_level to use pp_power_limit_level
simplify logic of smu_get_power_level
* Test
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11`
HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
lspci -nn | grep "VGA\|Display" ; \
echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \
echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \
echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default
* Test (VANGOGH only)
echo "=== power2 cap ===" ; cat $HWMON_DIR/power2_cap ; \
echo "=== power2 cap max ===" ; cat $HWMON_DIR/power2_cap_max ; \
echo "=== power2 cap def ===" ; cat $HWMON_DIR/power2_cap_default
Signed-off-by: Darren Powell <darren.powell@amd.com>
---
.../gpu/drm/amd/include/kgd_pp_interface.h | 11 +++++
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 18 ++++---
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 2 +-
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 47 ++++++++++++++-----
4 files changed, 59 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index e2d13131a432..cf98b9afb362 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -192,6 +192,17 @@ enum pp_df_cstate {
DF_CSTATE_ALLOW,
};
+enum pp_power_limit_level
+{
+ PP_PWR_LIMIT_MIN = -1,
+ PP_PWR_LIMIT_CURRENT,
+ PP_PWR_LIMIT_DEFAULT,
+ PP_PWR_LIMIT_MAX,
+ PP_PWR_LIMIT_FAST_CURRENT,
+ PP_PWR_LIMIT_FAST_DEFAULT,
+ PP_PWR_LIMIT_FAST_MAX,
+};
+
#define PP_GROUP_MASK 0xF0000000
#define PP_GROUP_SHIFT 28
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 13da377888d2..bd5af70ac739 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2718,7 +2718,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
struct amdgpu_device *adev = dev_get_drvdata(dev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
- uint32_t limit = limit_type << 24;
+ uint32_t limit;
+ enum pp_power_limit_level limit_level;
uint32_t max_limit = 0;
ssize_t size;
int r;
@@ -2734,8 +2735,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
return r;
}
+ limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_MAX : PP_PWR_LIMIT_MAX;
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
+ smu_get_power_limit(&adev->smu, &limit, limit_level);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle,
@@ -2758,7 +2760,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
struct amdgpu_device *adev = dev_get_drvdata(dev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
- uint32_t limit = limit_type << 24;
+ uint32_t limit;
+ enum pp_power_limit_level limit_level;
ssize_t size;
int r;
@@ -2773,8 +2776,9 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
return r;
}
+ limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_CURRENT : PP_PWR_LIMIT_CURRENT;
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
+ smu_get_power_limit(&adev->smu, &limit, limit_level);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle,
@@ -2797,7 +2801,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
struct amdgpu_device *adev = dev_get_drvdata(dev);
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int limit_type = to_sensor_dev_attr(attr)->index;
- uint32_t limit = limit_type << 24;
+ uint32_t limit;
+ enum pp_power_limit_level limit_level;
ssize_t size;
int r;
@@ -2812,8 +2817,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
return r;
}
+ limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_DEFAULT : PP_PWR_LIMIT_DEFAULT;
if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT);
+ smu_get_power_limit(&adev->smu, &limit, limit_level);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle,
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 523f9d2982e9..6bdd112d64cb 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1262,7 +1262,7 @@ enum smu_cmn2asic_mapping_type {
#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
- enum smu_ppt_limit_level limit_level);
+ enum pp_power_limit_level limit_level);
bool smu_mode1_reset_is_support(struct smu_context *smu);
bool smu_mode2_reset_is_support(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 8aff67a667fa..e192192e99d0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2168,33 +2168,56 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
int smu_get_power_limit(struct smu_context *smu,
uint32_t *limit,
- enum smu_ppt_limit_level limit_level)
+ enum pp_power_limit_level pwr_limit_level)
{
- uint32_t limit_type = *limit >> 24;
- int ret = 0;
+ enum smu_ppt_limit_level limit_level;
+ enum smu_ppt_limit_type limit_type;
+ int ret = -EOPNOTSUPP;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return -EOPNOTSUPP;
mutex_lock(&smu->mutex);
- if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
- if (smu->ppt_funcs->get_ppt_limit)
- ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
- } else {
- switch (limit_level) {
- case SMU_PPT_LIMIT_CURRENT:
+ switch (pwr_limit_level) {
+ case PP_PWR_LIMIT_CURRENT:
*limit = smu->current_power_limit;
+ ret = 0;
break;
- case SMU_PPT_LIMIT_DEFAULT:
+ case PP_PWR_LIMIT_DEFAULT:
*limit = smu->default_power_limit;
+ ret = 0;
break;
- case SMU_PPT_LIMIT_MAX:
+ case PP_PWR_LIMIT_MAX:
*limit = smu->max_power_limit;
+ ret = 0;
+ break;
+ case PP_PWR_LIMIT_FAST_CURRENT:
+ if (smu->ppt_funcs->get_ppt_limit) {
+ limit_type = SMU_FAST_PPT_LIMIT;
+ limit_level = SMU_PPT_LIMIT_CURRENT;
+ ret = smu->ppt_funcs->get_ppt_limit(smu,
+ limit, limit_type, limit_level);
+ }
+ break;
+ case PP_PWR_LIMIT_FAST_DEFAULT:
+ if (smu->ppt_funcs->get_ppt_limit) {
+ limit_type = SMU_FAST_PPT_LIMIT;
+ limit_level = SMU_PPT_LIMIT_DEFAULT;
+ ret = smu->ppt_funcs->get_ppt_limit(smu,
+ limit, limit_type, limit_level);
+ }
+ break;
+ case PP_PWR_LIMIT_FAST_MAX:
+ if (smu->ppt_funcs->get_ppt_limit) {
+ limit_type = SMU_FAST_PPT_LIMIT;
+ limit_level = SMU_PPT_LIMIT_MAX;
+ ret = smu->ppt_funcs->get_ppt_limit(smu,
+ limit, limit_type, limit_level);
+ }
break;
default:
break;
- }
}
mutex_unlock(&smu->mutex);
--
2.25.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH 2/5] amdgpu/pm: simplify logic of smu_get_power_level
2021-05-20 3:57 ` [PATCH 2/5] amdgpu/pm: simplify logic of smu_get_power_level Darren Powell
@ 2021-05-20 8:32 ` Lijo Lazar
0 siblings, 0 replies; 7+ messages in thread
From: Lijo Lazar @ 2021-05-20 8:32 UTC (permalink / raw)
To: Darren Powell, amd-gfx
On 5/20/2021 9:27 AM, Darren Powell wrote:
> new powerplay enumeration pp_power_limit_level
> modify hwmon show_power functions to use pp_power_limit_level
> remove insertion of byte field into smu_get_power_level output arg "limit"
> modify smu_get_power_level to use pp_power_limit_level
> simplify logic of smu_get_power_level
>
> * Test
> AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
> AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11`
> HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
>
> lspci -nn | grep "VGA\|Display" ; \
> echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \
> echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \
> echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default
>
> * Test (VANGOGH only)
> echo "=== power2 cap ===" ; cat $HWMON_DIR/power2_cap ; \
> echo "=== power2 cap max ===" ; cat $HWMON_DIR/power2_cap_max ; \
> echo "=== power2 cap def ===" ; cat $HWMON_DIR/power2_cap_default
>
> Signed-off-by: Darren Powell <darren.powell@amd.com>
> ---
> .../gpu/drm/amd/include/kgd_pp_interface.h | 11 +++++
> drivers/gpu/drm/amd/pm/amdgpu_pm.c | 18 ++++---
> drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 2 +-
> drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 47 ++++++++++++++-----
> 4 files changed, 59 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> index e2d13131a432..cf98b9afb362 100644
> --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
> @@ -192,6 +192,17 @@ enum pp_df_cstate {
> DF_CSTATE_ALLOW,
> };
>
> +enum pp_power_limit_level
> +{
> + PP_PWR_LIMIT_MIN = -1,
> + PP_PWR_LIMIT_CURRENT,
> + PP_PWR_LIMIT_DEFAULT,
> + PP_PWR_LIMIT_MAX,
> + PP_PWR_LIMIT_FAST_CURRENT,
> + PP_PWR_LIMIT_FAST_DEFAULT,
> + PP_PWR_LIMIT_FAST_MAX,
> +};
> +
Can't we keep the different limit types (DEFAULT/FAST/SLOW/SUSTAINED
etc) and different levels(MIN/MAX/CURRENT) separate here also?
Thanks,
Lijo
> #define PP_GROUP_MASK 0xF0000000
> #define PP_GROUP_SHIFT 28
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 13da377888d2..bd5af70ac739 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -2718,7 +2718,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
> struct amdgpu_device *adev = dev_get_drvdata(dev);
> const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
> int limit_type = to_sensor_dev_attr(attr)->index;
> - uint32_t limit = limit_type << 24;
> + uint32_t limit;
> + enum pp_power_limit_level limit_level;
> uint32_t max_limit = 0;
> ssize_t size;
> int r;
> @@ -2734,8 +2735,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
> return r;
> }
>
> + limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_MAX : PP_PWR_LIMIT_MAX;
> if (is_support_sw_smu(adev)) {
> - smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_MAX);
> + smu_get_power_limit(&adev->smu, &limit, limit_level);
> size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
> } else if (pp_funcs && pp_funcs->get_power_limit) {
> pp_funcs->get_power_limit(adev->powerplay.pp_handle,
> @@ -2758,7 +2760,8 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
> struct amdgpu_device *adev = dev_get_drvdata(dev);
> const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
> int limit_type = to_sensor_dev_attr(attr)->index;
> - uint32_t limit = limit_type << 24;
> + uint32_t limit;
> + enum pp_power_limit_level limit_level;
> ssize_t size;
> int r;
>
> @@ -2773,8 +2776,9 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
> return r;
> }
>
> + limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_CURRENT : PP_PWR_LIMIT_CURRENT;
> if (is_support_sw_smu(adev)) {
> - smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_CURRENT);
> + smu_get_power_limit(&adev->smu, &limit, limit_level);
> size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
> } else if (pp_funcs && pp_funcs->get_power_limit) {
> pp_funcs->get_power_limit(adev->powerplay.pp_handle,
> @@ -2797,7 +2801,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
> struct amdgpu_device *adev = dev_get_drvdata(dev);
> const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
> int limit_type = to_sensor_dev_attr(attr)->index;
> - uint32_t limit = limit_type << 24;
> + uint32_t limit;
> + enum pp_power_limit_level limit_level;
> ssize_t size;
> int r;
>
> @@ -2812,8 +2817,9 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
> return r;
> }
>
> + limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_DEFAULT : PP_PWR_LIMIT_DEFAULT;
> if (is_support_sw_smu(adev)) {
> - smu_get_power_limit(&adev->smu, &limit, SMU_PPT_LIMIT_DEFAULT);
> + smu_get_power_limit(&adev->smu, &limit, limit_level);
> size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
> } else if (pp_funcs && pp_funcs->get_power_limit) {
> pp_funcs->get_power_limit(adev->powerplay.pp_handle,
> diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> index 523f9d2982e9..6bdd112d64cb 100644
> --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
> @@ -1262,7 +1262,7 @@ enum smu_cmn2asic_mapping_type {
> #if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
> int smu_get_power_limit(struct smu_context *smu,
> uint32_t *limit,
> - enum smu_ppt_limit_level limit_level);
> + enum pp_power_limit_level limit_level);
>
> bool smu_mode1_reset_is_support(struct smu_context *smu);
> bool smu_mode2_reset_is_support(struct smu_context *smu);
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> index 8aff67a667fa..e192192e99d0 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -2168,33 +2168,56 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
>
> int smu_get_power_limit(struct smu_context *smu,
> uint32_t *limit,
> - enum smu_ppt_limit_level limit_level)
> + enum pp_power_limit_level pwr_limit_level)
> {
> - uint32_t limit_type = *limit >> 24;
> - int ret = 0;
> + enum smu_ppt_limit_level limit_level;
> + enum smu_ppt_limit_type limit_type;
> + int ret = -EOPNOTSUPP;
>
> if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
> return -EOPNOTSUPP;
>
> mutex_lock(&smu->mutex);
>
> - if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
> - if (smu->ppt_funcs->get_ppt_limit)
> - ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
> - } else {
> - switch (limit_level) {
> - case SMU_PPT_LIMIT_CURRENT:
> + switch (pwr_limit_level) {
> + case PP_PWR_LIMIT_CURRENT:
> *limit = smu->current_power_limit;
> + ret = 0;
> break;
> - case SMU_PPT_LIMIT_DEFAULT:
> + case PP_PWR_LIMIT_DEFAULT:
> *limit = smu->default_power_limit;
> + ret = 0;
> break;
> - case SMU_PPT_LIMIT_MAX:
> + case PP_PWR_LIMIT_MAX:
> *limit = smu->max_power_limit;
> + ret = 0;
> + break;
> + case PP_PWR_LIMIT_FAST_CURRENT:
> + if (smu->ppt_funcs->get_ppt_limit) {
> + limit_type = SMU_FAST_PPT_LIMIT;
> + limit_level = SMU_PPT_LIMIT_CURRENT;
> + ret = smu->ppt_funcs->get_ppt_limit(smu,
> + limit, limit_type, limit_level);
> + }
> + break;
> + case PP_PWR_LIMIT_FAST_DEFAULT:
> + if (smu->ppt_funcs->get_ppt_limit) {
> + limit_type = SMU_FAST_PPT_LIMIT;
> + limit_level = SMU_PPT_LIMIT_DEFAULT;
> + ret = smu->ppt_funcs->get_ppt_limit(smu,
> + limit, limit_type, limit_level);
> + }
> + break;
> + case PP_PWR_LIMIT_FAST_MAX:
> + if (smu->ppt_funcs->get_ppt_limit) {
> + limit_type = SMU_FAST_PPT_LIMIT;
> + limit_level = SMU_PPT_LIMIT_MAX;
> + ret = smu->ppt_funcs->get_ppt_limit(smu,
> + limit, limit_type, limit_level);
> + }
> break;
> default:
> break;
> - }
> }
>
> mutex_unlock(&smu->mutex);
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/5] amdgpu/pm: modify Powerplay API get_power_limit to use pp_power_limit_level
2021-05-20 3:57 [PATCH 0/5] Modify smu_get_power_limit to implement Powerplay API Darren Powell
2021-05-20 3:57 ` [PATCH 1/5] amdgpu/pm: reorder definition of swsmu_pm_funcs for readability Darren Powell
2021-05-20 3:57 ` [PATCH 2/5] amdgpu/pm: simplify logic of smu_get_power_level Darren Powell
@ 2021-05-20 3:57 ` Darren Powell
2021-05-20 3:57 ` [PATCH 4/5] amdgpu/pm: modify smu_get_power_limit to implement Powerplay API Darren Powell
2021-05-20 3:57 ` [PATCH 5/5] amdgpu/pm: add kernel documentation for smu_get_power_limit Darren Powell
4 siblings, 0 replies; 7+ messages in thread
From: Darren Powell @ 2021-05-20 3:57 UTC (permalink / raw)
To: amd-gfx; +Cc: Darren Powell
modify Powerplay API get_power_limit to use pp_power_limit_level
update Powerplay API get_power_limit calls to use pp_power_limit_level
modify pp_get_power_limit to use new Powerplay API
add new error return to pp_get_power_limit for unhandled pp_power_limit_level
* Test (non smu)
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11`
HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
lspci -nn | grep "VGA\|Display" ; \
echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \
echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \
echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default
Signed-off-by: Darren Powell <darren.powell@amd.com>
---
.../gpu/drm/amd/include/kgd_pp_interface.h | 4 +--
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 9 +++---
.../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 29 ++++++++++++-------
3 files changed, 24 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index cf98b9afb362..606c89eb206f 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -302,8 +302,8 @@ struct amd_pm_funcs {
uint32_t block_type, bool gate);
int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
int (*set_power_limit)(void *handle, uint32_t n);
- int (*get_power_limit)(void *handle, uint32_t *limit, uint32_t *max_limit,
- bool default_limit);
+ int (*get_power_limit)(void *handle, uint32_t *limit,
+ enum pp_power_limit_level pwr_limit_level);
int (*get_power_profile_mode)(void *handle, char *buf);
int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index bd5af70ac739..6130318dd993 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2720,7 +2720,6 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
int limit_type = to_sensor_dev_attr(attr)->index;
uint32_t limit;
enum pp_power_limit_level limit_level;
- uint32_t max_limit = 0;
ssize_t size;
int r;
@@ -2741,8 +2740,8 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle,
- &limit, &max_limit, true);
- size = snprintf(buf, PAGE_SIZE, "%u\n", max_limit * 1000000);
+ &limit, PP_PWR_LIMIT_MAX);
+ size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
}
@@ -2782,7 +2781,7 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle,
- &limit, NULL, false);
+ &limit, PP_PWR_LIMIT_CURRENT);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
@@ -2823,7 +2822,7 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else if (pp_funcs && pp_funcs->get_power_limit) {
pp_funcs->get_power_limit(adev->powerplay.pp_handle,
- &limit, NULL, true);
+ &limit, PP_PWR_LIMIT_DEFAULT);
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
} else {
size = snprintf(buf, PAGE_SIZE, "\n");
diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
index c73504e998e5..833e2d3f8f41 100644
--- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c
@@ -1035,31 +1035,38 @@ static int pp_set_power_limit(void *handle, uint32_t limit)
}
static int pp_get_power_limit(void *handle, uint32_t *limit,
- uint32_t *max_limit, bool default_limit)
+ enum pp_power_limit_level pwr_limit_level)
{
struct pp_hwmgr *hwmgr = handle;
+ int ret = 0;
if (!hwmgr || !hwmgr->pm_en ||!limit)
return -EINVAL;
mutex_lock(&hwmgr->smu_lock);
- if (default_limit) {
- *limit = hwmgr->default_power_limit;
- if (max_limit) {
- *max_limit = *limit;
+ switch (pwr_limit_level) {
+ case PP_PWR_LIMIT_CURRENT:
+ *limit = hwmgr->power_limit;
+ break;
+ case PP_PWR_LIMIT_DEFAULT:
+ *limit = hwmgr->default_power_limit;
+ break;
+ case PP_PWR_LIMIT_MAX:
+ *limit = hwmgr->default_power_limit;
if (hwmgr->od_enabled) {
- *max_limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
- *max_limit /= 100;
+ *limit *= (100 + hwmgr->platform_descriptor.TDPODLimit);
+ *limit /= 100;
}
- }
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
}
- else
- *limit = hwmgr->power_limit;
mutex_unlock(&hwmgr->smu_lock);
- return 0;
+ return ret;
}
static int pp_display_configuration_change(void *handle,
--
2.25.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 4/5] amdgpu/pm: modify smu_get_power_limit to implement Powerplay API
2021-05-20 3:57 [PATCH 0/5] Modify smu_get_power_limit to implement Powerplay API Darren Powell
` (2 preceding siblings ...)
2021-05-20 3:57 ` [PATCH 3/5] amdgpu/pm: modify Powerplay API get_power_limit to use pp_power_limit_level Darren Powell
@ 2021-05-20 3:57 ` Darren Powell
2021-05-20 3:57 ` [PATCH 5/5] amdgpu/pm: add kernel documentation for smu_get_power_limit Darren Powell
4 siblings, 0 replies; 7+ messages in thread
From: Darren Powell @ 2021-05-20 3:57 UTC (permalink / raw)
To: amd-gfx; +Cc: Darren Powell
modify smu_get_power_limit to match Powerplay .get_power_limit signature
add smu_get_power_limit to swsmu_pm_funcs
simplify calling functions to use Powerplay API rather than direct call
* Test
AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1`
AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | cut -d " " -f 11`
HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON}
lspci -nn | grep "VGA\|Display" ; \
echo "=== power1 cap ===" ; cat $HWMON_DIR/power1_cap ; \
echo "=== power1 cap max ===" ; cat $HWMON_DIR/power1_cap_max ; \
echo "=== power1 cap def ===" ; cat $HWMON_DIR/power1_cap_default
* Test (VANGOGH only)
echo "=== power2 cap ===" ; cat $HWMON_DIR/power2_cap ; \
echo "=== power2 cap max ===" ; cat $HWMON_DIR/power2_cap_max ; \
echo "=== power2 cap def ===" ; cat $HWMON_DIR/power2_cap_default
Signed-off-by: Darren Powell <darren.powell@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 48 +++++++++++------------
drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h | 5 +--
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 5 ++-
3 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 6130318dd993..1e8f9e8c13a2 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2735,16 +2735,16 @@ static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
}
limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_MAX : PP_PWR_LIMIT_MAX;
- if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, limit_level);
- size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
- } else if (pp_funcs && pp_funcs->get_power_limit) {
- pp_funcs->get_power_limit(adev->powerplay.pp_handle,
- &limit, PP_PWR_LIMIT_MAX);
+ if (pp_funcs && pp_funcs->get_power_limit)
+ r = pp_funcs->get_power_limit(adev->powerplay.pp_handle,
+ &limit, limit_level);
+ else
+ r = -ENODATA;
+
+ if (!r)
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
- } else {
+ else
size = snprintf(buf, PAGE_SIZE, "\n");
- }
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -2776,16 +2776,16 @@ static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
}
limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_CURRENT : PP_PWR_LIMIT_CURRENT;
- if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, limit_level);
- size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
- } else if (pp_funcs && pp_funcs->get_power_limit) {
- pp_funcs->get_power_limit(adev->powerplay.pp_handle,
- &limit, PP_PWR_LIMIT_CURRENT);
+ if (pp_funcs && pp_funcs->get_power_limit)
+ r = pp_funcs->get_power_limit(adev->powerplay.pp_handle,
+ &limit, limit_level);
+ else
+ r = -ENODATA;
+
+ if (!r)
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
- } else {
+ else
size = snprintf(buf, PAGE_SIZE, "\n");
- }
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
@@ -2817,16 +2817,16 @@ static ssize_t amdgpu_hwmon_show_power_cap_default(struct device *dev,
}
limit_level = (limit_type) ? PP_PWR_LIMIT_FAST_DEFAULT : PP_PWR_LIMIT_DEFAULT;
- if (is_support_sw_smu(adev)) {
- smu_get_power_limit(&adev->smu, &limit, limit_level);
- size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
- } else if (pp_funcs && pp_funcs->get_power_limit) {
- pp_funcs->get_power_limit(adev->powerplay.pp_handle,
- &limit, PP_PWR_LIMIT_DEFAULT);
+ if (pp_funcs && pp_funcs->get_power_limit)
+ r = pp_funcs->get_power_limit(adev->powerplay.pp_handle,
+ &limit, limit_level);
+ else
+ r = -ENODATA;
+
+ if (!r)
size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
- } else {
+ else
size = snprintf(buf, PAGE_SIZE, "\n");
- }
pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
index 6bdd112d64cb..3fbc5f7bf048 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_smu.h
@@ -1260,9 +1260,8 @@ enum smu_cmn2asic_mapping_type {
[profile] = {1, (workload)}
#if !defined(SWSMU_CODE_LAYER_L2) && !defined(SWSMU_CODE_LAYER_L3) && !defined(SWSMU_CODE_LAYER_L4)
-int smu_get_power_limit(struct smu_context *smu,
- uint32_t *limit,
- enum pp_power_limit_level limit_level);
+int smu_get_power_limit(void *handle, uint32_t *limit,
+ enum pp_power_limit_level pwr_limit_level);
bool smu_mode1_reset_is_support(struct smu_context *smu);
bool smu_mode2_reset_is_support(struct smu_context *smu);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index e192192e99d0..2815e932580b 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2166,10 +2166,10 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
return ret;
}
-int smu_get_power_limit(struct smu_context *smu,
- uint32_t *limit,
+int smu_get_power_limit(void *handle, uint32_t *limit,
enum pp_power_limit_level pwr_limit_level)
{
+ struct smu_context *smu = handle;
enum smu_ppt_limit_level limit_level;
enum smu_ppt_limit_type limit_type;
int ret = -EOPNOTSUPP;
@@ -3002,6 +3002,7 @@ static const struct amd_pm_funcs swsmu_pm_funcs = {
.load_firmware = smu_load_microcode,
.set_powergating_by_smu = smu_dpm_set_power_gate,
.set_power_limit = smu_set_power_limit,
+ .get_power_limit = smu_get_power_limit,
.get_power_profile_mode = smu_get_power_profile_mode,
.set_power_profile_mode = smu_set_power_profile_mode,
.odn_edit_dpm_table = smu_od_edit_dpm_table,
--
2.25.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 5/5] amdgpu/pm: add kernel documentation for smu_get_power_limit
2021-05-20 3:57 [PATCH 0/5] Modify smu_get_power_limit to implement Powerplay API Darren Powell
` (3 preceding siblings ...)
2021-05-20 3:57 ` [PATCH 4/5] amdgpu/pm: modify smu_get_power_limit to implement Powerplay API Darren Powell
@ 2021-05-20 3:57 ` Darren Powell
4 siblings, 0 replies; 7+ messages in thread
From: Darren Powell @ 2021-05-20 3:57 UTC (permalink / raw)
To: amd-gfx; +Cc: Darren Powell
Test:
* Temporary insertion into Documentation/gpu/amdgpu.rst
------------START------------
Test Documentation
==================
smu_get_power_limit
-------------------
.. kernel-doc:: drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
:identifiers: smu_get_power_limit
.. kernel-doc:: drivers/gpu/drm/amd/include/kgd_pp_interface.h
:identifiers: pp_power_limit_level
-------------END-------------
Signed-off-by: Darren Powell <darren.powell@amd.com>
---
.../gpu/drm/amd/include/kgd_pp_interface.h | 21 +++++++++++++++++++
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 10 +++++++++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
index 606c89eb206f..e86eecdf6a76 100644
--- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h
+++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h
@@ -192,6 +192,27 @@ enum pp_df_cstate {
DF_CSTATE_ALLOW,
};
+/**
+ * enum pp_power_limit_level - Used to query the power limits
+ *
+ * APU power is managed to system-level requirements through the PPT
+ * (package power tracking) feature. PPT is intended to limit power to the
+ * requirements of the power source and could be dynamically updated to
+ * maximize APU performance within the system power budget.
+ *
+ * PP_PWR_LIMIT_* manages the configurable, thermally significant
+ * moving average of APU power (default ~5000 ms).
+ * PP_PWR_LIMIT_FAST_* manages the ~10 ms moving average of APU power,
+ * where supported.
+ *
+ * @PP_PWR_LIMIT_MIN: Minimum Power Limit
+ * @PP_PWR_LIMIT_CURRENT: Current Power Limit (Long Window)
+ * @PP_PWR_LIMIT_DEFAULT: Default Power Limit (Long Window)
+ * @PP_PWR_LIMIT_MAX: Maximum Power Limit (Long Window)
+ * @PP_PWR_LIMIT_FAST_CURRENT: Current Power Limit (Short Window)
+ * @PP_PWR_LIMIT_FAST_DEFAULT: Default Power Limit (Short Window)
+ * @PP_PWR_LIMIT_FAST_MAX: Maximum Power Limit (Short Window)
+ */
enum pp_power_limit_level
{
PP_PWR_LIMIT_MIN = -1,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 2815e932580b..57f416732265 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -2166,6 +2166,16 @@ static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
return ret;
}
+/**
+ * smu_get_power_limit - Request one of the SMU Power Limits
+ *
+ * @handle: pointer to smu context
+ * @limit: requested limit is written back to this variable
+ * @pwr_limit_level: &pp_power_limit_level which power limit to return
+ *
+ * Return: 0 on success, <0 on error
+ *
+ */
int smu_get_power_limit(void *handle, uint32_t *limit,
enum pp_power_limit_level pwr_limit_level)
{
--
2.25.1
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