From mboxrd@z Thu Jan 1 00:00:00 1970 From: Green Wan Date: Thu, 20 May 2021 00:40:33 -0700 Subject: [PATCH v11 8/8] riscv: cpu: fu740: clear feature disable CSR In-Reply-To: <20210520074033.370234-1-green.wan@sifive.com> References: <20210520074033.370234-1-green.wan@sifive.com> Message-ID: <20210520074033.370234-9-green.wan@sifive.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf Signed-off-by: Green Wan Reviewed-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/cpu/fu740/spl.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c index ea0b2283a2..55e30346ff 100644 --- a/arch/riscv/cpu/fu740/spl.c +++ b/arch/riscv/cpu/fu740/spl.c @@ -6,6 +6,9 @@ #include #include +#include + +#define CSR_U74_FEATURE_DISABLE 0x7c1 int spl_soc_init(void) { @@ -21,3 +24,15 @@ int spl_soc_init(void) return 0; } + +void harts_early_init(void) +{ + /* + * Feature Disable CSR + * + * Clear feature disable CSR to '0' to turn on all features for + * each core. This operation must be in M-mode. + */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) + csr_write(CSR_U74_FEATURE_DISABLE, 0); +} -- 2.31.0