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* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission / DRM scheduler integration plan + new uAPI (rev2)
  2021-05-18 23:58 ` [Intel-gfx] " Matthew Brost
  (?)
@ 2021-05-18 23:47 ` Patchwork
  -1 siblings, 0 replies; 54+ messages in thread
From: Patchwork @ 2021-05-18 23:47 UTC (permalink / raw)
  To: Matthew Brost; +Cc: intel-gfx

== Series Details ==

Series: GuC submission / DRM scheduler integration plan + new uAPI (rev2)
URL   : https://patchwork.freedesktop.org/series/89840/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fe3698660450 drm/doc/rfc: i915 GuC submission / DRM scheduler
-:30: WARNING:BAD_SIGN_OFF: Duplicate signature
#30: 
Cc: Jason Ekstrand <jason@jlekstrand.net>

-:35: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#35: 
new file mode 100644

-:40: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#40: FILE: Documentation/gpu/rfc/i915_scheduler.rst:1:
+=========================================

-:65: ERROR:TRAILING_WHITESPACE: trailing whitespace
#65: FILE: Documentation/gpu/rfc/i915_scheduler.rst:26:
+^I  which configures a slot with N contexts $

total: 1 errors, 3 warnings, 0 checks, 92 lines checked
011aea469596 drm/doc/rfc: i915 new parallel submission uAPI plan
-:23: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#23: 
new file mode 100644

-:28: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#28: FILE: Documentation/gpu/rfc/i915_parallel_execbuf.h:1:
+#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */

-:51: WARNING:TYPO_SPELLING: 'inteface' may be misspelled - perhaps 'interface'?
#51: FILE: Documentation/gpu/rfc/i915_parallel_execbuf.h:24:
+ * inteface.
    ^^^^^^^^

-:152: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#152: FILE: Documentation/gpu/rfc/i915_parallel_execbuf.h:125:
+#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
                                    			  ^

-:160: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#160: FILE: Documentation/gpu/rfc/i915_parallel_execbuf.h:133:
+#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
                                           		  ^

-:170: WARNING:PREFER_DEFINED_ATTRIBUTE_MACRO: Prefer __packed over __attribute__((packed))
#170: FILE: Documentation/gpu/rfc/i915_parallel_execbuf.h:143:
+} __attribute__ ((packed));

-:184: WARNING:TYPO_SPELLING: 'explictly' may be misspelled - perhaps 'explicitly'?
#184: FILE: Documentation/gpu/rfc/i915_scheduler.rst:88:
+contexts in parallel with the GuC the context must be explictly registered with
                                                       ^^^^^^^^^

total: 0 errors, 5 warnings, 2 checks, 200 lines checked


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [Intel-gfx] ✗ Fi.CI.DOCS: warning for GuC submission / DRM scheduler integration plan + new uAPI (rev2)
  2021-05-18 23:58 ` [Intel-gfx] " Matthew Brost
  (?)
  (?)
@ 2021-05-18 23:51 ` Patchwork
  -1 siblings, 0 replies; 54+ messages in thread
From: Patchwork @ 2021-05-18 23:51 UTC (permalink / raw)
  To: Matthew Brost; +Cc: intel-gfx

== Series Details ==

Series: GuC submission / DRM scheduler integration plan + new uAPI (rev2)
URL   : https://patchwork.freedesktop.org/series/89840/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/rfc/i915_scheduler.rst:43: WARNING: Unexpected indentation.


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [RFC 0/2] GuC submission / DRM scheduler integration plan + new uAPI
@ 2021-05-18 23:58 ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-18 23:58 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: matthew.brost, tony.ye, tvrtko.ursulin, daniele.ceraolospurio,
	jason.ekstrand, michal.mrozek, jon.bloomfield, karl, mesa-dev,
	daniel.vetter, christian.koenig, john.c.harrison

Subject and patches say it all.

v2: Address comments, patches has details of changes

Signed-off-by: Matthew Brost <matthew.brost@intel.com>

Matthew Brost (2):
  drm/doc/rfc: i915 GuC submission / DRM scheduler
  drm/doc/rfc: i915 new parallel submission uAPI plan

 Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
 Documentation/gpu/rfc/i915_scheduler.rst      | 136 +++++++++++++++++
 Documentation/gpu/rfc/index.rst               |   4 +
 3 files changed, 284 insertions(+)
 create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
 create mode 100644 Documentation/gpu/rfc/i915_scheduler.rst

-- 
2.28.0


^ permalink raw reply	[flat|nested] 54+ messages in thread

* [Intel-gfx] [RFC 0/2] GuC submission / DRM scheduler integration plan + new uAPI
@ 2021-05-18 23:58 ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-18 23:58 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jason.ekstrand, karl, mesa-dev, daniel.vetter, christian.koenig

Subject and patches say it all.

v2: Address comments, patches has details of changes

Signed-off-by: Matthew Brost <matthew.brost@intel.com>

Matthew Brost (2):
  drm/doc/rfc: i915 GuC submission / DRM scheduler
  drm/doc/rfc: i915 new parallel submission uAPI plan

 Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
 Documentation/gpu/rfc/i915_scheduler.rst      | 136 +++++++++++++++++
 Documentation/gpu/rfc/index.rst               |   4 +
 3 files changed, 284 insertions(+)
 create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
 create mode 100644 Documentation/gpu/rfc/i915_scheduler.rst

-- 
2.28.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [RFC 1/2] drm/doc/rfc: i915 GuC submission / DRM scheduler
  2021-05-18 23:58 ` [Intel-gfx] " Matthew Brost
@ 2021-05-18 23:58   ` Matthew Brost
  -1 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-18 23:58 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: matthew.brost, tony.ye, tvrtko.ursulin, daniele.ceraolospurio,
	jason.ekstrand, michal.mrozek, jon.bloomfield, karl, mesa-dev,
	daniel.vetter, christian.koenig, john.c.harrison

Add entry for i915 GuC submission / DRM scheduler integration plan.
Follow up patch with details of new parallel submission uAPI to come.

v2:
 (Daniel Vetter)
  - Expand explaination of why bonding isn't supported for GuC
    submission
  - CC some of the DRM scheduler maintainers
  - Add priority inheritance / boosting use case
  - Add reasoning for removing in order assumptions
 (Daniel Stone)
  - Add links to priority spec

Cc: Christian König <christian.koenig@amd.com>
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Steven Price <steven.price@arm.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Dave Airlie <airlied@gmail.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 Documentation/gpu/rfc/i915_scheduler.rst | 85 ++++++++++++++++++++++++
 Documentation/gpu/rfc/index.rst          |  4 ++
 2 files changed, 89 insertions(+)
 create mode 100644 Documentation/gpu/rfc/i915_scheduler.rst

diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
new file mode 100644
index 000000000000..7faa46cde088
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_scheduler.rst
@@ -0,0 +1,85 @@
+=========================================
+I915 GuC Submission/DRM Scheduler Section
+=========================================
+
+Upstream plan
+=============
+For upstream the overall plan for landing GuC submission and integrating the
+i915 with the DRM scheduler is:
+
+* Merge basic GuC submission
+	* Basic submission support for all gen11+ platforms
+	* Not enabled by default on any current platforms but can be enabled via
+	  modparam enable_guc
+	* Lots of rework will need to be done to integrate with DRM scheduler so
+	  no need to nit pick everything in the code, it just should be
+	  functional, no major coding style / layering errors, and not regress
+	  execlists
+	* Update IGTs / selftests as needed to work with GuC submission
+	* Enable CI on supported platforms for a baseline
+	* Rework / get CI heathly for GuC submission in place as needed
+* Merge new parallel submission uAPI
+	* Bonding uAPI completely incompatible with GuC submission, plus it has
+	  severe design issues in general, which is why we want to retire it no
+	  matter what
+	* New uAPI adds I915_CONTEXT_ENGINES_EXT_PARALLEL context setup step
+	  which configures a slot with N contexts 
+	* After I915_CONTEXT_ENGINES_EXT_PARALLEL a user can submit N batches to
+	  a slot in a single execbuf IOCTL and the batches run on the GPU in
+	  paralllel
+	* Initially only for GuC submission but execlists can be supported if
+	  needed
+* Convert the i915 to use the DRM scheduler
+	* GuC submission backend fully integrated with DRM scheduler
+		* All request queues removed from backend (e.g. all backpressure
+		  handled in DRM scheduler)
+		* Resets / cancels hook in DRM scheduler
+		* Watchdog hooks into DRM scheduler
+		* Lots of complexity of the GuC backend can be pulled out once
+		  integrated with DRM scheduler (e.g. state machine gets
+		  simplier, locking gets simplier, etc...)
+	* Execlist backend will do the minimum required to hook in the DRM
+	  scheduler so it can live next to the fully integrated GuC backend
+		* Legacy interface
+		* Features like timeslicing / preemption / virtual engines would
+		  be difficult to integrate with the DRM scheduler and these
+		  features are not required for GuC submission as the GuC does
+		  these things for us
+		* ROI low on fully integrating into DRM scheduler
+		* Fully integrating would add lots of complexity to DRM
+		  scheduler
+	* Port i915 priority inheritance / boosting feature in DRM scheduler
+		* Used for i915 page flip, may be useful to other DRM drivers as
+		  well
+		* Will be an optional feature in the DRM scheduler
+	* Remove in-order completion assumptions from DRM scheduler
+		* Even when using the DRM scheduler the backends will handle
+		  preemption, timeslicing, etc... so it is possible for jobs to
+		  finish out of order
+	* Pull out i915 priority levels and use DRM priority levels
+	* Optimize DRM scheduler as needed
+
+New uAPI for basic GuC submission
+=================================
+No major changes are required to the uAPI for basic GuC submission. The only
+change is a new scheduler attribute: I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP.
+This attribute indicates the 2k i915 user priority levels are statically mapped
+into 3 levels as follows:
+
+* -1k to -1 Low priority
+* 0 Medium priority
+* 1 to 1k High priority
+
+This is needed because the GuC only has 4 priority bands. The highest priority
+band is reserved with the kernel. This aligns with the DRM scheduler priority
+levels too.
+
+Spec references:
+----------------
+https://www.khronos.org/registry/EGL/extensions/IMG/EGL_IMG_context_priority.txt
+https://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/chap5.html#devsandqueues-priority
+https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priority-t
+
+New parallel submission uAPI
+============================
+Details to come in a following patch.
diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst
index 05670442ca1b..91e93a705230 100644
--- a/Documentation/gpu/rfc/index.rst
+++ b/Documentation/gpu/rfc/index.rst
@@ -19,3 +19,7 @@ host such documentation:
 .. toctree::
 
     i915_gem_lmem.rst
+
+.. toctree::
+
+    i915_scheduler.rst
-- 
2.28.0


^ permalink raw reply	[flat|nested] 54+ messages in thread

* [Intel-gfx] [RFC 1/2] drm/doc/rfc: i915 GuC submission / DRM scheduler
@ 2021-05-18 23:58   ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-18 23:58 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jason.ekstrand, karl, mesa-dev, daniel.vetter, christian.koenig

Add entry for i915 GuC submission / DRM scheduler integration plan.
Follow up patch with details of new parallel submission uAPI to come.

v2:
 (Daniel Vetter)
  - Expand explaination of why bonding isn't supported for GuC
    submission
  - CC some of the DRM scheduler maintainers
  - Add priority inheritance / boosting use case
  - Add reasoning for removing in order assumptions
 (Daniel Stone)
  - Add links to priority spec

Cc: Christian König <christian.koenig@amd.com>
Cc: Luben Tuikov <luben.tuikov@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Steven Price <steven.price@arm.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: Dave Airlie <airlied@gmail.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 Documentation/gpu/rfc/i915_scheduler.rst | 85 ++++++++++++++++++++++++
 Documentation/gpu/rfc/index.rst          |  4 ++
 2 files changed, 89 insertions(+)
 create mode 100644 Documentation/gpu/rfc/i915_scheduler.rst

diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
new file mode 100644
index 000000000000..7faa46cde088
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_scheduler.rst
@@ -0,0 +1,85 @@
+=========================================
+I915 GuC Submission/DRM Scheduler Section
+=========================================
+
+Upstream plan
+=============
+For upstream the overall plan for landing GuC submission and integrating the
+i915 with the DRM scheduler is:
+
+* Merge basic GuC submission
+	* Basic submission support for all gen11+ platforms
+	* Not enabled by default on any current platforms but can be enabled via
+	  modparam enable_guc
+	* Lots of rework will need to be done to integrate with DRM scheduler so
+	  no need to nit pick everything in the code, it just should be
+	  functional, no major coding style / layering errors, and not regress
+	  execlists
+	* Update IGTs / selftests as needed to work with GuC submission
+	* Enable CI on supported platforms for a baseline
+	* Rework / get CI heathly for GuC submission in place as needed
+* Merge new parallel submission uAPI
+	* Bonding uAPI completely incompatible with GuC submission, plus it has
+	  severe design issues in general, which is why we want to retire it no
+	  matter what
+	* New uAPI adds I915_CONTEXT_ENGINES_EXT_PARALLEL context setup step
+	  which configures a slot with N contexts 
+	* After I915_CONTEXT_ENGINES_EXT_PARALLEL a user can submit N batches to
+	  a slot in a single execbuf IOCTL and the batches run on the GPU in
+	  paralllel
+	* Initially only for GuC submission but execlists can be supported if
+	  needed
+* Convert the i915 to use the DRM scheduler
+	* GuC submission backend fully integrated with DRM scheduler
+		* All request queues removed from backend (e.g. all backpressure
+		  handled in DRM scheduler)
+		* Resets / cancels hook in DRM scheduler
+		* Watchdog hooks into DRM scheduler
+		* Lots of complexity of the GuC backend can be pulled out once
+		  integrated with DRM scheduler (e.g. state machine gets
+		  simplier, locking gets simplier, etc...)
+	* Execlist backend will do the minimum required to hook in the DRM
+	  scheduler so it can live next to the fully integrated GuC backend
+		* Legacy interface
+		* Features like timeslicing / preemption / virtual engines would
+		  be difficult to integrate with the DRM scheduler and these
+		  features are not required for GuC submission as the GuC does
+		  these things for us
+		* ROI low on fully integrating into DRM scheduler
+		* Fully integrating would add lots of complexity to DRM
+		  scheduler
+	* Port i915 priority inheritance / boosting feature in DRM scheduler
+		* Used for i915 page flip, may be useful to other DRM drivers as
+		  well
+		* Will be an optional feature in the DRM scheduler
+	* Remove in-order completion assumptions from DRM scheduler
+		* Even when using the DRM scheduler the backends will handle
+		  preemption, timeslicing, etc... so it is possible for jobs to
+		  finish out of order
+	* Pull out i915 priority levels and use DRM priority levels
+	* Optimize DRM scheduler as needed
+
+New uAPI for basic GuC submission
+=================================
+No major changes are required to the uAPI for basic GuC submission. The only
+change is a new scheduler attribute: I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP.
+This attribute indicates the 2k i915 user priority levels are statically mapped
+into 3 levels as follows:
+
+* -1k to -1 Low priority
+* 0 Medium priority
+* 1 to 1k High priority
+
+This is needed because the GuC only has 4 priority bands. The highest priority
+band is reserved with the kernel. This aligns with the DRM scheduler priority
+levels too.
+
+Spec references:
+----------------
+https://www.khronos.org/registry/EGL/extensions/IMG/EGL_IMG_context_priority.txt
+https://www.khronos.org/registry/vulkan/specs/1.2-extensions/html/chap5.html#devsandqueues-priority
+https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priority-t
+
+New parallel submission uAPI
+============================
+Details to come in a following patch.
diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst
index 05670442ca1b..91e93a705230 100644
--- a/Documentation/gpu/rfc/index.rst
+++ b/Documentation/gpu/rfc/index.rst
@@ -19,3 +19,7 @@ host such documentation:
 .. toctree::
 
     i915_gem_lmem.rst
+
+.. toctree::
+
+    i915_scheduler.rst
-- 
2.28.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-18 23:58 ` [Intel-gfx] " Matthew Brost
@ 2021-05-18 23:58   ` Matthew Brost
  -1 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-18 23:58 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: matthew.brost, tony.ye, tvrtko.ursulin, daniele.ceraolospurio,
	jason.ekstrand, michal.mrozek, jon.bloomfield, karl, mesa-dev,
	daniel.vetter, christian.koenig, john.c.harrison

Add entry fpr i915 new parallel submission uAPI plan.

v2:
 (Daniel Vetter):
  - Expand logical order explaination
  - Add dummy header
  - Only allow N BBs in execbuf IOCTL
  - Configure parallel submission per slot not per gem context

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
CC: Carl Zhang <carl.zhang@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
 Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
 2 files changed, 196 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h

diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
new file mode 100644
index 000000000000..8c64b983ccad
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
@@ -0,0 +1,144 @@
+#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
+
+/*
+ * i915_context_engines_parallel_submit:
+ *
+ * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
+ * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
+ * hardware contexts are created internally in the i915 run these BBs. Once a
+ * slot is configured for N BBs only N BBs can be submitted in each execbuf
+ * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
+ * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
+ * the slots configuration).
+ *
+ * Their are two currently defined ways to control the placement of the
+ * hardware contexts on physical engines: default behavior (no flags) and
+ * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
+ * future as new hardware / use cases arise. Details of how to use this
+ * interface below above the flags.
+ *
+ * Returns -EINVAL if hardware context placement configuration invalid or if the
+ * placement configuration isn't supported on the platform / submission
+ * interface.
+ * Returns -ENODEV if extension isn't supported on the platform / submission
+ * inteface.
+ */
+struct i915_context_engines_parallel_submit {
+	struct i915_user_extension base;
+
+	__u16 engine_index;	/* slot for parallel engine */
+	__u16 width;		/* number of contexts per parallel engine */
+	__u16 num_siblings;	/* number of siblings per context */
+	__u16 mbz16;
+/*
+ * Default placement behvavior (currently unsupported):
+ *
+ * Rather than restricting parallel submission to a single class with a
+ * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
+ * enables parallel submission across multiple engine classes. In this case each
+ * context's logical engine mask indicates where that context can placed. It is
+ * implied in this mode that all contexts have mutual exclusive placement (e.g.
+ * if one context is running CS0 no other contexts can run on CS0).
+ *
+ * Example 1 pseudo code:
+ * CSX[Y] = engine class X, logical instance Y
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=2,
+ *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
+ *
+ * Results in the following valid placements:
+ * CS0[0], CS1[0]
+ * CS0[0], CS1[1]
+ * CS0[1], CS1[0]
+ * CS0[1], CS1[1]
+ *
+ * This can also be though of as 2 virtual engines:
+ * VE[0] = CS0[0], CS0[1]
+ * VE[1] = CS1[0], CS1[1]
+ *
+ * Example 2 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=3,
+ *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
+ *
+ * Results in the following valid placements:
+ * CS[0], CS[1]
+ * CS[0], CS[2]
+ * CS[1], CS[0]
+ * CS[1], CS[2]
+ * CS[2], CS[0]
+ * CS[2], CS[1]
+ *
+ *
+ * This can also be though of as 2 virtual engines:
+ * VE[0] = CS[0], CS[1], CS[2]
+ * VE[1] = CS[0], CS[1], CS[2]
+
+ * This enables a use case where all engines are created equally, we don't care
+ * where they are scheduled, we just want a certain number of resources, for
+ * those resources to be scheduled in parallel, and possibly across multiple
+ * engine classes.
+ */
+
+/*
+ * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
+ * Each context must have the same number sibling and bonds are implictly create
+ * of the siblings.
+ *
+ * All of the below examples are in logical space.
+ *
+ * Example 1 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=1,
+ *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
+ *
+ * Results in the following valid placements:
+ * CS[0], CS[1]
+ *
+ * Example 2 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=2,
+ *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
+ *
+ * Results in the following valid placements:
+ * CS[0], CS[1]
+ * CS[2], CS[3]
+ *
+ * This can also be though of as 2 virtual engines:
+ * VE[0] = CS[0], CS[2]
+ * VE[1] = CS[1], CS[3]
+ *
+ * This enables a use case where all engines are not equal and certain placement
+ * rules are required (i.e. split-frame requires all contexts to be placed in a
+ * logically contiguous order on the VCS engines on gen11+ platforms). This use
+ * case (logically contiguous placement, within a single engine class) is
+ * supported when using GuC submission. Execlist mode could support all possible
+ * bonding configurations but currently doesn't support this extension.
+ */
+#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
+/*
+ * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
+ * points on all hardware contexts between each set of BBs. An example use case
+ * of this feature is split-frame on gen11+ hardware. When using this feature a
+ * BB must be submitted on each hardware context in the parallel gem context.
+ * The execbuf2 IOCTL enforces the user adheres to policy.
+ */
+#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
+#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
+	__u64 flags;		/* all undefined flags must be zero */
+	__u64 mbz64[3];		/* reserved for future use; must be zero */
+
+	/*
+	 * width (i) * num_siblings (j) in length
+	 * index = j + i * num_siblings
+	 */
+	struct i915_engine_class_instance engines[0];
+} __attribute__ ((packed));
+
diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
index 7faa46cde088..64c539486ee4 100644
--- a/Documentation/gpu/rfc/i915_scheduler.rst
+++ b/Documentation/gpu/rfc/i915_scheduler.rst
@@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
 
 New parallel submission uAPI
 ============================
-Details to come in a following patch.
+The existing bonding uAPI is completely broken with GuC submission because
+whether a submission is a single context submit or parallel submit isn't known
+until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
+contexts in parallel with the GuC the context must be explictly registered with
+N contexts and all N contexts must be submitted in a single command to the GuC.
+These interfaces doesn't support dynamically changing between N contexts as the
+bonding uAPI does. Hence the need for a new parallel submission interface. Also
+the legacy bonding uAPI is quite confusing and not intuitive at all.
+
+The new parallel submission uAPI consists of 3 parts:
+
+* Export engines logical mapping
+* A 'set_parallel' extension to configure contexts for parallel
+  submission
+* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
+
+Export engines logical mapping
+------------------------------
+Certain use cases require BBs to be placed on engine instances in logical order
+(e.g. split-frame on gen11+). The logical mapping of engine instances can change
+based on fusing. Rather than making UMDs be aware of fusing, simply expose the
+logical mapping with the existing query engine info IOCTL. Also the GuC
+submission interface currently only supports submitting multiple contexts to
+engines in logical order which is a new requirement compared to execlists.
+Lastly, all current platforms have at most 2 instances and the logical order is
+the same a uABI order. This will change on platforms with more than 2 instances.
+
+A single bit will be added to drm_i915_engine_info.flags indicating that the
+logical instance has been returned and a new field,
+drm_i915_engine_info.logical_instance, returns the logical instance.
+
+A 'set_parallel' extension to configure contexts for parallel submission
+------------------------------------------------------------------------
+The 'set_parallel' extension configures a slot for parallel submission of N BBs.
+It is setup step that should be called before using any of the contexts. See
+I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
+similar existing examples. Once a slot is configured for parallel submission the
+execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
+support GuC submission. Execlist support can be added later if needed.
+
+Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
+i915_context_engines_parallel_submit to the uAPI to implement this extension.
+
+Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
+-------------------------------------------------------------------
+Contexts that have been configured with the 'set_parallel' extension are allowed
+to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
+objects in the drm_i915_gem_exec_object2 list or the first N if
+I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
+submitted and how it has been configured by 'set_parallel' or other extensions.
+No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
+the IOCTL.
-- 
2.28.0


^ permalink raw reply	[flat|nested] 54+ messages in thread

* [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-18 23:58   ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-18 23:58 UTC (permalink / raw)
  To: intel-gfx, dri-devel
  Cc: jason.ekstrand, karl, mesa-dev, daniel.vetter, christian.koenig

Add entry fpr i915 new parallel submission uAPI plan.

v2:
 (Daniel Vetter):
  - Expand logical order explaination
  - Add dummy header
  - Only allow N BBs in execbuf IOCTL
  - Configure parallel submission per slot not per gem context

Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
CC: Carl Zhang <carl.zhang@intel.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Matthew Brost <matthew.brost@intel.com>
---
 Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
 Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
 2 files changed, 196 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h

diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
new file mode 100644
index 000000000000..8c64b983ccad
--- /dev/null
+++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
@@ -0,0 +1,144 @@
+#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
+
+/*
+ * i915_context_engines_parallel_submit:
+ *
+ * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
+ * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
+ * hardware contexts are created internally in the i915 run these BBs. Once a
+ * slot is configured for N BBs only N BBs can be submitted in each execbuf
+ * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
+ * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
+ * the slots configuration).
+ *
+ * Their are two currently defined ways to control the placement of the
+ * hardware contexts on physical engines: default behavior (no flags) and
+ * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
+ * future as new hardware / use cases arise. Details of how to use this
+ * interface below above the flags.
+ *
+ * Returns -EINVAL if hardware context placement configuration invalid or if the
+ * placement configuration isn't supported on the platform / submission
+ * interface.
+ * Returns -ENODEV if extension isn't supported on the platform / submission
+ * inteface.
+ */
+struct i915_context_engines_parallel_submit {
+	struct i915_user_extension base;
+
+	__u16 engine_index;	/* slot for parallel engine */
+	__u16 width;		/* number of contexts per parallel engine */
+	__u16 num_siblings;	/* number of siblings per context */
+	__u16 mbz16;
+/*
+ * Default placement behvavior (currently unsupported):
+ *
+ * Rather than restricting parallel submission to a single class with a
+ * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
+ * enables parallel submission across multiple engine classes. In this case each
+ * context's logical engine mask indicates where that context can placed. It is
+ * implied in this mode that all contexts have mutual exclusive placement (e.g.
+ * if one context is running CS0 no other contexts can run on CS0).
+ *
+ * Example 1 pseudo code:
+ * CSX[Y] = engine class X, logical instance Y
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=2,
+ *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
+ *
+ * Results in the following valid placements:
+ * CS0[0], CS1[0]
+ * CS0[0], CS1[1]
+ * CS0[1], CS1[0]
+ * CS0[1], CS1[1]
+ *
+ * This can also be though of as 2 virtual engines:
+ * VE[0] = CS0[0], CS0[1]
+ * VE[1] = CS1[0], CS1[1]
+ *
+ * Example 2 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=3,
+ *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
+ *
+ * Results in the following valid placements:
+ * CS[0], CS[1]
+ * CS[0], CS[2]
+ * CS[1], CS[0]
+ * CS[1], CS[2]
+ * CS[2], CS[0]
+ * CS[2], CS[1]
+ *
+ *
+ * This can also be though of as 2 virtual engines:
+ * VE[0] = CS[0], CS[1], CS[2]
+ * VE[1] = CS[0], CS[1], CS[2]
+
+ * This enables a use case where all engines are created equally, we don't care
+ * where they are scheduled, we just want a certain number of resources, for
+ * those resources to be scheduled in parallel, and possibly across multiple
+ * engine classes.
+ */
+
+/*
+ * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
+ * Each context must have the same number sibling and bonds are implictly create
+ * of the siblings.
+ *
+ * All of the below examples are in logical space.
+ *
+ * Example 1 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=1,
+ *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
+ *
+ * Results in the following valid placements:
+ * CS[0], CS[1]
+ *
+ * Example 2 pseudo code:
+ * CS[X] = generic engine of same class, logical instance X
+ * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
+ * set_engines(INVALID)
+ * set_parallel(engine_index=0, width=2, num_siblings=2,
+ *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
+ *
+ * Results in the following valid placements:
+ * CS[0], CS[1]
+ * CS[2], CS[3]
+ *
+ * This can also be though of as 2 virtual engines:
+ * VE[0] = CS[0], CS[2]
+ * VE[1] = CS[1], CS[3]
+ *
+ * This enables a use case where all engines are not equal and certain placement
+ * rules are required (i.e. split-frame requires all contexts to be placed in a
+ * logically contiguous order on the VCS engines on gen11+ platforms). This use
+ * case (logically contiguous placement, within a single engine class) is
+ * supported when using GuC submission. Execlist mode could support all possible
+ * bonding configurations but currently doesn't support this extension.
+ */
+#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
+/*
+ * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
+ * points on all hardware contexts between each set of BBs. An example use case
+ * of this feature is split-frame on gen11+ hardware. When using this feature a
+ * BB must be submitted on each hardware context in the parallel gem context.
+ * The execbuf2 IOCTL enforces the user adheres to policy.
+ */
+#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
+#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
+	__u64 flags;		/* all undefined flags must be zero */
+	__u64 mbz64[3];		/* reserved for future use; must be zero */
+
+	/*
+	 * width (i) * num_siblings (j) in length
+	 * index = j + i * num_siblings
+	 */
+	struct i915_engine_class_instance engines[0];
+} __attribute__ ((packed));
+
diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
index 7faa46cde088..64c539486ee4 100644
--- a/Documentation/gpu/rfc/i915_scheduler.rst
+++ b/Documentation/gpu/rfc/i915_scheduler.rst
@@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
 
 New parallel submission uAPI
 ============================
-Details to come in a following patch.
+The existing bonding uAPI is completely broken with GuC submission because
+whether a submission is a single context submit or parallel submit isn't known
+until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
+contexts in parallel with the GuC the context must be explictly registered with
+N contexts and all N contexts must be submitted in a single command to the GuC.
+These interfaces doesn't support dynamically changing between N contexts as the
+bonding uAPI does. Hence the need for a new parallel submission interface. Also
+the legacy bonding uAPI is quite confusing and not intuitive at all.
+
+The new parallel submission uAPI consists of 3 parts:
+
+* Export engines logical mapping
+* A 'set_parallel' extension to configure contexts for parallel
+  submission
+* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
+
+Export engines logical mapping
+------------------------------
+Certain use cases require BBs to be placed on engine instances in logical order
+(e.g. split-frame on gen11+). The logical mapping of engine instances can change
+based on fusing. Rather than making UMDs be aware of fusing, simply expose the
+logical mapping with the existing query engine info IOCTL. Also the GuC
+submission interface currently only supports submitting multiple contexts to
+engines in logical order which is a new requirement compared to execlists.
+Lastly, all current platforms have at most 2 instances and the logical order is
+the same a uABI order. This will change on platforms with more than 2 instances.
+
+A single bit will be added to drm_i915_engine_info.flags indicating that the
+logical instance has been returned and a new field,
+drm_i915_engine_info.logical_instance, returns the logical instance.
+
+A 'set_parallel' extension to configure contexts for parallel submission
+------------------------------------------------------------------------
+The 'set_parallel' extension configures a slot for parallel submission of N BBs.
+It is setup step that should be called before using any of the contexts. See
+I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
+similar existing examples. Once a slot is configured for parallel submission the
+execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
+support GuC submission. Execlist support can be added later if needed.
+
+Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
+i915_context_engines_parallel_submit to the uAPI to implement this extension.
+
+Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
+-------------------------------------------------------------------
+Contexts that have been configured with the 'set_parallel' extension are allowed
+to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
+objects in the drm_i915_gem_exec_object2 list or the first N if
+I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
+submitted and how it has been configured by 'set_parallel' or other extensions.
+No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
+the IOCTL.
-- 
2.28.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [Intel-gfx] ✓ Fi.CI.BAT: success for GuC submission / DRM scheduler integration plan + new uAPI (rev2)
  2021-05-18 23:58 ` [Intel-gfx] " Matthew Brost
                   ` (4 preceding siblings ...)
  (?)
@ 2021-05-19  0:19 ` Patchwork
  -1 siblings, 0 replies; 54+ messages in thread
From: Patchwork @ 2021-05-19  0:19 UTC (permalink / raw)
  To: Matthew Brost; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 14146 bytes --]

== Series Details ==

Series: GuC submission / DRM scheduler integration plan + new uAPI (rev2)
URL   : https://patchwork.freedesktop.org/series/89840/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_10100 -> Patchwork_20150
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/index.html

Known issues
------------

  Here are the changes found in Patchwork_20150 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_basic@cs-compute:
    - fi-elk-e7500:       NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-elk-e7500/igt@amdgpu/amd_basic@cs-compute.html

  * igt@amdgpu/amd_cs_nop@sync-fork-compute0:
    - fi-snb-2600:        NOTRUN -> [SKIP][2] ([fdo#109271]) +17 similar issues
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-snb-2600/igt@amdgpu/amd_cs_nop@sync-fork-compute0.html

  * igt@gem_exec_fence@basic-await@vcs0:
    - fi-bsw-nick:        [PASS][3] -> [FAIL][4] ([i915#3457])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-nick/igt@gem_exec_fence@basic-await@vcs0.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bsw-nick/igt@gem_exec_fence@basic-await@vcs0.html

  * igt@gem_exec_fence@basic-await@vecs0:
    - fi-bsw-n3050:       [PASS][5] -> [FAIL][6] ([i915#3457])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-n3050/igt@gem_exec_fence@basic-await@vecs0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bsw-n3050/igt@gem_exec_fence@basic-await@vecs0.html

  * igt@gem_exec_fence@nb-await@vecs0:
    - fi-bsw-kefka:       [PASS][7] -> [FAIL][8] ([i915#3457])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vecs0.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vecs0.html

  * igt@gem_wait@busy@all:
    - fi-bsw-nick:        [PASS][9] -> [FAIL][10] ([i915#3177] / [i915#3457])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-nick/igt@gem_wait@busy@all.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bsw-nick/igt@gem_wait@busy@all.html

  * igt@i915_selftest@live@mman:
    - fi-elk-e7500:       NOTRUN -> [DMESG-FAIL][11] ([i915#3457])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-elk-e7500/igt@i915_selftest@live@mman.html

  * igt@kms_busy@basic@modeset:
    - fi-ilk-650:         [PASS][12] -> [INCOMPLETE][13] ([i915#3457])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-ilk-650/igt@kms_busy@basic@modeset.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-ilk-650/igt@kms_busy@basic@modeset.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-elk-e7500:       [PASS][14] -> [FAIL][15] ([i915#53])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-elk-e7500/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html

  
#### Possible fixes ####

  * igt@gem_exec_fence@basic-await@vcs0:
    - fi-bsw-n3050:       [FAIL][16] ([i915#3457]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-n3050/igt@gem_exec_fence@basic-await@vcs0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bsw-n3050/igt@gem_exec_fence@basic-await@vcs0.html

  * igt@gem_exec_fence@nb-await@vcs0:
    - fi-bsw-kefka:       [FAIL][18] ([i915#3457]) -> [PASS][19] +2 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bsw-kefka/igt@gem_exec_fence@nb-await@vcs0.html

  * igt@gem_wait@wait@all:
    - fi-bsw-nick:        [FAIL][20] ([i915#3457]) -> [PASS][21] +2 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-nick/igt@gem_wait@wait@all.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bsw-nick/igt@gem_wait@wait@all.html

  * igt@i915_selftest@live@hangcheck:
    - {fi-tgl-dsi}:       [DMESG-FAIL][22] ([i915#2927]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-tgl-dsi/igt@i915_selftest@live@hangcheck.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-tgl-dsi/igt@i915_selftest@live@hangcheck.html
    - fi-snb-2600:        [INCOMPLETE][24] ([i915#2782]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-snb-2600/igt@i915_selftest@live@hangcheck.html

  * igt@i915_selftest@live@sanitycheck:
    - fi-elk-e7500:       [SKIP][26] ([fdo#109271]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-elk-e7500/igt@i915_selftest@live@sanitycheck.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-elk-e7500/igt@i915_selftest@live@sanitycheck.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-ilk-650:         [FAIL][28] ([i915#53]) -> [PASS][29] +7 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-ilk-650/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-ilk-650/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-a:
    - fi-bsw-kefka:       [FAIL][30] ([i915#53]) -> [PASS][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@kms_pipe_crc_basic@read-crc-pipe-a.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bsw-kefka/igt@kms_pipe_crc_basic@read-crc-pipe-a.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-bwr-2160:        [FAIL][32] ([i915#53]) -> [PASS][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bwr-2160/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bwr-2160/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
#### Warnings ####

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [FAIL][34] ([i915#3472]) -> [FAIL][35] ([i915#3457] / [i915#3472])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@i915_module_load@reload:
    - fi-icl-u2:          [DMESG-WARN][36] ([i915#3457]) -> [DMESG-WARN][37] ([i915#1982] / [i915#3457])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-icl-u2/igt@i915_module_load@reload.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-icl-u2/igt@i915_module_load@reload.html
    - fi-elk-e7500:       [DMESG-FAIL][38] ([i915#3457]) -> [DMESG-WARN][39] ([i915#3457])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-elk-e7500/igt@i915_module_load@reload.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-elk-e7500/igt@i915_module_load@reload.html
    - fi-bsw-kefka:       [DMESG-FAIL][40] ([i915#1982] / [i915#3457]) -> [DMESG-WARN][41] ([i915#1982] / [i915#3457])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-kefka/igt@i915_module_load@reload.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bsw-kefka/igt@i915_module_load@reload.html

  * igt@i915_selftest@live@execlists:
    - fi-bsw-nick:        [DMESG-FAIL][42] -> [INCOMPLETE][43] ([i915#2782] / [i915#2940])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bsw-nick/igt@i915_selftest@live@execlists.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bsw-nick/igt@i915_selftest@live@execlists.html
    - fi-icl-u2:          [DMESG-FAIL][44] ([i915#3462]) -> [INCOMPLETE][45] ([i915#2782] / [i915#3462])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-icl-u2/igt@i915_selftest@live@execlists.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-icl-u2/igt@i915_selftest@live@execlists.html

  * igt@i915_selftest@live@mman:
    - fi-bwr-2160:        [DMESG-FAIL][46] ([i915#3457]) -> [DMESG-WARN][47] ([i915#3457])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-bwr-2160/igt@i915_selftest@live@mman.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-bwr-2160/igt@i915_selftest@live@mman.html

  * igt@runner@aborted:
    - fi-cfl-8700k:       [FAIL][48] ([i915#3363]) -> [FAIL][49] ([i915#2426] / [i915#3363])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-cfl-8700k/igt@runner@aborted.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-cfl-8700k/igt@runner@aborted.html
    - fi-icl-u2:          [FAIL][50] ([i915#2426] / [i915#2782] / [i915#3363]) -> [FAIL][51] ([i915#2782] / [i915#3363])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-icl-u2/igt@runner@aborted.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-icl-u2/igt@runner@aborted.html
    - fi-glk-dsi:         [FAIL][52] ([i915#3363] / [k.org#202321]) -> [FAIL][53] ([i915#2426] / [i915#3363] / [k.org#202321])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-glk-dsi/igt@runner@aborted.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-glk-dsi/igt@runner@aborted.html
    - fi-kbl-r:           [FAIL][54] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][55] ([i915#1569] / [i915#192] / [i915#193] / [i915#194] / [i915#3363])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-kbl-r/igt@runner@aborted.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-kbl-r/igt@runner@aborted.html
    - fi-kbl-soraka:      [FAIL][56] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][57] ([i915#1436] / [i915#3363])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-kbl-soraka/igt@runner@aborted.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-kbl-soraka/igt@runner@aborted.html
    - fi-cml-u2:          [FAIL][58] ([i915#2082] / [i915#2426] / [i915#3363]) -> [FAIL][59] ([i915#3363])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-cml-u2/igt@runner@aborted.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-cml-u2/igt@runner@aborted.html
    - fi-kbl-7567u:       [FAIL][60] ([i915#1436] / [i915#2426] / [i915#3363]) -> [FAIL][61] ([i915#1436] / [i915#3363])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/fi-kbl-7567u/igt@runner@aborted.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/fi-kbl-7567u/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
  [i915#1569]: https://gitlab.freedesktop.org/drm/intel/issues/1569
  [i915#192]: https://gitlab.freedesktop.org/drm/intel/issues/192
  [i915#193]: https://gitlab.freedesktop.org/drm/intel/issues/193
  [i915#194]: https://gitlab.freedesktop.org/drm/intel/issues/194
  [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
  [i915#2082]: https://gitlab.freedesktop.org/drm/intel/issues/2082
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
  [i915#2782]: https://gitlab.freedesktop.org/drm/intel/issues/2782
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#2932]: https://gitlab.freedesktop.org/drm/intel/issues/2932
  [i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
  [i915#2966]: https://gitlab.freedesktop.org/drm/intel/issues/2966
  [i915#3177]: https://gitlab.freedesktop.org/drm/intel/issues/3177
  [i915#3276]: https://gitlab.freedesktop.org/drm/intel/issues/3276
  [i915#3277]: https://gitlab.freedesktop.org/drm/intel/issues/3277
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3283]: https://gitlab.freedesktop.org/drm/intel/issues/3283
  [i915#3363]: https://gitlab.freedesktop.org/drm/intel/issues/3363
  [i915#3457]: https://gitlab.freedesktop.org/drm/intel/issues/3457
  [i915#3462]: https://gitlab.freedesktop.org/drm/intel/issues/3462
  [i915#3468]: https://gitlab.freedesktop.org/drm/intel/issues/3468
  [i915#3472]: https://gitlab.freedesktop.org/drm/intel/issues/3472
  [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (43 -> 39)
------------------------------

  Additional (1): fi-rkl-11500t 
  Missing    (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_10100 -> Patchwork_20150

  CI-20190529: 20190529
  CI_DRM_10100: cde0422496c99357e2fe968c091bf88ae0e96cd3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6087: a1772be7dede83a4f65e5986fd7083a9c8f89083 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_20150: 011aea4695965e8c8f46c2f99c1469a8ed8e1d75 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

011aea469596 drm/doc/rfc: i915 new parallel submission uAPI plan
fe3698660450 drm/doc/rfc: i915 GuC submission / DRM scheduler

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/index.html

[-- Attachment #1.2: Type: text/html, Size: 18319 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-18 23:58   ` [Intel-gfx] " Matthew Brost
@ 2021-05-19 11:10     ` Daniel Vetter
  -1 siblings, 0 replies; 54+ messages in thread
From: Daniel Vetter @ 2021-05-19 11:10 UTC (permalink / raw)
  To: Matthew Brost
  Cc: intel-gfx, dri-devel, jason.ekstrand, daniel.vetter, mesa-dev,
	karl, christian.koenig

On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> Add entry fpr i915 new parallel submission uAPI plan.
> 
> v2:
>  (Daniel Vetter):
>   - Expand logical order explaination
>   - Add dummy header
>   - Only allow N BBs in execbuf IOCTL
>   - Configure parallel submission per slot not per gem context
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> CC: Carl Zhang <carl.zhang@intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>  2 files changed, 196 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> 
> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> new file mode 100644
> index 000000000000..8c64b983ccad
> --- /dev/null
> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> @@ -0,0 +1,144 @@
> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> +
> +/*
> + * i915_context_engines_parallel_submit:
> + *
> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> + * hardware contexts are created internally in the i915 run these BBs. Once a
> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> + * the slots configuration).
> + *
> + * Their are two currently defined ways to control the placement of the
> + * hardware contexts on physical engines: default behavior (no flags) and
> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> + * future as new hardware / use cases arise. Details of how to use this
> + * interface below above the flags.
> + *
> + * Returns -EINVAL if hardware context placement configuration invalid or if the
> + * placement configuration isn't supported on the platform / submission
> + * interface.
> + * Returns -ENODEV if extension isn't supported on the platform / submission
> + * inteface.
> + */
> +struct i915_context_engines_parallel_submit {
> +	struct i915_user_extension base;
> +
> +	__u16 engine_index;	/* slot for parallel engine */
> +	__u16 width;		/* number of contexts per parallel engine */
> +	__u16 num_siblings;	/* number of siblings per context */
> +	__u16 mbz16;

Ok the big picture looks reasonable now, the flags still confuse me.

> +/*
> + * Default placement behvavior (currently unsupported):
> + *
> + * Rather than restricting parallel submission to a single class with a
> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> + * enables parallel submission across multiple engine classes. In this case each
> + * context's logical engine mask indicates where that context can placed. It is
> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> + * if one context is running CS0 no other contexts can run on CS0).
> + *
> + * Example 1 pseudo code:
> + * CSX[Y] = engine class X, logical instance Y
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> + *
> + * Results in the following valid placements:
> + * CS0[0], CS1[0]
> + * CS0[0], CS1[1]
> + * CS0[1], CS1[0]
> + * CS0[1], CS1[1]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS0[0], CS0[1]
> + * VE[1] = CS1[0], CS1[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=3,
> + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[0], CS[2]
> + * CS[1], CS[0]
> + * CS[1], CS[2]
> + * CS[2], CS[0]
> + * CS[2], CS[1]
> + *
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[1], CS[2]
> + * VE[1] = CS[0], CS[1], CS[2]
> +
> + * This enables a use case where all engines are created equally, we don't care
> + * where they are scheduled, we just want a certain number of resources, for
> + * those resources to be scheduled in parallel, and possibly across multiple
> + * engine classes.
> + */

So I don't really get what this does compared to setting the flag below.
Is this just about running the batchbuffers the wrong way round, i.e. if
you have (simplest case)

width=2, num_sibglings=1, engines=CS[0], CS[1]

Then both
CS[0], CS[1]
and
CS[1], CS[0]
are possible options for running 2 batches? Iow, the backend is allowed to
run the batchbuffers the wrong way round, which gains us nothing, since we
assume the batches take equally long and engines interchangeable. There is
no scheduling scenario where this additional flexibility can help.

Also we don't have flags to select the only available and then specify an
entire pipe dream about what the non-flag mode does, without an
implementation. What is this about?

If it's just "because bonded allowed this" then I think we should just
unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
welp.

> +
> +/*
> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> + * Each context must have the same number sibling and bonds are implictly create
> + * of the siblings.
> + *
> + * All of the below examples are in logical space.
> + *
> + * Example 1 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=1,
> + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[2], CS[3]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[2]
> + * VE[1] = CS[1], CS[3]
> + *
> + * This enables a use case where all engines are not equal and certain placement
> + * rules are required (i.e. split-frame requires all contexts to be placed in a
> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> + * case (logically contiguous placement, within a single engine class) is
> + * supported when using GuC submission. Execlist mode could support all possible
> + * bonding configurations but currently doesn't support this extension.
> + */
> +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)

Does this map to intel_context_set_nopreempt(), so we could implement it
also in execlist?

Also is this just an artifact of the implementation, or is this somehow
required functionality for userspace, i.e. the workload fails if e.g. GuC
decides to preempt all LRC of a parallel virtual engine? Of course just
preempting one is a bit a bug (but execlist I think happily does that).

Cheers, Daniel

> +/*
> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> + * points on all hardware contexts between each set of BBs. An example use case
> + * of this feature is split-frame on gen11+ hardware. When using this feature a
> + * BB must be submitted on each hardware context in the parallel gem context.
> + * The execbuf2 IOCTL enforces the user adheres to policy.
> + */
> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> +	__u64 flags;		/* all undefined flags must be zero */
> +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> +
> +	/*
> +	 * width (i) * num_siblings (j) in length
> +	 * index = j + i * num_siblings
> +	 */
> +	struct i915_engine_class_instance engines[0];
> +} __attribute__ ((packed));
> +
> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> index 7faa46cde088..64c539486ee4 100644
> --- a/Documentation/gpu/rfc/i915_scheduler.rst
> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
>  
>  New parallel submission uAPI
>  ============================
> -Details to come in a following patch.
> +The existing bonding uAPI is completely broken with GuC submission because
> +whether a submission is a single context submit or parallel submit isn't known
> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> +contexts in parallel with the GuC the context must be explictly registered with
> +N contexts and all N contexts must be submitted in a single command to the GuC.
> +These interfaces doesn't support dynamically changing between N contexts as the
> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> +the legacy bonding uAPI is quite confusing and not intuitive at all.
> +
> +The new parallel submission uAPI consists of 3 parts:
> +
> +* Export engines logical mapping
> +* A 'set_parallel' extension to configure contexts for parallel
> +  submission
> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +
> +Export engines logical mapping
> +------------------------------
> +Certain use cases require BBs to be placed on engine instances in logical order
> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> +logical mapping with the existing query engine info IOCTL. Also the GuC
> +submission interface currently only supports submitting multiple contexts to
> +engines in logical order which is a new requirement compared to execlists.
> +Lastly, all current platforms have at most 2 instances and the logical order is
> +the same a uABI order. This will change on platforms with more than 2 instances.
> +
> +A single bit will be added to drm_i915_engine_info.flags indicating that the
> +logical instance has been returned and a new field,
> +drm_i915_engine_info.logical_instance, returns the logical instance.
> +
> +A 'set_parallel' extension to configure contexts for parallel submission
> +------------------------------------------------------------------------
> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> +It is setup step that should be called before using any of the contexts. See
> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> +similar existing examples. Once a slot is configured for parallel submission the
> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> +support GuC submission. Execlist support can be added later if needed.
> +
> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> +
> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +-------------------------------------------------------------------
> +Contexts that have been configured with the 'set_parallel' extension are allowed
> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> +objects in the drm_i915_gem_exec_object2 list or the first N if
> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> +submitted and how it has been configured by 'set_parallel' or other extensions.
> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> +the IOCTL.
> -- 
> 2.28.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-19 11:10     ` Daniel Vetter
  0 siblings, 0 replies; 54+ messages in thread
From: Daniel Vetter @ 2021-05-19 11:10 UTC (permalink / raw)
  To: Matthew Brost
  Cc: intel-gfx, dri-devel, jason.ekstrand, daniel.vetter, mesa-dev,
	karl, christian.koenig

On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> Add entry fpr i915 new parallel submission uAPI plan.
> 
> v2:
>  (Daniel Vetter):
>   - Expand logical order explaination
>   - Add dummy header
>   - Only allow N BBs in execbuf IOCTL
>   - Configure parallel submission per slot not per gem context
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> CC: Carl Zhang <carl.zhang@intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>  2 files changed, 196 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> 
> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> new file mode 100644
> index 000000000000..8c64b983ccad
> --- /dev/null
> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> @@ -0,0 +1,144 @@
> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> +
> +/*
> + * i915_context_engines_parallel_submit:
> + *
> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> + * hardware contexts are created internally in the i915 run these BBs. Once a
> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> + * the slots configuration).
> + *
> + * Their are two currently defined ways to control the placement of the
> + * hardware contexts on physical engines: default behavior (no flags) and
> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> + * future as new hardware / use cases arise. Details of how to use this
> + * interface below above the flags.
> + *
> + * Returns -EINVAL if hardware context placement configuration invalid or if the
> + * placement configuration isn't supported on the platform / submission
> + * interface.
> + * Returns -ENODEV if extension isn't supported on the platform / submission
> + * inteface.
> + */
> +struct i915_context_engines_parallel_submit {
> +	struct i915_user_extension base;
> +
> +	__u16 engine_index;	/* slot for parallel engine */
> +	__u16 width;		/* number of contexts per parallel engine */
> +	__u16 num_siblings;	/* number of siblings per context */
> +	__u16 mbz16;

Ok the big picture looks reasonable now, the flags still confuse me.

> +/*
> + * Default placement behvavior (currently unsupported):
> + *
> + * Rather than restricting parallel submission to a single class with a
> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> + * enables parallel submission across multiple engine classes. In this case each
> + * context's logical engine mask indicates where that context can placed. It is
> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> + * if one context is running CS0 no other contexts can run on CS0).
> + *
> + * Example 1 pseudo code:
> + * CSX[Y] = engine class X, logical instance Y
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> + *
> + * Results in the following valid placements:
> + * CS0[0], CS1[0]
> + * CS0[0], CS1[1]
> + * CS0[1], CS1[0]
> + * CS0[1], CS1[1]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS0[0], CS0[1]
> + * VE[1] = CS1[0], CS1[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=3,
> + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[0], CS[2]
> + * CS[1], CS[0]
> + * CS[1], CS[2]
> + * CS[2], CS[0]
> + * CS[2], CS[1]
> + *
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[1], CS[2]
> + * VE[1] = CS[0], CS[1], CS[2]
> +
> + * This enables a use case where all engines are created equally, we don't care
> + * where they are scheduled, we just want a certain number of resources, for
> + * those resources to be scheduled in parallel, and possibly across multiple
> + * engine classes.
> + */

So I don't really get what this does compared to setting the flag below.
Is this just about running the batchbuffers the wrong way round, i.e. if
you have (simplest case)

width=2, num_sibglings=1, engines=CS[0], CS[1]

Then both
CS[0], CS[1]
and
CS[1], CS[0]
are possible options for running 2 batches? Iow, the backend is allowed to
run the batchbuffers the wrong way round, which gains us nothing, since we
assume the batches take equally long and engines interchangeable. There is
no scheduling scenario where this additional flexibility can help.

Also we don't have flags to select the only available and then specify an
entire pipe dream about what the non-flag mode does, without an
implementation. What is this about?

If it's just "because bonded allowed this" then I think we should just
unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
welp.

> +
> +/*
> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> + * Each context must have the same number sibling and bonds are implictly create
> + * of the siblings.
> + *
> + * All of the below examples are in logical space.
> + *
> + * Example 1 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=1,
> + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[2], CS[3]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[2]
> + * VE[1] = CS[1], CS[3]
> + *
> + * This enables a use case where all engines are not equal and certain placement
> + * rules are required (i.e. split-frame requires all contexts to be placed in a
> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> + * case (logically contiguous placement, within a single engine class) is
> + * supported when using GuC submission. Execlist mode could support all possible
> + * bonding configurations but currently doesn't support this extension.
> + */
> +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)

Does this map to intel_context_set_nopreempt(), so we could implement it
also in execlist?

Also is this just an artifact of the implementation, or is this somehow
required functionality for userspace, i.e. the workload fails if e.g. GuC
decides to preempt all LRC of a parallel virtual engine? Of course just
preempting one is a bit a bug (but execlist I think happily does that).

Cheers, Daniel

> +/*
> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> + * points on all hardware contexts between each set of BBs. An example use case
> + * of this feature is split-frame on gen11+ hardware. When using this feature a
> + * BB must be submitted on each hardware context in the parallel gem context.
> + * The execbuf2 IOCTL enforces the user adheres to policy.
> + */
> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> +	__u64 flags;		/* all undefined flags must be zero */
> +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> +
> +	/*
> +	 * width (i) * num_siblings (j) in length
> +	 * index = j + i * num_siblings
> +	 */
> +	struct i915_engine_class_instance engines[0];
> +} __attribute__ ((packed));
> +
> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> index 7faa46cde088..64c539486ee4 100644
> --- a/Documentation/gpu/rfc/i915_scheduler.rst
> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
>  
>  New parallel submission uAPI
>  ============================
> -Details to come in a following patch.
> +The existing bonding uAPI is completely broken with GuC submission because
> +whether a submission is a single context submit or parallel submit isn't known
> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> +contexts in parallel with the GuC the context must be explictly registered with
> +N contexts and all N contexts must be submitted in a single command to the GuC.
> +These interfaces doesn't support dynamically changing between N contexts as the
> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> +the legacy bonding uAPI is quite confusing and not intuitive at all.
> +
> +The new parallel submission uAPI consists of 3 parts:
> +
> +* Export engines logical mapping
> +* A 'set_parallel' extension to configure contexts for parallel
> +  submission
> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +
> +Export engines logical mapping
> +------------------------------
> +Certain use cases require BBs to be placed on engine instances in logical order
> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> +logical mapping with the existing query engine info IOCTL. Also the GuC
> +submission interface currently only supports submitting multiple contexts to
> +engines in logical order which is a new requirement compared to execlists.
> +Lastly, all current platforms have at most 2 instances and the logical order is
> +the same a uABI order. This will change on platforms with more than 2 instances.
> +
> +A single bit will be added to drm_i915_engine_info.flags indicating that the
> +logical instance has been returned and a new field,
> +drm_i915_engine_info.logical_instance, returns the logical instance.
> +
> +A 'set_parallel' extension to configure contexts for parallel submission
> +------------------------------------------------------------------------
> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> +It is setup step that should be called before using any of the contexts. See
> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> +similar existing examples. Once a slot is configured for parallel submission the
> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> +support GuC submission. Execlist support can be added later if needed.
> +
> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> +
> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +-------------------------------------------------------------------
> +Contexts that have been configured with the 'set_parallel' extension are allowed
> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> +objects in the drm_i915_gem_exec_object2 list or the first N if
> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> +submitted and how it has been configured by 'set_parallel' or other extensions.
> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> +the IOCTL.
> -- 
> 2.28.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-18 23:58   ` [Intel-gfx] " Matthew Brost
@ 2021-05-19 11:45     ` Christian König
  -1 siblings, 0 replies; 54+ messages in thread
From: Christian König @ 2021-05-19 11:45 UTC (permalink / raw)
  To: Matthew Brost, intel-gfx, dri-devel
  Cc: tony.ye, tvrtko.ursulin, jason.ekstrand, michal.mrozek,
	daniele.ceraolospurio, jon.bloomfield, daniel.vetter, mesa-dev,
	karl, christian.koenig, john.c.harrison

Oh, yeah we call that gang submit on the AMD side.

Had already some internal discussions how to implement this, but so far 
couldn't figure out how to cleanly introduce that into the DRM scheduler.

Can you briefly describe in a few words how that is supposed to work on 
the Intel side?

Thanks,
Christian.

Am 19.05.21 um 01:58 schrieb Matthew Brost:
> Add entry fpr i915 new parallel submission uAPI plan.
>
> v2:
>   (Daniel Vetter):
>    - Expand logical order explaination
>    - Add dummy header
>    - Only allow N BBs in execbuf IOCTL
>    - Configure parallel submission per slot not per gem context
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> CC: Carl Zhang <carl.zhang@intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>   2 files changed, 196 insertions(+), 1 deletion(-)
>   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>
> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> new file mode 100644
> index 000000000000..8c64b983ccad
> --- /dev/null
> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> @@ -0,0 +1,144 @@
> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> +
> +/*
> + * i915_context_engines_parallel_submit:
> + *
> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> + * hardware contexts are created internally in the i915 run these BBs. Once a
> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> + * the slots configuration).
> + *
> + * Their are two currently defined ways to control the placement of the
> + * hardware contexts on physical engines: default behavior (no flags) and
> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> + * future as new hardware / use cases arise. Details of how to use this
> + * interface below above the flags.
> + *
> + * Returns -EINVAL if hardware context placement configuration invalid or if the
> + * placement configuration isn't supported on the platform / submission
> + * interface.
> + * Returns -ENODEV if extension isn't supported on the platform / submission
> + * inteface.
> + */
> +struct i915_context_engines_parallel_submit {
> +	struct i915_user_extension base;
> +
> +	__u16 engine_index;	/* slot for parallel engine */
> +	__u16 width;		/* number of contexts per parallel engine */
> +	__u16 num_siblings;	/* number of siblings per context */
> +	__u16 mbz16;
> +/*
> + * Default placement behvavior (currently unsupported):
> + *
> + * Rather than restricting parallel submission to a single class with a
> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> + * enables parallel submission across multiple engine classes. In this case each
> + * context's logical engine mask indicates where that context can placed. It is
> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> + * if one context is running CS0 no other contexts can run on CS0).
> + *
> + * Example 1 pseudo code:
> + * CSX[Y] = engine class X, logical instance Y
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> + *
> + * Results in the following valid placements:
> + * CS0[0], CS1[0]
> + * CS0[0], CS1[1]
> + * CS0[1], CS1[0]
> + * CS0[1], CS1[1]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS0[0], CS0[1]
> + * VE[1] = CS1[0], CS1[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=3,
> + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[0], CS[2]
> + * CS[1], CS[0]
> + * CS[1], CS[2]
> + * CS[2], CS[0]
> + * CS[2], CS[1]
> + *
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[1], CS[2]
> + * VE[1] = CS[0], CS[1], CS[2]
> +
> + * This enables a use case where all engines are created equally, we don't care
> + * where they are scheduled, we just want a certain number of resources, for
> + * those resources to be scheduled in parallel, and possibly across multiple
> + * engine classes.
> + */
> +
> +/*
> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> + * Each context must have the same number sibling and bonds are implictly create
> + * of the siblings.
> + *
> + * All of the below examples are in logical space.
> + *
> + * Example 1 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=1,
> + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[2], CS[3]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[2]
> + * VE[1] = CS[1], CS[3]
> + *
> + * This enables a use case where all engines are not equal and certain placement
> + * rules are required (i.e. split-frame requires all contexts to be placed in a
> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> + * case (logically contiguous placement, within a single engine class) is
> + * supported when using GuC submission. Execlist mode could support all possible
> + * bonding configurations but currently doesn't support this extension.
> + */
> +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> +/*
> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> + * points on all hardware contexts between each set of BBs. An example use case
> + * of this feature is split-frame on gen11+ hardware. When using this feature a
> + * BB must be submitted on each hardware context in the parallel gem context.
> + * The execbuf2 IOCTL enforces the user adheres to policy.
> + */
> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> +	__u64 flags;		/* all undefined flags must be zero */
> +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> +
> +	/*
> +	 * width (i) * num_siblings (j) in length
> +	 * index = j + i * num_siblings
> +	 */
> +	struct i915_engine_class_instance engines[0];
> +} __attribute__ ((packed));
> +
> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> index 7faa46cde088..64c539486ee4 100644
> --- a/Documentation/gpu/rfc/i915_scheduler.rst
> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
>   
>   New parallel submission uAPI
>   ============================
> -Details to come in a following patch.
> +The existing bonding uAPI is completely broken with GuC submission because
> +whether a submission is a single context submit or parallel submit isn't known
> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> +contexts in parallel with the GuC the context must be explictly registered with
> +N contexts and all N contexts must be submitted in a single command to the GuC.
> +These interfaces doesn't support dynamically changing between N contexts as the
> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> +the legacy bonding uAPI is quite confusing and not intuitive at all.
> +
> +The new parallel submission uAPI consists of 3 parts:
> +
> +* Export engines logical mapping
> +* A 'set_parallel' extension to configure contexts for parallel
> +  submission
> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +
> +Export engines logical mapping
> +------------------------------
> +Certain use cases require BBs to be placed on engine instances in logical order
> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> +logical mapping with the existing query engine info IOCTL. Also the GuC
> +submission interface currently only supports submitting multiple contexts to
> +engines in logical order which is a new requirement compared to execlists.
> +Lastly, all current platforms have at most 2 instances and the logical order is
> +the same a uABI order. This will change on platforms with more than 2 instances.
> +
> +A single bit will be added to drm_i915_engine_info.flags indicating that the
> +logical instance has been returned and a new field,
> +drm_i915_engine_info.logical_instance, returns the logical instance.
> +
> +A 'set_parallel' extension to configure contexts for parallel submission
> +------------------------------------------------------------------------
> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> +It is setup step that should be called before using any of the contexts. See
> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> +similar existing examples. Once a slot is configured for parallel submission the
> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> +support GuC submission. Execlist support can be added later if needed.
> +
> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> +
> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +-------------------------------------------------------------------
> +Contexts that have been configured with the 'set_parallel' extension are allowed
> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> +objects in the drm_i915_gem_exec_object2 list or the first N if
> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> +submitted and how it has been configured by 'set_parallel' or other extensions.
> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> +the IOCTL.


^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-19 11:45     ` Christian König
  0 siblings, 0 replies; 54+ messages in thread
From: Christian König @ 2021-05-19 11:45 UTC (permalink / raw)
  To: Matthew Brost, intel-gfx, dri-devel
  Cc: jason.ekstrand, daniel.vetter, mesa-dev, karl, christian.koenig

Oh, yeah we call that gang submit on the AMD side.

Had already some internal discussions how to implement this, but so far 
couldn't figure out how to cleanly introduce that into the DRM scheduler.

Can you briefly describe in a few words how that is supposed to work on 
the Intel side?

Thanks,
Christian.

Am 19.05.21 um 01:58 schrieb Matthew Brost:
> Add entry fpr i915 new parallel submission uAPI plan.
>
> v2:
>   (Daniel Vetter):
>    - Expand logical order explaination
>    - Add dummy header
>    - Only allow N BBs in execbuf IOCTL
>    - Configure parallel submission per slot not per gem context
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> CC: Carl Zhang <carl.zhang@intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>   2 files changed, 196 insertions(+), 1 deletion(-)
>   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>
> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> new file mode 100644
> index 000000000000..8c64b983ccad
> --- /dev/null
> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> @@ -0,0 +1,144 @@
> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> +
> +/*
> + * i915_context_engines_parallel_submit:
> + *
> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> + * hardware contexts are created internally in the i915 run these BBs. Once a
> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> + * the slots configuration).
> + *
> + * Their are two currently defined ways to control the placement of the
> + * hardware contexts on physical engines: default behavior (no flags) and
> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> + * future as new hardware / use cases arise. Details of how to use this
> + * interface below above the flags.
> + *
> + * Returns -EINVAL if hardware context placement configuration invalid or if the
> + * placement configuration isn't supported on the platform / submission
> + * interface.
> + * Returns -ENODEV if extension isn't supported on the platform / submission
> + * inteface.
> + */
> +struct i915_context_engines_parallel_submit {
> +	struct i915_user_extension base;
> +
> +	__u16 engine_index;	/* slot for parallel engine */
> +	__u16 width;		/* number of contexts per parallel engine */
> +	__u16 num_siblings;	/* number of siblings per context */
> +	__u16 mbz16;
> +/*
> + * Default placement behvavior (currently unsupported):
> + *
> + * Rather than restricting parallel submission to a single class with a
> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> + * enables parallel submission across multiple engine classes. In this case each
> + * context's logical engine mask indicates where that context can placed. It is
> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> + * if one context is running CS0 no other contexts can run on CS0).
> + *
> + * Example 1 pseudo code:
> + * CSX[Y] = engine class X, logical instance Y
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> + *
> + * Results in the following valid placements:
> + * CS0[0], CS1[0]
> + * CS0[0], CS1[1]
> + * CS0[1], CS1[0]
> + * CS0[1], CS1[1]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS0[0], CS0[1]
> + * VE[1] = CS1[0], CS1[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=3,
> + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[0], CS[2]
> + * CS[1], CS[0]
> + * CS[1], CS[2]
> + * CS[2], CS[0]
> + * CS[2], CS[1]
> + *
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[1], CS[2]
> + * VE[1] = CS[0], CS[1], CS[2]
> +
> + * This enables a use case where all engines are created equally, we don't care
> + * where they are scheduled, we just want a certain number of resources, for
> + * those resources to be scheduled in parallel, and possibly across multiple
> + * engine classes.
> + */
> +
> +/*
> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> + * Each context must have the same number sibling and bonds are implictly create
> + * of the siblings.
> + *
> + * All of the below examples are in logical space.
> + *
> + * Example 1 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=1,
> + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[2], CS[3]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[2]
> + * VE[1] = CS[1], CS[3]
> + *
> + * This enables a use case where all engines are not equal and certain placement
> + * rules are required (i.e. split-frame requires all contexts to be placed in a
> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> + * case (logically contiguous placement, within a single engine class) is
> + * supported when using GuC submission. Execlist mode could support all possible
> + * bonding configurations but currently doesn't support this extension.
> + */
> +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> +/*
> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> + * points on all hardware contexts between each set of BBs. An example use case
> + * of this feature is split-frame on gen11+ hardware. When using this feature a
> + * BB must be submitted on each hardware context in the parallel gem context.
> + * The execbuf2 IOCTL enforces the user adheres to policy.
> + */
> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> +	__u64 flags;		/* all undefined flags must be zero */
> +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> +
> +	/*
> +	 * width (i) * num_siblings (j) in length
> +	 * index = j + i * num_siblings
> +	 */
> +	struct i915_engine_class_instance engines[0];
> +} __attribute__ ((packed));
> +
> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> index 7faa46cde088..64c539486ee4 100644
> --- a/Documentation/gpu/rfc/i915_scheduler.rst
> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
>   
>   New parallel submission uAPI
>   ============================
> -Details to come in a following patch.
> +The existing bonding uAPI is completely broken with GuC submission because
> +whether a submission is a single context submit or parallel submit isn't known
> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> +contexts in parallel with the GuC the context must be explictly registered with
> +N contexts and all N contexts must be submitted in a single command to the GuC.
> +These interfaces doesn't support dynamically changing between N contexts as the
> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> +the legacy bonding uAPI is quite confusing and not intuitive at all.
> +
> +The new parallel submission uAPI consists of 3 parts:
> +
> +* Export engines logical mapping
> +* A 'set_parallel' extension to configure contexts for parallel
> +  submission
> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +
> +Export engines logical mapping
> +------------------------------
> +Certain use cases require BBs to be placed on engine instances in logical order
> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> +logical mapping with the existing query engine info IOCTL. Also the GuC
> +submission interface currently only supports submitting multiple contexts to
> +engines in logical order which is a new requirement compared to execlists.
> +Lastly, all current platforms have at most 2 instances and the logical order is
> +the same a uABI order. This will change on platforms with more than 2 instances.
> +
> +A single bit will be added to drm_i915_engine_info.flags indicating that the
> +logical instance has been returned and a new field,
> +drm_i915_engine_info.logical_instance, returns the logical instance.
> +
> +A 'set_parallel' extension to configure contexts for parallel submission
> +------------------------------------------------------------------------
> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> +It is setup step that should be called before using any of the contexts. See
> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> +similar existing examples. Once a slot is configured for parallel submission the
> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> +support GuC submission. Execlist support can be added later if needed.
> +
> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> +
> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +-------------------------------------------------------------------
> +Contexts that have been configured with the 'set_parallel' extension are allowed
> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> +objects in the drm_i915_gem_exec_object2 list or the first N if
> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> +submitted and how it has been configured by 'set_parallel' or other extensions.
> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> +the IOCTL.

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-18 23:58   ` [Intel-gfx] " Matthew Brost
@ 2021-05-19 13:57     ` Marcin Ślusarz
  -1 siblings, 0 replies; 54+ messages in thread
From: Marcin Ślusarz @ 2021-05-19 13:57 UTC (permalink / raw)
  To: Matthew Brost
  Cc: tony.ye, tvrtko.ursulin, intel-gfx, dri-devel, jason.ekstrand,
	michal.mrozek, daniele.ceraolospurio, jon.bloomfield,
	daniel.vetter, ML mesa-dev, karl, christian.koenig,
	john.c.harrison

śr., 19 maj 2021 o 01:41 Matthew Brost <matthew.brost@intel.com> napisał(a):
>
> Add entry fpr i915 new parallel submission uAPI plan.

s/fpr/for/

>
> v2:
>  (Daniel Vetter):
>   - Expand logical order explaination
>   - Add dummy header
>   - Only allow N BBs in execbuf IOCTL
>   - Configure parallel submission per slot not per gem context
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> CC: Carl Zhang <carl.zhang@intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>  2 files changed, 196 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>
> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> new file mode 100644
> index 000000000000..8c64b983ccad
> --- /dev/null
> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> @@ -0,0 +1,144 @@
> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> +
> +/*
> + * i915_context_engines_parallel_submit:
> + *
> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> + * hardware contexts are created internally in the i915 run these BBs. Once a
> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> + * the slots configuration).
> + *
> + * Their are two currently defined ways to control the placement of the

s/Their/There/

> + * hardware contexts on physical engines: default behavior (no flags) and
> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the

IMPLICIT? This typo is repeated multiple times
s/the in the/in the/

> + * future as new hardware / use cases arise. Details of how to use this
> + * interface below above the flags.

"below above"? :)

> + *
> + * Returns -EINVAL if hardware context placement configuration invalid or if the

is invalid

> + * placement configuration isn't supported on the platform / submission
> + * interface.
> + * Returns -ENODEV if extension isn't supported on the platform / submission
> + * inteface.
> + */
> +struct i915_context_engines_parallel_submit {
> +       struct i915_user_extension base;
> +
> +       __u16 engine_index;     /* slot for parallel engine */
> +       __u16 width;            /* number of contexts per parallel engine */
> +       __u16 num_siblings;     /* number of siblings per context */
> +       __u16 mbz16;
> +/*
> + * Default placement behvavior (currently unsupported):

behavior

> + *
> + * Rather than restricting parallel submission to a single class with a
> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> + * enables parallel submission across multiple engine classes. In this case each
> + * context's logical engine mask indicates where that context can placed. It is

can be placed

> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> + * if one context is running CS0 no other contexts can run on CS0).
> + *
> + * Example 1 pseudo code:
> + * CSX[Y] = engine class X, logical instance Y
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *             engines=CS0[0],CS0[1],CS1[0],CS1[1])
> + *
> + * Results in the following valid placements:
> + * CS0[0], CS1[0]
> + * CS0[0], CS1[1]
> + * CS0[1], CS1[0]
> + * CS0[1], CS1[1]
> + *
> + * This can also be though of as 2 virtual engines:

thought
(This typo repeats multiple times)

> + * VE[0] = CS0[0], CS0[1]
> + * VE[1] = CS1[0], CS1[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=3,
> + *             engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[0], CS[2]
> + * CS[1], CS[0]
> + * CS[1], CS[2]
> + * CS[2], CS[0]
> + * CS[2], CS[1]
> + *
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[1], CS[2]
> + * VE[1] = CS[0], CS[1], CS[2]
> +
> + * This enables a use case where all engines are created equally, we don't care
> + * where they are scheduled, we just want a certain number of resources, for
> + * those resources to be scheduled in parallel, and possibly across multiple
> + * engine classes.
> + */
> +
> +/*
> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> + * Each context must have the same number sibling and bonds are implictly create

number of siblings

> + * of the siblings.

"bonds are implictly create of the siblings."
-ENOPARSE

(also typo in implicitly)

> + *
> + * All of the below examples are in logical space.
> + *
> + * Example 1 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=1,
> + *             engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *             engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[2], CS[3]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[2]
> + * VE[1] = CS[1], CS[3]
> + *
> + * This enables a use case where all engines are not equal and certain placement
> + * rules are required (i.e. split-frame requires all contexts to be placed in a
> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> + * case (logically contiguous placement, within a single engine class) is
> + * supported when using GuC submission. Execlist mode could support all possible
> + * bonding configurations but currently doesn't support this extension.
> + */
> +#define I915_PARALLEL_IMPLICT_BONDS                    (1<<0)
> +/*
> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> + * points on all hardware contexts between each set of BBs. An example use case
> + * of this feature is split-frame on gen11+ hardware. When using this feature a
> + * BB must be submitted on each hardware context in the parallel gem context.
> + * The execbuf2 IOCTL enforces the user adheres to policy.
> + */
> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH             (1<<1)
> +#define __I915_PARALLEL_UNKNOWN_FLAGS  (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> +       __u64 flags;            /* all undefined flags must be zero */
> +       __u64 mbz64[3];         /* reserved for future use; must be zero */
> +
> +       /*
> +        * width (i) * num_siblings (j) in length
> +        * index = j + i * num_siblings
> +        */
> +       struct i915_engine_class_instance engines[0];
> +} __attribute__ ((packed));
> +
> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> index 7faa46cde088..64c539486ee4 100644
> --- a/Documentation/gpu/rfc/i915_scheduler.rst
> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
>
>  New parallel submission uAPI
>  ============================
> -Details to come in a following patch.
> +The existing bonding uAPI is completely broken with GuC submission because
> +whether a submission is a single context submit or parallel submit isn't known
> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> +contexts in parallel with the GuC the context must be explictly registered with

explicitly

> +N contexts and all N contexts must be submitted in a single command to the GuC.
> +These interfaces doesn't support dynamically changing between N contexts as the

"this interface" or "don't support", I'm not sure what "these" refers to...

"changing" what? maybe "swapping"?

> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> +the legacy bonding uAPI is quite confusing and not intuitive at all.
> +
> +The new parallel submission uAPI consists of 3 parts:
> +
> +* Export engines logical mapping
> +* A 'set_parallel' extension to configure contexts for parallel
> +  submission
> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +
> +Export engines logical mapping
> +------------------------------
> +Certain use cases require BBs to be placed on engine instances in logical order
> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> +logical mapping with the existing query engine info IOCTL. Also the GuC
> +submission interface currently only supports submitting multiple contexts to
> +engines in logical order which is a new requirement compared to execlists.
> +Lastly, all current platforms have at most 2 instances and the logical order is

2 instances of what?

> +the same a uABI order. This will change on platforms with more than 2 instances.

probably s/a uABI/as uAPI/ (note: 2 typos)

> +
> +A single bit will be added to drm_i915_engine_info.flags indicating that the
> +logical instance has been returned and a new field,
> +drm_i915_engine_info.logical_instance, returns the logical instance.
> +
> +A 'set_parallel' extension to configure contexts for parallel submission
> +------------------------------------------------------------------------
> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> +It is setup step that should be called before using any of the contexts. See
> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> +similar existing examples. Once a slot is configured for parallel submission the
> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only

submitting

> +support GuC submission. Execlist support can be added later if needed.
> +
> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> +
> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +-------------------------------------------------------------------
> +Contexts that have been configured with the 'set_parallel' extension are allowed
> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> +objects in the drm_i915_gem_exec_object2 list or the first N if
> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> +submitted and how it has been configured by 'set_parallel' or other extensions.
> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> +the IOCTL.

worth mentioning where? :)

> --
> 2.28.0

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-19 13:57     ` Marcin Ślusarz
  0 siblings, 0 replies; 54+ messages in thread
From: Marcin Ślusarz @ 2021-05-19 13:57 UTC (permalink / raw)
  To: Matthew Brost
  Cc: intel-gfx, dri-devel, jason.ekstrand, daniel.vetter, ML mesa-dev,
	karl, christian.koenig

śr., 19 maj 2021 o 01:41 Matthew Brost <matthew.brost@intel.com> napisał(a):
>
> Add entry fpr i915 new parallel submission uAPI plan.

s/fpr/for/

>
> v2:
>  (Daniel Vetter):
>   - Expand logical order explaination
>   - Add dummy header
>   - Only allow N BBs in execbuf IOCTL
>   - Configure parallel submission per slot not per gem context
>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> CC: Carl Zhang <carl.zhang@intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>  2 files changed, 196 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>
> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> new file mode 100644
> index 000000000000..8c64b983ccad
> --- /dev/null
> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> @@ -0,0 +1,144 @@
> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> +
> +/*
> + * i915_context_engines_parallel_submit:
> + *
> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> + * hardware contexts are created internally in the i915 run these BBs. Once a
> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> + * the slots configuration).
> + *
> + * Their are two currently defined ways to control the placement of the

s/Their/There/

> + * hardware contexts on physical engines: default behavior (no flags) and
> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the

IMPLICIT? This typo is repeated multiple times
s/the in the/in the/

> + * future as new hardware / use cases arise. Details of how to use this
> + * interface below above the flags.

"below above"? :)

> + *
> + * Returns -EINVAL if hardware context placement configuration invalid or if the

is invalid

> + * placement configuration isn't supported on the platform / submission
> + * interface.
> + * Returns -ENODEV if extension isn't supported on the platform / submission
> + * inteface.
> + */
> +struct i915_context_engines_parallel_submit {
> +       struct i915_user_extension base;
> +
> +       __u16 engine_index;     /* slot for parallel engine */
> +       __u16 width;            /* number of contexts per parallel engine */
> +       __u16 num_siblings;     /* number of siblings per context */
> +       __u16 mbz16;
> +/*
> + * Default placement behvavior (currently unsupported):

behavior

> + *
> + * Rather than restricting parallel submission to a single class with a
> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> + * enables parallel submission across multiple engine classes. In this case each
> + * context's logical engine mask indicates where that context can placed. It is

can be placed

> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> + * if one context is running CS0 no other contexts can run on CS0).
> + *
> + * Example 1 pseudo code:
> + * CSX[Y] = engine class X, logical instance Y
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *             engines=CS0[0],CS0[1],CS1[0],CS1[1])
> + *
> + * Results in the following valid placements:
> + * CS0[0], CS1[0]
> + * CS0[0], CS1[1]
> + * CS0[1], CS1[0]
> + * CS0[1], CS1[1]
> + *
> + * This can also be though of as 2 virtual engines:

thought
(This typo repeats multiple times)

> + * VE[0] = CS0[0], CS0[1]
> + * VE[1] = CS1[0], CS1[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=3,
> + *             engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[0], CS[2]
> + * CS[1], CS[0]
> + * CS[1], CS[2]
> + * CS[2], CS[0]
> + * CS[2], CS[1]
> + *
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[1], CS[2]
> + * VE[1] = CS[0], CS[1], CS[2]
> +
> + * This enables a use case where all engines are created equally, we don't care
> + * where they are scheduled, we just want a certain number of resources, for
> + * those resources to be scheduled in parallel, and possibly across multiple
> + * engine classes.
> + */
> +
> +/*
> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> + * Each context must have the same number sibling and bonds are implictly create

number of siblings

> + * of the siblings.

"bonds are implictly create of the siblings."
-ENOPARSE

(also typo in implicitly)

> + *
> + * All of the below examples are in logical space.
> + *
> + * Example 1 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=1,
> + *             engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *             engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[2], CS[3]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[2]
> + * VE[1] = CS[1], CS[3]
> + *
> + * This enables a use case where all engines are not equal and certain placement
> + * rules are required (i.e. split-frame requires all contexts to be placed in a
> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> + * case (logically contiguous placement, within a single engine class) is
> + * supported when using GuC submission. Execlist mode could support all possible
> + * bonding configurations but currently doesn't support this extension.
> + */
> +#define I915_PARALLEL_IMPLICT_BONDS                    (1<<0)
> +/*
> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> + * points on all hardware contexts between each set of BBs. An example use case
> + * of this feature is split-frame on gen11+ hardware. When using this feature a
> + * BB must be submitted on each hardware context in the parallel gem context.
> + * The execbuf2 IOCTL enforces the user adheres to policy.
> + */
> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH             (1<<1)
> +#define __I915_PARALLEL_UNKNOWN_FLAGS  (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> +       __u64 flags;            /* all undefined flags must be zero */
> +       __u64 mbz64[3];         /* reserved for future use; must be zero */
> +
> +       /*
> +        * width (i) * num_siblings (j) in length
> +        * index = j + i * num_siblings
> +        */
> +       struct i915_engine_class_instance engines[0];
> +} __attribute__ ((packed));
> +
> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> index 7faa46cde088..64c539486ee4 100644
> --- a/Documentation/gpu/rfc/i915_scheduler.rst
> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
>
>  New parallel submission uAPI
>  ============================
> -Details to come in a following patch.
> +The existing bonding uAPI is completely broken with GuC submission because
> +whether a submission is a single context submit or parallel submit isn't known
> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> +contexts in parallel with the GuC the context must be explictly registered with

explicitly

> +N contexts and all N contexts must be submitted in a single command to the GuC.
> +These interfaces doesn't support dynamically changing between N contexts as the

"this interface" or "don't support", I'm not sure what "these" refers to...

"changing" what? maybe "swapping"?

> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> +the legacy bonding uAPI is quite confusing and not intuitive at all.
> +
> +The new parallel submission uAPI consists of 3 parts:
> +
> +* Export engines logical mapping
> +* A 'set_parallel' extension to configure contexts for parallel
> +  submission
> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +
> +Export engines logical mapping
> +------------------------------
> +Certain use cases require BBs to be placed on engine instances in logical order
> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> +logical mapping with the existing query engine info IOCTL. Also the GuC
> +submission interface currently only supports submitting multiple contexts to
> +engines in logical order which is a new requirement compared to execlists.
> +Lastly, all current platforms have at most 2 instances and the logical order is

2 instances of what?

> +the same a uABI order. This will change on platforms with more than 2 instances.

probably s/a uABI/as uAPI/ (note: 2 typos)

> +
> +A single bit will be added to drm_i915_engine_info.flags indicating that the
> +logical instance has been returned and a new field,
> +drm_i915_engine_info.logical_instance, returns the logical instance.
> +
> +A 'set_parallel' extension to configure contexts for parallel submission
> +------------------------------------------------------------------------
> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> +It is setup step that should be called before using any of the contexts. See
> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> +similar existing examples. Once a slot is configured for parallel submission the
> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only

submitting

> +support GuC submission. Execlist support can be added later if needed.
> +
> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> +
> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +-------------------------------------------------------------------
> +Contexts that have been configured with the 'set_parallel' extension are allowed
> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> +objects in the drm_i915_gem_exec_object2 list or the first N if
> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> +submitted and how it has been configured by 'set_parallel' or other extensions.
> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> +the IOCTL.

worth mentioning where? :)

> --
> 2.28.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-19 11:10     ` Daniel Vetter
@ 2021-05-19 15:29       ` Tvrtko Ursulin
  -1 siblings, 0 replies; 54+ messages in thread
From: Tvrtko Ursulin @ 2021-05-19 15:29 UTC (permalink / raw)
  To: Daniel Vetter, Matthew Brost
  Cc: intel-gfx, dri-devel, jason.ekstrand, mesa-dev, daniel.vetter,
	karl, christian.koenig


On 19/05/2021 12:10, Daniel Vetter wrote:
> On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
>> Add entry fpr i915 new parallel submission uAPI plan.
>>
>> v2:
>>   (Daniel Vetter):
>>    - Expand logical order explaination
>>    - Add dummy header
>>    - Only allow N BBs in execbuf IOCTL
>>    - Configure parallel submission per slot not per gem context
>>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Tony Ye <tony.ye@intel.com>
>> CC: Carl Zhang <carl.zhang@intel.com>
>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>> Cc: Jason Ekstrand <jason@jlekstrand.net>
>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>> ---
>>   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>>   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>>   2 files changed, 196 insertions(+), 1 deletion(-)
>>   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>>
>> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>> new file mode 100644
>> index 000000000000..8c64b983ccad
>> --- /dev/null
>> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>> @@ -0,0 +1,144 @@
>> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
>> +
>> +/*
>> + * i915_context_engines_parallel_submit:
>> + *
>> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
>> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
>> + * hardware contexts are created internally in the i915 run these BBs. Once a
>> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
>> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
>> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
>> + * the slots configuration).
>> + *
>> + * Their are two currently defined ways to control the placement of the
>> + * hardware contexts on physical engines: default behavior (no flags) and
>> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
>> + * future as new hardware / use cases arise. Details of how to use this
>> + * interface below above the flags.
>> + *
>> + * Returns -EINVAL if hardware context placement configuration invalid or if the
>> + * placement configuration isn't supported on the platform / submission
>> + * interface.
>> + * Returns -ENODEV if extension isn't supported on the platform / submission
>> + * inteface.
>> + */
>> +struct i915_context_engines_parallel_submit {
>> +	struct i915_user_extension base;
>> +
>> +	__u16 engine_index;	/* slot for parallel engine */
>> +	__u16 width;		/* number of contexts per parallel engine */
>> +	__u16 num_siblings;	/* number of siblings per context */
>> +	__u16 mbz16;
> 
> Ok the big picture looks reasonable now, the flags still confuse me.
> 
>> +/*
>> + * Default placement behvavior (currently unsupported):
>> + *
>> + * Rather than restricting parallel submission to a single class with a
>> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
>> + * enables parallel submission across multiple engine classes. In this case each
>> + * context's logical engine mask indicates where that context can placed. It is
>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>> + * if one context is running CS0 no other contexts can run on CS0).
>> + *
>> + * Example 1 pseudo code:
>> + * CSX[Y] = engine class X, logical instance Y
>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>> + * set_engines(INVALID)
>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
>> + *
>> + * Results in the following valid placements:
>> + * CS0[0], CS1[0]
>> + * CS0[0], CS1[1]
>> + * CS0[1], CS1[0]
>> + * CS0[1], CS1[1]
>> + *
>> + * This can also be though of as 2 virtual engines:
>> + * VE[0] = CS0[0], CS0[1]
>> + * VE[1] = CS1[0], CS1[1]
>> + *
>> + * Example 2 pseudo code:
>> + * CS[X] = generic engine of same class, logical instance X
>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>> + * set_engines(INVALID)
>> + * set_parallel(engine_index=0, width=2, num_siblings=3,
>> + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
>> + *
>> + * Results in the following valid placements:
>> + * CS[0], CS[1]
>> + * CS[0], CS[2]
>> + * CS[1], CS[0]
>> + * CS[1], CS[2]
>> + * CS[2], CS[0]
>> + * CS[2], CS[1]
>> + *
>> + *
>> + * This can also be though of as 2 virtual engines:
>> + * VE[0] = CS[0], CS[1], CS[2]
>> + * VE[1] = CS[0], CS[1], CS[2]
>> +
>> + * This enables a use case where all engines are created equally, we don't care
>> + * where they are scheduled, we just want a certain number of resources, for
>> + * those resources to be scheduled in parallel, and possibly across multiple
>> + * engine classes.
>> + */
> 
> So I don't really get what this does compared to setting the flag below.
> Is this just about running the batchbuffers the wrong way round, i.e. if
> you have (simplest case)
> 
> width=2, num_sibglings=1, engines=CS[0], CS[1]
> 
> Then both
> CS[0], CS[1]
> and
> CS[1], CS[0]
> are possible options for running 2 batches? Iow, the backend is allowed to
> run the batchbuffers the wrong way round, which gains us nothing, since we
> assume the batches take equally long and engines interchangeable. There is
> no scheduling scenario where this additional flexibility can help.
> 
> Also we don't have flags to select the only available and then specify an
> entire pipe dream about what the non-flag mode does, without an
> implementation. What is this about?
> 
> If it's just "because bonded allowed this" then I think we should just
> unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> welp.

At the risk of repeating some of the information:

Flexibility helps to avoid hardcoding the current limitations of media 
fixed function pipe into the uapi.

Today's media: Run on N consecutive instances.

Tomorrow's media: Run on N consecutive logical instances.

(Note that the engine addressing we expose today is class:instance based 
which is not this new logical instance name space. It's something else. 
Point of engine discovery and flexible bond configuration was to punt 
these questions to userspace.)

Tomorrow's compute: Run on any N instances.

Tomorrow's + 1 media: Who knows.

Consider the scheduling advantage when the "consecutiveness" is not 
hardcoded in the uapi:

cs0: busy with 1 wide context
cs1: idle
cs2: busy with 1 wide context
cs3: idle

2-wide job with hardcoded consecutive engines now can't run without 
scheduler needing to re-balance.

2-wide job with any-2 can run fine.

(Also keep in mind that all 1-wide, 2-wide and 4-wide contexts can fight 
for four physical engines.)

This was an argument for not hardcoding "consecutiveness". Then if we 
think about cs0 + cs1 vs cs1 + cs0 ordering inversion, for today's media 
there is indeed no benefit to allow the inversion (and it cannot be 
allowed).

But we can expand the argument into parallel submissions which 
absolutely have to run in parallel otherwise the GPU hangs, or at least 
progress stalls, versus the ones which benefit from running in parallel 
but do not strictly depend on it.

In the latter case allowing inversions of the set is a benefit. 
Scheduler can now put partial jobs on the GPU without having to idle, or 
wait for idle, on the other engines.

Overall, bonds weren't the mistake, as much I am sure there is a nice 
camp of people who hate them pasionately. (Hey I hate relocations 
because I can never remember what is offset and what is delta. Or maybe 
that is just because I don't use them enough.) Yes they can be hard to 
understand at first but they were not the mistake. Mistake was the 
disconnect between atomic parallel submission and separate execbufs tied 
with a submit fence which then takes double functionality.

Anyway, all that we need to do today and in the future can be expressed 
with bonds. All that was needed for the GuC backend is to reject the 
bond configuration GuC firmware cannot do. Cannot do today. Can't stress 
this "today" enough. Because we almost got an update of the GuC firmware 
already last year or so which would have broken this assumption for 
compute and made it more flexible.

Which is why I was pushing to make the set_parallel extension more 
flexible than just today's media use cases. Or you may end up adding 
more uapi year after year. Why if bonds can do it all? Why even if bonds 
are not even needed for generic parallel submit in proposed GuC 
multi-LRC changes for compute? They are only needed for media. So all 
the new uapi needed to add is a proper atomic parallel submit.

Literally my proposal was just to add a single flag of how wide the 
context is plus multi-bb execbuf extension and that's all that would be 
needed.

There is a document somewhere which lists all possible usecases that I 
suggest is looked at if the uapi is getting re-designed.

Regards,

Tvrtko

>> +
>> +/*
>> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
>> + * Each context must have the same number sibling and bonds are implictly create
>> + * of the siblings.
>> + *
>> + * All of the below examples are in logical space.
>> + *
>> + * Example 1 pseudo code:
>> + * CS[X] = generic engine of same class, logical instance X
>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>> + * set_engines(INVALID)
>> + * set_parallel(engine_index=0, width=2, num_siblings=1,
>> + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
>> + *
>> + * Results in the following valid placements:
>> + * CS[0], CS[1]
>> + *
>> + * Example 2 pseudo code:
>> + * CS[X] = generic engine of same class, logical instance X
>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>> + * set_engines(INVALID)
>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>> + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
>> + *
>> + * Results in the following valid placements:
>> + * CS[0], CS[1]
>> + * CS[2], CS[3]
>> + *
>> + * This can also be though of as 2 virtual engines:
>> + * VE[0] = CS[0], CS[2]
>> + * VE[1] = CS[1], CS[3]
>> + *
>> + * This enables a use case where all engines are not equal and certain placement
>> + * rules are required (i.e. split-frame requires all contexts to be placed in a
>> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
>> + * case (logically contiguous placement, within a single engine class) is
>> + * supported when using GuC submission. Execlist mode could support all possible
>> + * bonding configurations but currently doesn't support this extension.
>> + */
>> +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> 
> Does this map to intel_context_set_nopreempt(), so we could implement it
> also in execlist?
> 
> Also is this just an artifact of the implementation, or is this somehow
> required functionality for userspace, i.e. the workload fails if e.g. GuC
> decides to preempt all LRC of a parallel virtual engine? Of course just
> preempting one is a bit a bug (but execlist I think happily does that).
> 
> Cheers, Daniel
> 
>> +/*
>> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
>> + * points on all hardware contexts between each set of BBs. An example use case
>> + * of this feature is split-frame on gen11+ hardware. When using this feature a
>> + * BB must be submitted on each hardware context in the parallel gem context.
>> + * The execbuf2 IOCTL enforces the user adheres to policy.
>> + */
>> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
>> +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
>> +	__u64 flags;		/* all undefined flags must be zero */
>> +	__u64 mbz64[3];		/* reserved for future use; must be zero */
>> +
>> +	/*
>> +	 * width (i) * num_siblings (j) in length
>> +	 * index = j + i * num_siblings
>> +	 */
>> +	struct i915_engine_class_instance engines[0];
>> +} __attribute__ ((packed));
>> +
>> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
>> index 7faa46cde088..64c539486ee4 100644
>> --- a/Documentation/gpu/rfc/i915_scheduler.rst
>> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
>> @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
>>   
>>   New parallel submission uAPI
>>   ============================
>> -Details to come in a following patch.
>> +The existing bonding uAPI is completely broken with GuC submission because
>> +whether a submission is a single context submit or parallel submit isn't known
>> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
>> +contexts in parallel with the GuC the context must be explictly registered with
>> +N contexts and all N contexts must be submitted in a single command to the GuC.
>> +These interfaces doesn't support dynamically changing between N contexts as the
>> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
>> +the legacy bonding uAPI is quite confusing and not intuitive at all.
>> +
>> +The new parallel submission uAPI consists of 3 parts:
>> +
>> +* Export engines logical mapping
>> +* A 'set_parallel' extension to configure contexts for parallel
>> +  submission
>> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>> +
>> +Export engines logical mapping
>> +------------------------------
>> +Certain use cases require BBs to be placed on engine instances in logical order
>> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
>> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
>> +logical mapping with the existing query engine info IOCTL. Also the GuC
>> +submission interface currently only supports submitting multiple contexts to
>> +engines in logical order which is a new requirement compared to execlists.
>> +Lastly, all current platforms have at most 2 instances and the logical order is
>> +the same a uABI order. This will change on platforms with more than 2 instances.
>> +
>> +A single bit will be added to drm_i915_engine_info.flags indicating that the
>> +logical instance has been returned and a new field,
>> +drm_i915_engine_info.logical_instance, returns the logical instance.
>> +
>> +A 'set_parallel' extension to configure contexts for parallel submission
>> +------------------------------------------------------------------------
>> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
>> +It is setup step that should be called before using any of the contexts. See
>> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
>> +similar existing examples. Once a slot is configured for parallel submission the
>> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
>> +support GuC submission. Execlist support can be added later if needed.
>> +
>> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
>> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
>> +
>> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>> +-------------------------------------------------------------------
>> +Contexts that have been configured with the 'set_parallel' extension are allowed
>> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
>> +objects in the drm_i915_gem_exec_object2 list or the first N if
>> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
>> +submitted and how it has been configured by 'set_parallel' or other extensions.
>> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
>> +the IOCTL.
>> -- 
>> 2.28.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-19 15:29       ` Tvrtko Ursulin
  0 siblings, 0 replies; 54+ messages in thread
From: Tvrtko Ursulin @ 2021-05-19 15:29 UTC (permalink / raw)
  To: Daniel Vetter, Matthew Brost
  Cc: intel-gfx, dri-devel, jason.ekstrand, mesa-dev, daniel.vetter,
	karl, christian.koenig


On 19/05/2021 12:10, Daniel Vetter wrote:
> On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
>> Add entry fpr i915 new parallel submission uAPI plan.
>>
>> v2:
>>   (Daniel Vetter):
>>    - Expand logical order explaination
>>    - Add dummy header
>>    - Only allow N BBs in execbuf IOCTL
>>    - Configure parallel submission per slot not per gem context
>>
>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Tony Ye <tony.ye@intel.com>
>> CC: Carl Zhang <carl.zhang@intel.com>
>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>> Cc: Jason Ekstrand <jason@jlekstrand.net>
>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>> ---
>>   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>>   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>>   2 files changed, 196 insertions(+), 1 deletion(-)
>>   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>>
>> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>> new file mode 100644
>> index 000000000000..8c64b983ccad
>> --- /dev/null
>> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>> @@ -0,0 +1,144 @@
>> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
>> +
>> +/*
>> + * i915_context_engines_parallel_submit:
>> + *
>> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
>> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
>> + * hardware contexts are created internally in the i915 run these BBs. Once a
>> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
>> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
>> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
>> + * the slots configuration).
>> + *
>> + * Their are two currently defined ways to control the placement of the
>> + * hardware contexts on physical engines: default behavior (no flags) and
>> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
>> + * future as new hardware / use cases arise. Details of how to use this
>> + * interface below above the flags.
>> + *
>> + * Returns -EINVAL if hardware context placement configuration invalid or if the
>> + * placement configuration isn't supported on the platform / submission
>> + * interface.
>> + * Returns -ENODEV if extension isn't supported on the platform / submission
>> + * inteface.
>> + */
>> +struct i915_context_engines_parallel_submit {
>> +	struct i915_user_extension base;
>> +
>> +	__u16 engine_index;	/* slot for parallel engine */
>> +	__u16 width;		/* number of contexts per parallel engine */
>> +	__u16 num_siblings;	/* number of siblings per context */
>> +	__u16 mbz16;
> 
> Ok the big picture looks reasonable now, the flags still confuse me.
> 
>> +/*
>> + * Default placement behvavior (currently unsupported):
>> + *
>> + * Rather than restricting parallel submission to a single class with a
>> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
>> + * enables parallel submission across multiple engine classes. In this case each
>> + * context's logical engine mask indicates where that context can placed. It is
>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>> + * if one context is running CS0 no other contexts can run on CS0).
>> + *
>> + * Example 1 pseudo code:
>> + * CSX[Y] = engine class X, logical instance Y
>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>> + * set_engines(INVALID)
>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
>> + *
>> + * Results in the following valid placements:
>> + * CS0[0], CS1[0]
>> + * CS0[0], CS1[1]
>> + * CS0[1], CS1[0]
>> + * CS0[1], CS1[1]
>> + *
>> + * This can also be though of as 2 virtual engines:
>> + * VE[0] = CS0[0], CS0[1]
>> + * VE[1] = CS1[0], CS1[1]
>> + *
>> + * Example 2 pseudo code:
>> + * CS[X] = generic engine of same class, logical instance X
>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>> + * set_engines(INVALID)
>> + * set_parallel(engine_index=0, width=2, num_siblings=3,
>> + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
>> + *
>> + * Results in the following valid placements:
>> + * CS[0], CS[1]
>> + * CS[0], CS[2]
>> + * CS[1], CS[0]
>> + * CS[1], CS[2]
>> + * CS[2], CS[0]
>> + * CS[2], CS[1]
>> + *
>> + *
>> + * This can also be though of as 2 virtual engines:
>> + * VE[0] = CS[0], CS[1], CS[2]
>> + * VE[1] = CS[0], CS[1], CS[2]
>> +
>> + * This enables a use case where all engines are created equally, we don't care
>> + * where they are scheduled, we just want a certain number of resources, for
>> + * those resources to be scheduled in parallel, and possibly across multiple
>> + * engine classes.
>> + */
> 
> So I don't really get what this does compared to setting the flag below.
> Is this just about running the batchbuffers the wrong way round, i.e. if
> you have (simplest case)
> 
> width=2, num_sibglings=1, engines=CS[0], CS[1]
> 
> Then both
> CS[0], CS[1]
> and
> CS[1], CS[0]
> are possible options for running 2 batches? Iow, the backend is allowed to
> run the batchbuffers the wrong way round, which gains us nothing, since we
> assume the batches take equally long and engines interchangeable. There is
> no scheduling scenario where this additional flexibility can help.
> 
> Also we don't have flags to select the only available and then specify an
> entire pipe dream about what the non-flag mode does, without an
> implementation. What is this about?
> 
> If it's just "because bonded allowed this" then I think we should just
> unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> welp.

At the risk of repeating some of the information:

Flexibility helps to avoid hardcoding the current limitations of media 
fixed function pipe into the uapi.

Today's media: Run on N consecutive instances.

Tomorrow's media: Run on N consecutive logical instances.

(Note that the engine addressing we expose today is class:instance based 
which is not this new logical instance name space. It's something else. 
Point of engine discovery and flexible bond configuration was to punt 
these questions to userspace.)

Tomorrow's compute: Run on any N instances.

Tomorrow's + 1 media: Who knows.

Consider the scheduling advantage when the "consecutiveness" is not 
hardcoded in the uapi:

cs0: busy with 1 wide context
cs1: idle
cs2: busy with 1 wide context
cs3: idle

2-wide job with hardcoded consecutive engines now can't run without 
scheduler needing to re-balance.

2-wide job with any-2 can run fine.

(Also keep in mind that all 1-wide, 2-wide and 4-wide contexts can fight 
for four physical engines.)

This was an argument for not hardcoding "consecutiveness". Then if we 
think about cs0 + cs1 vs cs1 + cs0 ordering inversion, for today's media 
there is indeed no benefit to allow the inversion (and it cannot be 
allowed).

But we can expand the argument into parallel submissions which 
absolutely have to run in parallel otherwise the GPU hangs, or at least 
progress stalls, versus the ones which benefit from running in parallel 
but do not strictly depend on it.

In the latter case allowing inversions of the set is a benefit. 
Scheduler can now put partial jobs on the GPU without having to idle, or 
wait for idle, on the other engines.

Overall, bonds weren't the mistake, as much I am sure there is a nice 
camp of people who hate them pasionately. (Hey I hate relocations 
because I can never remember what is offset and what is delta. Or maybe 
that is just because I don't use them enough.) Yes they can be hard to 
understand at first but they were not the mistake. Mistake was the 
disconnect between atomic parallel submission and separate execbufs tied 
with a submit fence which then takes double functionality.

Anyway, all that we need to do today and in the future can be expressed 
with bonds. All that was needed for the GuC backend is to reject the 
bond configuration GuC firmware cannot do. Cannot do today. Can't stress 
this "today" enough. Because we almost got an update of the GuC firmware 
already last year or so which would have broken this assumption for 
compute and made it more flexible.

Which is why I was pushing to make the set_parallel extension more 
flexible than just today's media use cases. Or you may end up adding 
more uapi year after year. Why if bonds can do it all? Why even if bonds 
are not even needed for generic parallel submit in proposed GuC 
multi-LRC changes for compute? They are only needed for media. So all 
the new uapi needed to add is a proper atomic parallel submit.

Literally my proposal was just to add a single flag of how wide the 
context is plus multi-bb execbuf extension and that's all that would be 
needed.

There is a document somewhere which lists all possible usecases that I 
suggest is looked at if the uapi is getting re-designed.

Regards,

Tvrtko

>> +
>> +/*
>> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
>> + * Each context must have the same number sibling and bonds are implictly create
>> + * of the siblings.
>> + *
>> + * All of the below examples are in logical space.
>> + *
>> + * Example 1 pseudo code:
>> + * CS[X] = generic engine of same class, logical instance X
>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>> + * set_engines(INVALID)
>> + * set_parallel(engine_index=0, width=2, num_siblings=1,
>> + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
>> + *
>> + * Results in the following valid placements:
>> + * CS[0], CS[1]
>> + *
>> + * Example 2 pseudo code:
>> + * CS[X] = generic engine of same class, logical instance X
>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>> + * set_engines(INVALID)
>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>> + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
>> + *
>> + * Results in the following valid placements:
>> + * CS[0], CS[1]
>> + * CS[2], CS[3]
>> + *
>> + * This can also be though of as 2 virtual engines:
>> + * VE[0] = CS[0], CS[2]
>> + * VE[1] = CS[1], CS[3]
>> + *
>> + * This enables a use case where all engines are not equal and certain placement
>> + * rules are required (i.e. split-frame requires all contexts to be placed in a
>> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
>> + * case (logically contiguous placement, within a single engine class) is
>> + * supported when using GuC submission. Execlist mode could support all possible
>> + * bonding configurations but currently doesn't support this extension.
>> + */
>> +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> 
> Does this map to intel_context_set_nopreempt(), so we could implement it
> also in execlist?
> 
> Also is this just an artifact of the implementation, or is this somehow
> required functionality for userspace, i.e. the workload fails if e.g. GuC
> decides to preempt all LRC of a parallel virtual engine? Of course just
> preempting one is a bit a bug (but execlist I think happily does that).
> 
> Cheers, Daniel
> 
>> +/*
>> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
>> + * points on all hardware contexts between each set of BBs. An example use case
>> + * of this feature is split-frame on gen11+ hardware. When using this feature a
>> + * BB must be submitted on each hardware context in the parallel gem context.
>> + * The execbuf2 IOCTL enforces the user adheres to policy.
>> + */
>> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
>> +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
>> +	__u64 flags;		/* all undefined flags must be zero */
>> +	__u64 mbz64[3];		/* reserved for future use; must be zero */
>> +
>> +	/*
>> +	 * width (i) * num_siblings (j) in length
>> +	 * index = j + i * num_siblings
>> +	 */
>> +	struct i915_engine_class_instance engines[0];
>> +} __attribute__ ((packed));
>> +
>> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
>> index 7faa46cde088..64c539486ee4 100644
>> --- a/Documentation/gpu/rfc/i915_scheduler.rst
>> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
>> @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
>>   
>>   New parallel submission uAPI
>>   ============================
>> -Details to come in a following patch.
>> +The existing bonding uAPI is completely broken with GuC submission because
>> +whether a submission is a single context submit or parallel submit isn't known
>> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
>> +contexts in parallel with the GuC the context must be explictly registered with
>> +N contexts and all N contexts must be submitted in a single command to the GuC.
>> +These interfaces doesn't support dynamically changing between N contexts as the
>> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
>> +the legacy bonding uAPI is quite confusing and not intuitive at all.
>> +
>> +The new parallel submission uAPI consists of 3 parts:
>> +
>> +* Export engines logical mapping
>> +* A 'set_parallel' extension to configure contexts for parallel
>> +  submission
>> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>> +
>> +Export engines logical mapping
>> +------------------------------
>> +Certain use cases require BBs to be placed on engine instances in logical order
>> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
>> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
>> +logical mapping with the existing query engine info IOCTL. Also the GuC
>> +submission interface currently only supports submitting multiple contexts to
>> +engines in logical order which is a new requirement compared to execlists.
>> +Lastly, all current platforms have at most 2 instances and the logical order is
>> +the same a uABI order. This will change on platforms with more than 2 instances.
>> +
>> +A single bit will be added to drm_i915_engine_info.flags indicating that the
>> +logical instance has been returned and a new field,
>> +drm_i915_engine_info.logical_instance, returns the logical instance.
>> +
>> +A 'set_parallel' extension to configure contexts for parallel submission
>> +------------------------------------------------------------------------
>> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
>> +It is setup step that should be called before using any of the contexts. See
>> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
>> +similar existing examples. Once a slot is configured for parallel submission the
>> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
>> +support GuC submission. Execlist support can be added later if needed.
>> +
>> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
>> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
>> +
>> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>> +-------------------------------------------------------------------
>> +Contexts that have been configured with the 'set_parallel' extension are allowed
>> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
>> +objects in the drm_i915_gem_exec_object2 list or the first N if
>> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
>> +submitted and how it has been configured by 'set_parallel' or other extensions.
>> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
>> +the IOCTL.
>> -- 
>> 2.28.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-19 11:45     ` [Intel-gfx] " Christian König
@ 2021-05-19 16:51       ` Matthew Brost
  -1 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-19 16:51 UTC (permalink / raw)
  To: Christian König
  Cc: tony.ye, tvrtko.ursulin, intel-gfx, dri-devel, jason.ekstrand,
	michal.mrozek, daniele.ceraolospurio, jon.bloomfield,
	daniel.vetter, mesa-dev, karl, christian.koenig, john.c.harrison

On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
> Oh, yeah we call that gang submit on the AMD side.
> 
> Had already some internal discussions how to implement this, but so far
> couldn't figure out how to cleanly introduce that into the DRM scheduler.
> 
> Can you briefly describe in a few words how that is supposed to work on the
> Intel side?
> 

Sure, I've done a quick PoC internally and have been able to hook this
into the DRM scheduler.

Basically each BB still maps to a single job as each job is somewhat
unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
the jobs configured to run in parallel map to a single sched_entity
which maintains the order each job was generated from the execbuf IOCTL
(1 - N). When the backend receives jobs 1 to N - 1 it basically just
updates some internal state. When the backend sees job N (last job) it
actually does the submit for jobs 1 - N which with GuC submission is a
simple command moving the LRC tail of the N jobs.

Daniel has suggested that we create a single job for the NN BBs but that
would be huge rework to the internals of the i915 and likely won't
happen by the time this code first lands.

Also worth noting one way a job isn't really a treated individually is
the excl slot with dma-resv. In that case we create a composite fence of
all jobs (dma_fence_array).

Matt

> Thanks,
> Christian.
> 
> Am 19.05.21 um 01:58 schrieb Matthew Brost:
> > Add entry fpr i915 new parallel submission uAPI plan.
> > 
> > v2:
> >   (Daniel Vetter):
> >    - Expand logical order explaination
> >    - Add dummy header
> >    - Only allow N BBs in execbuf IOCTL
> >    - Configure parallel submission per slot not per gem context
> > 
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Tony Ye <tony.ye@intel.com>
> > CC: Carl Zhang <carl.zhang@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> >   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> >   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> >   2 files changed, 196 insertions(+), 1 deletion(-)
> >   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > 
> > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > new file mode 100644
> > index 000000000000..8c64b983ccad
> > --- /dev/null
> > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > @@ -0,0 +1,144 @@
> > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > +
> > +/*
> > + * i915_context_engines_parallel_submit:
> > + *
> > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > + * the slots configuration).
> > + *
> > + * Their are two currently defined ways to control the placement of the
> > + * hardware contexts on physical engines: default behavior (no flags) and
> > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > + * future as new hardware / use cases arise. Details of how to use this
> > + * interface below above the flags.
> > + *
> > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > + * placement configuration isn't supported on the platform / submission
> > + * interface.
> > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > + * inteface.
> > + */
> > +struct i915_context_engines_parallel_submit {
> > +	struct i915_user_extension base;
> > +
> > +	__u16 engine_index;	/* slot for parallel engine */
> > +	__u16 width;		/* number of contexts per parallel engine */
> > +	__u16 num_siblings;	/* number of siblings per context */
> > +	__u16 mbz16;
> > +/*
> > + * Default placement behvavior (currently unsupported):
> > + *
> > + * Rather than restricting parallel submission to a single class with a
> > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > + * enables parallel submission across multiple engine classes. In this case each
> > + * context's logical engine mask indicates where that context can placed. It is
> > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > + * if one context is running CS0 no other contexts can run on CS0).
> > + *
> > + * Example 1 pseudo code:
> > + * CSX[Y] = engine class X, logical instance Y
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > + *
> > + * Results in the following valid placements:
> > + * CS0[0], CS1[0]
> > + * CS0[0], CS1[1]
> > + * CS0[1], CS1[0]
> > + * CS0[1], CS1[1]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS0[0], CS0[1]
> > + * VE[1] = CS1[0], CS1[1]
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[0], CS[2]
> > + * CS[1], CS[0]
> > + * CS[1], CS[2]
> > + * CS[2], CS[0]
> > + * CS[2], CS[1]
> > + *
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[1], CS[2]
> > + * VE[1] = CS[0], CS[1], CS[2]
> > +
> > + * This enables a use case where all engines are created equally, we don't care
> > + * where they are scheduled, we just want a certain number of resources, for
> > + * those resources to be scheduled in parallel, and possibly across multiple
> > + * engine classes.
> > + */
> > +
> > +/*
> > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > + * Each context must have the same number sibling and bonds are implictly create
> > + * of the siblings.
> > + *
> > + * All of the below examples are in logical space.
> > + *
> > + * Example 1 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[2], CS[3]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[2]
> > + * VE[1] = CS[1], CS[3]
> > + *
> > + * This enables a use case where all engines are not equal and certain placement
> > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > + * case (logically contiguous placement, within a single engine class) is
> > + * supported when using GuC submission. Execlist mode could support all possible
> > + * bonding configurations but currently doesn't support this extension.
> > + */
> > +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> > +/*
> > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > + * points on all hardware contexts between each set of BBs. An example use case
> > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > + * BB must be submitted on each hardware context in the parallel gem context.
> > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > + */
> > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> > +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > +	__u64 flags;		/* all undefined flags must be zero */
> > +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> > +
> > +	/*
> > +	 * width (i) * num_siblings (j) in length
> > +	 * index = j + i * num_siblings
> > +	 */
> > +	struct i915_engine_class_instance engines[0];
> > +} __attribute__ ((packed));
> > +
> > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > index 7faa46cde088..64c539486ee4 100644
> > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> >   New parallel submission uAPI
> >   ============================
> > -Details to come in a following patch.
> > +The existing bonding uAPI is completely broken with GuC submission because
> > +whether a submission is a single context submit or parallel submit isn't known
> > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > +contexts in parallel with the GuC the context must be explictly registered with
> > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > +These interfaces doesn't support dynamically changing between N contexts as the
> > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > +
> > +The new parallel submission uAPI consists of 3 parts:
> > +
> > +* Export engines logical mapping
> > +* A 'set_parallel' extension to configure contexts for parallel
> > +  submission
> > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +
> > +Export engines logical mapping
> > +------------------------------
> > +Certain use cases require BBs to be placed on engine instances in logical order
> > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > +submission interface currently only supports submitting multiple contexts to
> > +engines in logical order which is a new requirement compared to execlists.
> > +Lastly, all current platforms have at most 2 instances and the logical order is
> > +the same a uABI order. This will change on platforms with more than 2 instances.
> > +
> > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > +logical instance has been returned and a new field,
> > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > +
> > +A 'set_parallel' extension to configure contexts for parallel submission
> > +------------------------------------------------------------------------
> > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > +It is setup step that should be called before using any of the contexts. See
> > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > +similar existing examples. Once a slot is configured for parallel submission the
> > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > +support GuC submission. Execlist support can be added later if needed.
> > +
> > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > +
> > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +-------------------------------------------------------------------
> > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > +the IOCTL.
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-19 16:51       ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-19 16:51 UTC (permalink / raw)
  To: Christian König
  Cc: intel-gfx, dri-devel, jason.ekstrand, daniel.vetter, mesa-dev,
	karl, christian.koenig

On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
> Oh, yeah we call that gang submit on the AMD side.
> 
> Had already some internal discussions how to implement this, but so far
> couldn't figure out how to cleanly introduce that into the DRM scheduler.
> 
> Can you briefly describe in a few words how that is supposed to work on the
> Intel side?
> 

Sure, I've done a quick PoC internally and have been able to hook this
into the DRM scheduler.

Basically each BB still maps to a single job as each job is somewhat
unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
the jobs configured to run in parallel map to a single sched_entity
which maintains the order each job was generated from the execbuf IOCTL
(1 - N). When the backend receives jobs 1 to N - 1 it basically just
updates some internal state. When the backend sees job N (last job) it
actually does the submit for jobs 1 - N which with GuC submission is a
simple command moving the LRC tail of the N jobs.

Daniel has suggested that we create a single job for the NN BBs but that
would be huge rework to the internals of the i915 and likely won't
happen by the time this code first lands.

Also worth noting one way a job isn't really a treated individually is
the excl slot with dma-resv. In that case we create a composite fence of
all jobs (dma_fence_array).

Matt

> Thanks,
> Christian.
> 
> Am 19.05.21 um 01:58 schrieb Matthew Brost:
> > Add entry fpr i915 new parallel submission uAPI plan.
> > 
> > v2:
> >   (Daniel Vetter):
> >    - Expand logical order explaination
> >    - Add dummy header
> >    - Only allow N BBs in execbuf IOCTL
> >    - Configure parallel submission per slot not per gem context
> > 
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Tony Ye <tony.ye@intel.com>
> > CC: Carl Zhang <carl.zhang@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> >   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> >   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> >   2 files changed, 196 insertions(+), 1 deletion(-)
> >   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > 
> > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > new file mode 100644
> > index 000000000000..8c64b983ccad
> > --- /dev/null
> > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > @@ -0,0 +1,144 @@
> > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > +
> > +/*
> > + * i915_context_engines_parallel_submit:
> > + *
> > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > + * the slots configuration).
> > + *
> > + * Their are two currently defined ways to control the placement of the
> > + * hardware contexts on physical engines: default behavior (no flags) and
> > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > + * future as new hardware / use cases arise. Details of how to use this
> > + * interface below above the flags.
> > + *
> > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > + * placement configuration isn't supported on the platform / submission
> > + * interface.
> > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > + * inteface.
> > + */
> > +struct i915_context_engines_parallel_submit {
> > +	struct i915_user_extension base;
> > +
> > +	__u16 engine_index;	/* slot for parallel engine */
> > +	__u16 width;		/* number of contexts per parallel engine */
> > +	__u16 num_siblings;	/* number of siblings per context */
> > +	__u16 mbz16;
> > +/*
> > + * Default placement behvavior (currently unsupported):
> > + *
> > + * Rather than restricting parallel submission to a single class with a
> > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > + * enables parallel submission across multiple engine classes. In this case each
> > + * context's logical engine mask indicates where that context can placed. It is
> > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > + * if one context is running CS0 no other contexts can run on CS0).
> > + *
> > + * Example 1 pseudo code:
> > + * CSX[Y] = engine class X, logical instance Y
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > + *
> > + * Results in the following valid placements:
> > + * CS0[0], CS1[0]
> > + * CS0[0], CS1[1]
> > + * CS0[1], CS1[0]
> > + * CS0[1], CS1[1]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS0[0], CS0[1]
> > + * VE[1] = CS1[0], CS1[1]
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[0], CS[2]
> > + * CS[1], CS[0]
> > + * CS[1], CS[2]
> > + * CS[2], CS[0]
> > + * CS[2], CS[1]
> > + *
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[1], CS[2]
> > + * VE[1] = CS[0], CS[1], CS[2]
> > +
> > + * This enables a use case where all engines are created equally, we don't care
> > + * where they are scheduled, we just want a certain number of resources, for
> > + * those resources to be scheduled in parallel, and possibly across multiple
> > + * engine classes.
> > + */
> > +
> > +/*
> > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > + * Each context must have the same number sibling and bonds are implictly create
> > + * of the siblings.
> > + *
> > + * All of the below examples are in logical space.
> > + *
> > + * Example 1 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[2], CS[3]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[2]
> > + * VE[1] = CS[1], CS[3]
> > + *
> > + * This enables a use case where all engines are not equal and certain placement
> > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > + * case (logically contiguous placement, within a single engine class) is
> > + * supported when using GuC submission. Execlist mode could support all possible
> > + * bonding configurations but currently doesn't support this extension.
> > + */
> > +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> > +/*
> > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > + * points on all hardware contexts between each set of BBs. An example use case
> > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > + * BB must be submitted on each hardware context in the parallel gem context.
> > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > + */
> > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> > +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > +	__u64 flags;		/* all undefined flags must be zero */
> > +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> > +
> > +	/*
> > +	 * width (i) * num_siblings (j) in length
> > +	 * index = j + i * num_siblings
> > +	 */
> > +	struct i915_engine_class_instance engines[0];
> > +} __attribute__ ((packed));
> > +
> > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > index 7faa46cde088..64c539486ee4 100644
> > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> >   New parallel submission uAPI
> >   ============================
> > -Details to come in a following patch.
> > +The existing bonding uAPI is completely broken with GuC submission because
> > +whether a submission is a single context submit or parallel submit isn't known
> > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > +contexts in parallel with the GuC the context must be explictly registered with
> > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > +These interfaces doesn't support dynamically changing between N contexts as the
> > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > +
> > +The new parallel submission uAPI consists of 3 parts:
> > +
> > +* Export engines logical mapping
> > +* A 'set_parallel' extension to configure contexts for parallel
> > +  submission
> > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +
> > +Export engines logical mapping
> > +------------------------------
> > +Certain use cases require BBs to be placed on engine instances in logical order
> > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > +submission interface currently only supports submitting multiple contexts to
> > +engines in logical order which is a new requirement compared to execlists.
> > +Lastly, all current platforms have at most 2 instances and the logical order is
> > +the same a uABI order. This will change on platforms with more than 2 instances.
> > +
> > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > +logical instance has been returned and a new field,
> > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > +
> > +A 'set_parallel' extension to configure contexts for parallel submission
> > +------------------------------------------------------------------------
> > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > +It is setup step that should be called before using any of the contexts. See
> > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > +similar existing examples. Once a slot is configured for parallel submission the
> > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > +support GuC submission. Execlist support can be added later if needed.
> > +
> > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > +
> > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +-------------------------------------------------------------------
> > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > +the IOCTL.
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-19 11:10     ` Daniel Vetter
@ 2021-05-19 17:11       ` Matthew Brost
  -1 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-19 17:11 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: intel-gfx, dri-devel, jason.ekstrand, daniel.vetter, mesa-dev,
	karl, christian.koenig

On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > Add entry fpr i915 new parallel submission uAPI plan.
> > 
> > v2:
> >  (Daniel Vetter):
> >   - Expand logical order explaination
> >   - Add dummy header
> >   - Only allow N BBs in execbuf IOCTL
> >   - Configure parallel submission per slot not per gem context
> > 
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Tony Ye <tony.ye@intel.com>
> > CC: Carl Zhang <carl.zhang@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> >  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> >  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> >  2 files changed, 196 insertions(+), 1 deletion(-)
> >  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > 
> > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > new file mode 100644
> > index 000000000000..8c64b983ccad
> > --- /dev/null
> > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > @@ -0,0 +1,144 @@
> > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > +
> > +/*
> > + * i915_context_engines_parallel_submit:
> > + *
> > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > + * the slots configuration).
> > + *
> > + * Their are two currently defined ways to control the placement of the
> > + * hardware contexts on physical engines: default behavior (no flags) and
> > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > + * future as new hardware / use cases arise. Details of how to use this
> > + * interface below above the flags.
> > + *
> > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > + * placement configuration isn't supported on the platform / submission
> > + * interface.
> > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > + * inteface.
> > + */
> > +struct i915_context_engines_parallel_submit {
> > +	struct i915_user_extension base;
> > +
> > +	__u16 engine_index;	/* slot for parallel engine */
> > +	__u16 width;		/* number of contexts per parallel engine */
> > +	__u16 num_siblings;	/* number of siblings per context */
> > +	__u16 mbz16;
> 
> Ok the big picture looks reasonable now, the flags still confuse me.
> 

Yea, it is a bit confusing.

> > +/*
> > + * Default placement behvavior (currently unsupported):
> > + *
> > + * Rather than restricting parallel submission to a single class with a
> > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > + * enables parallel submission across multiple engine classes. In this case each
> > + * context's logical engine mask indicates where that context can placed. It is
> > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > + * if one context is running CS0 no other contexts can run on CS0).
> > + *
> > + * Example 1 pseudo code:
> > + * CSX[Y] = engine class X, logical instance Y
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > + *
> > + * Results in the following valid placements:
> > + * CS0[0], CS1[0]
> > + * CS0[0], CS1[1]
> > + * CS0[1], CS1[0]
> > + * CS0[1], CS1[1]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS0[0], CS0[1]
> > + * VE[1] = CS1[0], CS1[1]
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[0], CS[2]
> > + * CS[1], CS[0]
> > + * CS[1], CS[2]
> > + * CS[2], CS[0]
> > + * CS[2], CS[1]
> > + *
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[1], CS[2]
> > + * VE[1] = CS[0], CS[1], CS[2]
> > +
> > + * This enables a use case where all engines are created equally, we don't care
> > + * where they are scheduled, we just want a certain number of resources, for
> > + * those resources to be scheduled in parallel, and possibly across multiple
> > + * engine classes.
> > + */
> 
> So I don't really get what this does compared to setting the flag below.
> Is this just about running the batchbuffers the wrong way round, i.e. if
> you have (simplest case)
> 
> width=2, num_sibglings=1, engines=CS[0], CS[1]
> 
> Then both
> CS[0], CS[1]
> and
> CS[1], CS[0]
> are possible options for running 2 batches? Iow, the backend is allowed to
> run the batchbuffers the wrong way round, which gains us nothing, since we
> assume the batches take equally long and engines interchangeable. There is
> no scheduling scenario where this additional flexibility can help.
> 
> Also we don't have flags to select the only available and then specify an
> entire pipe dream about what the non-flag mode does, without an
> implementation. What is this about?
> 
> If it's just "because bonded allowed this" then I think we should just
> unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> welp.
> 

High level the flags came out of internal discussions how this interface
should look. The default placement behavior is theoretically possible
with execlists but has no use cases. The GuC supports / current use
cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.

Argued about for months and this is where we landed. At the end of the
day I think we needed to show that this interface supports more
placement rules than what the GuC supports / current use cases to future
proof this interface.

For what is it worth it seems kinda backwards that we landed on the
default behavior not being supported in our current stack / HW.

> > +
> > +/*
> > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > + * Each context must have the same number sibling and bonds are implictly create
> > + * of the siblings.
> > + *
> > + * All of the below examples are in logical space.
> > + *
> > + * Example 1 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[2], CS[3]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[2]
> > + * VE[1] = CS[1], CS[3]
> > + *
> > + * This enables a use case where all engines are not equal and certain placement
> > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > + * case (logically contiguous placement, within a single engine class) is
> > + * supported when using GuC submission. Execlist mode could support all possible
> > + * bonding configurations but currently doesn't support this extension.
> > + */
> > +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> 
> Does this map to intel_context_set_nopreempt(), so we could implement it
> also in execlist?
>

intel_context_set_nopreempt is preempt is part of how this would be
implemented for execlists. For GuC submission there is a algorithm
between the i915 and GuC that inserts same preemption points between
each set of N batches. I believe the rules are if context 1 can
preempted the rest of the contexts (2 - N) can safely be preempted. A go
/ join algorithm, implemented with semaphores, around the batches
makes sure the i915 adheres to these rules.
 
> Also is this just an artifact of the implementation, or is this somehow
> required functionality for userspace, i.e. the workload fails if e.g. GuC
> decides to preempt all LRC of a parallel virtual engine? Of course just
> preempting one is a bit a bug (but execlist I think happily does that).
>

I think it is part of the implementation / HW limitations. Basically if
N batches are running in parallel if one of the batches gets preempted
it can hang all the other batches even if it gets restarted. Again the
idea behind this is only preempt any of these contexts between each set
of N batches. The GuC has no concept of batches only contexts hence the
aforementioned algorithm to insert same preemption points between each
set of batches.

Matt
 
> Cheers, Daniel
> 
> > +/*
> > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > + * points on all hardware contexts between each set of BBs. An example use case
> > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > + * BB must be submitted on each hardware context in the parallel gem context.
> > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > + */
> > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> > +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > +	__u64 flags;		/* all undefined flags must be zero */
> > +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> > +
> > +	/*
> > +	 * width (i) * num_siblings (j) in length
> > +	 * index = j + i * num_siblings
> > +	 */
> > +	struct i915_engine_class_instance engines[0];
> > +} __attribute__ ((packed));
> > +
> > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > index 7faa46cde088..64c539486ee4 100644
> > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> >  
> >  New parallel submission uAPI
> >  ============================
> > -Details to come in a following patch.
> > +The existing bonding uAPI is completely broken with GuC submission because
> > +whether a submission is a single context submit or parallel submit isn't known
> > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > +contexts in parallel with the GuC the context must be explictly registered with
> > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > +These interfaces doesn't support dynamically changing between N contexts as the
> > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > +
> > +The new parallel submission uAPI consists of 3 parts:
> > +
> > +* Export engines logical mapping
> > +* A 'set_parallel' extension to configure contexts for parallel
> > +  submission
> > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +
> > +Export engines logical mapping
> > +------------------------------
> > +Certain use cases require BBs to be placed on engine instances in logical order
> > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > +submission interface currently only supports submitting multiple contexts to
> > +engines in logical order which is a new requirement compared to execlists.
> > +Lastly, all current platforms have at most 2 instances and the logical order is
> > +the same a uABI order. This will change on platforms with more than 2 instances.
> > +
> > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > +logical instance has been returned and a new field,
> > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > +
> > +A 'set_parallel' extension to configure contexts for parallel submission
> > +------------------------------------------------------------------------
> > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > +It is setup step that should be called before using any of the contexts. See
> > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > +similar existing examples. Once a slot is configured for parallel submission the
> > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > +support GuC submission. Execlist support can be added later if needed.
> > +
> > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > +
> > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +-------------------------------------------------------------------
> > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > +the IOCTL.
> > -- 
> > 2.28.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-19 17:11       ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-19 17:11 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: intel-gfx, dri-devel, jason.ekstrand, daniel.vetter, mesa-dev,
	karl, christian.koenig

On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > Add entry fpr i915 new parallel submission uAPI plan.
> > 
> > v2:
> >  (Daniel Vetter):
> >   - Expand logical order explaination
> >   - Add dummy header
> >   - Only allow N BBs in execbuf IOCTL
> >   - Configure parallel submission per slot not per gem context
> > 
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Tony Ye <tony.ye@intel.com>
> > CC: Carl Zhang <carl.zhang@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> >  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> >  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> >  2 files changed, 196 insertions(+), 1 deletion(-)
> >  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > 
> > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > new file mode 100644
> > index 000000000000..8c64b983ccad
> > --- /dev/null
> > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > @@ -0,0 +1,144 @@
> > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > +
> > +/*
> > + * i915_context_engines_parallel_submit:
> > + *
> > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > + * the slots configuration).
> > + *
> > + * Their are two currently defined ways to control the placement of the
> > + * hardware contexts on physical engines: default behavior (no flags) and
> > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > + * future as new hardware / use cases arise. Details of how to use this
> > + * interface below above the flags.
> > + *
> > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > + * placement configuration isn't supported on the platform / submission
> > + * interface.
> > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > + * inteface.
> > + */
> > +struct i915_context_engines_parallel_submit {
> > +	struct i915_user_extension base;
> > +
> > +	__u16 engine_index;	/* slot for parallel engine */
> > +	__u16 width;		/* number of contexts per parallel engine */
> > +	__u16 num_siblings;	/* number of siblings per context */
> > +	__u16 mbz16;
> 
> Ok the big picture looks reasonable now, the flags still confuse me.
> 

Yea, it is a bit confusing.

> > +/*
> > + * Default placement behvavior (currently unsupported):
> > + *
> > + * Rather than restricting parallel submission to a single class with a
> > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > + * enables parallel submission across multiple engine classes. In this case each
> > + * context's logical engine mask indicates where that context can placed. It is
> > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > + * if one context is running CS0 no other contexts can run on CS0).
> > + *
> > + * Example 1 pseudo code:
> > + * CSX[Y] = engine class X, logical instance Y
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > + *
> > + * Results in the following valid placements:
> > + * CS0[0], CS1[0]
> > + * CS0[0], CS1[1]
> > + * CS0[1], CS1[0]
> > + * CS0[1], CS1[1]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS0[0], CS0[1]
> > + * VE[1] = CS1[0], CS1[1]
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[0], CS[2]
> > + * CS[1], CS[0]
> > + * CS[1], CS[2]
> > + * CS[2], CS[0]
> > + * CS[2], CS[1]
> > + *
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[1], CS[2]
> > + * VE[1] = CS[0], CS[1], CS[2]
> > +
> > + * This enables a use case where all engines are created equally, we don't care
> > + * where they are scheduled, we just want a certain number of resources, for
> > + * those resources to be scheduled in parallel, and possibly across multiple
> > + * engine classes.
> > + */
> 
> So I don't really get what this does compared to setting the flag below.
> Is this just about running the batchbuffers the wrong way round, i.e. if
> you have (simplest case)
> 
> width=2, num_sibglings=1, engines=CS[0], CS[1]
> 
> Then both
> CS[0], CS[1]
> and
> CS[1], CS[0]
> are possible options for running 2 batches? Iow, the backend is allowed to
> run the batchbuffers the wrong way round, which gains us nothing, since we
> assume the batches take equally long and engines interchangeable. There is
> no scheduling scenario where this additional flexibility can help.
> 
> Also we don't have flags to select the only available and then specify an
> entire pipe dream about what the non-flag mode does, without an
> implementation. What is this about?
> 
> If it's just "because bonded allowed this" then I think we should just
> unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> welp.
> 

High level the flags came out of internal discussions how this interface
should look. The default placement behavior is theoretically possible
with execlists but has no use cases. The GuC supports / current use
cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.

Argued about for months and this is where we landed. At the end of the
day I think we needed to show that this interface supports more
placement rules than what the GuC supports / current use cases to future
proof this interface.

For what is it worth it seems kinda backwards that we landed on the
default behavior not being supported in our current stack / HW.

> > +
> > +/*
> > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > + * Each context must have the same number sibling and bonds are implictly create
> > + * of the siblings.
> > + *
> > + * All of the below examples are in logical space.
> > + *
> > + * Example 1 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[2], CS[3]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[2]
> > + * VE[1] = CS[1], CS[3]
> > + *
> > + * This enables a use case where all engines are not equal and certain placement
> > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > + * case (logically contiguous placement, within a single engine class) is
> > + * supported when using GuC submission. Execlist mode could support all possible
> > + * bonding configurations but currently doesn't support this extension.
> > + */
> > +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> 
> Does this map to intel_context_set_nopreempt(), so we could implement it
> also in execlist?
>

intel_context_set_nopreempt is preempt is part of how this would be
implemented for execlists. For GuC submission there is a algorithm
between the i915 and GuC that inserts same preemption points between
each set of N batches. I believe the rules are if context 1 can
preempted the rest of the contexts (2 - N) can safely be preempted. A go
/ join algorithm, implemented with semaphores, around the batches
makes sure the i915 adheres to these rules.
 
> Also is this just an artifact of the implementation, or is this somehow
> required functionality for userspace, i.e. the workload fails if e.g. GuC
> decides to preempt all LRC of a parallel virtual engine? Of course just
> preempting one is a bit a bug (but execlist I think happily does that).
>

I think it is part of the implementation / HW limitations. Basically if
N batches are running in parallel if one of the batches gets preempted
it can hang all the other batches even if it gets restarted. Again the
idea behind this is only preempt any of these contexts between each set
of N batches. The GuC has no concept of batches only contexts hence the
aforementioned algorithm to insert same preemption points between each
set of batches.

Matt
 
> Cheers, Daniel
> 
> > +/*
> > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > + * points on all hardware contexts between each set of BBs. An example use case
> > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > + * BB must be submitted on each hardware context in the parallel gem context.
> > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > + */
> > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> > +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > +	__u64 flags;		/* all undefined flags must be zero */
> > +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> > +
> > +	/*
> > +	 * width (i) * num_siblings (j) in length
> > +	 * index = j + i * num_siblings
> > +	 */
> > +	struct i915_engine_class_instance engines[0];
> > +} __attribute__ ((packed));
> > +
> > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > index 7faa46cde088..64c539486ee4 100644
> > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> >  
> >  New parallel submission uAPI
> >  ============================
> > -Details to come in a following patch.
> > +The existing bonding uAPI is completely broken with GuC submission because
> > +whether a submission is a single context submit or parallel submit isn't known
> > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > +contexts in parallel with the GuC the context must be explictly registered with
> > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > +These interfaces doesn't support dynamically changing between N contexts as the
> > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > +
> > +The new parallel submission uAPI consists of 3 parts:
> > +
> > +* Export engines logical mapping
> > +* A 'set_parallel' extension to configure contexts for parallel
> > +  submission
> > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +
> > +Export engines logical mapping
> > +------------------------------
> > +Certain use cases require BBs to be placed on engine instances in logical order
> > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > +submission interface currently only supports submitting multiple contexts to
> > +engines in logical order which is a new requirement compared to execlists.
> > +Lastly, all current platforms have at most 2 instances and the logical order is
> > +the same a uABI order. This will change on platforms with more than 2 instances.
> > +
> > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > +logical instance has been returned and a new field,
> > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > +
> > +A 'set_parallel' extension to configure contexts for parallel submission
> > +------------------------------------------------------------------------
> > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > +It is setup step that should be called before using any of the contexts. See
> > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > +similar existing examples. Once a slot is configured for parallel submission the
> > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > +support GuC submission. Execlist support can be added later if needed.
> > +
> > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > +
> > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +-------------------------------------------------------------------
> > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > +the IOCTL.
> > -- 
> > 2.28.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* [Intel-gfx] ✗ Fi.CI.IGT: failure for GuC submission / DRM scheduler integration plan + new uAPI (rev2)
  2021-05-18 23:58 ` [Intel-gfx] " Matthew Brost
                   ` (5 preceding siblings ...)
  (?)
@ 2021-05-20  1:49 ` Patchwork
  -1 siblings, 0 replies; 54+ messages in thread
From: Patchwork @ 2021-05-20  1:49 UTC (permalink / raw)
  To: Matthew Brost; +Cc: intel-gfx


[-- Attachment #1.1: Type: text/plain, Size: 30288 bytes --]

== Series Details ==

Series: GuC submission / DRM scheduler integration plan + new uAPI (rev2)
URL   : https://patchwork.freedesktop.org/series/89840/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_10100_full -> Patchwork_20150_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_20150_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_20150_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_20150_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
    - shard-snb:          NOTRUN -> [INCOMPLETE][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb2/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html

  * igt@kms_prime@basic-crc@second-to-first:
    - shard-glk:          NOTRUN -> [FAIL][2]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@kms_prime@basic-crc@second-to-first.html

  
Known issues
------------

  Here are the changes found in Patchwork_20150_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-noreloc-purge-cache-random:
    - shard-glk:          NOTRUN -> [DMESG-FAIL][3] ([i915#3457]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@api_intel_bb@blit-noreloc-purge-cache-random.html

  * igt@api_intel_bb@intel-bb-blit-y:
    - shard-glk:          [PASS][4] -> [FAIL][5] ([i915#3471])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk6/igt@api_intel_bb@intel-bb-blit-y.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk5/igt@api_intel_bb@intel-bb-blit-y.html

  * igt@api_intel_bb@offset-control:
    - shard-snb:          NOTRUN -> [DMESG-WARN][6] ([i915#3457]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb7/igt@api_intel_bb@offset-control.html

  * igt@gem_create@create-massive:
    - shard-snb:          NOTRUN -> [DMESG-WARN][7] ([i915#3002])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb7/igt@gem_create@create-massive.html

  * igt@gem_ctx_engines@invalid-engines:
    - shard-snb:          NOTRUN -> [INCOMPLETE][8] ([i915#3457] / [i915#3468])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb5/igt@gem_ctx_engines@invalid-engines.html

  * igt@gem_ctx_persistence@legacy-engines-persistence:
    - shard-snb:          NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#1099]) +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb2/igt@gem_ctx_persistence@legacy-engines-persistence.html

  * igt@gem_ctx_shared@q-in-order:
    - shard-snb:          NOTRUN -> [SKIP][10] ([fdo#109271]) +125 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb5/igt@gem_ctx_shared@q-in-order.html

  * igt@gem_eio@unwedge-stress:
    - shard-snb:          NOTRUN -> [FAIL][11] ([i915#3354] / [i915#3457])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb5/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-apl:          NOTRUN -> [FAIL][12] ([i915#2846] / [i915#3457])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl6/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - shard-iclb:         [PASS][13] -> [FAIL][14] ([i915#2842] / [i915#3457])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb6/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_exec_fair@basic-none-solo@rcs0:
    - shard-kbl:          [PASS][15] -> [FAIL][16] ([i915#2842] / [i915#3457])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl6/igt@gem_exec_fair@basic-none-solo@rcs0.html

  * igt@gem_exec_fair@basic-none-vip@rcs0:
    - shard-iclb:         NOTRUN -> [FAIL][17] ([i915#2842] / [i915#3457])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@gem_exec_fair@basic-none-vip@rcs0.html

  * igt@gem_exec_fair@basic-pace@vcs0:
    - shard-tglb:         [PASS][18] -> [FAIL][19] ([i915#2842] / [i915#3457])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-tglb6/igt@gem_exec_fair@basic-pace@vcs0.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-tglb3/igt@gem_exec_fair@basic-pace@vcs0.html

  * igt@gem_exec_gttfill@all:
    - shard-apl:          NOTRUN -> [FAIL][20] ([i915#3491])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@gem_exec_gttfill@all.html

  * igt@gem_exec_gttfill@basic:
    - shard-glk:          [PASS][21] -> [FAIL][22] ([i915#3457] / [i915#3491])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk1/igt@gem_exec_gttfill@basic.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk6/igt@gem_exec_gttfill@basic.html

  * igt@gem_exec_schedule@preemptive-hang@rcs0:
    - shard-glk:          [PASS][23] -> [FAIL][24] ([i915#3457]) +22 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk4/igt@gem_exec_schedule@preemptive-hang@rcs0.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk1/igt@gem_exec_schedule@preemptive-hang@rcs0.html

  * igt@gem_exec_whisper@basic-queues-forked:
    - shard-glk:          [PASS][25] -> [DMESG-WARN][26] ([i915#118] / [i915#95])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk7/igt@gem_exec_whisper@basic-queues-forked.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk8/igt@gem_exec_whisper@basic-queues-forked.html

  * igt@gem_mmap_gtt@cpuset-basic-small-copy:
    - shard-snb:          NOTRUN -> [INCOMPLETE][27] ([i915#3468])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb2/igt@gem_mmap_gtt@cpuset-basic-small-copy.html

  * igt@gem_mmap_gtt@fault-concurrent-x:
    - shard-kbl:          NOTRUN -> [INCOMPLETE][28] ([i915#3468])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@gem_mmap_gtt@fault-concurrent-x.html

  * igt@gem_mmap_gtt@medium-copy-xy:
    - shard-kbl:          [PASS][29] -> [INCOMPLETE][30] ([i915#2502])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl6/igt@gem_mmap_gtt@medium-copy-xy.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl2/igt@gem_mmap_gtt@medium-copy-xy.html

  * igt@gem_ppgtt@blt-vs-render-ctxn:
    - shard-glk:          NOTRUN -> [FAIL][31] ([i915#3476])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@gem_ppgtt@blt-vs-render-ctxn.html

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
    - shard-skl:          NOTRUN -> [INCOMPLETE][32] ([i915#3468])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-iclb:         NOTRUN -> [SKIP][33] ([i915#768]) +1 similar issue
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_spin_batch@legacy@default:
    - shard-apl:          NOTRUN -> [FAIL][34] ([i915#2898] / [i915#3457]) +3 similar issues
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@gem_spin_batch@legacy@default.html

  * igt@gen3_mixed_blits:
    - shard-iclb:         NOTRUN -> [SKIP][35] ([fdo#109289])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@gen3_mixed_blits.html

  * igt@gen9_exec_parse@bb-large:
    - shard-kbl:          NOTRUN -> [FAIL][36] ([i915#3296])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@gen9_exec_parse@bb-large.html

  * igt@i915_hangman@engine-hang@vecs0:
    - shard-apl:          NOTRUN -> [DMESG-FAIL][37] ([i915#3457]) +2 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@i915_hangman@engine-hang@vecs0.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-skl:          NOTRUN -> [FAIL][38] ([i915#454])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp:
    - shard-kbl:          NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#1937])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html

  * igt@i915_pm_rpm@cursor:
    - shard-kbl:          [PASS][40] -> [DMESG-WARN][41] ([i915#3457])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl2/igt@i915_pm_rpm@cursor.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl6/igt@i915_pm_rpm@cursor.html
    - shard-glk:          [PASS][42] -> [DMESG-WARN][43] ([i915#3457])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk8/igt@i915_pm_rpm@cursor.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk1/igt@i915_pm_rpm@cursor.html

  * igt@i915_pm_rpm@cursor-dpms:
    - shard-tglb:         [PASS][44] -> [DMESG-WARN][45] ([i915#2411] / [i915#3457])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-tglb2/igt@i915_pm_rpm@cursor-dpms.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-tglb3/igt@i915_pm_rpm@cursor-dpms.html
    - shard-kbl:          NOTRUN -> [DMESG-WARN][46] ([i915#3457])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@i915_pm_rpm@cursor-dpms.html

  * igt@i915_pm_rpm@gem-mmap-type@uc:
    - shard-skl:          NOTRUN -> [DMESG-WARN][47] ([i915#1982] / [i915#3475])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@i915_pm_rpm@gem-mmap-type@uc.html
    - shard-kbl:          [PASS][48] -> [DMESG-WARN][49] ([i915#3475])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl7/igt@i915_pm_rpm@gem-mmap-type@uc.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl3/igt@i915_pm_rpm@gem-mmap-type@uc.html

  * igt@i915_pm_rpm@gem-mmap-type@wc:
    - shard-iclb:         [PASS][50] -> [DMESG-WARN][51] ([i915#3457])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-iclb8/igt@i915_pm_rpm@gem-mmap-type@wc.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb6/igt@i915_pm_rpm@gem-mmap-type@wc.html
    - shard-skl:          NOTRUN -> [DMESG-WARN][52] ([i915#3457]) +1 similar issue
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@i915_pm_rpm@gem-mmap-type@wc.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-apl:          NOTRUN -> [DMESG-WARN][53] ([i915#3457]) +3 similar issues
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@i915_pm_sseu@full-enable:
    - shard-glk:          NOTRUN -> [DMESG-WARN][54] ([i915#3457])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@i915_pm_sseu@full-enable.html

  * igt@kms_big_fb@linear-32bpp-rotate-90:
    - shard-iclb:         NOTRUN -> [SKIP][55] ([fdo#110725] / [fdo#111614])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_big_fb@linear-32bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
    - shard-iclb:         NOTRUN -> [SKIP][56] ([fdo#110723])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo:
    - shard-skl:          NOTRUN -> [SKIP][57] ([fdo#109271] / [fdo#111304]) +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_ccs@pipe-c-ccs-on-another-bo.html

  * igt@kms_chamelium@hdmi-edid-change-during-suspend:
    - shard-apl:          NOTRUN -> [SKIP][58] ([fdo#109271] / [fdo#111827]) +12 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@kms_chamelium@hdmi-edid-change-during-suspend.html

  * igt@kms_color@pipe-a-degamma:
    - shard-glk:          [PASS][59] -> [FAIL][60] ([fdo#108145] / [i915#71])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk8/igt@kms_color@pipe-a-degamma.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk5/igt@kms_color@pipe-a-degamma.html

  * igt@kms_color@pipe-c-degamma:
    - shard-iclb:         NOTRUN -> [FAIL][61] ([i915#1149])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_color@pipe-c-degamma.html

  * igt@kms_color_chamelium@pipe-a-ctm-limited-range:
    - shard-glk:          NOTRUN -> [SKIP][62] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@kms_color_chamelium@pipe-a-ctm-limited-range.html

  * igt@kms_color_chamelium@pipe-b-ctm-limited-range:
    - shard-kbl:          NOTRUN -> [SKIP][63] ([fdo#109271] / [fdo#111827]) +3 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@kms_color_chamelium@pipe-b-ctm-limited-range.html

  * igt@kms_color_chamelium@pipe-c-ctm-green-to-red:
    - shard-iclb:         NOTRUN -> [SKIP][64] ([fdo#109284] / [fdo#111827]) +1 similar issue
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_color_chamelium@pipe-c-ctm-green-to-red.html

  * igt@kms_color_chamelium@pipe-c-degamma:
    - shard-skl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [fdo#111827]) +10 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_color_chamelium@pipe-c-degamma.html

  * igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes:
    - shard-snb:          NOTRUN -> [SKIP][66] ([fdo#109271] / [fdo#111827]) +9 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb7/igt@kms_color_chamelium@pipe-invalid-ctm-matrix-sizes.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-apl:          NOTRUN -> [TIMEOUT][67] ([i915#1319]) +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen:
    - shard-apl:          NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#3457]) +18 similar issues
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen:
    - shard-iclb:         [PASS][69] -> [FAIL][70] ([i915#3457]) +1 similar issue
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb6/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
    - shard-kbl:          [PASS][71] -> [FAIL][72] ([i915#3444] / [i915#3457])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-64x21-offscreen.html

  * igt@kms_cursor_crc@pipe-a-cursor-dpms:
    - shard-skl:          NOTRUN -> [FAIL][73] ([i915#3444] / [i915#3457]) +9 similar issues
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-dpms.html

  * igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen:
    - shard-glk:          NOTRUN -> [FAIL][74] ([i915#3444] / [i915#3457]) +1 similar issue
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@kms_cursor_crc@pipe-b-cursor-128x128-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen:
    - shard-iclb:         NOTRUN -> [FAIL][75] ([i915#3457]) +2 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_cursor_crc@pipe-b-cursor-256x256-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
    - shard-snb:          NOTRUN -> [FAIL][76] ([i915#3457]) +2 similar issues
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb7/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html

  * igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen:
    - shard-skl:          NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#3457]) +19 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_cursor_crc@pipe-b-cursor-32x32-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen:
    - shard-glk:          [PASS][78] -> [FAIL][79] ([i915#3444] / [i915#3457]) +3 similar issues
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk4/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk1/igt@kms_cursor_crc@pipe-b-cursor-64x21-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding:
    - shard-apl:          NOTRUN -> [FAIL][80] ([i915#3444] / [i915#3457]) +4 similar issues
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-64x64-sliding.html

  * igt@kms_cursor_crc@pipe-c-cursor-128x128-sliding:
    - shard-kbl:          NOTRUN -> [FAIL][81] ([i915#3444] / [i915#3457]) +5 similar issues
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl2/igt@kms_cursor_crc@pipe-c-cursor-128x128-sliding.html

  * igt@kms_cursor_crc@pipe-c-cursor-64x21-random:
    - shard-snb:          NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#3457]) +20 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb7/igt@kms_cursor_crc@pipe-c-cursor-64x21-random.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x256-offscreen:
    - shard-tglb:         [PASS][83] -> [FAIL][84] ([i915#2124] / [i915#3457]) +2 similar issues
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-tglb3/igt@kms_cursor_crc@pipe-d-cursor-256x256-offscreen.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-256x256-offscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen:
    - shard-kbl:          NOTRUN -> [SKIP][85] ([fdo#109271] / [i915#3457]) +8 similar issues
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@kms_cursor_crc@pipe-d-cursor-256x256-onscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-64x21-onscreen:
    - shard-iclb:         NOTRUN -> [SKIP][86] ([fdo#109278] / [i915#3457]) +2 similar issues
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_cursor_crc@pipe-d-cursor-64x21-onscreen.html

  * igt@kms_cursor_crc@pipe-d-cursor-dpms:
    - shard-glk:          NOTRUN -> [SKIP][87] ([fdo#109271] / [i915#3457]) +5 similar issues
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@kms_cursor_crc@pipe-d-cursor-dpms.html

  * igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge:
    - shard-glk:          [PASS][88] -> [FAIL][89] ([i915#70])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk4/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk1/igt@kms_cursor_edge_walk@pipe-c-256x256-left-edge.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-iclb:         NOTRUN -> [SKIP][90] ([fdo#109274] / [fdo#109278]) +2 similar issues
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-apl:          NOTRUN -> [FAIL][91] ([i915#3457]) +8 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
    - shard-skl:          NOTRUN -> [FAIL][92] ([i915#2346] / [i915#3457])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@pipe-d-torture-bo:
    - shard-apl:          NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#533])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@kms_cursor_legacy@pipe-d-torture-bo.html

  * igt@kms_cursor_legacy@pipe-d-torture-move:
    - shard-skl:          NOTRUN -> [SKIP][94] ([fdo#109271]) +93 similar issues
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_cursor_legacy@pipe-d-torture-move.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          NOTRUN -> [INCOMPLETE][95] ([i915#155] / [i915#180] / [i915#636])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@2x-flip-vs-rmfb:
    - shard-iclb:         NOTRUN -> [SKIP][96] ([fdo#109274]) +1 similar issue
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_flip@2x-flip-vs-rmfb.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile:
    - shard-apl:          NOTRUN -> [SKIP][97] ([fdo#109271] / [i915#2642])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt:
    - shard-iclb:         NOTRUN -> [SKIP][98] ([fdo#109280]) +7 similar issues
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite:
    - shard-apl:          NOTRUN -> [SKIP][99] ([fdo#109271]) +104 similar issues
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
    - shard-kbl:          NOTRUN -> [SKIP][100] ([fdo#109271]) +51 similar issues
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          [PASS][101] -> [DMESG-WARN][102] ([i915#180]) +1 similar issue
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-kbl6/igt@kms_hdr@bpc-switch-suspend.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl1/igt@kms_hdr@bpc-switch-suspend.html
    - shard-skl:          NOTRUN -> [FAIL][103] ([i915#1188])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
    - shard-kbl:          NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#533])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-basic:
    - shard-glk:          NOTRUN -> [FAIL][105] ([fdo#108145] / [i915#265])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-apl:          NOTRUN -> [FAIL][106] ([fdo#108145] / [i915#265]) +2 similar issues
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html
    - shard-skl:          NOTRUN -> [FAIL][107] ([fdo#108145] / [i915#265]) +1 similar issue
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
    - shard-skl:          NOTRUN -> [FAIL][108] ([i915#265])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
    - shard-kbl:          NOTRUN -> [FAIL][109] ([fdo#108145] / [i915#265])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html

  * igt@kms_plane_alpha_blend@pipe-d-alpha-7efc:
    - shard-iclb:         NOTRUN -> [SKIP][110] ([fdo#109278]) +1 similar issue
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_plane_alpha_blend@pipe-d-alpha-7efc.html

  * igt@kms_plane_cursor@pipe-a-primary-size-128:
    - shard-glk:          NOTRUN -> [FAIL][111] ([i915#2657])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@kms_plane_cursor@pipe-a-primary-size-128.html

  * igt@kms_plane_cursor@pipe-a-primary-size-256:
    - shard-iclb:         NOTRUN -> [FAIL][112] ([i915#2657])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_plane_cursor@pipe-a-primary-size-256.html

  * igt@kms_plane_cursor@pipe-a-viewport-size-128:
    - shard-snb:          NOTRUN -> [FAIL][113] ([i915#2657])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-snb2/igt@kms_plane_cursor@pipe-a-viewport-size-128.html

  * igt@kms_plane_cursor@pipe-b-overlay-size-64:
    - shard-skl:          NOTRUN -> [FAIL][114] ([i915#2657])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_plane_cursor@pipe-b-overlay-size-64.html

  * igt@kms_plane_cursor@pipe-b-viewport-size-256:
    - shard-kbl:          NOTRUN -> [FAIL][115] ([i915#2657])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@kms_plane_cursor@pipe-b-viewport-size-256.html

  * igt@kms_plane_cursor@pipe-c-primary-size-64:
    - shard-iclb:         NOTRUN -> [FAIL][116] ([i915#2657] / [i915#3457])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_plane_cursor@pipe-c-primary-size-64.html

  * igt@kms_plane_cursor@pipe-c-viewport-size-128:
    - shard-skl:          NOTRUN -> [FAIL][117] ([i915#2657] / [i915#3457]) +2 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_plane_cursor@pipe-c-viewport-size-128.html

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
    - shard-glk:          [PASS][118] -> [FAIL][119] ([i915#1779])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk5/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk7/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2:
    - shard-apl:          NOTRUN -> [SKIP][120] ([fdo#109271] / [i915#658]) +1 similar issue
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-apl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-2.html

  * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5:
    - shard-kbl:          NOTRUN -> [SKIP][121] ([fdo#109271] / [i915#658])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area-5.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1:
    - shard-skl:          NOTRUN -> [SKIP][122] ([fdo#109271] / [i915#658]) +1 similar issue
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-skl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-1.html

  * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3:
    - shard-glk:          NOTRUN -> [SKIP][123] ([fdo#109271] / [i915#658])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-3.html

  * igt@kms_psr@psr2_primary_mmap_gtt:
    - shard-glk:          NOTRUN -> [SKIP][124] ([fdo#109271]) +26 similar issues
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@kms_psr@psr2_primary_mmap_gtt.html

  * igt@kms_vrr@flip-dpms:
    - shard-iclb:         NOTRUN -> [SKIP][125] ([fdo#109502])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-iclb1/igt@kms_vrr@flip-dpms.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-kbl:          NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#2437])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-kbl7/igt@kms_writeback@writeback-fb-id.html

  * igt@perf_pmu@most-busy-idle-check-all@rcs0:
    - shard-glk:          NOTRUN -> [FAIL][127] ([i915#3457]) +13 similar issues
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@perf_pmu@most-busy-idle-check-all@rcs0.html

  * igt@perf_pmu@most-busy-idle-check-all@vecs0:
    - shard-glk:          NOTRUN -> [FAIL][128] ([i915#2624] / [i915#3457])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/shard-glk2/igt@perf_pmu@most-busy-idle-check-all@vecs0.html

  * igt@perf_pmu@render-node-busy-idle@bcs0:
    - shard-glk:          [PASS][129] -> [WARN][130] ([i915#3457])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_10100/shard-glk2/igt@perf_pmu@render-node-busy-idle@bcs0.html
   [130]: https://in

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20150/index.html

[-- Attachment #1.2: Type: text/html, Size: 33871 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-19 17:11       ` Matthew Brost
@ 2021-05-20  9:54         ` Daniel Vetter
  -1 siblings, 0 replies; 54+ messages in thread
From: Daniel Vetter @ 2021-05-20  9:54 UTC (permalink / raw)
  To: Matthew Brost
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Daniel Vetter, Mesa Dev,
	karl, Christian König

On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
>
> On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > Add entry fpr i915 new parallel submission uAPI plan.
> > >
> > > v2:
> > >  (Daniel Vetter):
> > >   - Expand logical order explaination
> > >   - Add dummy header
> > >   - Only allow N BBs in execbuf IOCTL
> > >   - Configure parallel submission per slot not per gem context
> > >
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Cc: Tony Ye <tony.ye@intel.com>
> > > CC: Carl Zhang <carl.zhang@intel.com>
> > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > ---
> > >  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > >  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > >  2 files changed, 196 insertions(+), 1 deletion(-)
> > >  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > >
> > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > new file mode 100644
> > > index 000000000000..8c64b983ccad
> > > --- /dev/null
> > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > @@ -0,0 +1,144 @@
> > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > +
> > > +/*
> > > + * i915_context_engines_parallel_submit:
> > > + *
> > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > + * the slots configuration).
> > > + *
> > > + * Their are two currently defined ways to control the placement of the
> > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > + * future as new hardware / use cases arise. Details of how to use this
> > > + * interface below above the flags.
> > > + *
> > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > + * placement configuration isn't supported on the platform / submission
> > > + * interface.
> > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > + * inteface.
> > > + */
> > > +struct i915_context_engines_parallel_submit {
> > > +   struct i915_user_extension base;
> > > +
> > > +   __u16 engine_index;     /* slot for parallel engine */
> > > +   __u16 width;            /* number of contexts per parallel engine */
> > > +   __u16 num_siblings;     /* number of siblings per context */
> > > +   __u16 mbz16;
> >
> > Ok the big picture looks reasonable now, the flags still confuse me.
> >
>
> Yea, it is a bit confusing.
>
> > > +/*
> > > + * Default placement behvavior (currently unsupported):
> > > + *
> > > + * Rather than restricting parallel submission to a single class with a
> > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > + * enables parallel submission across multiple engine classes. In this case each
> > > + * context's logical engine mask indicates where that context can placed. It is
> > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > + * if one context is running CS0 no other contexts can run on CS0).
> > > + *
> > > + * Example 1 pseudo code:
> > > + * CSX[Y] = engine class X, logical instance Y
> > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > + * set_engines(INVALID)
> > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > + *
> > > + * Results in the following valid placements:
> > > + * CS0[0], CS1[0]
> > > + * CS0[0], CS1[1]
> > > + * CS0[1], CS1[0]
> > > + * CS0[1], CS1[1]
> > > + *
> > > + * This can also be though of as 2 virtual engines:
> > > + * VE[0] = CS0[0], CS0[1]
> > > + * VE[1] = CS1[0], CS1[1]
> > > + *
> > > + * Example 2 pseudo code:
> > > + * CS[X] = generic engine of same class, logical instance X
> > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > + * set_engines(INVALID)
> > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > + *
> > > + * Results in the following valid placements:
> > > + * CS[0], CS[1]
> > > + * CS[0], CS[2]
> > > + * CS[1], CS[0]
> > > + * CS[1], CS[2]
> > > + * CS[2], CS[0]
> > > + * CS[2], CS[1]
> > > + *
> > > + *
> > > + * This can also be though of as 2 virtual engines:
> > > + * VE[0] = CS[0], CS[1], CS[2]
> > > + * VE[1] = CS[0], CS[1], CS[2]
> > > +
> > > + * This enables a use case where all engines are created equally, we don't care
> > > + * where they are scheduled, we just want a certain number of resources, for
> > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > + * engine classes.
> > > + */
> >
> > So I don't really get what this does compared to setting the flag below.
> > Is this just about running the batchbuffers the wrong way round, i.e. if
> > you have (simplest case)
> >
> > width=2, num_sibglings=1, engines=CS[0], CS[1]
> >
> > Then both
> > CS[0], CS[1]
> > and
> > CS[1], CS[0]
> > are possible options for running 2 batches? Iow, the backend is allowed to
> > run the batchbuffers the wrong way round, which gains us nothing, since we
> > assume the batches take equally long and engines interchangeable. There is
> > no scheduling scenario where this additional flexibility can help.
> >
> > Also we don't have flags to select the only available and then specify an
> > entire pipe dream about what the non-flag mode does, without an
> > implementation. What is this about?
> >
> > If it's just "because bonded allowed this" then I think we should just
> > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > welp.
> >
>
> High level the flags came out of internal discussions how this interface
> should look. The default placement behavior is theoretically possible
> with execlists but has no use cases. The GuC supports / current use
> cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
>
> Argued about for months and this is where we landed. At the end of the
> day I think we needed to show that this interface supports more
> placement rules than what the GuC supports / current use cases to future
> proof this interface.
>
> For what is it worth it seems kinda backwards that we landed on the
> default behavior not being supported in our current stack / HW.

Yeah I think that should be inverted, doesn't make sense.

What I still don't get (and I've read Tvrtko's reply with the example)
is what exactly is the difference between implicit and not implicit
mode? Can you do a single example where the only difference is whether
this flag is set, and then explain with that what are the actual
differences in scheduling options that the backend is allowed to pick
for the set of N patches?

I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(

> > > +
> > > +/*
> > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > + * Each context must have the same number sibling and bonds are implictly create
> > > + * of the siblings.
> > > + *
> > > + * All of the below examples are in logical space.
> > > + *
> > > + * Example 1 pseudo code:
> > > + * CS[X] = generic engine of same class, logical instance X
> > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > + * set_engines(INVALID)
> > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > + *         engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > + *
> > > + * Results in the following valid placements:
> > > + * CS[0], CS[1]
> > > + *
> > > + * Example 2 pseudo code:
> > > + * CS[X] = generic engine of same class, logical instance X
> > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > + * set_engines(INVALID)
> > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > + *         engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > + *
> > > + * Results in the following valid placements:
> > > + * CS[0], CS[1]
> > > + * CS[2], CS[3]
> > > + *
> > > + * This can also be though of as 2 virtual engines:
> > > + * VE[0] = CS[0], CS[2]
> > > + * VE[1] = CS[1], CS[3]
> > > + *
> > > + * This enables a use case where all engines are not equal and certain placement
> > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > + * case (logically contiguous placement, within a single engine class) is
> > > + * supported when using GuC submission. Execlist mode could support all possible
> > > + * bonding configurations but currently doesn't support this extension.
> > > + */
> > > +#define I915_PARALLEL_IMPLICT_BONDS                        (1<<0)
> >
> > Does this map to intel_context_set_nopreempt(), so we could implement it
> > also in execlist?
> >
>
> intel_context_set_nopreempt is preempt is part of how this would be
> implemented for execlists. For GuC submission there is a algorithm
> between the i915 and GuC that inserts same preemption points between
> each set of N batches. I believe the rules are if context 1 can
> preempted the rest of the contexts (2 - N) can safely be preempted. A go
> / join algorithm, implemented with semaphores, around the batches
> makes sure the i915 adheres to these rules.
>
> > Also is this just an artifact of the implementation, or is this somehow
> > required functionality for userspace, i.e. the workload fails if e.g. GuC
> > decides to preempt all LRC of a parallel virtual engine? Of course just
> > preempting one is a bit a bug (but execlist I think happily does that).
> >
>
> I think it is part of the implementation / HW limitations. Basically if
> N batches are running in parallel if one of the batches gets preempted
> it can hang all the other batches even if it gets restarted. Again the
> idea behind this is only preempt any of these contexts between each set
> of N batches. The GuC has no concept of batches only contexts hence the
> aforementioned algorithm to insert same preemption points between each
> set of batches.

Well backend preempting one but not the other is a bug. I don't think
we need to talk about bugs :-)

Now wrt a preempt mode in context creation, I think that makes sense.
I'm just wondering whether this is correct here in the parallel
submission (and why), or is it just an implementation artifact
(current backends are buggy if we'd allow them to preempt) or what's
going on.

If this is just a case of "this is how current backends work,
userspace doesn't actually care whether we allow preempt or not" then
I think we should just document the behavior and that's it. Adding
uapi for an option for which there's not even an implementation isn't
great.

But if we can actually choose, and userspace wants to, then I'm all
fine with this. And we can always move this to a more generic place if
other engines need preempt control later on too.

Cheers, Daniel


> Matt
>
> > Cheers, Daniel
> >
> > > +/*
> > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > + * points on all hardware contexts between each set of BBs. An example use case
> > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > + */
> > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH         (1<<1)
> > > +#define __I915_PARALLEL_UNKNOWN_FLAGS      (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > +   __u64 flags;            /* all undefined flags must be zero */
> > > +   __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > +
> > > +   /*
> > > +    * width (i) * num_siblings (j) in length
> > > +    * index = j + i * num_siblings
> > > +    */
> > > +   struct i915_engine_class_instance engines[0];
> > > +} __attribute__ ((packed));
> > > +
> > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > index 7faa46cde088..64c539486ee4 100644
> > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> > >
> > >  New parallel submission uAPI
> > >  ============================
> > > -Details to come in a following patch.
> > > +The existing bonding uAPI is completely broken with GuC submission because
> > > +whether a submission is a single context submit or parallel submit isn't known
> > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > +contexts in parallel with the GuC the context must be explictly registered with
> > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > +
> > > +The new parallel submission uAPI consists of 3 parts:
> > > +
> > > +* Export engines logical mapping
> > > +* A 'set_parallel' extension to configure contexts for parallel
> > > +  submission
> > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > +
> > > +Export engines logical mapping
> > > +------------------------------
> > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > +submission interface currently only supports submitting multiple contexts to
> > > +engines in logical order which is a new requirement compared to execlists.
> > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > +
> > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > +logical instance has been returned and a new field,
> > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > +
> > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > +------------------------------------------------------------------------
> > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > +It is setup step that should be called before using any of the contexts. See
> > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > +similar existing examples. Once a slot is configured for parallel submission the
> > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > +support GuC submission. Execlist support can be added later if needed.
> > > +
> > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > +
> > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > +-------------------------------------------------------------------
> > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > +the IOCTL.
> > > --
> > > 2.28.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch



--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-20  9:54         ` Daniel Vetter
  0 siblings, 0 replies; 54+ messages in thread
From: Daniel Vetter @ 2021-05-20  9:54 UTC (permalink / raw)
  To: Matthew Brost
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Daniel Vetter, Mesa Dev,
	karl, Christian König

On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
>
> On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > Add entry fpr i915 new parallel submission uAPI plan.
> > >
> > > v2:
> > >  (Daniel Vetter):
> > >   - Expand logical order explaination
> > >   - Add dummy header
> > >   - Only allow N BBs in execbuf IOCTL
> > >   - Configure parallel submission per slot not per gem context
> > >
> > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Cc: Tony Ye <tony.ye@intel.com>
> > > CC: Carl Zhang <carl.zhang@intel.com>
> > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > ---
> > >  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > >  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > >  2 files changed, 196 insertions(+), 1 deletion(-)
> > >  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > >
> > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > new file mode 100644
> > > index 000000000000..8c64b983ccad
> > > --- /dev/null
> > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > @@ -0,0 +1,144 @@
> > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > +
> > > +/*
> > > + * i915_context_engines_parallel_submit:
> > > + *
> > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > + * the slots configuration).
> > > + *
> > > + * Their are two currently defined ways to control the placement of the
> > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > + * future as new hardware / use cases arise. Details of how to use this
> > > + * interface below above the flags.
> > > + *
> > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > + * placement configuration isn't supported on the platform / submission
> > > + * interface.
> > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > + * inteface.
> > > + */
> > > +struct i915_context_engines_parallel_submit {
> > > +   struct i915_user_extension base;
> > > +
> > > +   __u16 engine_index;     /* slot for parallel engine */
> > > +   __u16 width;            /* number of contexts per parallel engine */
> > > +   __u16 num_siblings;     /* number of siblings per context */
> > > +   __u16 mbz16;
> >
> > Ok the big picture looks reasonable now, the flags still confuse me.
> >
>
> Yea, it is a bit confusing.
>
> > > +/*
> > > + * Default placement behvavior (currently unsupported):
> > > + *
> > > + * Rather than restricting parallel submission to a single class with a
> > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > + * enables parallel submission across multiple engine classes. In this case each
> > > + * context's logical engine mask indicates where that context can placed. It is
> > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > + * if one context is running CS0 no other contexts can run on CS0).
> > > + *
> > > + * Example 1 pseudo code:
> > > + * CSX[Y] = engine class X, logical instance Y
> > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > + * set_engines(INVALID)
> > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > + *
> > > + * Results in the following valid placements:
> > > + * CS0[0], CS1[0]
> > > + * CS0[0], CS1[1]
> > > + * CS0[1], CS1[0]
> > > + * CS0[1], CS1[1]
> > > + *
> > > + * This can also be though of as 2 virtual engines:
> > > + * VE[0] = CS0[0], CS0[1]
> > > + * VE[1] = CS1[0], CS1[1]
> > > + *
> > > + * Example 2 pseudo code:
> > > + * CS[X] = generic engine of same class, logical instance X
> > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > + * set_engines(INVALID)
> > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > + *
> > > + * Results in the following valid placements:
> > > + * CS[0], CS[1]
> > > + * CS[0], CS[2]
> > > + * CS[1], CS[0]
> > > + * CS[1], CS[2]
> > > + * CS[2], CS[0]
> > > + * CS[2], CS[1]
> > > + *
> > > + *
> > > + * This can also be though of as 2 virtual engines:
> > > + * VE[0] = CS[0], CS[1], CS[2]
> > > + * VE[1] = CS[0], CS[1], CS[2]
> > > +
> > > + * This enables a use case where all engines are created equally, we don't care
> > > + * where they are scheduled, we just want a certain number of resources, for
> > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > + * engine classes.
> > > + */
> >
> > So I don't really get what this does compared to setting the flag below.
> > Is this just about running the batchbuffers the wrong way round, i.e. if
> > you have (simplest case)
> >
> > width=2, num_sibglings=1, engines=CS[0], CS[1]
> >
> > Then both
> > CS[0], CS[1]
> > and
> > CS[1], CS[0]
> > are possible options for running 2 batches? Iow, the backend is allowed to
> > run the batchbuffers the wrong way round, which gains us nothing, since we
> > assume the batches take equally long and engines interchangeable. There is
> > no scheduling scenario where this additional flexibility can help.
> >
> > Also we don't have flags to select the only available and then specify an
> > entire pipe dream about what the non-flag mode does, without an
> > implementation. What is this about?
> >
> > If it's just "because bonded allowed this" then I think we should just
> > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > welp.
> >
>
> High level the flags came out of internal discussions how this interface
> should look. The default placement behavior is theoretically possible
> with execlists but has no use cases. The GuC supports / current use
> cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
>
> Argued about for months and this is where we landed. At the end of the
> day I think we needed to show that this interface supports more
> placement rules than what the GuC supports / current use cases to future
> proof this interface.
>
> For what is it worth it seems kinda backwards that we landed on the
> default behavior not being supported in our current stack / HW.

Yeah I think that should be inverted, doesn't make sense.

What I still don't get (and I've read Tvrtko's reply with the example)
is what exactly is the difference between implicit and not implicit
mode? Can you do a single example where the only difference is whether
this flag is set, and then explain with that what are the actual
differences in scheduling options that the backend is allowed to pick
for the set of N patches?

I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(

> > > +
> > > +/*
> > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > + * Each context must have the same number sibling and bonds are implictly create
> > > + * of the siblings.
> > > + *
> > > + * All of the below examples are in logical space.
> > > + *
> > > + * Example 1 pseudo code:
> > > + * CS[X] = generic engine of same class, logical instance X
> > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > + * set_engines(INVALID)
> > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > + *         engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > + *
> > > + * Results in the following valid placements:
> > > + * CS[0], CS[1]
> > > + *
> > > + * Example 2 pseudo code:
> > > + * CS[X] = generic engine of same class, logical instance X
> > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > + * set_engines(INVALID)
> > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > + *         engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > + *
> > > + * Results in the following valid placements:
> > > + * CS[0], CS[1]
> > > + * CS[2], CS[3]
> > > + *
> > > + * This can also be though of as 2 virtual engines:
> > > + * VE[0] = CS[0], CS[2]
> > > + * VE[1] = CS[1], CS[3]
> > > + *
> > > + * This enables a use case where all engines are not equal and certain placement
> > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > + * case (logically contiguous placement, within a single engine class) is
> > > + * supported when using GuC submission. Execlist mode could support all possible
> > > + * bonding configurations but currently doesn't support this extension.
> > > + */
> > > +#define I915_PARALLEL_IMPLICT_BONDS                        (1<<0)
> >
> > Does this map to intel_context_set_nopreempt(), so we could implement it
> > also in execlist?
> >
>
> intel_context_set_nopreempt is preempt is part of how this would be
> implemented for execlists. For GuC submission there is a algorithm
> between the i915 and GuC that inserts same preemption points between
> each set of N batches. I believe the rules are if context 1 can
> preempted the rest of the contexts (2 - N) can safely be preempted. A go
> / join algorithm, implemented with semaphores, around the batches
> makes sure the i915 adheres to these rules.
>
> > Also is this just an artifact of the implementation, or is this somehow
> > required functionality for userspace, i.e. the workload fails if e.g. GuC
> > decides to preempt all LRC of a parallel virtual engine? Of course just
> > preempting one is a bit a bug (but execlist I think happily does that).
> >
>
> I think it is part of the implementation / HW limitations. Basically if
> N batches are running in parallel if one of the batches gets preempted
> it can hang all the other batches even if it gets restarted. Again the
> idea behind this is only preempt any of these contexts between each set
> of N batches. The GuC has no concept of batches only contexts hence the
> aforementioned algorithm to insert same preemption points between each
> set of batches.

Well backend preempting one but not the other is a bug. I don't think
we need to talk about bugs :-)

Now wrt a preempt mode in context creation, I think that makes sense.
I'm just wondering whether this is correct here in the parallel
submission (and why), or is it just an implementation artifact
(current backends are buggy if we'd allow them to preempt) or what's
going on.

If this is just a case of "this is how current backends work,
userspace doesn't actually care whether we allow preempt or not" then
I think we should just document the behavior and that's it. Adding
uapi for an option for which there's not even an implementation isn't
great.

But if we can actually choose, and userspace wants to, then I'm all
fine with this. And we can always move this to a more generic place if
other engines need preempt control later on too.

Cheers, Daniel


> Matt
>
> > Cheers, Daniel
> >
> > > +/*
> > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > + * points on all hardware contexts between each set of BBs. An example use case
> > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > + */
> > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH         (1<<1)
> > > +#define __I915_PARALLEL_UNKNOWN_FLAGS      (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > +   __u64 flags;            /* all undefined flags must be zero */
> > > +   __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > +
> > > +   /*
> > > +    * width (i) * num_siblings (j) in length
> > > +    * index = j + i * num_siblings
> > > +    */
> > > +   struct i915_engine_class_instance engines[0];
> > > +} __attribute__ ((packed));
> > > +
> > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > index 7faa46cde088..64c539486ee4 100644
> > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> > >
> > >  New parallel submission uAPI
> > >  ============================
> > > -Details to come in a following patch.
> > > +The existing bonding uAPI is completely broken with GuC submission because
> > > +whether a submission is a single context submit or parallel submit isn't known
> > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > +contexts in parallel with the GuC the context must be explictly registered with
> > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > +
> > > +The new parallel submission uAPI consists of 3 parts:
> > > +
> > > +* Export engines logical mapping
> > > +* A 'set_parallel' extension to configure contexts for parallel
> > > +  submission
> > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > +
> > > +Export engines logical mapping
> > > +------------------------------
> > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > +submission interface currently only supports submitting multiple contexts to
> > > +engines in logical order which is a new requirement compared to execlists.
> > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > +
> > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > +logical instance has been returned and a new field,
> > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > +
> > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > +------------------------------------------------------------------------
> > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > +It is setup step that should be called before using any of the contexts. See
> > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > +similar existing examples. Once a slot is configured for parallel submission the
> > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > +support GuC submission. Execlist support can be added later if needed.
> > > +
> > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > +
> > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > +-------------------------------------------------------------------
> > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > +the IOCTL.
> > > --
> > > 2.28.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch



--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-20  9:54         ` Daniel Vetter
@ 2021-05-20 10:57           ` Tvrtko Ursulin
  -1 siblings, 0 replies; 54+ messages in thread
From: Tvrtko Ursulin @ 2021-05-20 10:57 UTC (permalink / raw)
  To: Daniel Vetter, Matthew Brost
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Mesa Dev, Daniel Vetter,
	karl, Christian König


On 20/05/2021 10:54, Daniel Vetter wrote:
> On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
>>
>> On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
>>> On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
>>>> Add entry fpr i915 new parallel submission uAPI plan.
>>>>
>>>> v2:
>>>>   (Daniel Vetter):
>>>>    - Expand logical order explaination
>>>>    - Add dummy header
>>>>    - Only allow N BBs in execbuf IOCTL
>>>>    - Configure parallel submission per slot not per gem context
>>>>
>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> Cc: Tony Ye <tony.ye@intel.com>
>>>> CC: Carl Zhang <carl.zhang@intel.com>
>>>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>>>> Cc: Jason Ekstrand <jason@jlekstrand.net>
>>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>>> ---
>>>>   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>>>>   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>>>>   2 files changed, 196 insertions(+), 1 deletion(-)
>>>>   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>
>>>> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>> new file mode 100644
>>>> index 000000000000..8c64b983ccad
>>>> --- /dev/null
>>>> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>> @@ -0,0 +1,144 @@
>>>> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
>>>> +
>>>> +/*
>>>> + * i915_context_engines_parallel_submit:
>>>> + *
>>>> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
>>>> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
>>>> + * hardware contexts are created internally in the i915 run these BBs. Once a
>>>> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
>>>> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
>>>> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
>>>> + * the slots configuration).
>>>> + *
>>>> + * Their are two currently defined ways to control the placement of the
>>>> + * hardware contexts on physical engines: default behavior (no flags) and
>>>> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
>>>> + * future as new hardware / use cases arise. Details of how to use this
>>>> + * interface below above the flags.
>>>> + *
>>>> + * Returns -EINVAL if hardware context placement configuration invalid or if the
>>>> + * placement configuration isn't supported on the platform / submission
>>>> + * interface.
>>>> + * Returns -ENODEV if extension isn't supported on the platform / submission
>>>> + * inteface.
>>>> + */
>>>> +struct i915_context_engines_parallel_submit {
>>>> +   struct i915_user_extension base;
>>>> +
>>>> +   __u16 engine_index;     /* slot for parallel engine */
>>>> +   __u16 width;            /* number of contexts per parallel engine */
>>>> +   __u16 num_siblings;     /* number of siblings per context */
>>>> +   __u16 mbz16;
>>>
>>> Ok the big picture looks reasonable now, the flags still confuse me.
>>>
>>
>> Yea, it is a bit confusing.
>>
>>>> +/*
>>>> + * Default placement behvavior (currently unsupported):
>>>> + *
>>>> + * Rather than restricting parallel submission to a single class with a
>>>> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
>>>> + * enables parallel submission across multiple engine classes. In this case each
>>>> + * context's logical engine mask indicates where that context can placed. It is
>>>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>>>> + * if one context is running CS0 no other contexts can run on CS0).
>>>> + *
>>>> + * Example 1 pseudo code:
>>>> + * CSX[Y] = engine class X, logical instance Y
>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>> + * set_engines(INVALID)
>>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>>> + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
>>>> + *
>>>> + * Results in the following valid placements:
>>>> + * CS0[0], CS1[0]
>>>> + * CS0[0], CS1[1]
>>>> + * CS0[1], CS1[0]
>>>> + * CS0[1], CS1[1]
>>>> + *
>>>> + * This can also be though of as 2 virtual engines:
>>>> + * VE[0] = CS0[0], CS0[1]
>>>> + * VE[1] = CS1[0], CS1[1]
>>>> + *
>>>> + * Example 2 pseudo code:
>>>> + * CS[X] = generic engine of same class, logical instance X
>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>> + * set_engines(INVALID)
>>>> + * set_parallel(engine_index=0, width=2, num_siblings=3,
>>>> + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
>>>> + *
>>>> + * Results in the following valid placements:
>>>> + * CS[0], CS[1]
>>>> + * CS[0], CS[2]
>>>> + * CS[1], CS[0]
>>>> + * CS[1], CS[2]
>>>> + * CS[2], CS[0]
>>>> + * CS[2], CS[1]
>>>> + *
>>>> + *
>>>> + * This can also be though of as 2 virtual engines:
>>>> + * VE[0] = CS[0], CS[1], CS[2]
>>>> + * VE[1] = CS[0], CS[1], CS[2]
>>>> +
>>>> + * This enables a use case where all engines are created equally, we don't care
>>>> + * where they are scheduled, we just want a certain number of resources, for
>>>> + * those resources to be scheduled in parallel, and possibly across multiple
>>>> + * engine classes.
>>>> + */
>>>
>>> So I don't really get what this does compared to setting the flag below.
>>> Is this just about running the batchbuffers the wrong way round, i.e. if
>>> you have (simplest case)
>>>
>>> width=2, num_sibglings=1, engines=CS[0], CS[1]
>>>
>>> Then both
>>> CS[0], CS[1]
>>> and
>>> CS[1], CS[0]
>>> are possible options for running 2 batches? Iow, the backend is allowed to
>>> run the batchbuffers the wrong way round, which gains us nothing, since we
>>> assume the batches take equally long and engines interchangeable. There is
>>> no scheduling scenario where this additional flexibility can help.
>>>
>>> Also we don't have flags to select the only available and then specify an
>>> entire pipe dream about what the non-flag mode does, without an
>>> implementation. What is this about?
>>>
>>> If it's just "because bonded allowed this" then I think we should just
>>> unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
>>> welp.
>>>
>>
>> High level the flags came out of internal discussions how this interface
>> should look. The default placement behavior is theoretically possible
>> with execlists but has no use cases. The GuC supports / current use
>> cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
>>
>> Argued about for months and this is where we landed. At the end of the
>> day I think we needed to show that this interface supports more
>> placement rules than what the GuC supports / current use cases to future
>> proof this interface.
>>
>> For what is it worth it seems kinda backwards that we landed on the
>> default behavior not being supported in our current stack / HW.
> 
> Yeah I think that should be inverted, doesn't make sense.
> 
> What I still don't get (and I've read Tvrtko's reply with the example)
> is what exactly is the difference between implicit and not implicit
> mode? Can you do a single example where the only difference is whether
> this flag is set, and then explain with that what are the actual
> differences in scheduling options that the backend is allowed to pick
> for the set of N patches?
> 
> I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(

2-wide compute context:

  .engine_map([-1, -1])
  .load_balance(0: [cs0, cs1, cs2, cs3]) // place virtual engine at slot 0
  .load_balance(1: [cs0, cs1, cs2, cs3])
  .set_parallel()

This tells the scheduler any two of the four possible engines can be used. cs0 + cs3 is fine, cs3 + cs1 also, ... any. Only implicit rule is they have to be different and that works for all.

2-wide "implicit bonds mode" aka media fixed function limitation:

  .engine_map([-1, -1])
  .load_balance(0: [cs0, cs2])
  .load_balance(1: [cs1, cs3])
  .set_parallel(flags = implicit_bond)

Think of implicit flag creating a "link" between vertical columns in each virtual engine slot. So valid pairs end up cs0 + cs1 and cs2 + cs3 only.

You can also think of the implicit flag as a shortcut to avoid specifying bonds via the existing extension. In which case context setup would be written along the lines of:

  .engine_map([-1, -1])
  .load_balance(0: [cs0, cs2])
  .load_balance(1: [cs1, cs3])
  .bond(1: master = cs0, bond = [cs1])
  .bond(1: master = cs2, bond = [cs3])
  .set_parallel()

So the implicit flag is just a shortcut to avoid typing the bonds. Not really needed as explained in my previous reply.

This was at least the "old" set_parallel. I see this latest RFC changed things a bit which I don't really follow yet.

It's not perfect but needs to add very little (just one context extension, on top of multi batch execbuf which is needed anyways), doesn't need to deprecate anything, didn't require rewrites of the UMD, and it all works today and in the future.

I did not really like this new uapi for all the reasons I listed already, but as not many people were seeing the advantage of not churning on the uapi, if we are churning already I did suggests a different idea. I mean if we are churning we might as well go full in. So that proposal, which didn't get any traction, was along the lines of:

  .engine_map([-1])
  .load_balance_wide(0: width=2, engines=[[cs0, cs2], [cs1, cs3]])

This would create an explicit wide virtual engine which should work for GuC fine I think. For execlists it may require a bit of extra glue but I don't think too much.

Advantage is there is one engine in the map now and it is N-wide by definition.

Since no one did bite on that idea back then, I didn't really pursue is to see if it works for all use cases. But I think it should even if it probably requires further thinking to be sure.

If we apply it to compute use case..

  .engine_map([-1])
  .load_balance_wide(0: width=2, engines=[[cs0, cs1, cs2, cs3], [cs0, cs1, cs2, cs3]])

This means the only implicit wart in there is that cs0 + cs0 obviously shouldn't be picked. But that should be fine both for execlists and hopefully for the GuC.

Regards,

Tvrtko

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-20 10:57           ` Tvrtko Ursulin
  0 siblings, 0 replies; 54+ messages in thread
From: Tvrtko Ursulin @ 2021-05-20 10:57 UTC (permalink / raw)
  To: Daniel Vetter, Matthew Brost
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Mesa Dev, Daniel Vetter,
	karl, Christian König


On 20/05/2021 10:54, Daniel Vetter wrote:
> On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
>>
>> On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
>>> On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
>>>> Add entry fpr i915 new parallel submission uAPI plan.
>>>>
>>>> v2:
>>>>   (Daniel Vetter):
>>>>    - Expand logical order explaination
>>>>    - Add dummy header
>>>>    - Only allow N BBs in execbuf IOCTL
>>>>    - Configure parallel submission per slot not per gem context
>>>>
>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> Cc: Tony Ye <tony.ye@intel.com>
>>>> CC: Carl Zhang <carl.zhang@intel.com>
>>>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>>>> Cc: Jason Ekstrand <jason@jlekstrand.net>
>>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>>> ---
>>>>   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>>>>   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>>>>   2 files changed, 196 insertions(+), 1 deletion(-)
>>>>   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>
>>>> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>> new file mode 100644
>>>> index 000000000000..8c64b983ccad
>>>> --- /dev/null
>>>> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>> @@ -0,0 +1,144 @@
>>>> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
>>>> +
>>>> +/*
>>>> + * i915_context_engines_parallel_submit:
>>>> + *
>>>> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
>>>> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
>>>> + * hardware contexts are created internally in the i915 run these BBs. Once a
>>>> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
>>>> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
>>>> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
>>>> + * the slots configuration).
>>>> + *
>>>> + * Their are two currently defined ways to control the placement of the
>>>> + * hardware contexts on physical engines: default behavior (no flags) and
>>>> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
>>>> + * future as new hardware / use cases arise. Details of how to use this
>>>> + * interface below above the flags.
>>>> + *
>>>> + * Returns -EINVAL if hardware context placement configuration invalid or if the
>>>> + * placement configuration isn't supported on the platform / submission
>>>> + * interface.
>>>> + * Returns -ENODEV if extension isn't supported on the platform / submission
>>>> + * inteface.
>>>> + */
>>>> +struct i915_context_engines_parallel_submit {
>>>> +   struct i915_user_extension base;
>>>> +
>>>> +   __u16 engine_index;     /* slot for parallel engine */
>>>> +   __u16 width;            /* number of contexts per parallel engine */
>>>> +   __u16 num_siblings;     /* number of siblings per context */
>>>> +   __u16 mbz16;
>>>
>>> Ok the big picture looks reasonable now, the flags still confuse me.
>>>
>>
>> Yea, it is a bit confusing.
>>
>>>> +/*
>>>> + * Default placement behvavior (currently unsupported):
>>>> + *
>>>> + * Rather than restricting parallel submission to a single class with a
>>>> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
>>>> + * enables parallel submission across multiple engine classes. In this case each
>>>> + * context's logical engine mask indicates where that context can placed. It is
>>>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>>>> + * if one context is running CS0 no other contexts can run on CS0).
>>>> + *
>>>> + * Example 1 pseudo code:
>>>> + * CSX[Y] = engine class X, logical instance Y
>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>> + * set_engines(INVALID)
>>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>>> + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
>>>> + *
>>>> + * Results in the following valid placements:
>>>> + * CS0[0], CS1[0]
>>>> + * CS0[0], CS1[1]
>>>> + * CS0[1], CS1[0]
>>>> + * CS0[1], CS1[1]
>>>> + *
>>>> + * This can also be though of as 2 virtual engines:
>>>> + * VE[0] = CS0[0], CS0[1]
>>>> + * VE[1] = CS1[0], CS1[1]
>>>> + *
>>>> + * Example 2 pseudo code:
>>>> + * CS[X] = generic engine of same class, logical instance X
>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>> + * set_engines(INVALID)
>>>> + * set_parallel(engine_index=0, width=2, num_siblings=3,
>>>> + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
>>>> + *
>>>> + * Results in the following valid placements:
>>>> + * CS[0], CS[1]
>>>> + * CS[0], CS[2]
>>>> + * CS[1], CS[0]
>>>> + * CS[1], CS[2]
>>>> + * CS[2], CS[0]
>>>> + * CS[2], CS[1]
>>>> + *
>>>> + *
>>>> + * This can also be though of as 2 virtual engines:
>>>> + * VE[0] = CS[0], CS[1], CS[2]
>>>> + * VE[1] = CS[0], CS[1], CS[2]
>>>> +
>>>> + * This enables a use case where all engines are created equally, we don't care
>>>> + * where they are scheduled, we just want a certain number of resources, for
>>>> + * those resources to be scheduled in parallel, and possibly across multiple
>>>> + * engine classes.
>>>> + */
>>>
>>> So I don't really get what this does compared to setting the flag below.
>>> Is this just about running the batchbuffers the wrong way round, i.e. if
>>> you have (simplest case)
>>>
>>> width=2, num_sibglings=1, engines=CS[0], CS[1]
>>>
>>> Then both
>>> CS[0], CS[1]
>>> and
>>> CS[1], CS[0]
>>> are possible options for running 2 batches? Iow, the backend is allowed to
>>> run the batchbuffers the wrong way round, which gains us nothing, since we
>>> assume the batches take equally long and engines interchangeable. There is
>>> no scheduling scenario where this additional flexibility can help.
>>>
>>> Also we don't have flags to select the only available and then specify an
>>> entire pipe dream about what the non-flag mode does, without an
>>> implementation. What is this about?
>>>
>>> If it's just "because bonded allowed this" then I think we should just
>>> unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
>>> welp.
>>>
>>
>> High level the flags came out of internal discussions how this interface
>> should look. The default placement behavior is theoretically possible
>> with execlists but has no use cases. The GuC supports / current use
>> cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
>>
>> Argued about for months and this is where we landed. At the end of the
>> day I think we needed to show that this interface supports more
>> placement rules than what the GuC supports / current use cases to future
>> proof this interface.
>>
>> For what is it worth it seems kinda backwards that we landed on the
>> default behavior not being supported in our current stack / HW.
> 
> Yeah I think that should be inverted, doesn't make sense.
> 
> What I still don't get (and I've read Tvrtko's reply with the example)
> is what exactly is the difference between implicit and not implicit
> mode? Can you do a single example where the only difference is whether
> this flag is set, and then explain with that what are the actual
> differences in scheduling options that the backend is allowed to pick
> for the set of N patches?
> 
> I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(

2-wide compute context:

  .engine_map([-1, -1])
  .load_balance(0: [cs0, cs1, cs2, cs3]) // place virtual engine at slot 0
  .load_balance(1: [cs0, cs1, cs2, cs3])
  .set_parallel()

This tells the scheduler any two of the four possible engines can be used. cs0 + cs3 is fine, cs3 + cs1 also, ... any. Only implicit rule is they have to be different and that works for all.

2-wide "implicit bonds mode" aka media fixed function limitation:

  .engine_map([-1, -1])
  .load_balance(0: [cs0, cs2])
  .load_balance(1: [cs1, cs3])
  .set_parallel(flags = implicit_bond)

Think of implicit flag creating a "link" between vertical columns in each virtual engine slot. So valid pairs end up cs0 + cs1 and cs2 + cs3 only.

You can also think of the implicit flag as a shortcut to avoid specifying bonds via the existing extension. In which case context setup would be written along the lines of:

  .engine_map([-1, -1])
  .load_balance(0: [cs0, cs2])
  .load_balance(1: [cs1, cs3])
  .bond(1: master = cs0, bond = [cs1])
  .bond(1: master = cs2, bond = [cs3])
  .set_parallel()

So the implicit flag is just a shortcut to avoid typing the bonds. Not really needed as explained in my previous reply.

This was at least the "old" set_parallel. I see this latest RFC changed things a bit which I don't really follow yet.

It's not perfect but needs to add very little (just one context extension, on top of multi batch execbuf which is needed anyways), doesn't need to deprecate anything, didn't require rewrites of the UMD, and it all works today and in the future.

I did not really like this new uapi for all the reasons I listed already, but as not many people were seeing the advantage of not churning on the uapi, if we are churning already I did suggests a different idea. I mean if we are churning we might as well go full in. So that proposal, which didn't get any traction, was along the lines of:

  .engine_map([-1])
  .load_balance_wide(0: width=2, engines=[[cs0, cs2], [cs1, cs3]])

This would create an explicit wide virtual engine which should work for GuC fine I think. For execlists it may require a bit of extra glue but I don't think too much.

Advantage is there is one engine in the map now and it is N-wide by definition.

Since no one did bite on that idea back then, I didn't really pursue is to see if it works for all use cases. But I think it should even if it probably requires further thinking to be sure.

If we apply it to compute use case..

  .engine_map([-1])
  .load_balance_wide(0: width=2, engines=[[cs0, cs1, cs2, cs3], [cs0, cs1, cs2, cs3]])

This means the only implicit wart in there is that cs0 + cs0 obviously shouldn't be picked. But that should be fine both for execlists and hopefully for the GuC.

Regards,

Tvrtko
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-19 16:51       ` [Intel-gfx] " Matthew Brost
@ 2021-05-20 11:11         ` Christian König
  -1 siblings, 0 replies; 54+ messages in thread
From: Christian König @ 2021-05-20 11:11 UTC (permalink / raw)
  To: Matthew Brost, Christian König
  Cc: tony.ye, tvrtko.ursulin, intel-gfx, dri-devel, jason.ekstrand,
	michal.mrozek, daniele.ceraolospurio, jon.bloomfield,
	daniel.vetter, mesa-dev, karl, john.c.harrison

Am 19.05.21 um 18:51 schrieb Matthew Brost:
> On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
>> Oh, yeah we call that gang submit on the AMD side.
>>
>> Had already some internal discussions how to implement this, but so far
>> couldn't figure out how to cleanly introduce that into the DRM scheduler.
>>
>> Can you briefly describe in a few words how that is supposed to work on the
>> Intel side?
>>
> Sure, I've done a quick PoC internally and have been able to hook this
> into the DRM scheduler.
>
> Basically each BB still maps to a single job as each job is somewhat
> unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
> the jobs configured to run in parallel map to a single sched_entity
> which maintains the order each job was generated from the execbuf IOCTL
> (1 - N). When the backend receives jobs 1 to N - 1 it basically just
> updates some internal state. When the backend sees job N (last job) it
> actually does the submit for jobs 1 - N which with GuC submission is a
> simple command moving the LRC tail of the N jobs.
>
> Daniel has suggested that we create a single job for the NN BBs but that
> would be huge rework to the internals of the i915 and likely won't
> happen by the time this code first lands.
>
> Also worth noting one way a job isn't really a treated individually is
> the excl slot with dma-resv. In that case we create a composite fence of
> all jobs (dma_fence_array).

Yeah, that's something we have discussed as well.

How do you prevent the scheduler from over committing to a single ring 
buffer in this scenario?

Christian.

>
> Matt
>
>> Thanks,
>> Christian.
>>
>> Am 19.05.21 um 01:58 schrieb Matthew Brost:
>>> Add entry fpr i915 new parallel submission uAPI plan.
>>>
>>> v2:
>>>    (Daniel Vetter):
>>>     - Expand logical order explaination
>>>     - Add dummy header
>>>     - Only allow N BBs in execbuf IOCTL
>>>     - Configure parallel submission per slot not per gem context
>>>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> Cc: Tony Ye <tony.ye@intel.com>
>>> CC: Carl Zhang <carl.zhang@intel.com>
>>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>>> Cc: Jason Ekstrand <jason@jlekstrand.net>
>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>> ---
>>>    Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>>>    Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>>>    2 files changed, 196 insertions(+), 1 deletion(-)
>>>    create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>
>>> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>> new file mode 100644
>>> index 000000000000..8c64b983ccad
>>> --- /dev/null
>>> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>> @@ -0,0 +1,144 @@
>>> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
>>> +
>>> +/*
>>> + * i915_context_engines_parallel_submit:
>>> + *
>>> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
>>> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
>>> + * hardware contexts are created internally in the i915 run these BBs. Once a
>>> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
>>> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
>>> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
>>> + * the slots configuration).
>>> + *
>>> + * Their are two currently defined ways to control the placement of the
>>> + * hardware contexts on physical engines: default behavior (no flags) and
>>> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
>>> + * future as new hardware / use cases arise. Details of how to use this
>>> + * interface below above the flags.
>>> + *
>>> + * Returns -EINVAL if hardware context placement configuration invalid or if the
>>> + * placement configuration isn't supported on the platform / submission
>>> + * interface.
>>> + * Returns -ENODEV if extension isn't supported on the platform / submission
>>> + * inteface.
>>> + */
>>> +struct i915_context_engines_parallel_submit {
>>> +	struct i915_user_extension base;
>>> +
>>> +	__u16 engine_index;	/* slot for parallel engine */
>>> +	__u16 width;		/* number of contexts per parallel engine */
>>> +	__u16 num_siblings;	/* number of siblings per context */
>>> +	__u16 mbz16;
>>> +/*
>>> + * Default placement behvavior (currently unsupported):
>>> + *
>>> + * Rather than restricting parallel submission to a single class with a
>>> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
>>> + * enables parallel submission across multiple engine classes. In this case each
>>> + * context's logical engine mask indicates where that context can placed. It is
>>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>>> + * if one context is running CS0 no other contexts can run on CS0).
>>> + *
>>> + * Example 1 pseudo code:
>>> + * CSX[Y] = engine class X, logical instance Y
>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>> + * set_engines(INVALID)
>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
>>> + *
>>> + * Results in the following valid placements:
>>> + * CS0[0], CS1[0]
>>> + * CS0[0], CS1[1]
>>> + * CS0[1], CS1[0]
>>> + * CS0[1], CS1[1]
>>> + *
>>> + * This can also be though of as 2 virtual engines:
>>> + * VE[0] = CS0[0], CS0[1]
>>> + * VE[1] = CS1[0], CS1[1]
>>> + *
>>> + * Example 2 pseudo code:
>>> + * CS[X] = generic engine of same class, logical instance X
>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>> + * set_engines(INVALID)
>>> + * set_parallel(engine_index=0, width=2, num_siblings=3,
>>> + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
>>> + *
>>> + * Results in the following valid placements:
>>> + * CS[0], CS[1]
>>> + * CS[0], CS[2]
>>> + * CS[1], CS[0]
>>> + * CS[1], CS[2]
>>> + * CS[2], CS[0]
>>> + * CS[2], CS[1]
>>> + *
>>> + *
>>> + * This can also be though of as 2 virtual engines:
>>> + * VE[0] = CS[0], CS[1], CS[2]
>>> + * VE[1] = CS[0], CS[1], CS[2]
>>> +
>>> + * This enables a use case where all engines are created equally, we don't care
>>> + * where they are scheduled, we just want a certain number of resources, for
>>> + * those resources to be scheduled in parallel, and possibly across multiple
>>> + * engine classes.
>>> + */
>>> +
>>> +/*
>>> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
>>> + * Each context must have the same number sibling and bonds are implictly create
>>> + * of the siblings.
>>> + *
>>> + * All of the below examples are in logical space.
>>> + *
>>> + * Example 1 pseudo code:
>>> + * CS[X] = generic engine of same class, logical instance X
>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>> + * set_engines(INVALID)
>>> + * set_parallel(engine_index=0, width=2, num_siblings=1,
>>> + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
>>> + *
>>> + * Results in the following valid placements:
>>> + * CS[0], CS[1]
>>> + *
>>> + * Example 2 pseudo code:
>>> + * CS[X] = generic engine of same class, logical instance X
>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>> + * set_engines(INVALID)
>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>> + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
>>> + *
>>> + * Results in the following valid placements:
>>> + * CS[0], CS[1]
>>> + * CS[2], CS[3]
>>> + *
>>> + * This can also be though of as 2 virtual engines:
>>> + * VE[0] = CS[0], CS[2]
>>> + * VE[1] = CS[1], CS[3]
>>> + *
>>> + * This enables a use case where all engines are not equal and certain placement
>>> + * rules are required (i.e. split-frame requires all contexts to be placed in a
>>> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
>>> + * case (logically contiguous placement, within a single engine class) is
>>> + * supported when using GuC submission. Execlist mode could support all possible
>>> + * bonding configurations but currently doesn't support this extension.
>>> + */
>>> +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
>>> +/*
>>> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
>>> + * points on all hardware contexts between each set of BBs. An example use case
>>> + * of this feature is split-frame on gen11+ hardware. When using this feature a
>>> + * BB must be submitted on each hardware context in the parallel gem context.
>>> + * The execbuf2 IOCTL enforces the user adheres to policy.
>>> + */
>>> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
>>> +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
>>> +	__u64 flags;		/* all undefined flags must be zero */
>>> +	__u64 mbz64[3];		/* reserved for future use; must be zero */
>>> +
>>> +	/*
>>> +	 * width (i) * num_siblings (j) in length
>>> +	 * index = j + i * num_siblings
>>> +	 */
>>> +	struct i915_engine_class_instance engines[0];
>>> +} __attribute__ ((packed));
>>> +
>>> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
>>> index 7faa46cde088..64c539486ee4 100644
>>> --- a/Documentation/gpu/rfc/i915_scheduler.rst
>>> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
>>> @@ -82,4 +82,55 @@ https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fspec.oneapi.com%2Flevel-zero%2Flatest%2Fcore%2Fapi.html%23ze-command-queue-priorit&amp;data=04%7C01%7Cchristian.koenig%40amd.com%7C49a7557f4e494090755608d91ae758a6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637570403202969375%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=dn3PVdxYQpkpWIru5eAXHgbfuLDkppAA5daV5sHQF7s%3D&amp;reserved=0
>>>    New parallel submission uAPI
>>>    ============================
>>> -Details to come in a following patch.
>>> +The existing bonding uAPI is completely broken with GuC submission because
>>> +whether a submission is a single context submit or parallel submit isn't known
>>> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
>>> +contexts in parallel with the GuC the context must be explictly registered with
>>> +N contexts and all N contexts must be submitted in a single command to the GuC.
>>> +These interfaces doesn't support dynamically changing between N contexts as the
>>> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
>>> +the legacy bonding uAPI is quite confusing and not intuitive at all.
>>> +
>>> +The new parallel submission uAPI consists of 3 parts:
>>> +
>>> +* Export engines logical mapping
>>> +* A 'set_parallel' extension to configure contexts for parallel
>>> +  submission
>>> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>>> +
>>> +Export engines logical mapping
>>> +------------------------------
>>> +Certain use cases require BBs to be placed on engine instances in logical order
>>> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
>>> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
>>> +logical mapping with the existing query engine info IOCTL. Also the GuC
>>> +submission interface currently only supports submitting multiple contexts to
>>> +engines in logical order which is a new requirement compared to execlists.
>>> +Lastly, all current platforms have at most 2 instances and the logical order is
>>> +the same a uABI order. This will change on platforms with more than 2 instances.
>>> +
>>> +A single bit will be added to drm_i915_engine_info.flags indicating that the
>>> +logical instance has been returned and a new field,
>>> +drm_i915_engine_info.logical_instance, returns the logical instance.
>>> +
>>> +A 'set_parallel' extension to configure contexts for parallel submission
>>> +------------------------------------------------------------------------
>>> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
>>> +It is setup step that should be called before using any of the contexts. See
>>> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
>>> +similar existing examples. Once a slot is configured for parallel submission the
>>> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
>>> +support GuC submission. Execlist support can be added later if needed.
>>> +
>>> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
>>> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
>>> +
>>> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>>> +-------------------------------------------------------------------
>>> +Contexts that have been configured with the 'set_parallel' extension are allowed
>>> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
>>> +objects in the drm_i915_gem_exec_object2 list or the first N if
>>> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
>>> +submitted and how it has been configured by 'set_parallel' or other extensions.
>>> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
>>> +the IOCTL.


^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-20 11:11         ` Christian König
  0 siblings, 0 replies; 54+ messages in thread
From: Christian König @ 2021-05-20 11:11 UTC (permalink / raw)
  To: Matthew Brost, Christian König
  Cc: intel-gfx, dri-devel, jason.ekstrand, daniel.vetter, mesa-dev, karl

Am 19.05.21 um 18:51 schrieb Matthew Brost:
> On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
>> Oh, yeah we call that gang submit on the AMD side.
>>
>> Had already some internal discussions how to implement this, but so far
>> couldn't figure out how to cleanly introduce that into the DRM scheduler.
>>
>> Can you briefly describe in a few words how that is supposed to work on the
>> Intel side?
>>
> Sure, I've done a quick PoC internally and have been able to hook this
> into the DRM scheduler.
>
> Basically each BB still maps to a single job as each job is somewhat
> unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
> the jobs configured to run in parallel map to a single sched_entity
> which maintains the order each job was generated from the execbuf IOCTL
> (1 - N). When the backend receives jobs 1 to N - 1 it basically just
> updates some internal state. When the backend sees job N (last job) it
> actually does the submit for jobs 1 - N which with GuC submission is a
> simple command moving the LRC tail of the N jobs.
>
> Daniel has suggested that we create a single job for the NN BBs but that
> would be huge rework to the internals of the i915 and likely won't
> happen by the time this code first lands.
>
> Also worth noting one way a job isn't really a treated individually is
> the excl slot with dma-resv. In that case we create a composite fence of
> all jobs (dma_fence_array).

Yeah, that's something we have discussed as well.

How do you prevent the scheduler from over committing to a single ring 
buffer in this scenario?

Christian.

>
> Matt
>
>> Thanks,
>> Christian.
>>
>> Am 19.05.21 um 01:58 schrieb Matthew Brost:
>>> Add entry fpr i915 new parallel submission uAPI plan.
>>>
>>> v2:
>>>    (Daniel Vetter):
>>>     - Expand logical order explaination
>>>     - Add dummy header
>>>     - Only allow N BBs in execbuf IOCTL
>>>     - Configure parallel submission per slot not per gem context
>>>
>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>> Cc: Tony Ye <tony.ye@intel.com>
>>> CC: Carl Zhang <carl.zhang@intel.com>
>>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>>> Cc: Jason Ekstrand <jason@jlekstrand.net>
>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>> ---
>>>    Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>>>    Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>>>    2 files changed, 196 insertions(+), 1 deletion(-)
>>>    create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>
>>> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>> new file mode 100644
>>> index 000000000000..8c64b983ccad
>>> --- /dev/null
>>> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>> @@ -0,0 +1,144 @@
>>> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
>>> +
>>> +/*
>>> + * i915_context_engines_parallel_submit:
>>> + *
>>> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
>>> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
>>> + * hardware contexts are created internally in the i915 run these BBs. Once a
>>> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
>>> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
>>> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
>>> + * the slots configuration).
>>> + *
>>> + * Their are two currently defined ways to control the placement of the
>>> + * hardware contexts on physical engines: default behavior (no flags) and
>>> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
>>> + * future as new hardware / use cases arise. Details of how to use this
>>> + * interface below above the flags.
>>> + *
>>> + * Returns -EINVAL if hardware context placement configuration invalid or if the
>>> + * placement configuration isn't supported on the platform / submission
>>> + * interface.
>>> + * Returns -ENODEV if extension isn't supported on the platform / submission
>>> + * inteface.
>>> + */
>>> +struct i915_context_engines_parallel_submit {
>>> +	struct i915_user_extension base;
>>> +
>>> +	__u16 engine_index;	/* slot for parallel engine */
>>> +	__u16 width;		/* number of contexts per parallel engine */
>>> +	__u16 num_siblings;	/* number of siblings per context */
>>> +	__u16 mbz16;
>>> +/*
>>> + * Default placement behvavior (currently unsupported):
>>> + *
>>> + * Rather than restricting parallel submission to a single class with a
>>> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
>>> + * enables parallel submission across multiple engine classes. In this case each
>>> + * context's logical engine mask indicates where that context can placed. It is
>>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>>> + * if one context is running CS0 no other contexts can run on CS0).
>>> + *
>>> + * Example 1 pseudo code:
>>> + * CSX[Y] = engine class X, logical instance Y
>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>> + * set_engines(INVALID)
>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
>>> + *
>>> + * Results in the following valid placements:
>>> + * CS0[0], CS1[0]
>>> + * CS0[0], CS1[1]
>>> + * CS0[1], CS1[0]
>>> + * CS0[1], CS1[1]
>>> + *
>>> + * This can also be though of as 2 virtual engines:
>>> + * VE[0] = CS0[0], CS0[1]
>>> + * VE[1] = CS1[0], CS1[1]
>>> + *
>>> + * Example 2 pseudo code:
>>> + * CS[X] = generic engine of same class, logical instance X
>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>> + * set_engines(INVALID)
>>> + * set_parallel(engine_index=0, width=2, num_siblings=3,
>>> + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
>>> + *
>>> + * Results in the following valid placements:
>>> + * CS[0], CS[1]
>>> + * CS[0], CS[2]
>>> + * CS[1], CS[0]
>>> + * CS[1], CS[2]
>>> + * CS[2], CS[0]
>>> + * CS[2], CS[1]
>>> + *
>>> + *
>>> + * This can also be though of as 2 virtual engines:
>>> + * VE[0] = CS[0], CS[1], CS[2]
>>> + * VE[1] = CS[0], CS[1], CS[2]
>>> +
>>> + * This enables a use case where all engines are created equally, we don't care
>>> + * where they are scheduled, we just want a certain number of resources, for
>>> + * those resources to be scheduled in parallel, and possibly across multiple
>>> + * engine classes.
>>> + */
>>> +
>>> +/*
>>> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
>>> + * Each context must have the same number sibling and bonds are implictly create
>>> + * of the siblings.
>>> + *
>>> + * All of the below examples are in logical space.
>>> + *
>>> + * Example 1 pseudo code:
>>> + * CS[X] = generic engine of same class, logical instance X
>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>> + * set_engines(INVALID)
>>> + * set_parallel(engine_index=0, width=2, num_siblings=1,
>>> + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
>>> + *
>>> + * Results in the following valid placements:
>>> + * CS[0], CS[1]
>>> + *
>>> + * Example 2 pseudo code:
>>> + * CS[X] = generic engine of same class, logical instance X
>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>> + * set_engines(INVALID)
>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>> + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
>>> + *
>>> + * Results in the following valid placements:
>>> + * CS[0], CS[1]
>>> + * CS[2], CS[3]
>>> + *
>>> + * This can also be though of as 2 virtual engines:
>>> + * VE[0] = CS[0], CS[2]
>>> + * VE[1] = CS[1], CS[3]
>>> + *
>>> + * This enables a use case where all engines are not equal and certain placement
>>> + * rules are required (i.e. split-frame requires all contexts to be placed in a
>>> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
>>> + * case (logically contiguous placement, within a single engine class) is
>>> + * supported when using GuC submission. Execlist mode could support all possible
>>> + * bonding configurations but currently doesn't support this extension.
>>> + */
>>> +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
>>> +/*
>>> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
>>> + * points on all hardware contexts between each set of BBs. An example use case
>>> + * of this feature is split-frame on gen11+ hardware. When using this feature a
>>> + * BB must be submitted on each hardware context in the parallel gem context.
>>> + * The execbuf2 IOCTL enforces the user adheres to policy.
>>> + */
>>> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
>>> +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
>>> +	__u64 flags;		/* all undefined flags must be zero */
>>> +	__u64 mbz64[3];		/* reserved for future use; must be zero */
>>> +
>>> +	/*
>>> +	 * width (i) * num_siblings (j) in length
>>> +	 * index = j + i * num_siblings
>>> +	 */
>>> +	struct i915_engine_class_instance engines[0];
>>> +} __attribute__ ((packed));
>>> +
>>> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
>>> index 7faa46cde088..64c539486ee4 100644
>>> --- a/Documentation/gpu/rfc/i915_scheduler.rst
>>> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
>>> @@ -82,4 +82,55 @@ https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fspec.oneapi.com%2Flevel-zero%2Flatest%2Fcore%2Fapi.html%23ze-command-queue-priorit&amp;data=04%7C01%7Cchristian.koenig%40amd.com%7C49a7557f4e494090755608d91ae758a6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637570403202969375%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=dn3PVdxYQpkpWIru5eAXHgbfuLDkppAA5daV5sHQF7s%3D&amp;reserved=0
>>>    New parallel submission uAPI
>>>    ============================
>>> -Details to come in a following patch.
>>> +The existing bonding uAPI is completely broken with GuC submission because
>>> +whether a submission is a single context submit or parallel submit isn't known
>>> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
>>> +contexts in parallel with the GuC the context must be explictly registered with
>>> +N contexts and all N contexts must be submitted in a single command to the GuC.
>>> +These interfaces doesn't support dynamically changing between N contexts as the
>>> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
>>> +the legacy bonding uAPI is quite confusing and not intuitive at all.
>>> +
>>> +The new parallel submission uAPI consists of 3 parts:
>>> +
>>> +* Export engines logical mapping
>>> +* A 'set_parallel' extension to configure contexts for parallel
>>> +  submission
>>> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>>> +
>>> +Export engines logical mapping
>>> +------------------------------
>>> +Certain use cases require BBs to be placed on engine instances in logical order
>>> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
>>> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
>>> +logical mapping with the existing query engine info IOCTL. Also the GuC
>>> +submission interface currently only supports submitting multiple contexts to
>>> +engines in logical order which is a new requirement compared to execlists.
>>> +Lastly, all current platforms have at most 2 instances and the logical order is
>>> +the same a uABI order. This will change on platforms with more than 2 instances.
>>> +
>>> +A single bit will be added to drm_i915_engine_info.flags indicating that the
>>> +logical instance has been returned and a new field,
>>> +drm_i915_engine_info.logical_instance, returns the logical instance.
>>> +
>>> +A 'set_parallel' extension to configure contexts for parallel submission
>>> +------------------------------------------------------------------------
>>> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
>>> +It is setup step that should be called before using any of the contexts. See
>>> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
>>> +similar existing examples. Once a slot is configured for parallel submission the
>>> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
>>> +support GuC submission. Execlist support can be added later if needed.
>>> +
>>> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
>>> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
>>> +
>>> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>>> +-------------------------------------------------------------------
>>> +Contexts that have been configured with the 'set_parallel' extension are allowed
>>> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
>>> +objects in the drm_i915_gem_exec_object2 list or the first N if
>>> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
>>> +submitted and how it has been configured by 'set_parallel' or other extensions.
>>> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
>>> +the IOCTL.

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-20  9:54         ` Daniel Vetter
@ 2021-05-20 15:10           ` Matthew Brost
  -1 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-20 15:10 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Mesa Dev, Daniel Vetter,
	karl, Christian König

On Thu, May 20, 2021 at 11:54:25AM +0200, Daniel Vetter wrote:
> On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
> >
> > On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > >
> > > > v2:
> > > >  (Daniel Vetter):
> > > >   - Expand logical order explaination
> > > >   - Add dummy header
> > > >   - Only allow N BBs in execbuf IOCTL
> > > >   - Configure parallel submission per slot not per gem context
> > > >
> > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > ---
> > > >  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > >  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > >  2 files changed, 196 insertions(+), 1 deletion(-)
> > > >  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > >
> > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > new file mode 100644
> > > > index 000000000000..8c64b983ccad
> > > > --- /dev/null
> > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > @@ -0,0 +1,144 @@
> > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > +
> > > > +/*
> > > > + * i915_context_engines_parallel_submit:
> > > > + *
> > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > + * the slots configuration).
> > > > + *
> > > > + * Their are two currently defined ways to control the placement of the
> > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > + * interface below above the flags.
> > > > + *
> > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > + * placement configuration isn't supported on the platform / submission
> > > > + * interface.
> > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > + * inteface.
> > > > + */
> > > > +struct i915_context_engines_parallel_submit {
> > > > +   struct i915_user_extension base;
> > > > +
> > > > +   __u16 engine_index;     /* slot for parallel engine */
> > > > +   __u16 width;            /* number of contexts per parallel engine */
> > > > +   __u16 num_siblings;     /* number of siblings per context */
> > > > +   __u16 mbz16;
> > >
> > > Ok the big picture looks reasonable now, the flags still confuse me.
> > >
> >
> > Yea, it is a bit confusing.
> >
> > > > +/*
> > > > + * Default placement behvavior (currently unsupported):
> > > > + *
> > > > + * Rather than restricting parallel submission to a single class with a
> > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > + *
> > > > + * Example 1 pseudo code:
> > > > + * CSX[Y] = engine class X, logical instance Y
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS0[0], CS1[0]
> > > > + * CS0[0], CS1[1]
> > > > + * CS0[1], CS1[0]
> > > > + * CS0[1], CS1[1]
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS0[0], CS0[1]
> > > > + * VE[1] = CS1[0], CS1[1]
> > > > + *
> > > > + * Example 2 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + * CS[0], CS[2]
> > > > + * CS[1], CS[0]
> > > > + * CS[1], CS[2]
> > > > + * CS[2], CS[0]
> > > > + * CS[2], CS[1]
> > > > + *
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > +
> > > > + * This enables a use case where all engines are created equally, we don't care
> > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > + * engine classes.
> > > > + */
> > >
> > > So I don't really get what this does compared to setting the flag below.
> > > Is this just about running the batchbuffers the wrong way round, i.e. if
> > > you have (simplest case)
> > >
> > > width=2, num_sibglings=1, engines=CS[0], CS[1]
> > >
> > > Then both
> > > CS[0], CS[1]
> > > and
> > > CS[1], CS[0]
> > > are possible options for running 2 batches? Iow, the backend is allowed to
> > > run the batchbuffers the wrong way round, which gains us nothing, since we
> > > assume the batches take equally long and engines interchangeable. There is
> > > no scheduling scenario where this additional flexibility can help.
> > >
> > > Also we don't have flags to select the only available and then specify an
> > > entire pipe dream about what the non-flag mode does, without an
> > > implementation. What is this about?
> > >
> > > If it's just "because bonded allowed this" then I think we should just
> > > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > > welp.
> > >
> >
> > High level the flags came out of internal discussions how this interface
> > should look. The default placement behavior is theoretically possible
> > with execlists but has no use cases. The GuC supports / current use
> > cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
> >
> > Argued about for months and this is where we landed. At the end of the
> > day I think we needed to show that this interface supports more
> > placement rules than what the GuC supports / current use cases to future
> > proof this interface.
> >
> > For what is it worth it seems kinda backwards that we landed on the
> > default behavior not being supported in our current stack / HW.
> 
> Yeah I think that should be inverted, doesn't make sense.
> 
> What I still don't get (and I've read Tvrtko's reply with the example)
> is what exactly is the difference between implicit and not implicit
> mode? Can you do a single example where the only difference is whether
> this flag is set, and then explain with that what are the actual
> differences in scheduling options that the backend is allowed to pick
> for the set of N patches?
> 
> I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
> 
> > > > +
> > > > +/*
> > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > + * of the siblings.
> > > > + *
> > > > + * All of the below examples are in logical space.
> > > > + *
> > > > + * Example 1 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > + *         engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + *
> > > > + * Example 2 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > + *         engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + * CS[2], CS[3]
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS[0], CS[2]
> > > > + * VE[1] = CS[1], CS[3]
> > > > + *
> > > > + * This enables a use case where all engines are not equal and certain placement
> > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > + * case (logically contiguous placement, within a single engine class) is
> > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > + * bonding configurations but currently doesn't support this extension.
> > > > + */
> > > > +#define I915_PARALLEL_IMPLICT_BONDS                        (1<<0)
> > >
> > > Does this map to intel_context_set_nopreempt(), so we could implement it
> > > also in execlist?
> > >
> >
> > intel_context_set_nopreempt is preempt is part of how this would be
> > implemented for execlists. For GuC submission there is a algorithm
> > between the i915 and GuC that inserts same preemption points between
> > each set of N batches. I believe the rules are if context 1 can
> > preempted the rest of the contexts (2 - N) can safely be preempted. A go
> > / join algorithm, implemented with semaphores, around the batches
> > makes sure the i915 adheres to these rules.
> >
> > > Also is this just an artifact of the implementation, or is this somehow
> > > required functionality for userspace, i.e. the workload fails if e.g. GuC
> > > decides to preempt all LRC of a parallel virtual engine? Of course just
> > > preempting one is a bit a bug (but execlist I think happily does that).
> > >
> >
> > I think it is part of the implementation / HW limitations. Basically if
> > N batches are running in parallel if one of the batches gets preempted
> > it can hang all the other batches even if it gets restarted. Again the
> > idea behind this is only preempt any of these contexts between each set
> > of N batches. The GuC has no concept of batches only contexts hence the
> > aforementioned algorithm to insert same preemption points between each
> > set of batches.
> 
> Well backend preempting one but not the other is a bug. I don't think
> we need to talk about bugs :-)
>

I think it is more that backend can't preempt each context atomically as these
are running on independent engines. Let say the backend tries to preempt 2
engines at the same time and only 1 responds, now we are broken with certain
batches. With the algorithm implmented between the i915 and the Guc the GuC will
try to preempt the first context if that works, all the other contexts can be
preempted.

> Now wrt a preempt mode in context creation, I think that makes sense.
> I'm just wondering whether this is correct here in the parallel
> submission (and why), or is it just an implementation artifact
> (current backends are buggy if we'd allow them to preempt) or what's
> going on.
>
> If this is just a case of "this is how current backends work,
> userspace doesn't actually care whether we allow preempt or not" then
> I think we should just document the behavior and that's it. Adding
> uapi for an option for which there's not even an implementation isn't
> great.
> 

I don't think it is a case of 'this is how current backends work...', I think
user space knows if it is ok for 1 of the batches to preempted and not the
others without breaking the batches.

Matt

> But if we can actually choose, and userspace wants to, then I'm all
> fine with this. And we can always move this to a more generic place if
> other engines need preempt control later on too.
> 
> Cheers, Daniel
> 
> 
> > Matt
> >
> > > Cheers, Daniel
> > >
> > > > +/*
> > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > + */
> > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH         (1<<1)
> > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS      (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > +   __u64 flags;            /* all undefined flags must be zero */
> > > > +   __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > > +
> > > > +   /*
> > > > +    * width (i) * num_siblings (j) in length
> > > > +    * index = j + i * num_siblings
> > > > +    */
> > > > +   struct i915_engine_class_instance engines[0];
> > > > +} __attribute__ ((packed));
> > > > +
> > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > index 7faa46cde088..64c539486ee4 100644
> > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> > > >
> > > >  New parallel submission uAPI
> > > >  ============================
> > > > -Details to come in a following patch.
> > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > +
> > > > +The new parallel submission uAPI consists of 3 parts:
> > > > +
> > > > +* Export engines logical mapping
> > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > +  submission
> > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > +
> > > > +Export engines logical mapping
> > > > +------------------------------
> > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > +submission interface currently only supports submitting multiple contexts to
> > > > +engines in logical order which is a new requirement compared to execlists.
> > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > +
> > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > +logical instance has been returned and a new field,
> > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > +
> > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > +------------------------------------------------------------------------
> > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > +It is setup step that should be called before using any of the contexts. See
> > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > +support GuC submission. Execlist support can be added later if needed.
> > > > +
> > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > +
> > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > +-------------------------------------------------------------------
> > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > +the IOCTL.
> > > > --
> > > > 2.28.0
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > > --
> > > Daniel Vetter
> > > Software Engineer, Intel Corporation
> > > http://blog.ffwll.ch
> 
> 
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-20 15:10           ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-20 15:10 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Mesa Dev, Daniel Vetter,
	karl, Christian König

On Thu, May 20, 2021 at 11:54:25AM +0200, Daniel Vetter wrote:
> On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
> >
> > On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > >
> > > > v2:
> > > >  (Daniel Vetter):
> > > >   - Expand logical order explaination
> > > >   - Add dummy header
> > > >   - Only allow N BBs in execbuf IOCTL
> > > >   - Configure parallel submission per slot not per gem context
> > > >
> > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > ---
> > > >  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > >  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > >  2 files changed, 196 insertions(+), 1 deletion(-)
> > > >  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > >
> > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > new file mode 100644
> > > > index 000000000000..8c64b983ccad
> > > > --- /dev/null
> > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > @@ -0,0 +1,144 @@
> > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > +
> > > > +/*
> > > > + * i915_context_engines_parallel_submit:
> > > > + *
> > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > + * the slots configuration).
> > > > + *
> > > > + * Their are two currently defined ways to control the placement of the
> > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > + * interface below above the flags.
> > > > + *
> > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > + * placement configuration isn't supported on the platform / submission
> > > > + * interface.
> > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > + * inteface.
> > > > + */
> > > > +struct i915_context_engines_parallel_submit {
> > > > +   struct i915_user_extension base;
> > > > +
> > > > +   __u16 engine_index;     /* slot for parallel engine */
> > > > +   __u16 width;            /* number of contexts per parallel engine */
> > > > +   __u16 num_siblings;     /* number of siblings per context */
> > > > +   __u16 mbz16;
> > >
> > > Ok the big picture looks reasonable now, the flags still confuse me.
> > >
> >
> > Yea, it is a bit confusing.
> >
> > > > +/*
> > > > + * Default placement behvavior (currently unsupported):
> > > > + *
> > > > + * Rather than restricting parallel submission to a single class with a
> > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > + *
> > > > + * Example 1 pseudo code:
> > > > + * CSX[Y] = engine class X, logical instance Y
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS0[0], CS1[0]
> > > > + * CS0[0], CS1[1]
> > > > + * CS0[1], CS1[0]
> > > > + * CS0[1], CS1[1]
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS0[0], CS0[1]
> > > > + * VE[1] = CS1[0], CS1[1]
> > > > + *
> > > > + * Example 2 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + * CS[0], CS[2]
> > > > + * CS[1], CS[0]
> > > > + * CS[1], CS[2]
> > > > + * CS[2], CS[0]
> > > > + * CS[2], CS[1]
> > > > + *
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > +
> > > > + * This enables a use case where all engines are created equally, we don't care
> > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > + * engine classes.
> > > > + */
> > >
> > > So I don't really get what this does compared to setting the flag below.
> > > Is this just about running the batchbuffers the wrong way round, i.e. if
> > > you have (simplest case)
> > >
> > > width=2, num_sibglings=1, engines=CS[0], CS[1]
> > >
> > > Then both
> > > CS[0], CS[1]
> > > and
> > > CS[1], CS[0]
> > > are possible options for running 2 batches? Iow, the backend is allowed to
> > > run the batchbuffers the wrong way round, which gains us nothing, since we
> > > assume the batches take equally long and engines interchangeable. There is
> > > no scheduling scenario where this additional flexibility can help.
> > >
> > > Also we don't have flags to select the only available and then specify an
> > > entire pipe dream about what the non-flag mode does, without an
> > > implementation. What is this about?
> > >
> > > If it's just "because bonded allowed this" then I think we should just
> > > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > > welp.
> > >
> >
> > High level the flags came out of internal discussions how this interface
> > should look. The default placement behavior is theoretically possible
> > with execlists but has no use cases. The GuC supports / current use
> > cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
> >
> > Argued about for months and this is where we landed. At the end of the
> > day I think we needed to show that this interface supports more
> > placement rules than what the GuC supports / current use cases to future
> > proof this interface.
> >
> > For what is it worth it seems kinda backwards that we landed on the
> > default behavior not being supported in our current stack / HW.
> 
> Yeah I think that should be inverted, doesn't make sense.
> 
> What I still don't get (and I've read Tvrtko's reply with the example)
> is what exactly is the difference between implicit and not implicit
> mode? Can you do a single example where the only difference is whether
> this flag is set, and then explain with that what are the actual
> differences in scheduling options that the backend is allowed to pick
> for the set of N patches?
> 
> I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
> 
> > > > +
> > > > +/*
> > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > + * of the siblings.
> > > > + *
> > > > + * All of the below examples are in logical space.
> > > > + *
> > > > + * Example 1 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > + *         engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + *
> > > > + * Example 2 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > + *         engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + * CS[2], CS[3]
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS[0], CS[2]
> > > > + * VE[1] = CS[1], CS[3]
> > > > + *
> > > > + * This enables a use case where all engines are not equal and certain placement
> > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > + * case (logically contiguous placement, within a single engine class) is
> > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > + * bonding configurations but currently doesn't support this extension.
> > > > + */
> > > > +#define I915_PARALLEL_IMPLICT_BONDS                        (1<<0)
> > >
> > > Does this map to intel_context_set_nopreempt(), so we could implement it
> > > also in execlist?
> > >
> >
> > intel_context_set_nopreempt is preempt is part of how this would be
> > implemented for execlists. For GuC submission there is a algorithm
> > between the i915 and GuC that inserts same preemption points between
> > each set of N batches. I believe the rules are if context 1 can
> > preempted the rest of the contexts (2 - N) can safely be preempted. A go
> > / join algorithm, implemented with semaphores, around the batches
> > makes sure the i915 adheres to these rules.
> >
> > > Also is this just an artifact of the implementation, or is this somehow
> > > required functionality for userspace, i.e. the workload fails if e.g. GuC
> > > decides to preempt all LRC of a parallel virtual engine? Of course just
> > > preempting one is a bit a bug (but execlist I think happily does that).
> > >
> >
> > I think it is part of the implementation / HW limitations. Basically if
> > N batches are running in parallel if one of the batches gets preempted
> > it can hang all the other batches even if it gets restarted. Again the
> > idea behind this is only preempt any of these contexts between each set
> > of N batches. The GuC has no concept of batches only contexts hence the
> > aforementioned algorithm to insert same preemption points between each
> > set of batches.
> 
> Well backend preempting one but not the other is a bug. I don't think
> we need to talk about bugs :-)
>

I think it is more that backend can't preempt each context atomically as these
are running on independent engines. Let say the backend tries to preempt 2
engines at the same time and only 1 responds, now we are broken with certain
batches. With the algorithm implmented between the i915 and the Guc the GuC will
try to preempt the first context if that works, all the other contexts can be
preempted.

> Now wrt a preempt mode in context creation, I think that makes sense.
> I'm just wondering whether this is correct here in the parallel
> submission (and why), or is it just an implementation artifact
> (current backends are buggy if we'd allow them to preempt) or what's
> going on.
>
> If this is just a case of "this is how current backends work,
> userspace doesn't actually care whether we allow preempt or not" then
> I think we should just document the behavior and that's it. Adding
> uapi for an option for which there's not even an implementation isn't
> great.
> 

I don't think it is a case of 'this is how current backends work...', I think
user space knows if it is ok for 1 of the batches to preempted and not the
others without breaking the batches.

Matt

> But if we can actually choose, and userspace wants to, then I'm all
> fine with this. And we can always move this to a more generic place if
> other engines need preempt control later on too.
> 
> Cheers, Daniel
> 
> 
> > Matt
> >
> > > Cheers, Daniel
> > >
> > > > +/*
> > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > + */
> > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH         (1<<1)
> > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS      (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > +   __u64 flags;            /* all undefined flags must be zero */
> > > > +   __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > > +
> > > > +   /*
> > > > +    * width (i) * num_siblings (j) in length
> > > > +    * index = j + i * num_siblings
> > > > +    */
> > > > +   struct i915_engine_class_instance engines[0];
> > > > +} __attribute__ ((packed));
> > > > +
> > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > index 7faa46cde088..64c539486ee4 100644
> > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> > > >
> > > >  New parallel submission uAPI
> > > >  ============================
> > > > -Details to come in a following patch.
> > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > +
> > > > +The new parallel submission uAPI consists of 3 parts:
> > > > +
> > > > +* Export engines logical mapping
> > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > +  submission
> > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > +
> > > > +Export engines logical mapping
> > > > +------------------------------
> > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > +submission interface currently only supports submitting multiple contexts to
> > > > +engines in logical order which is a new requirement compared to execlists.
> > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > +
> > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > +logical instance has been returned and a new field,
> > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > +
> > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > +------------------------------------------------------------------------
> > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > +It is setup step that should be called before using any of the contexts. See
> > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > +support GuC submission. Execlist support can be added later if needed.
> > > > +
> > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > +
> > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > +-------------------------------------------------------------------
> > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > +the IOCTL.
> > > > --
> > > > 2.28.0
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> > > --
> > > Daniel Vetter
> > > Software Engineer, Intel Corporation
> > > http://blog.ffwll.ch
> 
> 
> 
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-20 11:11         ` [Intel-gfx] " Christian König
@ 2021-05-20 15:39           ` Matthew Brost
  -1 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-20 15:39 UTC (permalink / raw)
  To: Christian König
  Cc: tony.ye, tvrtko.ursulin, Christian König, intel-gfx,
	dri-devel, jason.ekstrand, michal.mrozek, daniele.ceraolospurio,
	jon.bloomfield, daniel.vetter, mesa-dev, karl, john.c.harrison

On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote:
> Am 19.05.21 um 18:51 schrieb Matthew Brost:
> > On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
> > > Oh, yeah we call that gang submit on the AMD side.
> > > 
> > > Had already some internal discussions how to implement this, but so far
> > > couldn't figure out how to cleanly introduce that into the DRM scheduler.
> > > 
> > > Can you briefly describe in a few words how that is supposed to work on the
> > > Intel side?
> > > 
> > Sure, I've done a quick PoC internally and have been able to hook this
> > into the DRM scheduler.
> > 
> > Basically each BB still maps to a single job as each job is somewhat
> > unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
> > the jobs configured to run in parallel map to a single sched_entity
> > which maintains the order each job was generated from the execbuf IOCTL
> > (1 - N). When the backend receives jobs 1 to N - 1 it basically just
> > updates some internal state. When the backend sees job N (last job) it
> > actually does the submit for jobs 1 - N which with GuC submission is a
> > simple command moving the LRC tail of the N jobs.
> > 
> > Daniel has suggested that we create a single job for the NN BBs but that
> > would be huge rework to the internals of the i915 and likely won't
> > happen by the time this code first lands.
> > 
> > Also worth noting one way a job isn't really a treated individually is
> > the excl slot with dma-resv. In that case we create a composite fence of
> > all jobs (dma_fence_array).
> 
> Yeah, that's something we have discussed as well.
> 
> How do you prevent the scheduler from over committing to a single ring
> buffer in this scenario?
> 

Each job has its own ring, the execbuf IOCTL throttles itself for each
job if there isn't space in the ring. This is exactly the same as
non-parallel submits.

I think this is what you were asking? If not, maybe try explaining the
question a bit more.

Matt

> Christian.
> 
> > 
> > Matt
> > 
> > > Thanks,
> > > Christian.
> > > 
> > > Am 19.05.21 um 01:58 schrieb Matthew Brost:
> > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > 
> > > > v2:
> > > >    (Daniel Vetter):
> > > >     - Expand logical order explaination
> > > >     - Add dummy header
> > > >     - Only allow N BBs in execbuf IOCTL
> > > >     - Configure parallel submission per slot not per gem context
> > > > 
> > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > ---
> > > >    Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > >    Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > >    2 files changed, 196 insertions(+), 1 deletion(-)
> > > >    create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > 
> > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > new file mode 100644
> > > > index 000000000000..8c64b983ccad
> > > > --- /dev/null
> > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > @@ -0,0 +1,144 @@
> > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > +
> > > > +/*
> > > > + * i915_context_engines_parallel_submit:
> > > > + *
> > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > + * the slots configuration).
> > > > + *
> > > > + * Their are two currently defined ways to control the placement of the
> > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > + * interface below above the flags.
> > > > + *
> > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > + * placement configuration isn't supported on the platform / submission
> > > > + * interface.
> > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > + * inteface.
> > > > + */
> > > > +struct i915_context_engines_parallel_submit {
> > > > +	struct i915_user_extension base;
> > > > +
> > > > +	__u16 engine_index;	/* slot for parallel engine */
> > > > +	__u16 width;		/* number of contexts per parallel engine */
> > > > +	__u16 num_siblings;	/* number of siblings per context */
> > > > +	__u16 mbz16;
> > > > +/*
> > > > + * Default placement behvavior (currently unsupported):
> > > > + *
> > > > + * Rather than restricting parallel submission to a single class with a
> > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > + *
> > > > + * Example 1 pseudo code:
> > > > + * CSX[Y] = engine class X, logical instance Y
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS0[0], CS1[0]
> > > > + * CS0[0], CS1[1]
> > > > + * CS0[1], CS1[0]
> > > > + * CS0[1], CS1[1]
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS0[0], CS0[1]
> > > > + * VE[1] = CS1[0], CS1[1]
> > > > + *
> > > > + * Example 2 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + * CS[0], CS[2]
> > > > + * CS[1], CS[0]
> > > > + * CS[1], CS[2]
> > > > + * CS[2], CS[0]
> > > > + * CS[2], CS[1]
> > > > + *
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > +
> > > > + * This enables a use case where all engines are created equally, we don't care
> > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > + * engine classes.
> > > > + */
> > > > +
> > > > +/*
> > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > + * of the siblings.
> > > > + *
> > > > + * All of the below examples are in logical space.
> > > > + *
> > > > + * Example 1 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + *
> > > > + * Example 2 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + * CS[2], CS[3]
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS[0], CS[2]
> > > > + * VE[1] = CS[1], CS[3]
> > > > + *
> > > > + * This enables a use case where all engines are not equal and certain placement
> > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > + * case (logically contiguous placement, within a single engine class) is
> > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > + * bonding configurations but currently doesn't support this extension.
> > > > + */
> > > > +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> > > > +/*
> > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > + */
> > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > +	__u64 flags;		/* all undefined flags must be zero */
> > > > +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> > > > +
> > > > +	/*
> > > > +	 * width (i) * num_siblings (j) in length
> > > > +	 * index = j + i * num_siblings
> > > > +	 */
> > > > +	struct i915_engine_class_instance engines[0];
> > > > +} __attribute__ ((packed));
> > > > +
> > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > index 7faa46cde088..64c539486ee4 100644
> > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > @@ -82,4 +82,55 @@ https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fspec.oneapi.com%2Flevel-zero%2Flatest%2Fcore%2Fapi.html%23ze-command-queue-priorit&amp;data=04%7C01%7Cchristian.koenig%40amd.com%7C49a7557f4e494090755608d91ae758a6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637570403202969375%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=dn3PVdxYQpkpWIru5eAXHgbfuLDkppAA5daV5sHQF7s%3D&amp;reserved=0
> > > >    New parallel submission uAPI
> > > >    ============================
> > > > -Details to come in a following patch.
> > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > +
> > > > +The new parallel submission uAPI consists of 3 parts:
> > > > +
> > > > +* Export engines logical mapping
> > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > +  submission
> > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > +
> > > > +Export engines logical mapping
> > > > +------------------------------
> > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > +submission interface currently only supports submitting multiple contexts to
> > > > +engines in logical order which is a new requirement compared to execlists.
> > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > +
> > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > +logical instance has been returned and a new field,
> > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > +
> > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > +------------------------------------------------------------------------
> > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > +It is setup step that should be called before using any of the contexts. See
> > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > +support GuC submission. Execlist support can be added later if needed.
> > > > +
> > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > +
> > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > +-------------------------------------------------------------------
> > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > +the IOCTL.
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-20 15:39           ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-20 15:39 UTC (permalink / raw)
  To: Christian König
  Cc: Christian König, intel-gfx, dri-devel, jason.ekstrand,
	daniel.vetter, mesa-dev, karl

On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote:
> Am 19.05.21 um 18:51 schrieb Matthew Brost:
> > On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
> > > Oh, yeah we call that gang submit on the AMD side.
> > > 
> > > Had already some internal discussions how to implement this, but so far
> > > couldn't figure out how to cleanly introduce that into the DRM scheduler.
> > > 
> > > Can you briefly describe in a few words how that is supposed to work on the
> > > Intel side?
> > > 
> > Sure, I've done a quick PoC internally and have been able to hook this
> > into the DRM scheduler.
> > 
> > Basically each BB still maps to a single job as each job is somewhat
> > unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
> > the jobs configured to run in parallel map to a single sched_entity
> > which maintains the order each job was generated from the execbuf IOCTL
> > (1 - N). When the backend receives jobs 1 to N - 1 it basically just
> > updates some internal state. When the backend sees job N (last job) it
> > actually does the submit for jobs 1 - N which with GuC submission is a
> > simple command moving the LRC tail of the N jobs.
> > 
> > Daniel has suggested that we create a single job for the NN BBs but that
> > would be huge rework to the internals of the i915 and likely won't
> > happen by the time this code first lands.
> > 
> > Also worth noting one way a job isn't really a treated individually is
> > the excl slot with dma-resv. In that case we create a composite fence of
> > all jobs (dma_fence_array).
> 
> Yeah, that's something we have discussed as well.
> 
> How do you prevent the scheduler from over committing to a single ring
> buffer in this scenario?
> 

Each job has its own ring, the execbuf IOCTL throttles itself for each
job if there isn't space in the ring. This is exactly the same as
non-parallel submits.

I think this is what you were asking? If not, maybe try explaining the
question a bit more.

Matt

> Christian.
> 
> > 
> > Matt
> > 
> > > Thanks,
> > > Christian.
> > > 
> > > Am 19.05.21 um 01:58 schrieb Matthew Brost:
> > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > 
> > > > v2:
> > > >    (Daniel Vetter):
> > > >     - Expand logical order explaination
> > > >     - Add dummy header
> > > >     - Only allow N BBs in execbuf IOCTL
> > > >     - Configure parallel submission per slot not per gem context
> > > > 
> > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > ---
> > > >    Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > >    Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > >    2 files changed, 196 insertions(+), 1 deletion(-)
> > > >    create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > 
> > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > new file mode 100644
> > > > index 000000000000..8c64b983ccad
> > > > --- /dev/null
> > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > @@ -0,0 +1,144 @@
> > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > +
> > > > +/*
> > > > + * i915_context_engines_parallel_submit:
> > > > + *
> > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > + * the slots configuration).
> > > > + *
> > > > + * Their are two currently defined ways to control the placement of the
> > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > + * interface below above the flags.
> > > > + *
> > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > + * placement configuration isn't supported on the platform / submission
> > > > + * interface.
> > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > + * inteface.
> > > > + */
> > > > +struct i915_context_engines_parallel_submit {
> > > > +	struct i915_user_extension base;
> > > > +
> > > > +	__u16 engine_index;	/* slot for parallel engine */
> > > > +	__u16 width;		/* number of contexts per parallel engine */
> > > > +	__u16 num_siblings;	/* number of siblings per context */
> > > > +	__u16 mbz16;
> > > > +/*
> > > > + * Default placement behvavior (currently unsupported):
> > > > + *
> > > > + * Rather than restricting parallel submission to a single class with a
> > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > + *
> > > > + * Example 1 pseudo code:
> > > > + * CSX[Y] = engine class X, logical instance Y
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS0[0], CS1[0]
> > > > + * CS0[0], CS1[1]
> > > > + * CS0[1], CS1[0]
> > > > + * CS0[1], CS1[1]
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS0[0], CS0[1]
> > > > + * VE[1] = CS1[0], CS1[1]
> > > > + *
> > > > + * Example 2 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + * CS[0], CS[2]
> > > > + * CS[1], CS[0]
> > > > + * CS[1], CS[2]
> > > > + * CS[2], CS[0]
> > > > + * CS[2], CS[1]
> > > > + *
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > +
> > > > + * This enables a use case where all engines are created equally, we don't care
> > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > + * engine classes.
> > > > + */
> > > > +
> > > > +/*
> > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > + * of the siblings.
> > > > + *
> > > > + * All of the below examples are in logical space.
> > > > + *
> > > > + * Example 1 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + *
> > > > + * Example 2 pseudo code:
> > > > + * CS[X] = generic engine of same class, logical instance X
> > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > + * set_engines(INVALID)
> > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > + *
> > > > + * Results in the following valid placements:
> > > > + * CS[0], CS[1]
> > > > + * CS[2], CS[3]
> > > > + *
> > > > + * This can also be though of as 2 virtual engines:
> > > > + * VE[0] = CS[0], CS[2]
> > > > + * VE[1] = CS[1], CS[3]
> > > > + *
> > > > + * This enables a use case where all engines are not equal and certain placement
> > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > + * case (logically contiguous placement, within a single engine class) is
> > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > + * bonding configurations but currently doesn't support this extension.
> > > > + */
> > > > +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> > > > +/*
> > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > + */
> > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > +	__u64 flags;		/* all undefined flags must be zero */
> > > > +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> > > > +
> > > > +	/*
> > > > +	 * width (i) * num_siblings (j) in length
> > > > +	 * index = j + i * num_siblings
> > > > +	 */
> > > > +	struct i915_engine_class_instance engines[0];
> > > > +} __attribute__ ((packed));
> > > > +
> > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > index 7faa46cde088..64c539486ee4 100644
> > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > @@ -82,4 +82,55 @@ https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fspec.oneapi.com%2Flevel-zero%2Flatest%2Fcore%2Fapi.html%23ze-command-queue-priorit&amp;data=04%7C01%7Cchristian.koenig%40amd.com%7C49a7557f4e494090755608d91ae758a6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637570403202969375%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=dn3PVdxYQpkpWIru5eAXHgbfuLDkppAA5daV5sHQF7s%3D&amp;reserved=0
> > > >    New parallel submission uAPI
> > > >    ============================
> > > > -Details to come in a following patch.
> > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > +
> > > > +The new parallel submission uAPI consists of 3 parts:
> > > > +
> > > > +* Export engines logical mapping
> > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > +  submission
> > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > +
> > > > +Export engines logical mapping
> > > > +------------------------------
> > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > +submission interface currently only supports submitting multiple contexts to
> > > > +engines in logical order which is a new requirement compared to execlists.
> > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > +
> > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > +logical instance has been returned and a new field,
> > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > +
> > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > +------------------------------------------------------------------------
> > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > +It is setup step that should be called before using any of the contexts. See
> > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > +support GuC submission. Execlist support can be added later if needed.
> > > > +
> > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > +
> > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > +-------------------------------------------------------------------
> > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > +the IOCTL.
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-20 10:57           ` Tvrtko Ursulin
@ 2021-05-20 19:41             ` Daniel Vetter
  -1 siblings, 0 replies; 54+ messages in thread
From: Daniel Vetter @ 2021-05-20 19:41 UTC (permalink / raw)
  To: Tvrtko Ursulin
  Cc: Matthew Brost, intel-gfx, dri-devel, Jason Ekstrand, Mesa Dev,
	Daniel Vetter, karl, Christian König

On Thu, May 20, 2021 at 11:57:44AM +0100, Tvrtko Ursulin wrote:
> 
> On 20/05/2021 10:54, Daniel Vetter wrote:
> > On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
> > > 
> > > On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > > > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > > 
> > > > > v2:
> > > > >   (Daniel Vetter):
> > > > >    - Expand logical order explaination
> > > > >    - Add dummy header
> > > > >    - Only allow N BBs in execbuf IOCTL
> > > > >    - Configure parallel submission per slot not per gem context
> > > > > 
> > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > ---
> > > > >   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > >   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > >   2 files changed, 196 insertions(+), 1 deletion(-)
> > > > >   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > 
> > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > new file mode 100644
> > > > > index 000000000000..8c64b983ccad
> > > > > --- /dev/null
> > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > @@ -0,0 +1,144 @@
> > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > +
> > > > > +/*
> > > > > + * i915_context_engines_parallel_submit:
> > > > > + *
> > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > + * the slots configuration).
> > > > > + *
> > > > > + * Their are two currently defined ways to control the placement of the
> > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > + * interface below above the flags.
> > > > > + *
> > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > + * placement configuration isn't supported on the platform / submission
> > > > > + * interface.
> > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > + * inteface.
> > > > > + */
> > > > > +struct i915_context_engines_parallel_submit {
> > > > > +   struct i915_user_extension base;
> > > > > +
> > > > > +   __u16 engine_index;     /* slot for parallel engine */
> > > > > +   __u16 width;            /* number of contexts per parallel engine */
> > > > > +   __u16 num_siblings;     /* number of siblings per context */
> > > > > +   __u16 mbz16;
> > > > 
> > > > Ok the big picture looks reasonable now, the flags still confuse me.
> > > > 
> > > 
> > > Yea, it is a bit confusing.
> > > 
> > > > > +/*
> > > > > + * Default placement behvavior (currently unsupported):
> > > > > + *
> > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > + *
> > > > > + * Example 1 pseudo code:
> > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS0[0], CS1[0]
> > > > > + * CS0[0], CS1[1]
> > > > > + * CS0[1], CS1[0]
> > > > > + * CS0[1], CS1[1]
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > + *
> > > > > + * Example 2 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + * CS[0], CS[2]
> > > > > + * CS[1], CS[0]
> > > > > + * CS[1], CS[2]
> > > > > + * CS[2], CS[0]
> > > > > + * CS[2], CS[1]
> > > > > + *
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > +
> > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > + * engine classes.
> > > > > + */
> > > > 
> > > > So I don't really get what this does compared to setting the flag below.
> > > > Is this just about running the batchbuffers the wrong way round, i.e. if
> > > > you have (simplest case)
> > > > 
> > > > width=2, num_sibglings=1, engines=CS[0], CS[1]
> > > > 
> > > > Then both
> > > > CS[0], CS[1]
> > > > and
> > > > CS[1], CS[0]
> > > > are possible options for running 2 batches? Iow, the backend is allowed to
> > > > run the batchbuffers the wrong way round, which gains us nothing, since we
> > > > assume the batches take equally long and engines interchangeable. There is
> > > > no scheduling scenario where this additional flexibility can help.
> > > > 
> > > > Also we don't have flags to select the only available and then specify an
> > > > entire pipe dream about what the non-flag mode does, without an
> > > > implementation. What is this about?
> > > > 
> > > > If it's just "because bonded allowed this" then I think we should just
> > > > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > > > welp.
> > > > 
> > > 
> > > High level the flags came out of internal discussions how this interface
> > > should look. The default placement behavior is theoretically possible
> > > with execlists but has no use cases. The GuC supports / current use
> > > cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
> > > 
> > > Argued about for months and this is where we landed. At the end of the
> > > day I think we needed to show that this interface supports more
> > > placement rules than what the GuC supports / current use cases to future
> > > proof this interface.
> > > 
> > > For what is it worth it seems kinda backwards that we landed on the
> > > default behavior not being supported in our current stack / HW.
> > 
> > Yeah I think that should be inverted, doesn't make sense.
> > 
> > What I still don't get (and I've read Tvrtko's reply with the example)
> > is what exactly is the difference between implicit and not implicit
> > mode? Can you do a single example where the only difference is whether
> > this flag is set, and then explain with that what are the actual
> > differences in scheduling options that the backend is allowed to pick
> > for the set of N patches?
> > 
> > I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
> 
> 2-wide compute context:
> 
>  .engine_map([-1, -1])
>  .load_balance(0: [cs0, cs1, cs2, cs3]) // place virtual engine at slot 0
>  .load_balance(1: [cs0, cs1, cs2, cs3])
>  .set_parallel()
> 
> This tells the scheduler any two of the four possible engines can be used. cs0 + cs3 is fine, cs3 + cs1 also, ... any. Only implicit rule is they have to be different and that works for all.
> 
> 2-wide "implicit bonds mode" aka media fixed function limitation:
> 
>  .engine_map([-1, -1])
>  .load_balance(0: [cs0, cs2])
>  .load_balance(1: [cs1, cs3])
>  .set_parallel(flags = implicit_bond)
> 
> Think of implicit flag creating a "link" between vertical columns in each virtual engine slot. So valid pairs end up cs0 + cs1 and cs2 + cs3 only.
> 
> You can also think of the implicit flag as a shortcut to avoid specifying bonds via the existing extension. In which case context setup would be written along the lines of:
> 
>  .engine_map([-1, -1])
>  .load_balance(0: [cs0, cs2])
>  .load_balance(1: [cs1, cs3])
>  .bond(1: master = cs0, bond = [cs1])
>  .bond(1: master = cs2, bond = [cs3])
>  .set_parallel()
> 
> So the implicit flag is just a shortcut to avoid typing the bonds. Not really needed as explained in my previous reply.

Ah now I get both what this means, why it exists and where it's all come
from. With the backstory makes a bunch more sense now. Thanks for
explaining again.

> This was at least the "old" set_parallel. I see this latest RFC changed
> things a bit which I don't really follow yet.
> 
> It's not perfect but needs to add very little (just one context
> extension, on top of multi batch execbuf which is needed anyways),
> doesn't need to deprecate anything, didn't require rewrites of the UMD,
> and it all works today and in the future.
> 
> I did not really like this new uapi for all the reasons I listed
> already, but as not many people were seeing the advantage of not
> churning on the uapi, if we are churning already I did suggests a
> different idea. I mean if we are churning we might as well go full in.
> So that proposal, which didn't get any traction, was along the lines of:
> 
>  .engine_map([-1])
>  .load_balance_wide(0: width=2, engines=[[cs0, cs2], [cs1, cs3]])
> 
> This would create an explicit wide virtual engine which should work for
> GuC fine I think. For execlists it may require a bit of extra glue but I
> don't think too much.
> 
> Advantage is there is one engine in the map now and it is N-wide by
> definition.
> 
> Since no one did bite on that idea back then, I didn't really pursue is
> to see if it works for all use cases. But I think it should even if it
> probably requires further thinking to be sure.
> 
> If we apply it to compute use case..
> 
>  .engine_map([-1])
>  .load_balance_wide(0: width=2, engines=[[cs0, cs1, cs2, cs3], [cs0, cs1, cs2, cs3]])
> 
> This means the only implicit wart in there is that cs0 + cs0 obviously
> shouldn't be picked. But that should be fine both for execlists and
> hopefully for the GuC.

Yeah. Another option would be to simply allow any valid pair to be listed.
Gets maybe a bit too long for full combinatorials. Or we do an N-out-of-M
load balance, and you just specifiy the one vector for the engine set that
gets fully combined.

Either way I think simple to add if/when compute comes around and asks for
it.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-20 19:41             ` Daniel Vetter
  0 siblings, 0 replies; 54+ messages in thread
From: Daniel Vetter @ 2021-05-20 19:41 UTC (permalink / raw)
  To: Tvrtko Ursulin
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Mesa Dev, Daniel Vetter,
	karl, Christian König

On Thu, May 20, 2021 at 11:57:44AM +0100, Tvrtko Ursulin wrote:
> 
> On 20/05/2021 10:54, Daniel Vetter wrote:
> > On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
> > > 
> > > On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > > > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > > 
> > > > > v2:
> > > > >   (Daniel Vetter):
> > > > >    - Expand logical order explaination
> > > > >    - Add dummy header
> > > > >    - Only allow N BBs in execbuf IOCTL
> > > > >    - Configure parallel submission per slot not per gem context
> > > > > 
> > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > ---
> > > > >   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > >   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > >   2 files changed, 196 insertions(+), 1 deletion(-)
> > > > >   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > 
> > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > new file mode 100644
> > > > > index 000000000000..8c64b983ccad
> > > > > --- /dev/null
> > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > @@ -0,0 +1,144 @@
> > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > +
> > > > > +/*
> > > > > + * i915_context_engines_parallel_submit:
> > > > > + *
> > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > + * the slots configuration).
> > > > > + *
> > > > > + * Their are two currently defined ways to control the placement of the
> > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > + * interface below above the flags.
> > > > > + *
> > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > + * placement configuration isn't supported on the platform / submission
> > > > > + * interface.
> > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > + * inteface.
> > > > > + */
> > > > > +struct i915_context_engines_parallel_submit {
> > > > > +   struct i915_user_extension base;
> > > > > +
> > > > > +   __u16 engine_index;     /* slot for parallel engine */
> > > > > +   __u16 width;            /* number of contexts per parallel engine */
> > > > > +   __u16 num_siblings;     /* number of siblings per context */
> > > > > +   __u16 mbz16;
> > > > 
> > > > Ok the big picture looks reasonable now, the flags still confuse me.
> > > > 
> > > 
> > > Yea, it is a bit confusing.
> > > 
> > > > > +/*
> > > > > + * Default placement behvavior (currently unsupported):
> > > > > + *
> > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > + *
> > > > > + * Example 1 pseudo code:
> > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS0[0], CS1[0]
> > > > > + * CS0[0], CS1[1]
> > > > > + * CS0[1], CS1[0]
> > > > > + * CS0[1], CS1[1]
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > + *
> > > > > + * Example 2 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + * CS[0], CS[2]
> > > > > + * CS[1], CS[0]
> > > > > + * CS[1], CS[2]
> > > > > + * CS[2], CS[0]
> > > > > + * CS[2], CS[1]
> > > > > + *
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > +
> > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > + * engine classes.
> > > > > + */
> > > > 
> > > > So I don't really get what this does compared to setting the flag below.
> > > > Is this just about running the batchbuffers the wrong way round, i.e. if
> > > > you have (simplest case)
> > > > 
> > > > width=2, num_sibglings=1, engines=CS[0], CS[1]
> > > > 
> > > > Then both
> > > > CS[0], CS[1]
> > > > and
> > > > CS[1], CS[0]
> > > > are possible options for running 2 batches? Iow, the backend is allowed to
> > > > run the batchbuffers the wrong way round, which gains us nothing, since we
> > > > assume the batches take equally long and engines interchangeable. There is
> > > > no scheduling scenario where this additional flexibility can help.
> > > > 
> > > > Also we don't have flags to select the only available and then specify an
> > > > entire pipe dream about what the non-flag mode does, without an
> > > > implementation. What is this about?
> > > > 
> > > > If it's just "because bonded allowed this" then I think we should just
> > > > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > > > welp.
> > > > 
> > > 
> > > High level the flags came out of internal discussions how this interface
> > > should look. The default placement behavior is theoretically possible
> > > with execlists but has no use cases. The GuC supports / current use
> > > cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
> > > 
> > > Argued about for months and this is where we landed. At the end of the
> > > day I think we needed to show that this interface supports more
> > > placement rules than what the GuC supports / current use cases to future
> > > proof this interface.
> > > 
> > > For what is it worth it seems kinda backwards that we landed on the
> > > default behavior not being supported in our current stack / HW.
> > 
> > Yeah I think that should be inverted, doesn't make sense.
> > 
> > What I still don't get (and I've read Tvrtko's reply with the example)
> > is what exactly is the difference between implicit and not implicit
> > mode? Can you do a single example where the only difference is whether
> > this flag is set, and then explain with that what are the actual
> > differences in scheduling options that the backend is allowed to pick
> > for the set of N patches?
> > 
> > I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
> 
> 2-wide compute context:
> 
>  .engine_map([-1, -1])
>  .load_balance(0: [cs0, cs1, cs2, cs3]) // place virtual engine at slot 0
>  .load_balance(1: [cs0, cs1, cs2, cs3])
>  .set_parallel()
> 
> This tells the scheduler any two of the four possible engines can be used. cs0 + cs3 is fine, cs3 + cs1 also, ... any. Only implicit rule is they have to be different and that works for all.
> 
> 2-wide "implicit bonds mode" aka media fixed function limitation:
> 
>  .engine_map([-1, -1])
>  .load_balance(0: [cs0, cs2])
>  .load_balance(1: [cs1, cs3])
>  .set_parallel(flags = implicit_bond)
> 
> Think of implicit flag creating a "link" between vertical columns in each virtual engine slot. So valid pairs end up cs0 + cs1 and cs2 + cs3 only.
> 
> You can also think of the implicit flag as a shortcut to avoid specifying bonds via the existing extension. In which case context setup would be written along the lines of:
> 
>  .engine_map([-1, -1])
>  .load_balance(0: [cs0, cs2])
>  .load_balance(1: [cs1, cs3])
>  .bond(1: master = cs0, bond = [cs1])
>  .bond(1: master = cs2, bond = [cs3])
>  .set_parallel()
> 
> So the implicit flag is just a shortcut to avoid typing the bonds. Not really needed as explained in my previous reply.

Ah now I get both what this means, why it exists and where it's all come
from. With the backstory makes a bunch more sense now. Thanks for
explaining again.

> This was at least the "old" set_parallel. I see this latest RFC changed
> things a bit which I don't really follow yet.
> 
> It's not perfect but needs to add very little (just one context
> extension, on top of multi batch execbuf which is needed anyways),
> doesn't need to deprecate anything, didn't require rewrites of the UMD,
> and it all works today and in the future.
> 
> I did not really like this new uapi for all the reasons I listed
> already, but as not many people were seeing the advantage of not
> churning on the uapi, if we are churning already I did suggests a
> different idea. I mean if we are churning we might as well go full in.
> So that proposal, which didn't get any traction, was along the lines of:
> 
>  .engine_map([-1])
>  .load_balance_wide(0: width=2, engines=[[cs0, cs2], [cs1, cs3]])
> 
> This would create an explicit wide virtual engine which should work for
> GuC fine I think. For execlists it may require a bit of extra glue but I
> don't think too much.
> 
> Advantage is there is one engine in the map now and it is N-wide by
> definition.
> 
> Since no one did bite on that idea back then, I didn't really pursue is
> to see if it works for all use cases. But I think it should even if it
> probably requires further thinking to be sure.
> 
> If we apply it to compute use case..
> 
>  .engine_map([-1])
>  .load_balance_wide(0: width=2, engines=[[cs0, cs1, cs2, cs3], [cs0, cs1, cs2, cs3]])
> 
> This means the only implicit wart in there is that cs0 + cs0 obviously
> shouldn't be picked. But that should be fine both for execlists and
> hopefully for the GuC.

Yeah. Another option would be to simply allow any valid pair to be listed.
Gets maybe a bit too long for full combinatorials. Or we do an N-out-of-M
load balance, and you just specifiy the one vector for the engine set that
gets fully combined.

Either way I think simple to add if/when compute comes around and asks for
it.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-20 15:10           ` Matthew Brost
@ 2021-05-20 19:44             ` Daniel Vetter
  -1 siblings, 0 replies; 54+ messages in thread
From: Daniel Vetter @ 2021-05-20 19:44 UTC (permalink / raw)
  To: Matthew Brost
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Mesa Dev, Daniel Vetter,
	karl, Christian König

On Thu, May 20, 2021 at 08:10:59AM -0700, Matthew Brost wrote:
> On Thu, May 20, 2021 at 11:54:25AM +0200, Daniel Vetter wrote:
> > On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
> > >
> > > On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > > > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > >
> > > > > v2:
> > > > >  (Daniel Vetter):
> > > > >   - Expand logical order explaination
> > > > >   - Add dummy header
> > > > >   - Only allow N BBs in execbuf IOCTL
> > > > >   - Configure parallel submission per slot not per gem context
> > > > >
> > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > ---
> > > > >  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > >  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > >  2 files changed, 196 insertions(+), 1 deletion(-)
> > > > >  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > >
> > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > new file mode 100644
> > > > > index 000000000000..8c64b983ccad
> > > > > --- /dev/null
> > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > @@ -0,0 +1,144 @@
> > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > +
> > > > > +/*
> > > > > + * i915_context_engines_parallel_submit:
> > > > > + *
> > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > + * the slots configuration).
> > > > > + *
> > > > > + * Their are two currently defined ways to control the placement of the
> > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > + * interface below above the flags.
> > > > > + *
> > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > + * placement configuration isn't supported on the platform / submission
> > > > > + * interface.
> > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > + * inteface.
> > > > > + */
> > > > > +struct i915_context_engines_parallel_submit {
> > > > > +   struct i915_user_extension base;
> > > > > +
> > > > > +   __u16 engine_index;     /* slot for parallel engine */
> > > > > +   __u16 width;            /* number of contexts per parallel engine */
> > > > > +   __u16 num_siblings;     /* number of siblings per context */
> > > > > +   __u16 mbz16;
> > > >
> > > > Ok the big picture looks reasonable now, the flags still confuse me.
> > > >
> > >
> > > Yea, it is a bit confusing.
> > >
> > > > > +/*
> > > > > + * Default placement behvavior (currently unsupported):
> > > > > + *
> > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > + *
> > > > > + * Example 1 pseudo code:
> > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS0[0], CS1[0]
> > > > > + * CS0[0], CS1[1]
> > > > > + * CS0[1], CS1[0]
> > > > > + * CS0[1], CS1[1]
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > + *
> > > > > + * Example 2 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + * CS[0], CS[2]
> > > > > + * CS[1], CS[0]
> > > > > + * CS[1], CS[2]
> > > > > + * CS[2], CS[0]
> > > > > + * CS[2], CS[1]
> > > > > + *
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > +
> > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > + * engine classes.
> > > > > + */
> > > >
> > > > So I don't really get what this does compared to setting the flag below.
> > > > Is this just about running the batchbuffers the wrong way round, i.e. if
> > > > you have (simplest case)
> > > >
> > > > width=2, num_sibglings=1, engines=CS[0], CS[1]
> > > >
> > > > Then both
> > > > CS[0], CS[1]
> > > > and
> > > > CS[1], CS[0]
> > > > are possible options for running 2 batches? Iow, the backend is allowed to
> > > > run the batchbuffers the wrong way round, which gains us nothing, since we
> > > > assume the batches take equally long and engines interchangeable. There is
> > > > no scheduling scenario where this additional flexibility can help.
> > > >
> > > > Also we don't have flags to select the only available and then specify an
> > > > entire pipe dream about what the non-flag mode does, without an
> > > > implementation. What is this about?
> > > >
> > > > If it's just "because bonded allowed this" then I think we should just
> > > > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > > > welp.
> > > >
> > >
> > > High level the flags came out of internal discussions how this interface
> > > should look. The default placement behavior is theoretically possible
> > > with execlists but has no use cases. The GuC supports / current use
> > > cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
> > >
> > > Argued about for months and this is where we landed. At the end of the
> > > day I think we needed to show that this interface supports more
> > > placement rules than what the GuC supports / current use cases to future
> > > proof this interface.
> > >
> > > For what is it worth it seems kinda backwards that we landed on the
> > > default behavior not being supported in our current stack / HW.
> > 
> > Yeah I think that should be inverted, doesn't make sense.
> > 
> > What I still don't get (and I've read Tvrtko's reply with the example)
> > is what exactly is the difference between implicit and not implicit
> > mode? Can you do a single example where the only difference is whether
> > this flag is set, and then explain with that what are the actual
> > differences in scheduling options that the backend is allowed to pick
> > for the set of N patches?
> > 
> > I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
> > 
> > > > > +
> > > > > +/*
> > > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > > + * of the siblings.
> > > > > + *
> > > > > + * All of the below examples are in logical space.
> > > > > + *
> > > > > + * Example 1 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > > + *         engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + *
> > > > > + * Example 2 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > + *         engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + * CS[2], CS[3]
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS[0], CS[2]
> > > > > + * VE[1] = CS[1], CS[3]
> > > > > + *
> > > > > + * This enables a use case where all engines are not equal and certain placement
> > > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > > + * case (logically contiguous placement, within a single engine class) is
> > > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > > + * bonding configurations but currently doesn't support this extension.
> > > > > + */
> > > > > +#define I915_PARALLEL_IMPLICT_BONDS                        (1<<0)
> > > >
> > > > Does this map to intel_context_set_nopreempt(), so we could implement it
> > > > also in execlist?
> > > >
> > >
> > > intel_context_set_nopreempt is preempt is part of how this would be
> > > implemented for execlists. For GuC submission there is a algorithm
> > > between the i915 and GuC that inserts same preemption points between
> > > each set of N batches. I believe the rules are if context 1 can
> > > preempted the rest of the contexts (2 - N) can safely be preempted. A go
> > > / join algorithm, implemented with semaphores, around the batches
> > > makes sure the i915 adheres to these rules.
> > >
> > > > Also is this just an artifact of the implementation, or is this somehow
> > > > required functionality for userspace, i.e. the workload fails if e.g. GuC
> > > > decides to preempt all LRC of a parallel virtual engine? Of course just
> > > > preempting one is a bit a bug (but execlist I think happily does that).
> > > >
> > >
> > > I think it is part of the implementation / HW limitations. Basically if
> > > N batches are running in parallel if one of the batches gets preempted
> > > it can hang all the other batches even if it gets restarted. Again the
> > > idea behind this is only preempt any of these contexts between each set
> > > of N batches. The GuC has no concept of batches only contexts hence the
> > > aforementioned algorithm to insert same preemption points between each
> > > set of batches.
> > 
> > Well backend preempting one but not the other is a bug. I don't think
> > we need to talk about bugs :-)
> >
> 
> I think it is more that backend can't preempt each context atomically as these
> are running on independent engines. Let say the backend tries to preempt 2
> engines at the same time and only 1 responds, now we are broken with certain
> batches. With the algorithm implmented between the i915 and the Guc the GuC will
> try to preempt the first context if that works, all the other contexts can be
> preempted.

Ah right, we might have a workload with long non-preemptible sections, but
I guess the MI_SEMAPHORE_WAIT can always preempt. So if GuC just tries on
one of these, it will result in tears.

> > Now wrt a preempt mode in context creation, I think that makes sense.
> > I'm just wondering whether this is correct here in the parallel
> > submission (and why), or is it just an implementation artifact
> > (current backends are buggy if we'd allow them to preempt) or what's
> > going on.
> >
> > If this is just a case of "this is how current backends work,
> > userspace doesn't actually care whether we allow preempt or not" then
> > I think we should just document the behavior and that's it. Adding
> > uapi for an option for which there's not even an implementation isn't
> > great.
> > 
> 
> I don't think it is a case of 'this is how current backends work...', I think
> user space knows if it is ok for 1 of the batches to preempted and not the
> others without breaking the batches.

Yeah this makes more sense as an explanation: Currently the backend (guc
or execlist) figure out whether something can be preempted by just trying.
Since we're dealing with N contexts that's a suboptimal approach, and we
need a flag that indicates whether it's worth it or not.

So makes sense to me to have this. I guess userspace does actually need
both modes for now, depending upon what it's doing?
-Daniel

> 
> Matt
> 
> > But if we can actually choose, and userspace wants to, then I'm all
> > fine with this. And we can always move this to a more generic place if
> > other engines need preempt control later on too.
> > 
> > Cheers, Daniel
> > 
> > 
> > > Matt
> > >
> > > > Cheers, Daniel
> > > >
> > > > > +/*
> > > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > > + */
> > > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH         (1<<1)
> > > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS      (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > > +   __u64 flags;            /* all undefined flags must be zero */
> > > > > +   __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > > > +
> > > > > +   /*
> > > > > +    * width (i) * num_siblings (j) in length
> > > > > +    * index = j + i * num_siblings
> > > > > +    */
> > > > > +   struct i915_engine_class_instance engines[0];
> > > > > +} __attribute__ ((packed));
> > > > > +
> > > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > index 7faa46cde088..64c539486ee4 100644
> > > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> > > > >
> > > > >  New parallel submission uAPI
> > > > >  ============================
> > > > > -Details to come in a following patch.
> > > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > > +
> > > > > +The new parallel submission uAPI consists of 3 parts:
> > > > > +
> > > > > +* Export engines logical mapping
> > > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > > +  submission
> > > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > +
> > > > > +Export engines logical mapping
> > > > > +------------------------------
> > > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > > +submission interface currently only supports submitting multiple contexts to
> > > > > +engines in logical order which is a new requirement compared to execlists.
> > > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > > +
> > > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > > +logical instance has been returned and a new field,
> > > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > > +
> > > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > > +------------------------------------------------------------------------
> > > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > > +It is setup step that should be called before using any of the contexts. See
> > > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > > +support GuC submission. Execlist support can be added later if needed.
> > > > > +
> > > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > > +
> > > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > +-------------------------------------------------------------------
> > > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > > +the IOCTL.
> > > > > --
> > > > > 2.28.0
> > > > >
> > > > > _______________________________________________
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > >
> > > > --
> > > > Daniel Vetter
> > > > Software Engineer, Intel Corporation
> > > > http://blog.ffwll.ch
> > 
> > 
> > 
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-20 19:44             ` Daniel Vetter
  0 siblings, 0 replies; 54+ messages in thread
From: Daniel Vetter @ 2021-05-20 19:44 UTC (permalink / raw)
  To: Matthew Brost
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Mesa Dev, Daniel Vetter,
	karl, Christian König

On Thu, May 20, 2021 at 08:10:59AM -0700, Matthew Brost wrote:
> On Thu, May 20, 2021 at 11:54:25AM +0200, Daniel Vetter wrote:
> > On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
> > >
> > > On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > > > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > >
> > > > > v2:
> > > > >  (Daniel Vetter):
> > > > >   - Expand logical order explaination
> > > > >   - Add dummy header
> > > > >   - Only allow N BBs in execbuf IOCTL
> > > > >   - Configure parallel submission per slot not per gem context
> > > > >
> > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > ---
> > > > >  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > >  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > >  2 files changed, 196 insertions(+), 1 deletion(-)
> > > > >  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > >
> > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > new file mode 100644
> > > > > index 000000000000..8c64b983ccad
> > > > > --- /dev/null
> > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > @@ -0,0 +1,144 @@
> > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > +
> > > > > +/*
> > > > > + * i915_context_engines_parallel_submit:
> > > > > + *
> > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > + * the slots configuration).
> > > > > + *
> > > > > + * Their are two currently defined ways to control the placement of the
> > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > + * interface below above the flags.
> > > > > + *
> > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > + * placement configuration isn't supported on the platform / submission
> > > > > + * interface.
> > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > + * inteface.
> > > > > + */
> > > > > +struct i915_context_engines_parallel_submit {
> > > > > +   struct i915_user_extension base;
> > > > > +
> > > > > +   __u16 engine_index;     /* slot for parallel engine */
> > > > > +   __u16 width;            /* number of contexts per parallel engine */
> > > > > +   __u16 num_siblings;     /* number of siblings per context */
> > > > > +   __u16 mbz16;
> > > >
> > > > Ok the big picture looks reasonable now, the flags still confuse me.
> > > >
> > >
> > > Yea, it is a bit confusing.
> > >
> > > > > +/*
> > > > > + * Default placement behvavior (currently unsupported):
> > > > > + *
> > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > + *
> > > > > + * Example 1 pseudo code:
> > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS0[0], CS1[0]
> > > > > + * CS0[0], CS1[1]
> > > > > + * CS0[1], CS1[0]
> > > > > + * CS0[1], CS1[1]
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > + *
> > > > > + * Example 2 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + * CS[0], CS[2]
> > > > > + * CS[1], CS[0]
> > > > > + * CS[1], CS[2]
> > > > > + * CS[2], CS[0]
> > > > > + * CS[2], CS[1]
> > > > > + *
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > +
> > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > + * engine classes.
> > > > > + */
> > > >
> > > > So I don't really get what this does compared to setting the flag below.
> > > > Is this just about running the batchbuffers the wrong way round, i.e. if
> > > > you have (simplest case)
> > > >
> > > > width=2, num_sibglings=1, engines=CS[0], CS[1]
> > > >
> > > > Then both
> > > > CS[0], CS[1]
> > > > and
> > > > CS[1], CS[0]
> > > > are possible options for running 2 batches? Iow, the backend is allowed to
> > > > run the batchbuffers the wrong way round, which gains us nothing, since we
> > > > assume the batches take equally long and engines interchangeable. There is
> > > > no scheduling scenario where this additional flexibility can help.
> > > >
> > > > Also we don't have flags to select the only available and then specify an
> > > > entire pipe dream about what the non-flag mode does, without an
> > > > implementation. What is this about?
> > > >
> > > > If it's just "because bonded allowed this" then I think we should just
> > > > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > > > welp.
> > > >
> > >
> > > High level the flags came out of internal discussions how this interface
> > > should look. The default placement behavior is theoretically possible
> > > with execlists but has no use cases. The GuC supports / current use
> > > cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
> > >
> > > Argued about for months and this is where we landed. At the end of the
> > > day I think we needed to show that this interface supports more
> > > placement rules than what the GuC supports / current use cases to future
> > > proof this interface.
> > >
> > > For what is it worth it seems kinda backwards that we landed on the
> > > default behavior not being supported in our current stack / HW.
> > 
> > Yeah I think that should be inverted, doesn't make sense.
> > 
> > What I still don't get (and I've read Tvrtko's reply with the example)
> > is what exactly is the difference between implicit and not implicit
> > mode? Can you do a single example where the only difference is whether
> > this flag is set, and then explain with that what are the actual
> > differences in scheduling options that the backend is allowed to pick
> > for the set of N patches?
> > 
> > I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
> > 
> > > > > +
> > > > > +/*
> > > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > > + * of the siblings.
> > > > > + *
> > > > > + * All of the below examples are in logical space.
> > > > > + *
> > > > > + * Example 1 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > > + *         engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + *
> > > > > + * Example 2 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > + *         engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + * CS[2], CS[3]
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS[0], CS[2]
> > > > > + * VE[1] = CS[1], CS[3]
> > > > > + *
> > > > > + * This enables a use case where all engines are not equal and certain placement
> > > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > > + * case (logically contiguous placement, within a single engine class) is
> > > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > > + * bonding configurations but currently doesn't support this extension.
> > > > > + */
> > > > > +#define I915_PARALLEL_IMPLICT_BONDS                        (1<<0)
> > > >
> > > > Does this map to intel_context_set_nopreempt(), so we could implement it
> > > > also in execlist?
> > > >
> > >
> > > intel_context_set_nopreempt is preempt is part of how this would be
> > > implemented for execlists. For GuC submission there is a algorithm
> > > between the i915 and GuC that inserts same preemption points between
> > > each set of N batches. I believe the rules are if context 1 can
> > > preempted the rest of the contexts (2 - N) can safely be preempted. A go
> > > / join algorithm, implemented with semaphores, around the batches
> > > makes sure the i915 adheres to these rules.
> > >
> > > > Also is this just an artifact of the implementation, or is this somehow
> > > > required functionality for userspace, i.e. the workload fails if e.g. GuC
> > > > decides to preempt all LRC of a parallel virtual engine? Of course just
> > > > preempting one is a bit a bug (but execlist I think happily does that).
> > > >
> > >
> > > I think it is part of the implementation / HW limitations. Basically if
> > > N batches are running in parallel if one of the batches gets preempted
> > > it can hang all the other batches even if it gets restarted. Again the
> > > idea behind this is only preempt any of these contexts between each set
> > > of N batches. The GuC has no concept of batches only contexts hence the
> > > aforementioned algorithm to insert same preemption points between each
> > > set of batches.
> > 
> > Well backend preempting one but not the other is a bug. I don't think
> > we need to talk about bugs :-)
> >
> 
> I think it is more that backend can't preempt each context atomically as these
> are running on independent engines. Let say the backend tries to preempt 2
> engines at the same time and only 1 responds, now we are broken with certain
> batches. With the algorithm implmented between the i915 and the Guc the GuC will
> try to preempt the first context if that works, all the other contexts can be
> preempted.

Ah right, we might have a workload with long non-preemptible sections, but
I guess the MI_SEMAPHORE_WAIT can always preempt. So if GuC just tries on
one of these, it will result in tears.

> > Now wrt a preempt mode in context creation, I think that makes sense.
> > I'm just wondering whether this is correct here in the parallel
> > submission (and why), or is it just an implementation artifact
> > (current backends are buggy if we'd allow them to preempt) or what's
> > going on.
> >
> > If this is just a case of "this is how current backends work,
> > userspace doesn't actually care whether we allow preempt or not" then
> > I think we should just document the behavior and that's it. Adding
> > uapi for an option for which there's not even an implementation isn't
> > great.
> > 
> 
> I don't think it is a case of 'this is how current backends work...', I think
> user space knows if it is ok for 1 of the batches to preempted and not the
> others without breaking the batches.

Yeah this makes more sense as an explanation: Currently the backend (guc
or execlist) figure out whether something can be preempted by just trying.
Since we're dealing with N contexts that's a suboptimal approach, and we
need a flag that indicates whether it's worth it or not.

So makes sense to me to have this. I guess userspace does actually need
both modes for now, depending upon what it's doing?
-Daniel

> 
> Matt
> 
> > But if we can actually choose, and userspace wants to, then I'm all
> > fine with this. And we can always move this to a more generic place if
> > other engines need preempt control later on too.
> > 
> > Cheers, Daniel
> > 
> > 
> > > Matt
> > >
> > > > Cheers, Daniel
> > > >
> > > > > +/*
> > > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > > + */
> > > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH         (1<<1)
> > > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS      (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > > +   __u64 flags;            /* all undefined flags must be zero */
> > > > > +   __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > > > +
> > > > > +   /*
> > > > > +    * width (i) * num_siblings (j) in length
> > > > > +    * index = j + i * num_siblings
> > > > > +    */
> > > > > +   struct i915_engine_class_instance engines[0];
> > > > > +} __attribute__ ((packed));
> > > > > +
> > > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > index 7faa46cde088..64c539486ee4 100644
> > > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> > > > >
> > > > >  New parallel submission uAPI
> > > > >  ============================
> > > > > -Details to come in a following patch.
> > > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > > +
> > > > > +The new parallel submission uAPI consists of 3 parts:
> > > > > +
> > > > > +* Export engines logical mapping
> > > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > > +  submission
> > > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > +
> > > > > +Export engines logical mapping
> > > > > +------------------------------
> > > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > > +submission interface currently only supports submitting multiple contexts to
> > > > > +engines in logical order which is a new requirement compared to execlists.
> > > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > > +
> > > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > > +logical instance has been returned and a new field,
> > > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > > +
> > > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > > +------------------------------------------------------------------------
> > > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > > +It is setup step that should be called before using any of the contexts. See
> > > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > > +support GuC submission. Execlist support can be added later if needed.
> > > > > +
> > > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > > +
> > > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > +-------------------------------------------------------------------
> > > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > > +the IOCTL.
> > > > > --
> > > > > 2.28.0
> > > > >
> > > > > _______________________________________________
> > > > > Intel-gfx mailing list
> > > > > Intel-gfx@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > >
> > > > --
> > > > Daniel Vetter
> > > > Software Engineer, Intel Corporation
> > > > http://blog.ffwll.ch
> > 
> > 
> > 
> > --
> > Daniel Vetter
> > Software Engineer, Intel Corporation
> > http://blog.ffwll.ch

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-20 15:39           ` [Intel-gfx] " Matthew Brost
@ 2021-05-20 21:38             ` Jason Ekstrand
  -1 siblings, 0 replies; 54+ messages in thread
From: Jason Ekstrand @ 2021-05-20 21:38 UTC (permalink / raw)
  To: Matthew Brost
  Cc: Christian König, Intel GFX, Maling list - DRI developers,
	Jason Ekstrand, ML mesa-dev, Daniel Vetter, karl,
	Christian König

On Thu, May 20, 2021 at 10:46 AM Matthew Brost <matthew.brost@intel.com> wrote:
>
> On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote:
> > Am 19.05.21 um 18:51 schrieb Matthew Brost:
> > > On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
> > > > Oh, yeah we call that gang submit on the AMD side.
> > > >
> > > > Had already some internal discussions how to implement this, but so far
> > > > couldn't figure out how to cleanly introduce that into the DRM scheduler.
> > > >
> > > > Can you briefly describe in a few words how that is supposed to work on the
> > > > Intel side?

On Intel, we actually have two cases which don't fit the current
drm/scheduler model well: balanced and bonded.

In the balanced model, we want to submit a batch which can go to any
one of some set of engines and we don't care which.  It's up to the
kernel to pick an engine.  Imagine you had 64 identical HW compute
queues, for instance.  This could be done by making all the identical
engines share a single drm_gpu_scheduler and round-robin around the HW
queues or something.  I don't know that we strictly need drm/scheduler
to be aware of it but it might be nice if it grew support for this
mode so we could maintain a 1:1 relationship between HW queues and
drm_gpu_schedulers.  That said, I'm not sure how this would play with
GuC queues so maybe it doesn't help?

The bonded model is like your ganged, I think.  We want to submit N
batches to run in parallel.  And they actually have to be executing on
the GPU simultaneously and not just sort-of at similar times.  We need
this for video.  There are also potential use-cases in Vulkan or even
GL that might be able to use this.  One difference with the balanced
mode is that bonds don't, strictly speaking, need to be on the same
type of engine.  Imagine, for instance, a 3D batch with a parallel
compute batch doing vertex pre-processing.

I'm pretty sure the bonded case is something that the mobile drivers
(panfrost, etc.) would like as well for doing Vulkan on tilers where
you often have to have two command buffers running in parallel.
They're currently doing it by submitting a giant pile of batches where
they split the batch and add sync primitives every time some GL call
requires them to sync between fragment and vertex pipes.

So, to sum up, I think there's likely some good collaboration to be
had here for everyone. :-)

--Jason

> > > Sure, I've done a quick PoC internally and have been able to hook this
> > > into the DRM scheduler.
> > >
> > > Basically each BB still maps to a single job as each job is somewhat
> > > unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
> > > the jobs configured to run in parallel map to a single sched_entity
> > > which maintains the order each job was generated from the execbuf IOCTL
> > > (1 - N). When the backend receives jobs 1 to N - 1 it basically just
> > > updates some internal state. When the backend sees job N (last job) it
> > > actually does the submit for jobs 1 - N which with GuC submission is a
> > > simple command moving the LRC tail of the N jobs.
> > >
> > > Daniel has suggested that we create a single job for the NN BBs but that
> > > would be huge rework to the internals of the i915 and likely won't
> > > happen by the time this code first lands.
> > >
> > > Also worth noting one way a job isn't really a treated individually is
> > > the excl slot with dma-resv. In that case we create a composite fence of
> > > all jobs (dma_fence_array).
> >
> > Yeah, that's something we have discussed as well.
> >
> > How do you prevent the scheduler from over committing to a single ring
> > buffer in this scenario?
> >
>
> Each job has its own ring, the execbuf IOCTL throttles itself for each
> job if there isn't space in the ring. This is exactly the same as
> non-parallel submits.
>
> I think this is what you were asking? If not, maybe try explaining the
> question a bit more.
>
> Matt
>
> > Christian.
> >
> > >
> > > Matt
> > >
> > > > Thanks,
> > > > Christian.
> > > >
> > > > Am 19.05.21 um 01:58 schrieb Matthew Brost:
> > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > >
> > > > > v2:
> > > > >    (Daniel Vetter):
> > > > >     - Expand logical order explaination
> > > > >     - Add dummy header
> > > > >     - Only allow N BBs in execbuf IOCTL
> > > > >     - Configure parallel submission per slot not per gem context
> > > > >
> > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > ---
> > > > >    Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > >    Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > >    2 files changed, 196 insertions(+), 1 deletion(-)
> > > > >    create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > >
> > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > new file mode 100644
> > > > > index 000000000000..8c64b983ccad
> > > > > --- /dev/null
> > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > @@ -0,0 +1,144 @@
> > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > +
> > > > > +/*
> > > > > + * i915_context_engines_parallel_submit:
> > > > > + *
> > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > + * the slots configuration).
> > > > > + *
> > > > > + * Their are two currently defined ways to control the placement of the
> > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > + * interface below above the flags.
> > > > > + *
> > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > + * placement configuration isn't supported on the platform / submission
> > > > > + * interface.
> > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > + * inteface.
> > > > > + */
> > > > > +struct i915_context_engines_parallel_submit {
> > > > > +       struct i915_user_extension base;
> > > > > +
> > > > > +       __u16 engine_index;     /* slot for parallel engine */
> > > > > +       __u16 width;            /* number of contexts per parallel engine */
> > > > > +       __u16 num_siblings;     /* number of siblings per context */
> > > > > +       __u16 mbz16;
> > > > > +/*
> > > > > + * Default placement behvavior (currently unsupported):
> > > > > + *
> > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > + *
> > > > > + * Example 1 pseudo code:
> > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > + *             engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS0[0], CS1[0]
> > > > > + * CS0[0], CS1[1]
> > > > > + * CS0[1], CS1[0]
> > > > > + * CS0[1], CS1[1]
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > + *
> > > > > + * Example 2 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > + *             engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + * CS[0], CS[2]
> > > > > + * CS[1], CS[0]
> > > > > + * CS[1], CS[2]
> > > > > + * CS[2], CS[0]
> > > > > + * CS[2], CS[1]
> > > > > + *
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > +
> > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > + * engine classes.
> > > > > + */
> > > > > +
> > > > > +/*
> > > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > > + * of the siblings.
> > > > > + *
> > > > > + * All of the below examples are in logical space.
> > > > > + *
> > > > > + * Example 1 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > > + *             engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + *
> > > > > + * Example 2 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > + *             engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + * CS[2], CS[3]
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS[0], CS[2]
> > > > > + * VE[1] = CS[1], CS[3]
> > > > > + *
> > > > > + * This enables a use case where all engines are not equal and certain placement
> > > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > > + * case (logically contiguous placement, within a single engine class) is
> > > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > > + * bonding configurations but currently doesn't support this extension.
> > > > > + */
> > > > > +#define I915_PARALLEL_IMPLICT_BONDS                    (1<<0)
> > > > > +/*
> > > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > > + */
> > > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH             (1<<1)
> > > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS  (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > > +       __u64 flags;            /* all undefined flags must be zero */
> > > > > +       __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > > > +
> > > > > +       /*
> > > > > +        * width (i) * num_siblings (j) in length
> > > > > +        * index = j + i * num_siblings
> > > > > +        */
> > > > > +       struct i915_engine_class_instance engines[0];
> > > > > +} __attribute__ ((packed));
> > > > > +
> > > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > index 7faa46cde088..64c539486ee4 100644
> > > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > @@ -82,4 +82,55 @@ https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fspec.oneapi.com%2Flevel-zero%2Flatest%2Fcore%2Fapi.html%23ze-command-queue-priorit&amp;data=04%7C01%7Cchristian.koenig%40amd.com%7C49a7557f4e494090755608d91ae758a6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637570403202969375%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=dn3PVdxYQpkpWIru5eAXHgbfuLDkppAA5daV5sHQF7s%3D&amp;reserved=0
> > > > >    New parallel submission uAPI
> > > > >    ============================
> > > > > -Details to come in a following patch.
> > > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > > +
> > > > > +The new parallel submission uAPI consists of 3 parts:
> > > > > +
> > > > > +* Export engines logical mapping
> > > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > > +  submission
> > > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > +
> > > > > +Export engines logical mapping
> > > > > +------------------------------
> > > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > > +submission interface currently only supports submitting multiple contexts to
> > > > > +engines in logical order which is a new requirement compared to execlists.
> > > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > > +
> > > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > > +logical instance has been returned and a new field,
> > > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > > +
> > > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > > +------------------------------------------------------------------------
> > > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > > +It is setup step that should be called before using any of the contexts. See
> > > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > > +support GuC submission. Execlist support can be added later if needed.
> > > > > +
> > > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > > +
> > > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > +-------------------------------------------------------------------
> > > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > > +the IOCTL.
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-20 21:38             ` Jason Ekstrand
  0 siblings, 0 replies; 54+ messages in thread
From: Jason Ekstrand @ 2021-05-20 21:38 UTC (permalink / raw)
  To: Matthew Brost
  Cc: Christian König, Intel GFX, Maling list - DRI developers,
	Jason Ekstrand, ML mesa-dev, Daniel Vetter, karl,
	Christian König

On Thu, May 20, 2021 at 10:46 AM Matthew Brost <matthew.brost@intel.com> wrote:
>
> On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote:
> > Am 19.05.21 um 18:51 schrieb Matthew Brost:
> > > On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
> > > > Oh, yeah we call that gang submit on the AMD side.
> > > >
> > > > Had already some internal discussions how to implement this, but so far
> > > > couldn't figure out how to cleanly introduce that into the DRM scheduler.
> > > >
> > > > Can you briefly describe in a few words how that is supposed to work on the
> > > > Intel side?

On Intel, we actually have two cases which don't fit the current
drm/scheduler model well: balanced and bonded.

In the balanced model, we want to submit a batch which can go to any
one of some set of engines and we don't care which.  It's up to the
kernel to pick an engine.  Imagine you had 64 identical HW compute
queues, for instance.  This could be done by making all the identical
engines share a single drm_gpu_scheduler and round-robin around the HW
queues or something.  I don't know that we strictly need drm/scheduler
to be aware of it but it might be nice if it grew support for this
mode so we could maintain a 1:1 relationship between HW queues and
drm_gpu_schedulers.  That said, I'm not sure how this would play with
GuC queues so maybe it doesn't help?

The bonded model is like your ganged, I think.  We want to submit N
batches to run in parallel.  And they actually have to be executing on
the GPU simultaneously and not just sort-of at similar times.  We need
this for video.  There are also potential use-cases in Vulkan or even
GL that might be able to use this.  One difference with the balanced
mode is that bonds don't, strictly speaking, need to be on the same
type of engine.  Imagine, for instance, a 3D batch with a parallel
compute batch doing vertex pre-processing.

I'm pretty sure the bonded case is something that the mobile drivers
(panfrost, etc.) would like as well for doing Vulkan on tilers where
you often have to have two command buffers running in parallel.
They're currently doing it by submitting a giant pile of batches where
they split the batch and add sync primitives every time some GL call
requires them to sync between fragment and vertex pipes.

So, to sum up, I think there's likely some good collaboration to be
had here for everyone. :-)

--Jason

> > > Sure, I've done a quick PoC internally and have been able to hook this
> > > into the DRM scheduler.
> > >
> > > Basically each BB still maps to a single job as each job is somewhat
> > > unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
> > > the jobs configured to run in parallel map to a single sched_entity
> > > which maintains the order each job was generated from the execbuf IOCTL
> > > (1 - N). When the backend receives jobs 1 to N - 1 it basically just
> > > updates some internal state. When the backend sees job N (last job) it
> > > actually does the submit for jobs 1 - N which with GuC submission is a
> > > simple command moving the LRC tail of the N jobs.
> > >
> > > Daniel has suggested that we create a single job for the NN BBs but that
> > > would be huge rework to the internals of the i915 and likely won't
> > > happen by the time this code first lands.
> > >
> > > Also worth noting one way a job isn't really a treated individually is
> > > the excl slot with dma-resv. In that case we create a composite fence of
> > > all jobs (dma_fence_array).
> >
> > Yeah, that's something we have discussed as well.
> >
> > How do you prevent the scheduler from over committing to a single ring
> > buffer in this scenario?
> >
>
> Each job has its own ring, the execbuf IOCTL throttles itself for each
> job if there isn't space in the ring. This is exactly the same as
> non-parallel submits.
>
> I think this is what you were asking? If not, maybe try explaining the
> question a bit more.
>
> Matt
>
> > Christian.
> >
> > >
> > > Matt
> > >
> > > > Thanks,
> > > > Christian.
> > > >
> > > > Am 19.05.21 um 01:58 schrieb Matthew Brost:
> > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > >
> > > > > v2:
> > > > >    (Daniel Vetter):
> > > > >     - Expand logical order explaination
> > > > >     - Add dummy header
> > > > >     - Only allow N BBs in execbuf IOCTL
> > > > >     - Configure parallel submission per slot not per gem context
> > > > >
> > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > ---
> > > > >    Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > >    Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > >    2 files changed, 196 insertions(+), 1 deletion(-)
> > > > >    create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > >
> > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > new file mode 100644
> > > > > index 000000000000..8c64b983ccad
> > > > > --- /dev/null
> > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > @@ -0,0 +1,144 @@
> > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > +
> > > > > +/*
> > > > > + * i915_context_engines_parallel_submit:
> > > > > + *
> > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > + * the slots configuration).
> > > > > + *
> > > > > + * Their are two currently defined ways to control the placement of the
> > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > + * interface below above the flags.
> > > > > + *
> > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > + * placement configuration isn't supported on the platform / submission
> > > > > + * interface.
> > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > + * inteface.
> > > > > + */
> > > > > +struct i915_context_engines_parallel_submit {
> > > > > +       struct i915_user_extension base;
> > > > > +
> > > > > +       __u16 engine_index;     /* slot for parallel engine */
> > > > > +       __u16 width;            /* number of contexts per parallel engine */
> > > > > +       __u16 num_siblings;     /* number of siblings per context */
> > > > > +       __u16 mbz16;
> > > > > +/*
> > > > > + * Default placement behvavior (currently unsupported):
> > > > > + *
> > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > + *
> > > > > + * Example 1 pseudo code:
> > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > + *             engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS0[0], CS1[0]
> > > > > + * CS0[0], CS1[1]
> > > > > + * CS0[1], CS1[0]
> > > > > + * CS0[1], CS1[1]
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > + *
> > > > > + * Example 2 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > + *             engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + * CS[0], CS[2]
> > > > > + * CS[1], CS[0]
> > > > > + * CS[1], CS[2]
> > > > > + * CS[2], CS[0]
> > > > > + * CS[2], CS[1]
> > > > > + *
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > +
> > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > + * engine classes.
> > > > > + */
> > > > > +
> > > > > +/*
> > > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > > + * of the siblings.
> > > > > + *
> > > > > + * All of the below examples are in logical space.
> > > > > + *
> > > > > + * Example 1 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > > + *             engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + *
> > > > > + * Example 2 pseudo code:
> > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > + * set_engines(INVALID)
> > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > + *             engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > + *
> > > > > + * Results in the following valid placements:
> > > > > + * CS[0], CS[1]
> > > > > + * CS[2], CS[3]
> > > > > + *
> > > > > + * This can also be though of as 2 virtual engines:
> > > > > + * VE[0] = CS[0], CS[2]
> > > > > + * VE[1] = CS[1], CS[3]
> > > > > + *
> > > > > + * This enables a use case where all engines are not equal and certain placement
> > > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > > + * case (logically contiguous placement, within a single engine class) is
> > > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > > + * bonding configurations but currently doesn't support this extension.
> > > > > + */
> > > > > +#define I915_PARALLEL_IMPLICT_BONDS                    (1<<0)
> > > > > +/*
> > > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > > + */
> > > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH             (1<<1)
> > > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS  (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > > +       __u64 flags;            /* all undefined flags must be zero */
> > > > > +       __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > > > +
> > > > > +       /*
> > > > > +        * width (i) * num_siblings (j) in length
> > > > > +        * index = j + i * num_siblings
> > > > > +        */
> > > > > +       struct i915_engine_class_instance engines[0];
> > > > > +} __attribute__ ((packed));
> > > > > +
> > > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > index 7faa46cde088..64c539486ee4 100644
> > > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > @@ -82,4 +82,55 @@ https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fspec.oneapi.com%2Flevel-zero%2Flatest%2Fcore%2Fapi.html%23ze-command-queue-priorit&amp;data=04%7C01%7Cchristian.koenig%40amd.com%7C49a7557f4e494090755608d91ae758a6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637570403202969375%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=dn3PVdxYQpkpWIru5eAXHgbfuLDkppAA5daV5sHQF7s%3D&amp;reserved=0
> > > > >    New parallel submission uAPI
> > > > >    ============================
> > > > > -Details to come in a following patch.
> > > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > > +
> > > > > +The new parallel submission uAPI consists of 3 parts:
> > > > > +
> > > > > +* Export engines logical mapping
> > > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > > +  submission
> > > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > +
> > > > > +Export engines logical mapping
> > > > > +------------------------------
> > > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > > +submission interface currently only supports submitting multiple contexts to
> > > > > +engines in logical order which is a new requirement compared to execlists.
> > > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > > +
> > > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > > +logical instance has been returned and a new field,
> > > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > > +
> > > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > > +------------------------------------------------------------------------
> > > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > > +It is setup step that should be called before using any of the contexts. See
> > > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > > +support GuC submission. Execlist support can be added later if needed.
> > > > > +
> > > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > > +
> > > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > +-------------------------------------------------------------------
> > > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > > +the IOCTL.
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-20 21:38             ` Jason Ekstrand
@ 2021-05-21  8:35               ` Christian König
  -1 siblings, 0 replies; 54+ messages in thread
From: Christian König @ 2021-05-21  8:35 UTC (permalink / raw)
  To: Jason Ekstrand, Matthew Brost
  Cc: Intel GFX, Maling list - DRI developers, Jason Ekstrand,
	ML mesa-dev, Daniel Vetter, karl, Christian König

Am 20.05.21 um 23:38 schrieb Jason Ekstrand:
> On Thu, May 20, 2021 at 10:46 AM Matthew Brost <matthew.brost@intel.com> wrote:
>> On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote:
>>> Am 19.05.21 um 18:51 schrieb Matthew Brost:
>>>> On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
>>>>> Oh, yeah we call that gang submit on the AMD side.
>>>>>
>>>>> Had already some internal discussions how to implement this, but so far
>>>>> couldn't figure out how to cleanly introduce that into the DRM scheduler.
>>>>>
>>>>> Can you briefly describe in a few words how that is supposed to work on the
>>>>> Intel side?
> On Intel, we actually have two cases which don't fit the current
> drm/scheduler model well: balanced and bonded.
>
> In the balanced model, we want to submit a batch which can go to any
> one of some set of engines and we don't care which.  It's up to the
> kernel to pick an engine.  Imagine you had 64 identical HW compute
> queues, for instance.  This could be done by making all the identical
> engines share a single drm_gpu_scheduler and round-robin around the HW
> queues or something.  I don't know that we strictly need drm/scheduler
> to be aware of it but it might be nice if it grew support for this
> mode so we could maintain a 1:1 relationship between HW queues and
> drm_gpu_schedulers.  That said, I'm not sure how this would play with
> GuC queues so maybe it doesn't help?

Oh, we do have support for load balancing like that.

When you call drm_sched_entity_init() you can give a list of 
drm_gpu_scheduler object to use round robing for scheduling.

New jobs are then scheduler to the drm_gpu_scheduler instance which is 
idle or rather the least busy one.

> The bonded model is like your ganged, I think.  We want to submit N
> batches to run in parallel.  And they actually have to be executing on
> the GPU simultaneously and not just sort-of at similar times.  We need
> this for video.  There are also potential use-cases in Vulkan or even
> GL that might be able to use this.  One difference with the balanced
> mode is that bonds don't, strictly speaking, need to be on the same
> type of engine.  Imagine, for instance, a 3D batch with a parallel
> compute batch doing vertex pre-processing.
>
> I'm pretty sure the bonded case is something that the mobile drivers
> (panfrost, etc.) would like as well for doing Vulkan on tilers where
> you often have to have two command buffers running in parallel.
> They're currently doing it by submitting a giant pile of batches where
> they split the batch and add sync primitives every time some GL call
> requires them to sync between fragment and vertex pipes.

Yeah, we have exactly the same problem as well.

But so far every model we discussed has some drawbacks and it is rather 
hard for the scheduler to guarantee that stuff runs at the same time.

So if you got any ideas how to cleanly implement that then they would be 
rather welcomed.

Regards,
Christian.

>
> So, to sum up, I think there's likely some good collaboration to be
> had here for everyone. :-)
>
> --Jason
>
>>>> Sure, I've done a quick PoC internally and have been able to hook this
>>>> into the DRM scheduler.
>>>>
>>>> Basically each BB still maps to a single job as each job is somewhat
>>>> unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
>>>> the jobs configured to run in parallel map to a single sched_entity
>>>> which maintains the order each job was generated from the execbuf IOCTL
>>>> (1 - N). When the backend receives jobs 1 to N - 1 it basically just
>>>> updates some internal state. When the backend sees job N (last job) it
>>>> actually does the submit for jobs 1 - N which with GuC submission is a
>>>> simple command moving the LRC tail of the N jobs.
>>>>
>>>> Daniel has suggested that we create a single job for the NN BBs but that
>>>> would be huge rework to the internals of the i915 and likely won't
>>>> happen by the time this code first lands.
>>>>
>>>> Also worth noting one way a job isn't really a treated individually is
>>>> the excl slot with dma-resv. In that case we create a composite fence of
>>>> all jobs (dma_fence_array).
>>> Yeah, that's something we have discussed as well.
>>>
>>> How do you prevent the scheduler from over committing to a single ring
>>> buffer in this scenario?
>>>
>> Each job has its own ring, the execbuf IOCTL throttles itself for each
>> job if there isn't space in the ring. This is exactly the same as
>> non-parallel submits.
>>
>> I think this is what you were asking? If not, maybe try explaining the
>> question a bit more.
>>
>> Matt
>>
>>> Christian.
>>>
>>>> Matt
>>>>
>>>>> Thanks,
>>>>> Christian.
>>>>>
>>>>> Am 19.05.21 um 01:58 schrieb Matthew Brost:
>>>>>> Add entry fpr i915 new parallel submission uAPI plan.
>>>>>>
>>>>>> v2:
>>>>>>     (Daniel Vetter):
>>>>>>      - Expand logical order explaination
>>>>>>      - Add dummy header
>>>>>>      - Only allow N BBs in execbuf IOCTL
>>>>>>      - Configure parallel submission per slot not per gem context
>>>>>>
>>>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>>> Cc: Tony Ye <tony.ye@intel.com>
>>>>>> CC: Carl Zhang <carl.zhang@intel.com>
>>>>>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>>>>>> Cc: Jason Ekstrand <jason@jlekstrand.net>
>>>>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>>>>> ---
>>>>>>     Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>>>>>>     Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>>>>>>     2 files changed, 196 insertions(+), 1 deletion(-)
>>>>>>     create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>>
>>>>>> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>> new file mode 100644
>>>>>> index 000000000000..8c64b983ccad
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>> @@ -0,0 +1,144 @@
>>>>>> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
>>>>>> +
>>>>>> +/*
>>>>>> + * i915_context_engines_parallel_submit:
>>>>>> + *
>>>>>> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
>>>>>> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
>>>>>> + * hardware contexts are created internally in the i915 run these BBs. Once a
>>>>>> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
>>>>>> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
>>>>>> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
>>>>>> + * the slots configuration).
>>>>>> + *
>>>>>> + * Their are two currently defined ways to control the placement of the
>>>>>> + * hardware contexts on physical engines: default behavior (no flags) and
>>>>>> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
>>>>>> + * future as new hardware / use cases arise. Details of how to use this
>>>>>> + * interface below above the flags.
>>>>>> + *
>>>>>> + * Returns -EINVAL if hardware context placement configuration invalid or if the
>>>>>> + * placement configuration isn't supported on the platform / submission
>>>>>> + * interface.
>>>>>> + * Returns -ENODEV if extension isn't supported on the platform / submission
>>>>>> + * inteface.
>>>>>> + */
>>>>>> +struct i915_context_engines_parallel_submit {
>>>>>> +       struct i915_user_extension base;
>>>>>> +
>>>>>> +       __u16 engine_index;     /* slot for parallel engine */
>>>>>> +       __u16 width;            /* number of contexts per parallel engine */
>>>>>> +       __u16 num_siblings;     /* number of siblings per context */
>>>>>> +       __u16 mbz16;
>>>>>> +/*
>>>>>> + * Default placement behvavior (currently unsupported):
>>>>>> + *
>>>>>> + * Rather than restricting parallel submission to a single class with a
>>>>>> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
>>>>>> + * enables parallel submission across multiple engine classes. In this case each
>>>>>> + * context's logical engine mask indicates where that context can placed. It is
>>>>>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>>>>>> + * if one context is running CS0 no other contexts can run on CS0).
>>>>>> + *
>>>>>> + * Example 1 pseudo code:
>>>>>> + * CSX[Y] = engine class X, logical instance Y
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>>>>> + *             engines=CS0[0],CS0[1],CS1[0],CS1[1])
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS0[0], CS1[0]
>>>>>> + * CS0[0], CS1[1]
>>>>>> + * CS0[1], CS1[0]
>>>>>> + * CS0[1], CS1[1]
>>>>>> + *
>>>>>> + * This can also be though of as 2 virtual engines:
>>>>>> + * VE[0] = CS0[0], CS0[1]
>>>>>> + * VE[1] = CS1[0], CS1[1]
>>>>>> + *
>>>>>> + * Example 2 pseudo code:
>>>>>> + * CS[X] = generic engine of same class, logical instance X
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=3,
>>>>>> + *             engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS[0], CS[1]
>>>>>> + * CS[0], CS[2]
>>>>>> + * CS[1], CS[0]
>>>>>> + * CS[1], CS[2]
>>>>>> + * CS[2], CS[0]
>>>>>> + * CS[2], CS[1]
>>>>>> + *
>>>>>> + *
>>>>>> + * This can also be though of as 2 virtual engines:
>>>>>> + * VE[0] = CS[0], CS[1], CS[2]
>>>>>> + * VE[1] = CS[0], CS[1], CS[2]
>>>>>> +
>>>>>> + * This enables a use case where all engines are created equally, we don't care
>>>>>> + * where they are scheduled, we just want a certain number of resources, for
>>>>>> + * those resources to be scheduled in parallel, and possibly across multiple
>>>>>> + * engine classes.
>>>>>> + */
>>>>>> +
>>>>>> +/*
>>>>>> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
>>>>>> + * Each context must have the same number sibling and bonds are implictly create
>>>>>> + * of the siblings.
>>>>>> + *
>>>>>> + * All of the below examples are in logical space.
>>>>>> + *
>>>>>> + * Example 1 pseudo code:
>>>>>> + * CS[X] = generic engine of same class, logical instance X
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=1,
>>>>>> + *             engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS[0], CS[1]
>>>>>> + *
>>>>>> + * Example 2 pseudo code:
>>>>>> + * CS[X] = generic engine of same class, logical instance X
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>>>>> + *             engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS[0], CS[1]
>>>>>> + * CS[2], CS[3]
>>>>>> + *
>>>>>> + * This can also be though of as 2 virtual engines:
>>>>>> + * VE[0] = CS[0], CS[2]
>>>>>> + * VE[1] = CS[1], CS[3]
>>>>>> + *
>>>>>> + * This enables a use case where all engines are not equal and certain placement
>>>>>> + * rules are required (i.e. split-frame requires all contexts to be placed in a
>>>>>> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
>>>>>> + * case (logically contiguous placement, within a single engine class) is
>>>>>> + * supported when using GuC submission. Execlist mode could support all possible
>>>>>> + * bonding configurations but currently doesn't support this extension.
>>>>>> + */
>>>>>> +#define I915_PARALLEL_IMPLICT_BONDS                    (1<<0)
>>>>>> +/*
>>>>>> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
>>>>>> + * points on all hardware contexts between each set of BBs. An example use case
>>>>>> + * of this feature is split-frame on gen11+ hardware. When using this feature a
>>>>>> + * BB must be submitted on each hardware context in the parallel gem context.
>>>>>> + * The execbuf2 IOCTL enforces the user adheres to policy.
>>>>>> + */
>>>>>> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH             (1<<1)
>>>>>> +#define __I915_PARALLEL_UNKNOWN_FLAGS  (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
>>>>>> +       __u64 flags;            /* all undefined flags must be zero */
>>>>>> +       __u64 mbz64[3];         /* reserved for future use; must be zero */
>>>>>> +
>>>>>> +       /*
>>>>>> +        * width (i) * num_siblings (j) in length
>>>>>> +        * index = j + i * num_siblings
>>>>>> +        */
>>>>>> +       struct i915_engine_class_instance engines[0];
>>>>>> +} __attribute__ ((packed));
>>>>>> +
>>>>>> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
>>>>>> index 7faa46cde088..64c539486ee4 100644
>>>>>> --- a/Documentation/gpu/rfc/i915_scheduler.rst
>>>>>> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
>>>>>> @@ -82,4 +82,55 @@ https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fspec.oneapi.com%2Flevel-zero%2Flatest%2Fcore%2Fapi.html%23ze-command-queue-priorit&amp;data=04%7C01%7Cchristian.koenig%40amd.com%7C49a7557f4e494090755608d91ae758a6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637570403202969375%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=dn3PVdxYQpkpWIru5eAXHgbfuLDkppAA5daV5sHQF7s%3D&amp;reserved=0
>>>>>>     New parallel submission uAPI
>>>>>>     ============================
>>>>>> -Details to come in a following patch.
>>>>>> +The existing bonding uAPI is completely broken with GuC submission because
>>>>>> +whether a submission is a single context submit or parallel submit isn't known
>>>>>> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
>>>>>> +contexts in parallel with the GuC the context must be explictly registered with
>>>>>> +N contexts and all N contexts must be submitted in a single command to the GuC.
>>>>>> +These interfaces doesn't support dynamically changing between N contexts as the
>>>>>> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
>>>>>> +the legacy bonding uAPI is quite confusing and not intuitive at all.
>>>>>> +
>>>>>> +The new parallel submission uAPI consists of 3 parts:
>>>>>> +
>>>>>> +* Export engines logical mapping
>>>>>> +* A 'set_parallel' extension to configure contexts for parallel
>>>>>> +  submission
>>>>>> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>>>>>> +
>>>>>> +Export engines logical mapping
>>>>>> +------------------------------
>>>>>> +Certain use cases require BBs to be placed on engine instances in logical order
>>>>>> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
>>>>>> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
>>>>>> +logical mapping with the existing query engine info IOCTL. Also the GuC
>>>>>> +submission interface currently only supports submitting multiple contexts to
>>>>>> +engines in logical order which is a new requirement compared to execlists.
>>>>>> +Lastly, all current platforms have at most 2 instances and the logical order is
>>>>>> +the same a uABI order. This will change on platforms with more than 2 instances.
>>>>>> +
>>>>>> +A single bit will be added to drm_i915_engine_info.flags indicating that the
>>>>>> +logical instance has been returned and a new field,
>>>>>> +drm_i915_engine_info.logical_instance, returns the logical instance.
>>>>>> +
>>>>>> +A 'set_parallel' extension to configure contexts for parallel submission
>>>>>> +------------------------------------------------------------------------
>>>>>> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
>>>>>> +It is setup step that should be called before using any of the contexts. See
>>>>>> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
>>>>>> +similar existing examples. Once a slot is configured for parallel submission the
>>>>>> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
>>>>>> +support GuC submission. Execlist support can be added later if needed.
>>>>>> +
>>>>>> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
>>>>>> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
>>>>>> +
>>>>>> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>>>>>> +-------------------------------------------------------------------
>>>>>> +Contexts that have been configured with the 'set_parallel' extension are allowed
>>>>>> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
>>>>>> +objects in the drm_i915_gem_exec_object2 list or the first N if
>>>>>> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
>>>>>> +submitted and how it has been configured by 'set_parallel' or other extensions.
>>>>>> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
>>>>>> +the IOCTL.
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx


^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-21  8:35               ` Christian König
  0 siblings, 0 replies; 54+ messages in thread
From: Christian König @ 2021-05-21  8:35 UTC (permalink / raw)
  To: Jason Ekstrand, Matthew Brost
  Cc: Intel GFX, Maling list - DRI developers, Jason Ekstrand,
	ML mesa-dev, Daniel Vetter, karl, Christian König

Am 20.05.21 um 23:38 schrieb Jason Ekstrand:
> On Thu, May 20, 2021 at 10:46 AM Matthew Brost <matthew.brost@intel.com> wrote:
>> On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote:
>>> Am 19.05.21 um 18:51 schrieb Matthew Brost:
>>>> On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
>>>>> Oh, yeah we call that gang submit on the AMD side.
>>>>>
>>>>> Had already some internal discussions how to implement this, but so far
>>>>> couldn't figure out how to cleanly introduce that into the DRM scheduler.
>>>>>
>>>>> Can you briefly describe in a few words how that is supposed to work on the
>>>>> Intel side?
> On Intel, we actually have two cases which don't fit the current
> drm/scheduler model well: balanced and bonded.
>
> In the balanced model, we want to submit a batch which can go to any
> one of some set of engines and we don't care which.  It's up to the
> kernel to pick an engine.  Imagine you had 64 identical HW compute
> queues, for instance.  This could be done by making all the identical
> engines share a single drm_gpu_scheduler and round-robin around the HW
> queues or something.  I don't know that we strictly need drm/scheduler
> to be aware of it but it might be nice if it grew support for this
> mode so we could maintain a 1:1 relationship between HW queues and
> drm_gpu_schedulers.  That said, I'm not sure how this would play with
> GuC queues so maybe it doesn't help?

Oh, we do have support for load balancing like that.

When you call drm_sched_entity_init() you can give a list of 
drm_gpu_scheduler object to use round robing for scheduling.

New jobs are then scheduler to the drm_gpu_scheduler instance which is 
idle or rather the least busy one.

> The bonded model is like your ganged, I think.  We want to submit N
> batches to run in parallel.  And they actually have to be executing on
> the GPU simultaneously and not just sort-of at similar times.  We need
> this for video.  There are also potential use-cases in Vulkan or even
> GL that might be able to use this.  One difference with the balanced
> mode is that bonds don't, strictly speaking, need to be on the same
> type of engine.  Imagine, for instance, a 3D batch with a parallel
> compute batch doing vertex pre-processing.
>
> I'm pretty sure the bonded case is something that the mobile drivers
> (panfrost, etc.) would like as well for doing Vulkan on tilers where
> you often have to have two command buffers running in parallel.
> They're currently doing it by submitting a giant pile of batches where
> they split the batch and add sync primitives every time some GL call
> requires them to sync between fragment and vertex pipes.

Yeah, we have exactly the same problem as well.

But so far every model we discussed has some drawbacks and it is rather 
hard for the scheduler to guarantee that stuff runs at the same time.

So if you got any ideas how to cleanly implement that then they would be 
rather welcomed.

Regards,
Christian.

>
> So, to sum up, I think there's likely some good collaboration to be
> had here for everyone. :-)
>
> --Jason
>
>>>> Sure, I've done a quick PoC internally and have been able to hook this
>>>> into the DRM scheduler.
>>>>
>>>> Basically each BB still maps to a single job as each job is somewhat
>>>> unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
>>>> the jobs configured to run in parallel map to a single sched_entity
>>>> which maintains the order each job was generated from the execbuf IOCTL
>>>> (1 - N). When the backend receives jobs 1 to N - 1 it basically just
>>>> updates some internal state. When the backend sees job N (last job) it
>>>> actually does the submit for jobs 1 - N which with GuC submission is a
>>>> simple command moving the LRC tail of the N jobs.
>>>>
>>>> Daniel has suggested that we create a single job for the NN BBs but that
>>>> would be huge rework to the internals of the i915 and likely won't
>>>> happen by the time this code first lands.
>>>>
>>>> Also worth noting one way a job isn't really a treated individually is
>>>> the excl slot with dma-resv. In that case we create a composite fence of
>>>> all jobs (dma_fence_array).
>>> Yeah, that's something we have discussed as well.
>>>
>>> How do you prevent the scheduler from over committing to a single ring
>>> buffer in this scenario?
>>>
>> Each job has its own ring, the execbuf IOCTL throttles itself for each
>> job if there isn't space in the ring. This is exactly the same as
>> non-parallel submits.
>>
>> I think this is what you were asking? If not, maybe try explaining the
>> question a bit more.
>>
>> Matt
>>
>>> Christian.
>>>
>>>> Matt
>>>>
>>>>> Thanks,
>>>>> Christian.
>>>>>
>>>>> Am 19.05.21 um 01:58 schrieb Matthew Brost:
>>>>>> Add entry fpr i915 new parallel submission uAPI plan.
>>>>>>
>>>>>> v2:
>>>>>>     (Daniel Vetter):
>>>>>>      - Expand logical order explaination
>>>>>>      - Add dummy header
>>>>>>      - Only allow N BBs in execbuf IOCTL
>>>>>>      - Configure parallel submission per slot not per gem context
>>>>>>
>>>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>>> Cc: Tony Ye <tony.ye@intel.com>
>>>>>> CC: Carl Zhang <carl.zhang@intel.com>
>>>>>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>>>>>> Cc: Jason Ekstrand <jason@jlekstrand.net>
>>>>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>>>>> ---
>>>>>>     Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>>>>>>     Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>>>>>>     2 files changed, 196 insertions(+), 1 deletion(-)
>>>>>>     create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>>
>>>>>> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>> new file mode 100644
>>>>>> index 000000000000..8c64b983ccad
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>> @@ -0,0 +1,144 @@
>>>>>> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
>>>>>> +
>>>>>> +/*
>>>>>> + * i915_context_engines_parallel_submit:
>>>>>> + *
>>>>>> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
>>>>>> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
>>>>>> + * hardware contexts are created internally in the i915 run these BBs. Once a
>>>>>> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
>>>>>> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
>>>>>> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
>>>>>> + * the slots configuration).
>>>>>> + *
>>>>>> + * Their are two currently defined ways to control the placement of the
>>>>>> + * hardware contexts on physical engines: default behavior (no flags) and
>>>>>> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
>>>>>> + * future as new hardware / use cases arise. Details of how to use this
>>>>>> + * interface below above the flags.
>>>>>> + *
>>>>>> + * Returns -EINVAL if hardware context placement configuration invalid or if the
>>>>>> + * placement configuration isn't supported on the platform / submission
>>>>>> + * interface.
>>>>>> + * Returns -ENODEV if extension isn't supported on the platform / submission
>>>>>> + * inteface.
>>>>>> + */
>>>>>> +struct i915_context_engines_parallel_submit {
>>>>>> +       struct i915_user_extension base;
>>>>>> +
>>>>>> +       __u16 engine_index;     /* slot for parallel engine */
>>>>>> +       __u16 width;            /* number of contexts per parallel engine */
>>>>>> +       __u16 num_siblings;     /* number of siblings per context */
>>>>>> +       __u16 mbz16;
>>>>>> +/*
>>>>>> + * Default placement behvavior (currently unsupported):
>>>>>> + *
>>>>>> + * Rather than restricting parallel submission to a single class with a
>>>>>> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
>>>>>> + * enables parallel submission across multiple engine classes. In this case each
>>>>>> + * context's logical engine mask indicates where that context can placed. It is
>>>>>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>>>>>> + * if one context is running CS0 no other contexts can run on CS0).
>>>>>> + *
>>>>>> + * Example 1 pseudo code:
>>>>>> + * CSX[Y] = engine class X, logical instance Y
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>>>>> + *             engines=CS0[0],CS0[1],CS1[0],CS1[1])
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS0[0], CS1[0]
>>>>>> + * CS0[0], CS1[1]
>>>>>> + * CS0[1], CS1[0]
>>>>>> + * CS0[1], CS1[1]
>>>>>> + *
>>>>>> + * This can also be though of as 2 virtual engines:
>>>>>> + * VE[0] = CS0[0], CS0[1]
>>>>>> + * VE[1] = CS1[0], CS1[1]
>>>>>> + *
>>>>>> + * Example 2 pseudo code:
>>>>>> + * CS[X] = generic engine of same class, logical instance X
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=3,
>>>>>> + *             engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS[0], CS[1]
>>>>>> + * CS[0], CS[2]
>>>>>> + * CS[1], CS[0]
>>>>>> + * CS[1], CS[2]
>>>>>> + * CS[2], CS[0]
>>>>>> + * CS[2], CS[1]
>>>>>> + *
>>>>>> + *
>>>>>> + * This can also be though of as 2 virtual engines:
>>>>>> + * VE[0] = CS[0], CS[1], CS[2]
>>>>>> + * VE[1] = CS[0], CS[1], CS[2]
>>>>>> +
>>>>>> + * This enables a use case where all engines are created equally, we don't care
>>>>>> + * where they are scheduled, we just want a certain number of resources, for
>>>>>> + * those resources to be scheduled in parallel, and possibly across multiple
>>>>>> + * engine classes.
>>>>>> + */
>>>>>> +
>>>>>> +/*
>>>>>> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
>>>>>> + * Each context must have the same number sibling and bonds are implictly create
>>>>>> + * of the siblings.
>>>>>> + *
>>>>>> + * All of the below examples are in logical space.
>>>>>> + *
>>>>>> + * Example 1 pseudo code:
>>>>>> + * CS[X] = generic engine of same class, logical instance X
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=1,
>>>>>> + *             engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS[0], CS[1]
>>>>>> + *
>>>>>> + * Example 2 pseudo code:
>>>>>> + * CS[X] = generic engine of same class, logical instance X
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>>>>> + *             engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS[0], CS[1]
>>>>>> + * CS[2], CS[3]
>>>>>> + *
>>>>>> + * This can also be though of as 2 virtual engines:
>>>>>> + * VE[0] = CS[0], CS[2]
>>>>>> + * VE[1] = CS[1], CS[3]
>>>>>> + *
>>>>>> + * This enables a use case where all engines are not equal and certain placement
>>>>>> + * rules are required (i.e. split-frame requires all contexts to be placed in a
>>>>>> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
>>>>>> + * case (logically contiguous placement, within a single engine class) is
>>>>>> + * supported when using GuC submission. Execlist mode could support all possible
>>>>>> + * bonding configurations but currently doesn't support this extension.
>>>>>> + */
>>>>>> +#define I915_PARALLEL_IMPLICT_BONDS                    (1<<0)
>>>>>> +/*
>>>>>> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
>>>>>> + * points on all hardware contexts between each set of BBs. An example use case
>>>>>> + * of this feature is split-frame on gen11+ hardware. When using this feature a
>>>>>> + * BB must be submitted on each hardware context in the parallel gem context.
>>>>>> + * The execbuf2 IOCTL enforces the user adheres to policy.
>>>>>> + */
>>>>>> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH             (1<<1)
>>>>>> +#define __I915_PARALLEL_UNKNOWN_FLAGS  (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
>>>>>> +       __u64 flags;            /* all undefined flags must be zero */
>>>>>> +       __u64 mbz64[3];         /* reserved for future use; must be zero */
>>>>>> +
>>>>>> +       /*
>>>>>> +        * width (i) * num_siblings (j) in length
>>>>>> +        * index = j + i * num_siblings
>>>>>> +        */
>>>>>> +       struct i915_engine_class_instance engines[0];
>>>>>> +} __attribute__ ((packed));
>>>>>> +
>>>>>> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
>>>>>> index 7faa46cde088..64c539486ee4 100644
>>>>>> --- a/Documentation/gpu/rfc/i915_scheduler.rst
>>>>>> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
>>>>>> @@ -82,4 +82,55 @@ https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fspec.oneapi.com%2Flevel-zero%2Flatest%2Fcore%2Fapi.html%23ze-command-queue-priorit&amp;data=04%7C01%7Cchristian.koenig%40amd.com%7C49a7557f4e494090755608d91ae758a6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637570403202969375%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=dn3PVdxYQpkpWIru5eAXHgbfuLDkppAA5daV5sHQF7s%3D&amp;reserved=0
>>>>>>     New parallel submission uAPI
>>>>>>     ============================
>>>>>> -Details to come in a following patch.
>>>>>> +The existing bonding uAPI is completely broken with GuC submission because
>>>>>> +whether a submission is a single context submit or parallel submit isn't known
>>>>>> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
>>>>>> +contexts in parallel with the GuC the context must be explictly registered with
>>>>>> +N contexts and all N contexts must be submitted in a single command to the GuC.
>>>>>> +These interfaces doesn't support dynamically changing between N contexts as the
>>>>>> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
>>>>>> +the legacy bonding uAPI is quite confusing and not intuitive at all.
>>>>>> +
>>>>>> +The new parallel submission uAPI consists of 3 parts:
>>>>>> +
>>>>>> +* Export engines logical mapping
>>>>>> +* A 'set_parallel' extension to configure contexts for parallel
>>>>>> +  submission
>>>>>> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>>>>>> +
>>>>>> +Export engines logical mapping
>>>>>> +------------------------------
>>>>>> +Certain use cases require BBs to be placed on engine instances in logical order
>>>>>> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
>>>>>> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
>>>>>> +logical mapping with the existing query engine info IOCTL. Also the GuC
>>>>>> +submission interface currently only supports submitting multiple contexts to
>>>>>> +engines in logical order which is a new requirement compared to execlists.
>>>>>> +Lastly, all current platforms have at most 2 instances and the logical order is
>>>>>> +the same a uABI order. This will change on platforms with more than 2 instances.
>>>>>> +
>>>>>> +A single bit will be added to drm_i915_engine_info.flags indicating that the
>>>>>> +logical instance has been returned and a new field,
>>>>>> +drm_i915_engine_info.logical_instance, returns the logical instance.
>>>>>> +
>>>>>> +A 'set_parallel' extension to configure contexts for parallel submission
>>>>>> +------------------------------------------------------------------------
>>>>>> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
>>>>>> +It is setup step that should be called before using any of the contexts. See
>>>>>> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
>>>>>> +similar existing examples. Once a slot is configured for parallel submission the
>>>>>> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
>>>>>> +support GuC submission. Execlist support can be added later if needed.
>>>>>> +
>>>>>> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
>>>>>> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
>>>>>> +
>>>>>> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
>>>>>> +-------------------------------------------------------------------
>>>>>> +Contexts that have been configured with the 'set_parallel' extension are allowed
>>>>>> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
>>>>>> +objects in the drm_i915_gem_exec_object2 list or the first N if
>>>>>> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
>>>>>> +submitted and how it has been configured by 'set_parallel' or other extensions.
>>>>>> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
>>>>>> +the IOCTL.
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-18 23:58   ` [Intel-gfx] " Matthew Brost
@ 2021-05-21 12:00     ` Tvrtko Ursulin
  -1 siblings, 0 replies; 54+ messages in thread
From: Tvrtko Ursulin @ 2021-05-21 12:00 UTC (permalink / raw)
  To: Matthew Brost, intel-gfx, dri-devel
  Cc: jason.ekstrand, mesa-dev, karl, christian.koenig, daniel.vetter


On 19/05/2021 00:58, Matthew Brost wrote:
> Add entry fpr i915 new parallel submission uAPI plan.
> 
> v2:
>   (Daniel Vetter):
>    - Expand logical order explaination
>    - Add dummy header
>    - Only allow N BBs in execbuf IOCTL
>    - Configure parallel submission per slot not per gem context
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> CC: Carl Zhang <carl.zhang@intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>   2 files changed, 196 insertions(+), 1 deletion(-)
>   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> 
> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> new file mode 100644
> index 000000000000..8c64b983ccad
> --- /dev/null
> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> @@ -0,0 +1,144 @@
> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> +
> +/*
> + * i915_context_engines_parallel_submit:
> + *
> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> + * hardware contexts are created internally in the i915 run these BBs. Once a
> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> + * the slots configuration).

1)
Expand the term slot here with "slot in the context engine map" least 
once for clarity.

2)
About where execbuf will implicitly be finding batches - suggest to also 
cover first/last flag here. I know you have it in the readme but I think 
it is good if uapi header is as self-contained as possible.

> + *
> + * Their are two currently defined ways to control the placement of the
> + * hardware contexts on physical engines: default behavior (no flags) and
> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> + * future as new hardware / use cases arise. Details of how to use this
> + * interface below above the flags.
> + *
> + * Returns -EINVAL if hardware context placement configuration invalid or if the
> + * placement configuration isn't supported on the platform / submission
> + * interface.
> + * Returns -ENODEV if extension isn't supported on the platform / submission
> + * inteface.
> + */
> +struct i915_context_engines_parallel_submit {
> +	struct i915_user_extension base;
> +
> +	__u16 engine_index;	/* slot for parallel engine */
> +	__u16 width;		/* number of contexts per parallel engine */
> +	__u16 num_siblings;	/* number of siblings per context */
> +	__u16 mbz16;
> +/*
> + * Default placement behvavior (currently unsupported):
> + *
> + * Rather than restricting parallel submission to a single class with a
> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that

What do you mean with logically contiguous here? It sounds ambiguous 
versus logical vs "normal" engine instance numbers.

> + * enables parallel submission across multiple engine classes. In this case each
> + * context's logical engine mask indicates where that context can placed. It is
> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> + * if one context is running CS0 no other contexts can run on CS0).

I think talk about logical context and its mask is too implementation 
detail at the uapi level. Instead I would suggest more userspace 
programmer centric description.

> + *
> + * Example 1 pseudo code:
> + * CSX[Y] = engine class X, logical instance Y
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> + *
> + * Results in the following valid placements:
> + * CS0[0], CS1[0]
> + * CS0[0], CS1[1]
> + * CS0[1], CS1[0]
> + * CS0[1], CS1[1]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS0[0], CS0[1]
> + * VE[1] = CS1[0], CS1[1]

Ah okay so essentially similar to what I was proposing a year ago. But 
then it is no longer "set_parallel" really. It is one slot in the engine 
map, right, with the idea to super class intel_context in the 
implementation?

So really a wide virtual engine, as opposed to single one. In which case 
I think it makes sense to stay close to the existing naming of the 
load_balance extension for consistency. Load_balance_wide? 
Load_balance_parallel? Multi?

I also have to say the notation "CS0[0]" - I who know this problem space 
am finding it hard to penetrate what that actually means. (Also 
uppercase IMO makes it hard to read, but maybe it is just me.)

Looking a bit lower below, extension seems to be taking a 2d array of 
class:instance pairs, right? If so then reading these docs in order, or 
even just looking further down, I don't think that is explicitly called 
out clearly enough.

So I think a paragraph or two explaining clearly how the 2d array of 
engines corresponds to the allowed engines for full virtual engine 
width. Or maybe just a 2d diagram?

   2-wide virtual engine:
     .engines = [
       /* channel 0 allowed engines: */  [cs0, cs1],
       /* channel 1 allowed engines: */  [cs0, cs1]
      ]

Not sure if that's better.

Also to be noted, this only allows uniform number of allowed engines per 
channel. I am not saying we need the non-uniform setup today but with 
bonds there isn't this limitation.

> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=3,
> + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[0], CS[2]
> + * CS[1], CS[0]
> + * CS[1], CS[2]
> + * CS[2], CS[0]
> + * CS[2], CS[1]

And now here you use different notation than above (CS0[0] vs CS[0]) 
which is confusing.

> + *
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[1], CS[2]
> + * VE[1] = CS[0], CS[1], CS[2]
> +
> + * This enables a use case where all engines are created equally, we don't care
> + * where they are scheduled, we just want a certain number of resources, for
> + * those resources to be scheduled in parallel, and possibly across multiple
> + * engine classes.
> + */
> +
> +/*
> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> + * Each context must have the same number sibling and bonds are implictly create
> + * of the siblings.
> + *
> + * All of the below examples are in logical space.
> + *
> + * Example 1 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=1,
> + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[2], CS[3]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[2]
> + * VE[1] = CS[1], CS[3]
> + *
> + * This enables a use case where all engines are not equal and certain placement
> + * rules are required (i.e. split-frame requires all contexts to be placed in a
> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> + * case (logically contiguous placement, within a single engine class) is
> + * supported when using GuC submission. Execlist mode could support all possible
> + * bonding configurations but currently doesn't support this extension.
> + */
> +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> +/*
> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> + * points on all hardware contexts between each set of BBs. An example use case
> + * of this feature is split-frame on gen11+ hardware. When using this feature a
> + * BB must be submitted on each hardware context in the parallel gem context.
> + * The execbuf2 IOCTL enforces the user adheres to policy.
> + */
Is the part about execbuf2 enforcing num_batches == context_width still 
valid, I mean is the latest proposal supporting num_batches < 
context_width? Does media needs this option?

I would also have this flag as a separate patch because it strictly 
isn't about parallel submission per-se but a specific hw limitation on 
top of it.

Regards,

Tvrtko

> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> +	__u64 flags;		/* all undefined flags must be zero */
> +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> +
> +	/*
> +	 * width (i) * num_siblings (j) in length
> +	 * index = j + i * num_siblings
> +	 */
> +	struct i915_engine_class_instance engines[0];
> +} __attribute__ ((packed));
> +
> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> index 7faa46cde088..64c539486ee4 100644
> --- a/Documentation/gpu/rfc/i915_scheduler.rst
> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
>   
>   New parallel submission uAPI
>   ============================
> -Details to come in a following patch.
> +The existing bonding uAPI is completely broken with GuC submission because
> +whether a submission is a single context submit or parallel submit isn't known
> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> +contexts in parallel with the GuC the context must be explictly registered with
> +N contexts and all N contexts must be submitted in a single command to the GuC.
> +These interfaces doesn't support dynamically changing between N contexts as the
> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> +the legacy bonding uAPI is quite confusing and not intuitive at all.
> +
> +The new parallel submission uAPI consists of 3 parts:
> +
> +* Export engines logical mapping
> +* A 'set_parallel' extension to configure contexts for parallel
> +  submission
> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +
> +Export engines logical mapping
> +------------------------------
> +Certain use cases require BBs to be placed on engine instances in logical order
> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> +logical mapping with the existing query engine info IOCTL. Also the GuC
> +submission interface currently only supports submitting multiple contexts to
> +engines in logical order which is a new requirement compared to execlists.
> +Lastly, all current platforms have at most 2 instances and the logical order is
> +the same a uABI order. This will change on platforms with more than 2 instances.
> +
> +A single bit will be added to drm_i915_engine_info.flags indicating that the
> +logical instance has been returned and a new field,
> +drm_i915_engine_info.logical_instance, returns the logical instance.
> +
> +A 'set_parallel' extension to configure contexts for parallel submission
> +------------------------------------------------------------------------
> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> +It is setup step that should be called before using any of the contexts. See
> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> +similar existing examples. Once a slot is configured for parallel submission the
> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> +support GuC submission. Execlist support can be added later if needed.
> +
> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> +
> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +-------------------------------------------------------------------
> +Contexts that have been configured with the 'set_parallel' extension are allowed
> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> +objects in the drm_i915_gem_exec_object2 list or the first N if
> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> +submitted and how it has been configured by 'set_parallel' or other extensions.
> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> +the IOCTL.
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-21 12:00     ` Tvrtko Ursulin
  0 siblings, 0 replies; 54+ messages in thread
From: Tvrtko Ursulin @ 2021-05-21 12:00 UTC (permalink / raw)
  To: Matthew Brost, intel-gfx, dri-devel
  Cc: jason.ekstrand, mesa-dev, karl, christian.koenig, daniel.vetter


On 19/05/2021 00:58, Matthew Brost wrote:
> Add entry fpr i915 new parallel submission uAPI plan.
> 
> v2:
>   (Daniel Vetter):
>    - Expand logical order explaination
>    - Add dummy header
>    - Only allow N BBs in execbuf IOCTL
>    - Configure parallel submission per slot not per gem context
> 
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Tony Ye <tony.ye@intel.com>
> CC: Carl Zhang <carl.zhang@intel.com>
> Cc: Daniel Vetter <daniel.vetter@intel.com>
> Cc: Jason Ekstrand <jason@jlekstrand.net>
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> ---
>   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>   2 files changed, 196 insertions(+), 1 deletion(-)
>   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> 
> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> new file mode 100644
> index 000000000000..8c64b983ccad
> --- /dev/null
> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> @@ -0,0 +1,144 @@
> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> +
> +/*
> + * i915_context_engines_parallel_submit:
> + *
> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> + * hardware contexts are created internally in the i915 run these BBs. Once a
> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> + * the slots configuration).

1)
Expand the term slot here with "slot in the context engine map" least 
once for clarity.

2)
About where execbuf will implicitly be finding batches - suggest to also 
cover first/last flag here. I know you have it in the readme but I think 
it is good if uapi header is as self-contained as possible.

> + *
> + * Their are two currently defined ways to control the placement of the
> + * hardware contexts on physical engines: default behavior (no flags) and
> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> + * future as new hardware / use cases arise. Details of how to use this
> + * interface below above the flags.
> + *
> + * Returns -EINVAL if hardware context placement configuration invalid or if the
> + * placement configuration isn't supported on the platform / submission
> + * interface.
> + * Returns -ENODEV if extension isn't supported on the platform / submission
> + * inteface.
> + */
> +struct i915_context_engines_parallel_submit {
> +	struct i915_user_extension base;
> +
> +	__u16 engine_index;	/* slot for parallel engine */
> +	__u16 width;		/* number of contexts per parallel engine */
> +	__u16 num_siblings;	/* number of siblings per context */
> +	__u16 mbz16;
> +/*
> + * Default placement behvavior (currently unsupported):
> + *
> + * Rather than restricting parallel submission to a single class with a
> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that

What do you mean with logically contiguous here? It sounds ambiguous 
versus logical vs "normal" engine instance numbers.

> + * enables parallel submission across multiple engine classes. In this case each
> + * context's logical engine mask indicates where that context can placed. It is
> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> + * if one context is running CS0 no other contexts can run on CS0).

I think talk about logical context and its mask is too implementation 
detail at the uapi level. Instead I would suggest more userspace 
programmer centric description.

> + *
> + * Example 1 pseudo code:
> + * CSX[Y] = engine class X, logical instance Y
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> + *
> + * Results in the following valid placements:
> + * CS0[0], CS1[0]
> + * CS0[0], CS1[1]
> + * CS0[1], CS1[0]
> + * CS0[1], CS1[1]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS0[0], CS0[1]
> + * VE[1] = CS1[0], CS1[1]

Ah okay so essentially similar to what I was proposing a year ago. But 
then it is no longer "set_parallel" really. It is one slot in the engine 
map, right, with the idea to super class intel_context in the 
implementation?

So really a wide virtual engine, as opposed to single one. In which case 
I think it makes sense to stay close to the existing naming of the 
load_balance extension for consistency. Load_balance_wide? 
Load_balance_parallel? Multi?

I also have to say the notation "CS0[0]" - I who know this problem space 
am finding it hard to penetrate what that actually means. (Also 
uppercase IMO makes it hard to read, but maybe it is just me.)

Looking a bit lower below, extension seems to be taking a 2d array of 
class:instance pairs, right? If so then reading these docs in order, or 
even just looking further down, I don't think that is explicitly called 
out clearly enough.

So I think a paragraph or two explaining clearly how the 2d array of 
engines corresponds to the allowed engines for full virtual engine 
width. Or maybe just a 2d diagram?

   2-wide virtual engine:
     .engines = [
       /* channel 0 allowed engines: */  [cs0, cs1],
       /* channel 1 allowed engines: */  [cs0, cs1]
      ]

Not sure if that's better.

Also to be noted, this only allows uniform number of allowed engines per 
channel. I am not saying we need the non-uniform setup today but with 
bonds there isn't this limitation.

> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=3,
> + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[0], CS[2]
> + * CS[1], CS[0]
> + * CS[1], CS[2]
> + * CS[2], CS[0]
> + * CS[2], CS[1]

And now here you use different notation than above (CS0[0] vs CS[0]) 
which is confusing.

> + *
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[1], CS[2]
> + * VE[1] = CS[0], CS[1], CS[2]
> +
> + * This enables a use case where all engines are created equally, we don't care
> + * where they are scheduled, we just want a certain number of resources, for
> + * those resources to be scheduled in parallel, and possibly across multiple
> + * engine classes.
> + */
> +
> +/*
> + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> + * Each context must have the same number sibling and bonds are implictly create
> + * of the siblings.
> + *
> + * All of the below examples are in logical space.
> + *
> + * Example 1 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=1,
> + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + *
> + * Example 2 pseudo code:
> + * CS[X] = generic engine of same class, logical instance X
> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> + * set_engines(INVALID)
> + * set_parallel(engine_index=0, width=2, num_siblings=2,
> + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> + *
> + * Results in the following valid placements:
> + * CS[0], CS[1]
> + * CS[2], CS[3]
> + *
> + * This can also be though of as 2 virtual engines:
> + * VE[0] = CS[0], CS[2]
> + * VE[1] = CS[1], CS[3]
> + *
> + * This enables a use case where all engines are not equal and certain placement
> + * rules are required (i.e. split-frame requires all contexts to be placed in a
> + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> + * case (logically contiguous placement, within a single engine class) is
> + * supported when using GuC submission. Execlist mode could support all possible
> + * bonding configurations but currently doesn't support this extension.
> + */
> +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> +/*
> + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> + * points on all hardware contexts between each set of BBs. An example use case
> + * of this feature is split-frame on gen11+ hardware. When using this feature a
> + * BB must be submitted on each hardware context in the parallel gem context.
> + * The execbuf2 IOCTL enforces the user adheres to policy.
> + */
Is the part about execbuf2 enforcing num_batches == context_width still 
valid, I mean is the latest proposal supporting num_batches < 
context_width? Does media needs this option?

I would also have this flag as a separate patch because it strictly 
isn't about parallel submission per-se but a specific hw limitation on 
top of it.

Regards,

Tvrtko

> +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> +	__u64 flags;		/* all undefined flags must be zero */
> +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> +
> +	/*
> +	 * width (i) * num_siblings (j) in length
> +	 * index = j + i * num_siblings
> +	 */
> +	struct i915_engine_class_instance engines[0];
> +} __attribute__ ((packed));
> +
> diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> index 7faa46cde088..64c539486ee4 100644
> --- a/Documentation/gpu/rfc/i915_scheduler.rst
> +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
>   
>   New parallel submission uAPI
>   ============================
> -Details to come in a following patch.
> +The existing bonding uAPI is completely broken with GuC submission because
> +whether a submission is a single context submit or parallel submit isn't known
> +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> +contexts in parallel with the GuC the context must be explictly registered with
> +N contexts and all N contexts must be submitted in a single command to the GuC.
> +These interfaces doesn't support dynamically changing between N contexts as the
> +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> +the legacy bonding uAPI is quite confusing and not intuitive at all.
> +
> +The new parallel submission uAPI consists of 3 parts:
> +
> +* Export engines logical mapping
> +* A 'set_parallel' extension to configure contexts for parallel
> +  submission
> +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +
> +Export engines logical mapping
> +------------------------------
> +Certain use cases require BBs to be placed on engine instances in logical order
> +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> +logical mapping with the existing query engine info IOCTL. Also the GuC
> +submission interface currently only supports submitting multiple contexts to
> +engines in logical order which is a new requirement compared to execlists.
> +Lastly, all current platforms have at most 2 instances and the logical order is
> +the same a uABI order. This will change on platforms with more than 2 instances.
> +
> +A single bit will be added to drm_i915_engine_info.flags indicating that the
> +logical instance has been returned and a new field,
> +drm_i915_engine_info.logical_instance, returns the logical instance.
> +
> +A 'set_parallel' extension to configure contexts for parallel submission
> +------------------------------------------------------------------------
> +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> +It is setup step that should be called before using any of the contexts. See
> +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> +similar existing examples. Once a slot is configured for parallel submission the
> +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> +support GuC submission. Execlist support can be added later if needed.
> +
> +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> +
> +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> +-------------------------------------------------------------------
> +Contexts that have been configured with the 'set_parallel' extension are allowed
> +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> +objects in the drm_i915_gem_exec_object2 list or the first N if
> +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> +submitted and how it has been configured by 'set_parallel' or other extensions.
> +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> +the IOCTL.
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-20 19:41             ` Daniel Vetter
@ 2021-05-21 12:12               ` Tvrtko Ursulin
  -1 siblings, 0 replies; 54+ messages in thread
From: Tvrtko Ursulin @ 2021-05-21 12:12 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: Matthew Brost, intel-gfx, dri-devel, Jason Ekstrand,
	Daniel Vetter, Mesa Dev, karl, Christian König


On 20/05/2021 20:41, Daniel Vetter wrote:
> On Thu, May 20, 2021 at 11:57:44AM +0100, Tvrtko Ursulin wrote:
>>
>> On 20/05/2021 10:54, Daniel Vetter wrote:
>>> On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
>>>>
>>>> On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
>>>>> On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
>>>>>> Add entry fpr i915 new parallel submission uAPI plan.
>>>>>>
>>>>>> v2:
>>>>>>    (Daniel Vetter):
>>>>>>     - Expand logical order explaination
>>>>>>     - Add dummy header
>>>>>>     - Only allow N BBs in execbuf IOCTL
>>>>>>     - Configure parallel submission per slot not per gem context
>>>>>>
>>>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>>> Cc: Tony Ye <tony.ye@intel.com>
>>>>>> CC: Carl Zhang <carl.zhang@intel.com>
>>>>>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>>>>>> Cc: Jason Ekstrand <jason@jlekstrand.net>
>>>>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>>>>> ---
>>>>>>    Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>>>>>>    Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>>>>>>    2 files changed, 196 insertions(+), 1 deletion(-)
>>>>>>    create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>>
>>>>>> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>> new file mode 100644
>>>>>> index 000000000000..8c64b983ccad
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>> @@ -0,0 +1,144 @@
>>>>>> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
>>>>>> +
>>>>>> +/*
>>>>>> + * i915_context_engines_parallel_submit:
>>>>>> + *
>>>>>> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
>>>>>> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
>>>>>> + * hardware contexts are created internally in the i915 run these BBs. Once a
>>>>>> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
>>>>>> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
>>>>>> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
>>>>>> + * the slots configuration).
>>>>>> + *
>>>>>> + * Their are two currently defined ways to control the placement of the
>>>>>> + * hardware contexts on physical engines: default behavior (no flags) and
>>>>>> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
>>>>>> + * future as new hardware / use cases arise. Details of how to use this
>>>>>> + * interface below above the flags.
>>>>>> + *
>>>>>> + * Returns -EINVAL if hardware context placement configuration invalid or if the
>>>>>> + * placement configuration isn't supported on the platform / submission
>>>>>> + * interface.
>>>>>> + * Returns -ENODEV if extension isn't supported on the platform / submission
>>>>>> + * inteface.
>>>>>> + */
>>>>>> +struct i915_context_engines_parallel_submit {
>>>>>> +   struct i915_user_extension base;
>>>>>> +
>>>>>> +   __u16 engine_index;     /* slot for parallel engine */
>>>>>> +   __u16 width;            /* number of contexts per parallel engine */
>>>>>> +   __u16 num_siblings;     /* number of siblings per context */
>>>>>> +   __u16 mbz16;
>>>>>
>>>>> Ok the big picture looks reasonable now, the flags still confuse me.
>>>>>
>>>>
>>>> Yea, it is a bit confusing.
>>>>
>>>>>> +/*
>>>>>> + * Default placement behvavior (currently unsupported):
>>>>>> + *
>>>>>> + * Rather than restricting parallel submission to a single class with a
>>>>>> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
>>>>>> + * enables parallel submission across multiple engine classes. In this case each
>>>>>> + * context's logical engine mask indicates where that context can placed. It is
>>>>>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>>>>>> + * if one context is running CS0 no other contexts can run on CS0).
>>>>>> + *
>>>>>> + * Example 1 pseudo code:
>>>>>> + * CSX[Y] = engine class X, logical instance Y
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>>>>> + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS0[0], CS1[0]
>>>>>> + * CS0[0], CS1[1]
>>>>>> + * CS0[1], CS1[0]
>>>>>> + * CS0[1], CS1[1]
>>>>>> + *
>>>>>> + * This can also be though of as 2 virtual engines:
>>>>>> + * VE[0] = CS0[0], CS0[1]
>>>>>> + * VE[1] = CS1[0], CS1[1]
>>>>>> + *
>>>>>> + * Example 2 pseudo code:
>>>>>> + * CS[X] = generic engine of same class, logical instance X
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=3,
>>>>>> + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS[0], CS[1]
>>>>>> + * CS[0], CS[2]
>>>>>> + * CS[1], CS[0]
>>>>>> + * CS[1], CS[2]
>>>>>> + * CS[2], CS[0]
>>>>>> + * CS[2], CS[1]
>>>>>> + *
>>>>>> + *
>>>>>> + * This can also be though of as 2 virtual engines:
>>>>>> + * VE[0] = CS[0], CS[1], CS[2]
>>>>>> + * VE[1] = CS[0], CS[1], CS[2]
>>>>>> +
>>>>>> + * This enables a use case where all engines are created equally, we don't care
>>>>>> + * where they are scheduled, we just want a certain number of resources, for
>>>>>> + * those resources to be scheduled in parallel, and possibly across multiple
>>>>>> + * engine classes.
>>>>>> + */
>>>>>
>>>>> So I don't really get what this does compared to setting the flag below.
>>>>> Is this just about running the batchbuffers the wrong way round, i.e. if
>>>>> you have (simplest case)
>>>>>
>>>>> width=2, num_sibglings=1, engines=CS[0], CS[1]
>>>>>
>>>>> Then both
>>>>> CS[0], CS[1]
>>>>> and
>>>>> CS[1], CS[0]
>>>>> are possible options for running 2 batches? Iow, the backend is allowed to
>>>>> run the batchbuffers the wrong way round, which gains us nothing, since we
>>>>> assume the batches take equally long and engines interchangeable. There is
>>>>> no scheduling scenario where this additional flexibility can help.
>>>>>
>>>>> Also we don't have flags to select the only available and then specify an
>>>>> entire pipe dream about what the non-flag mode does, without an
>>>>> implementation. What is this about?
>>>>>
>>>>> If it's just "because bonded allowed this" then I think we should just
>>>>> unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
>>>>> welp.
>>>>>
>>>>
>>>> High level the flags came out of internal discussions how this interface
>>>> should look. The default placement behavior is theoretically possible
>>>> with execlists but has no use cases. The GuC supports / current use
>>>> cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
>>>>
>>>> Argued about for months and this is where we landed. At the end of the
>>>> day I think we needed to show that this interface supports more
>>>> placement rules than what the GuC supports / current use cases to future
>>>> proof this interface.
>>>>
>>>> For what is it worth it seems kinda backwards that we landed on the
>>>> default behavior not being supported in our current stack / HW.
>>>
>>> Yeah I think that should be inverted, doesn't make sense.
>>>
>>> What I still don't get (and I've read Tvrtko's reply with the example)
>>> is what exactly is the difference between implicit and not implicit
>>> mode? Can you do a single example where the only difference is whether
>>> this flag is set, and then explain with that what are the actual
>>> differences in scheduling options that the backend is allowed to pick
>>> for the set of N patches?
>>>
>>> I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
>>
>> 2-wide compute context:
>>
>>   .engine_map([-1, -1])
>>   .load_balance(0: [cs0, cs1, cs2, cs3]) // place virtual engine at slot 0
>>   .load_balance(1: [cs0, cs1, cs2, cs3])
>>   .set_parallel()
>>
>> This tells the scheduler any two of the four possible engines can be used. cs0 + cs3 is fine, cs3 + cs1 also, ... any. Only implicit rule is they have to be different and that works for all.
>>
>> 2-wide "implicit bonds mode" aka media fixed function limitation:
>>
>>   .engine_map([-1, -1])
>>   .load_balance(0: [cs0, cs2])
>>   .load_balance(1: [cs1, cs3])
>>   .set_parallel(flags = implicit_bond)
>>
>> Think of implicit flag creating a "link" between vertical columns in each virtual engine slot. So valid pairs end up cs0 + cs1 and cs2 + cs3 only.
>>
>> You can also think of the implicit flag as a shortcut to avoid specifying bonds via the existing extension. In which case context setup would be written along the lines of:
>>
>>   .engine_map([-1, -1])
>>   .load_balance(0: [cs0, cs2])
>>   .load_balance(1: [cs1, cs3])
>>   .bond(1: master = cs0, bond = [cs1])
>>   .bond(1: master = cs2, bond = [cs3])
>>   .set_parallel()
>>
>> So the implicit flag is just a shortcut to avoid typing the bonds. Not really needed as explained in my previous reply.
> 
> Ah now I get both what this means, why it exists and where it's all come
> from. With the backstory makes a bunch more sense now. Thanks for
> explaining again.
> 
>> This was at least the "old" set_parallel. I see this latest RFC changed
>> things a bit which I don't really follow yet.
>>
>> It's not perfect but needs to add very little (just one context
>> extension, on top of multi batch execbuf which is needed anyways),
>> doesn't need to deprecate anything, didn't require rewrites of the UMD,
>> and it all works today and in the future.
>>
>> I did not really like this new uapi for all the reasons I listed
>> already, but as not many people were seeing the advantage of not
>> churning on the uapi, if we are churning already I did suggests a
>> different idea. I mean if we are churning we might as well go full in.
>> So that proposal, which didn't get any traction, was along the lines of:
>>
>>   .engine_map([-1])
>>   .load_balance_wide(0: width=2, engines=[[cs0, cs2], [cs1, cs3]])
>>
>> This would create an explicit wide virtual engine which should work for
>> GuC fine I think. For execlists it may require a bit of extra glue but I
>> don't think too much.
>>
>> Advantage is there is one engine in the map now and it is N-wide by
>> definition.
>>
>> Since no one did bite on that idea back then, I didn't really pursue is
>> to see if it works for all use cases. But I think it should even if it
>> probably requires further thinking to be sure.
>>
>> If we apply it to compute use case..
>>
>>   .engine_map([-1])
>>   .load_balance_wide(0: width=2, engines=[[cs0, cs1, cs2, cs3], [cs0, cs1, cs2, cs3]])
>>
>> This means the only implicit wart in there is that cs0 + cs0 obviously
>> shouldn't be picked. But that should be fine both for execlists and
>> hopefully for the GuC.
> 
> Yeah. Another option would be to simply allow any valid pair to be listed.
> Gets maybe a bit too long for full combinatorials. Or we do an N-out-of-M
> load balance, and you just specifiy the one vector for the engine set that
> gets fully combined.

Well main complaint against bonds were that they are too verbose. 
Listing all combinations is pretty much the same so...

> Either way I think simple to add if/when compute comes around and asks for
> it.

Add what sorry lost you?

Because having just read the latest proposal it seems it is actually 
doing pretty much what I described above. Unless I got it wrong..

Anyway, I still maintain we don't really needs to add a new context 
extension apart from set_parallel(bool) since bonds can express it all 
already.

And GuC backend will have to validate the new extension anyway, as it 
would need to validate the bonds, since who says userspace has passed in 
a supported configuration even with the implicit bonds flag set. Still 
needs to check it..

At which point I really don't see the point in the uapi churn. All we 
really need is a multi batch execbuf.

*If* the desire is so strong to go the single entry in engine map can be 
N-wide then it can be done, but actually still the GuC backend will need 
to validate it all makes sense for what firmware can do.

So to me it's very questionable. Even the complaints about the weird 
stuff GuC backend does in construction-deconstruction on submit are not 
really an *uapi* problem.

Even with just set_parallel(bool) backend could interpret it all 
correctly, create a single whatever it wants, and submit a single 
whatever it wants to the GuC.

Regards,

Tvrtko

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-21 12:12               ` Tvrtko Ursulin
  0 siblings, 0 replies; 54+ messages in thread
From: Tvrtko Ursulin @ 2021-05-21 12:12 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Daniel Vetter, Mesa Dev,
	karl, Christian König


On 20/05/2021 20:41, Daniel Vetter wrote:
> On Thu, May 20, 2021 at 11:57:44AM +0100, Tvrtko Ursulin wrote:
>>
>> On 20/05/2021 10:54, Daniel Vetter wrote:
>>> On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
>>>>
>>>> On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
>>>>> On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
>>>>>> Add entry fpr i915 new parallel submission uAPI plan.
>>>>>>
>>>>>> v2:
>>>>>>    (Daniel Vetter):
>>>>>>     - Expand logical order explaination
>>>>>>     - Add dummy header
>>>>>>     - Only allow N BBs in execbuf IOCTL
>>>>>>     - Configure parallel submission per slot not per gem context
>>>>>>
>>>>>> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>>> Cc: Tony Ye <tony.ye@intel.com>
>>>>>> CC: Carl Zhang <carl.zhang@intel.com>
>>>>>> Cc: Daniel Vetter <daniel.vetter@intel.com>
>>>>>> Cc: Jason Ekstrand <jason@jlekstrand.net>
>>>>>> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
>>>>>> ---
>>>>>>    Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
>>>>>>    Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
>>>>>>    2 files changed, 196 insertions(+), 1 deletion(-)
>>>>>>    create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>>
>>>>>> diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>> new file mode 100644
>>>>>> index 000000000000..8c64b983ccad
>>>>>> --- /dev/null
>>>>>> +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
>>>>>> @@ -0,0 +1,144 @@
>>>>>> +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
>>>>>> +
>>>>>> +/*
>>>>>> + * i915_context_engines_parallel_submit:
>>>>>> + *
>>>>>> + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
>>>>>> + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
>>>>>> + * hardware contexts are created internally in the i915 run these BBs. Once a
>>>>>> + * slot is configured for N BBs only N BBs can be submitted in each execbuf
>>>>>> + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
>>>>>> + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
>>>>>> + * the slots configuration).
>>>>>> + *
>>>>>> + * Their are two currently defined ways to control the placement of the
>>>>>> + * hardware contexts on physical engines: default behavior (no flags) and
>>>>>> + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
>>>>>> + * future as new hardware / use cases arise. Details of how to use this
>>>>>> + * interface below above the flags.
>>>>>> + *
>>>>>> + * Returns -EINVAL if hardware context placement configuration invalid or if the
>>>>>> + * placement configuration isn't supported on the platform / submission
>>>>>> + * interface.
>>>>>> + * Returns -ENODEV if extension isn't supported on the platform / submission
>>>>>> + * inteface.
>>>>>> + */
>>>>>> +struct i915_context_engines_parallel_submit {
>>>>>> +   struct i915_user_extension base;
>>>>>> +
>>>>>> +   __u16 engine_index;     /* slot for parallel engine */
>>>>>> +   __u16 width;            /* number of contexts per parallel engine */
>>>>>> +   __u16 num_siblings;     /* number of siblings per context */
>>>>>> +   __u16 mbz16;
>>>>>
>>>>> Ok the big picture looks reasonable now, the flags still confuse me.
>>>>>
>>>>
>>>> Yea, it is a bit confusing.
>>>>
>>>>>> +/*
>>>>>> + * Default placement behvavior (currently unsupported):
>>>>>> + *
>>>>>> + * Rather than restricting parallel submission to a single class with a
>>>>>> + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
>>>>>> + * enables parallel submission across multiple engine classes. In this case each
>>>>>> + * context's logical engine mask indicates where that context can placed. It is
>>>>>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>>>>>> + * if one context is running CS0 no other contexts can run on CS0).
>>>>>> + *
>>>>>> + * Example 1 pseudo code:
>>>>>> + * CSX[Y] = engine class X, logical instance Y
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>>>>> + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS0[0], CS1[0]
>>>>>> + * CS0[0], CS1[1]
>>>>>> + * CS0[1], CS1[0]
>>>>>> + * CS0[1], CS1[1]
>>>>>> + *
>>>>>> + * This can also be though of as 2 virtual engines:
>>>>>> + * VE[0] = CS0[0], CS0[1]
>>>>>> + * VE[1] = CS1[0], CS1[1]
>>>>>> + *
>>>>>> + * Example 2 pseudo code:
>>>>>> + * CS[X] = generic engine of same class, logical instance X
>>>>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>>>>> + * set_engines(INVALID)
>>>>>> + * set_parallel(engine_index=0, width=2, num_siblings=3,
>>>>>> + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
>>>>>> + *
>>>>>> + * Results in the following valid placements:
>>>>>> + * CS[0], CS[1]
>>>>>> + * CS[0], CS[2]
>>>>>> + * CS[1], CS[0]
>>>>>> + * CS[1], CS[2]
>>>>>> + * CS[2], CS[0]
>>>>>> + * CS[2], CS[1]
>>>>>> + *
>>>>>> + *
>>>>>> + * This can also be though of as 2 virtual engines:
>>>>>> + * VE[0] = CS[0], CS[1], CS[2]
>>>>>> + * VE[1] = CS[0], CS[1], CS[2]
>>>>>> +
>>>>>> + * This enables a use case where all engines are created equally, we don't care
>>>>>> + * where they are scheduled, we just want a certain number of resources, for
>>>>>> + * those resources to be scheduled in parallel, and possibly across multiple
>>>>>> + * engine classes.
>>>>>> + */
>>>>>
>>>>> So I don't really get what this does compared to setting the flag below.
>>>>> Is this just about running the batchbuffers the wrong way round, i.e. if
>>>>> you have (simplest case)
>>>>>
>>>>> width=2, num_sibglings=1, engines=CS[0], CS[1]
>>>>>
>>>>> Then both
>>>>> CS[0], CS[1]
>>>>> and
>>>>> CS[1], CS[0]
>>>>> are possible options for running 2 batches? Iow, the backend is allowed to
>>>>> run the batchbuffers the wrong way round, which gains us nothing, since we
>>>>> assume the batches take equally long and engines interchangeable. There is
>>>>> no scheduling scenario where this additional flexibility can help.
>>>>>
>>>>> Also we don't have flags to select the only available and then specify an
>>>>> entire pipe dream about what the non-flag mode does, without an
>>>>> implementation. What is this about?
>>>>>
>>>>> If it's just "because bonded allowed this" then I think we should just
>>>>> unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
>>>>> welp.
>>>>>
>>>>
>>>> High level the flags came out of internal discussions how this interface
>>>> should look. The default placement behavior is theoretically possible
>>>> with execlists but has no use cases. The GuC supports / current use
>>>> cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
>>>>
>>>> Argued about for months and this is where we landed. At the end of the
>>>> day I think we needed to show that this interface supports more
>>>> placement rules than what the GuC supports / current use cases to future
>>>> proof this interface.
>>>>
>>>> For what is it worth it seems kinda backwards that we landed on the
>>>> default behavior not being supported in our current stack / HW.
>>>
>>> Yeah I think that should be inverted, doesn't make sense.
>>>
>>> What I still don't get (and I've read Tvrtko's reply with the example)
>>> is what exactly is the difference between implicit and not implicit
>>> mode? Can you do a single example where the only difference is whether
>>> this flag is set, and then explain with that what are the actual
>>> differences in scheduling options that the backend is allowed to pick
>>> for the set of N patches?
>>>
>>> I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
>>
>> 2-wide compute context:
>>
>>   .engine_map([-1, -1])
>>   .load_balance(0: [cs0, cs1, cs2, cs3]) // place virtual engine at slot 0
>>   .load_balance(1: [cs0, cs1, cs2, cs3])
>>   .set_parallel()
>>
>> This tells the scheduler any two of the four possible engines can be used. cs0 + cs3 is fine, cs3 + cs1 also, ... any. Only implicit rule is they have to be different and that works for all.
>>
>> 2-wide "implicit bonds mode" aka media fixed function limitation:
>>
>>   .engine_map([-1, -1])
>>   .load_balance(0: [cs0, cs2])
>>   .load_balance(1: [cs1, cs3])
>>   .set_parallel(flags = implicit_bond)
>>
>> Think of implicit flag creating a "link" between vertical columns in each virtual engine slot. So valid pairs end up cs0 + cs1 and cs2 + cs3 only.
>>
>> You can also think of the implicit flag as a shortcut to avoid specifying bonds via the existing extension. In which case context setup would be written along the lines of:
>>
>>   .engine_map([-1, -1])
>>   .load_balance(0: [cs0, cs2])
>>   .load_balance(1: [cs1, cs3])
>>   .bond(1: master = cs0, bond = [cs1])
>>   .bond(1: master = cs2, bond = [cs3])
>>   .set_parallel()
>>
>> So the implicit flag is just a shortcut to avoid typing the bonds. Not really needed as explained in my previous reply.
> 
> Ah now I get both what this means, why it exists and where it's all come
> from. With the backstory makes a bunch more sense now. Thanks for
> explaining again.
> 
>> This was at least the "old" set_parallel. I see this latest RFC changed
>> things a bit which I don't really follow yet.
>>
>> It's not perfect but needs to add very little (just one context
>> extension, on top of multi batch execbuf which is needed anyways),
>> doesn't need to deprecate anything, didn't require rewrites of the UMD,
>> and it all works today and in the future.
>>
>> I did not really like this new uapi for all the reasons I listed
>> already, but as not many people were seeing the advantage of not
>> churning on the uapi, if we are churning already I did suggests a
>> different idea. I mean if we are churning we might as well go full in.
>> So that proposal, which didn't get any traction, was along the lines of:
>>
>>   .engine_map([-1])
>>   .load_balance_wide(0: width=2, engines=[[cs0, cs2], [cs1, cs3]])
>>
>> This would create an explicit wide virtual engine which should work for
>> GuC fine I think. For execlists it may require a bit of extra glue but I
>> don't think too much.
>>
>> Advantage is there is one engine in the map now and it is N-wide by
>> definition.
>>
>> Since no one did bite on that idea back then, I didn't really pursue is
>> to see if it works for all use cases. But I think it should even if it
>> probably requires further thinking to be sure.
>>
>> If we apply it to compute use case..
>>
>>   .engine_map([-1])
>>   .load_balance_wide(0: width=2, engines=[[cs0, cs1, cs2, cs3], [cs0, cs1, cs2, cs3]])
>>
>> This means the only implicit wart in there is that cs0 + cs0 obviously
>> shouldn't be picked. But that should be fine both for execlists and
>> hopefully for the GuC.
> 
> Yeah. Another option would be to simply allow any valid pair to be listed.
> Gets maybe a bit too long for full combinatorials. Or we do an N-out-of-M
> load balance, and you just specifiy the one vector for the engine set that
> gets fully combined.

Well main complaint against bonds were that they are too verbose. 
Listing all combinations is pretty much the same so...

> Either way I think simple to add if/when compute comes around and asks for
> it.

Add what sorry lost you?

Because having just read the latest proposal it seems it is actually 
doing pretty much what I described above. Unless I got it wrong..

Anyway, I still maintain we don't really needs to add a new context 
extension apart from set_parallel(bool) since bonds can express it all 
already.

And GuC backend will have to validate the new extension anyway, as it 
would need to validate the bonds, since who says userspace has passed in 
a supported configuration even with the implicit bonds flag set. Still 
needs to check it..

At which point I really don't see the point in the uapi churn. All we 
really need is a multi batch execbuf.

*If* the desire is so strong to go the single entry in engine map can be 
N-wide then it can be done, but actually still the GuC backend will need 
to validate it all makes sense for what firmware can do.

So to me it's very questionable. Even the complaints about the weird 
stuff GuC backend does in construction-deconstruction on submit are not 
really an *uapi* problem.

Even with just set_parallel(bool) backend could interpret it all 
correctly, create a single whatever it wants, and submit a single 
whatever it wants to the GuC.

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-21  8:35               ` Christian König
@ 2021-05-21 16:14                 ` Matthew Brost
  -1 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-21 16:14 UTC (permalink / raw)
  To: Christian König
  Cc: Intel GFX, Maling list - DRI developers, Jason Ekstrand,
	Jason Ekstrand, ML mesa-dev, Daniel Vetter, karl,
	Christian König

On Fri, May 21, 2021 at 10:35:37AM +0200, Christian König wrote:
> Am 20.05.21 um 23:38 schrieb Jason Ekstrand:
> > On Thu, May 20, 2021 at 10:46 AM Matthew Brost <matthew.brost@intel.com> wrote:
> > > On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote:
> > > > Am 19.05.21 um 18:51 schrieb Matthew Brost:
> > > > > On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
> > > > > > Oh, yeah we call that gang submit on the AMD side.
> > > > > > 
> > > > > > Had already some internal discussions how to implement this, but so far
> > > > > > couldn't figure out how to cleanly introduce that into the DRM scheduler.
> > > > > > 
> > > > > > Can you briefly describe in a few words how that is supposed to work on the
> > > > > > Intel side?
> > On Intel, we actually have two cases which don't fit the current
> > drm/scheduler model well: balanced and bonded.
> > 
> > In the balanced model, we want to submit a batch which can go to any
> > one of some set of engines and we don't care which.  It's up to the
> > kernel to pick an engine.  Imagine you had 64 identical HW compute
> > queues, for instance.  This could be done by making all the identical
> > engines share a single drm_gpu_scheduler and round-robin around the HW
> > queues or something.  I don't know that we strictly need drm/scheduler
> > to be aware of it but it might be nice if it grew support for this
> > mode so we could maintain a 1:1 relationship between HW queues and
> > drm_gpu_schedulers.  That said, I'm not sure how this would play with
> > GuC queues so maybe it doesn't help?
> 
> Oh, we do have support for load balancing like that.
> 
> When you call drm_sched_entity_init() you can give a list of
> drm_gpu_scheduler object to use round robing for scheduling.
> 
> New jobs are then scheduler to the drm_gpu_scheduler instance which is idle
> or rather the least busy one.
> 
> > The bonded model is like your ganged, I think.  We want to submit N
> > batches to run in parallel.  And they actually have to be executing on
> > the GPU simultaneously and not just sort-of at similar times.  We need
> > this for video.  There are also potential use-cases in Vulkan or even
> > GL that might be able to use this.  One difference with the balanced
> > mode is that bonds don't, strictly speaking, need to be on the same
> > type of engine.  Imagine, for instance, a 3D batch with a parallel
> > compute batch doing vertex pre-processing.
> > 
> > I'm pretty sure the bonded case is something that the mobile drivers
> > (panfrost, etc.) would like as well for doing Vulkan on tilers where
> > you often have to have two command buffers running in parallel.
> > They're currently doing it by submitting a giant pile of batches where
> > they split the batch and add sync primitives every time some GL call
> > requires them to sync between fragment and vertex pipes.
> 
> Yeah, we have exactly the same problem as well.
> 
> But so far every model we discussed has some drawbacks and it is rather hard
> for the scheduler to guarantee that stuff runs at the same time.
> 
> So if you got any ideas how to cleanly implement that then they would be
> rather welcomed.
> 

Everything Jason said about our submission modes is correct for execlists, we
have balanced + bonded models which is tightly coupled with that backend.

Fortunately with GuC submission most of this complexity goes away as the GuC
handles this for us. e.g. For balanced when we register a context we just give
it a mask of which physical engines a context is allowed to run on. For parallel
we register N contexts in a single command with the placement information +
submit to all the contexts with a command which moves the tails in LRCs for us.
We really don't need to bake any of this into the DRM scheduler for GuC
submission. 

Execlists is different story but I think our plan is to do the minimum possible
to plum that into the DRM scheduler (e.g. leave the balanced / bonded code in
the backend). Could we update the DRM scheduler to understand balanced (seems
like already does to some extent) and bonded? Yes we could but IMO the ROI on
that is low for Intel. The DRM scheduler is quite clean at the moment compared
to our near incomprehensible execlist backend. Execlists are basically a legacy
interface so pushing features which are only required for that backend to the
DRM scheduler doesn't make sense to me. That being said, if this is something
AMD needs in the DRM scheduler of course we can support you.

Matt

> Regards,
> Christian.
> 
> > 
> > So, to sum up, I think there's likely some good collaboration to be
> > had here for everyone. :-)
> > 
> > --Jason
> > 
> > > > > Sure, I've done a quick PoC internally and have been able to hook this
> > > > > into the DRM scheduler.
> > > > > 
> > > > > Basically each BB still maps to a single job as each job is somewhat
> > > > > unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
> > > > > the jobs configured to run in parallel map to a single sched_entity
> > > > > which maintains the order each job was generated from the execbuf IOCTL
> > > > > (1 - N). When the backend receives jobs 1 to N - 1 it basically just
> > > > > updates some internal state. When the backend sees job N (last job) it
> > > > > actually does the submit for jobs 1 - N which with GuC submission is a
> > > > > simple command moving the LRC tail of the N jobs.
> > > > > 
> > > > > Daniel has suggested that we create a single job for the NN BBs but that
> > > > > would be huge rework to the internals of the i915 and likely won't
> > > > > happen by the time this code first lands.
> > > > > 
> > > > > Also worth noting one way a job isn't really a treated individually is
> > > > > the excl slot with dma-resv. In that case we create a composite fence of
> > > > > all jobs (dma_fence_array).
> > > > Yeah, that's something we have discussed as well.
> > > > 
> > > > How do you prevent the scheduler from over committing to a single ring
> > > > buffer in this scenario?
> > > > 
> > > Each job has its own ring, the execbuf IOCTL throttles itself for each
> > > job if there isn't space in the ring. This is exactly the same as
> > > non-parallel submits.
> > > 
> > > I think this is what you were asking? If not, maybe try explaining the
> > > question a bit more.
> > > 
> > > Matt
> > > 
> > > > Christian.
> > > > 
> > > > > Matt
> > > > > 
> > > > > > Thanks,
> > > > > > Christian.
> > > > > > 
> > > > > > Am 19.05.21 um 01:58 schrieb Matthew Brost:
> > > > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > > > > 
> > > > > > > v2:
> > > > > > >     (Daniel Vetter):
> > > > > > >      - Expand logical order explaination
> > > > > > >      - Add dummy header
> > > > > > >      - Only allow N BBs in execbuf IOCTL
> > > > > > >      - Configure parallel submission per slot not per gem context
> > > > > > > 
> > > > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > > > ---
> > > > > > >     Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > > > >     Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > > > >     2 files changed, 196 insertions(+), 1 deletion(-)
> > > > > > >     create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > > 
> > > > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > > new file mode 100644
> > > > > > > index 000000000000..8c64b983ccad
> > > > > > > --- /dev/null
> > > > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > > @@ -0,0 +1,144 @@
> > > > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > > > +
> > > > > > > +/*
> > > > > > > + * i915_context_engines_parallel_submit:
> > > > > > > + *
> > > > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > > > + * the slots configuration).
> > > > > > > + *
> > > > > > > + * Their are two currently defined ways to control the placement of the
> > > > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > > > + * interface below above the flags.
> > > > > > > + *
> > > > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > > > + * placement configuration isn't supported on the platform / submission
> > > > > > > + * interface.
> > > > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > > > + * inteface.
> > > > > > > + */
> > > > > > > +struct i915_context_engines_parallel_submit {
> > > > > > > +       struct i915_user_extension base;
> > > > > > > +
> > > > > > > +       __u16 engine_index;     /* slot for parallel engine */
> > > > > > > +       __u16 width;            /* number of contexts per parallel engine */
> > > > > > > +       __u16 num_siblings;     /* number of siblings per context */
> > > > > > > +       __u16 mbz16;
> > > > > > > +/*
> > > > > > > + * Default placement behvavior (currently unsupported):
> > > > > > > + *
> > > > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > > > + *
> > > > > > > + * Example 1 pseudo code:
> > > > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > > + * set_engines(INVALID)
> > > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > > > + *             engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > > > + *
> > > > > > > + * Results in the following valid placements:
> > > > > > > + * CS0[0], CS1[0]
> > > > > > > + * CS0[0], CS1[1]
> > > > > > > + * CS0[1], CS1[0]
> > > > > > > + * CS0[1], CS1[1]
> > > > > > > + *
> > > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > > > + *
> > > > > > > + * Example 2 pseudo code:
> > > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > > + * set_engines(INVALID)
> > > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > > > + *             engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > > > + *
> > > > > > > + * Results in the following valid placements:
> > > > > > > + * CS[0], CS[1]
> > > > > > > + * CS[0], CS[2]
> > > > > > > + * CS[1], CS[0]
> > > > > > > + * CS[1], CS[2]
> > > > > > > + * CS[2], CS[0]
> > > > > > > + * CS[2], CS[1]
> > > > > > > + *
> > > > > > > + *
> > > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > > > +
> > > > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > > > + * engine classes.
> > > > > > > + */
> > > > > > > +
> > > > > > > +/*
> > > > > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > > > > + * of the siblings.
> > > > > > > + *
> > > > > > > + * All of the below examples are in logical space.
> > > > > > > + *
> > > > > > > + * Example 1 pseudo code:
> > > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > > + * set_engines(INVALID)
> > > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > > > > + *             engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > > > + *
> > > > > > > + * Results in the following valid placements:
> > > > > > > + * CS[0], CS[1]
> > > > > > > + *
> > > > > > > + * Example 2 pseudo code:
> > > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > > + * set_engines(INVALID)
> > > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > > > + *             engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > > > + *
> > > > > > > + * Results in the following valid placements:
> > > > > > > + * CS[0], CS[1]
> > > > > > > + * CS[2], CS[3]
> > > > > > > + *
> > > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > > + * VE[0] = CS[0], CS[2]
> > > > > > > + * VE[1] = CS[1], CS[3]
> > > > > > > + *
> > > > > > > + * This enables a use case where all engines are not equal and certain placement
> > > > > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > > > > + * case (logically contiguous placement, within a single engine class) is
> > > > > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > > > > + * bonding configurations but currently doesn't support this extension.
> > > > > > > + */
> > > > > > > +#define I915_PARALLEL_IMPLICT_BONDS                    (1<<0)
> > > > > > > +/*
> > > > > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > > > > + */
> > > > > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH             (1<<1)
> > > > > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS  (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > > > > +       __u64 flags;            /* all undefined flags must be zero */
> > > > > > > +       __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > > > > > +
> > > > > > > +       /*
> > > > > > > +        * width (i) * num_siblings (j) in length
> > > > > > > +        * index = j + i * num_siblings
> > > > > > > +        */
> > > > > > > +       struct i915_engine_class_instance engines[0];
> > > > > > > +} __attribute__ ((packed));
> > > > > > > +
> > > > > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > > index 7faa46cde088..64c539486ee4 100644
> > > > > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > > @@ -82,4 +82,55 @@ https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fspec.oneapi.com%2Flevel-zero%2Flatest%2Fcore%2Fapi.html%23ze-command-queue-priorit&amp;data=04%7C01%7Cchristian.koenig%40amd.com%7C49a7557f4e494090755608d91ae758a6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637570403202969375%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=dn3PVdxYQpkpWIru5eAXHgbfuLDkppAA5daV5sHQF7s%3D&amp;reserved=0
> > > > > > >     New parallel submission uAPI
> > > > > > >     ============================
> > > > > > > -Details to come in a following patch.
> > > > > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > > > > +
> > > > > > > +The new parallel submission uAPI consists of 3 parts:
> > > > > > > +
> > > > > > > +* Export engines logical mapping
> > > > > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > > > > +  submission
> > > > > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > > > +
> > > > > > > +Export engines logical mapping
> > > > > > > +------------------------------
> > > > > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > > > > +submission interface currently only supports submitting multiple contexts to
> > > > > > > +engines in logical order which is a new requirement compared to execlists.
> > > > > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > > > > +
> > > > > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > > > > +logical instance has been returned and a new field,
> > > > > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > > > > +
> > > > > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > > > > +------------------------------------------------------------------------
> > > > > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > > > > +It is setup step that should be called before using any of the contexts. See
> > > > > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > > > > +support GuC submission. Execlist support can be added later if needed.
> > > > > > > +
> > > > > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > > > > +
> > > > > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > > > +-------------------------------------------------------------------
> > > > > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > > > > +the IOCTL.
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [Mesa-dev] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-21 16:14                 ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-21 16:14 UTC (permalink / raw)
  To: Christian König
  Cc: Intel GFX, Maling list - DRI developers, Jason Ekstrand,
	ML mesa-dev, Daniel Vetter, karl, Christian König

On Fri, May 21, 2021 at 10:35:37AM +0200, Christian König wrote:
> Am 20.05.21 um 23:38 schrieb Jason Ekstrand:
> > On Thu, May 20, 2021 at 10:46 AM Matthew Brost <matthew.brost@intel.com> wrote:
> > > On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote:
> > > > Am 19.05.21 um 18:51 schrieb Matthew Brost:
> > > > > On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
> > > > > > Oh, yeah we call that gang submit on the AMD side.
> > > > > > 
> > > > > > Had already some internal discussions how to implement this, but so far
> > > > > > couldn't figure out how to cleanly introduce that into the DRM scheduler.
> > > > > > 
> > > > > > Can you briefly describe in a few words how that is supposed to work on the
> > > > > > Intel side?
> > On Intel, we actually have two cases which don't fit the current
> > drm/scheduler model well: balanced and bonded.
> > 
> > In the balanced model, we want to submit a batch which can go to any
> > one of some set of engines and we don't care which.  It's up to the
> > kernel to pick an engine.  Imagine you had 64 identical HW compute
> > queues, for instance.  This could be done by making all the identical
> > engines share a single drm_gpu_scheduler and round-robin around the HW
> > queues or something.  I don't know that we strictly need drm/scheduler
> > to be aware of it but it might be nice if it grew support for this
> > mode so we could maintain a 1:1 relationship between HW queues and
> > drm_gpu_schedulers.  That said, I'm not sure how this would play with
> > GuC queues so maybe it doesn't help?
> 
> Oh, we do have support for load balancing like that.
> 
> When you call drm_sched_entity_init() you can give a list of
> drm_gpu_scheduler object to use round robing for scheduling.
> 
> New jobs are then scheduler to the drm_gpu_scheduler instance which is idle
> or rather the least busy one.
> 
> > The bonded model is like your ganged, I think.  We want to submit N
> > batches to run in parallel.  And they actually have to be executing on
> > the GPU simultaneously and not just sort-of at similar times.  We need
> > this for video.  There are also potential use-cases in Vulkan or even
> > GL that might be able to use this.  One difference with the balanced
> > mode is that bonds don't, strictly speaking, need to be on the same
> > type of engine.  Imagine, for instance, a 3D batch with a parallel
> > compute batch doing vertex pre-processing.
> > 
> > I'm pretty sure the bonded case is something that the mobile drivers
> > (panfrost, etc.) would like as well for doing Vulkan on tilers where
> > you often have to have two command buffers running in parallel.
> > They're currently doing it by submitting a giant pile of batches where
> > they split the batch and add sync primitives every time some GL call
> > requires them to sync between fragment and vertex pipes.
> 
> Yeah, we have exactly the same problem as well.
> 
> But so far every model we discussed has some drawbacks and it is rather hard
> for the scheduler to guarantee that stuff runs at the same time.
> 
> So if you got any ideas how to cleanly implement that then they would be
> rather welcomed.
> 

Everything Jason said about our submission modes is correct for execlists, we
have balanced + bonded models which is tightly coupled with that backend.

Fortunately with GuC submission most of this complexity goes away as the GuC
handles this for us. e.g. For balanced when we register a context we just give
it a mask of which physical engines a context is allowed to run on. For parallel
we register N contexts in a single command with the placement information +
submit to all the contexts with a command which moves the tails in LRCs for us.
We really don't need to bake any of this into the DRM scheduler for GuC
submission. 

Execlists is different story but I think our plan is to do the minimum possible
to plum that into the DRM scheduler (e.g. leave the balanced / bonded code in
the backend). Could we update the DRM scheduler to understand balanced (seems
like already does to some extent) and bonded? Yes we could but IMO the ROI on
that is low for Intel. The DRM scheduler is quite clean at the moment compared
to our near incomprehensible execlist backend. Execlists are basically a legacy
interface so pushing features which are only required for that backend to the
DRM scheduler doesn't make sense to me. That being said, if this is something
AMD needs in the DRM scheduler of course we can support you.

Matt

> Regards,
> Christian.
> 
> > 
> > So, to sum up, I think there's likely some good collaboration to be
> > had here for everyone. :-)
> > 
> > --Jason
> > 
> > > > > Sure, I've done a quick PoC internally and have been able to hook this
> > > > > into the DRM scheduler.
> > > > > 
> > > > > Basically each BB still maps to a single job as each job is somewhat
> > > > > unique (e.g. each job has its own ring, lrc, seqno, etc...). However all
> > > > > the jobs configured to run in parallel map to a single sched_entity
> > > > > which maintains the order each job was generated from the execbuf IOCTL
> > > > > (1 - N). When the backend receives jobs 1 to N - 1 it basically just
> > > > > updates some internal state. When the backend sees job N (last job) it
> > > > > actually does the submit for jobs 1 - N which with GuC submission is a
> > > > > simple command moving the LRC tail of the N jobs.
> > > > > 
> > > > > Daniel has suggested that we create a single job for the NN BBs but that
> > > > > would be huge rework to the internals of the i915 and likely won't
> > > > > happen by the time this code first lands.
> > > > > 
> > > > > Also worth noting one way a job isn't really a treated individually is
> > > > > the excl slot with dma-resv. In that case we create a composite fence of
> > > > > all jobs (dma_fence_array).
> > > > Yeah, that's something we have discussed as well.
> > > > 
> > > > How do you prevent the scheduler from over committing to a single ring
> > > > buffer in this scenario?
> > > > 
> > > Each job has its own ring, the execbuf IOCTL throttles itself for each
> > > job if there isn't space in the ring. This is exactly the same as
> > > non-parallel submits.
> > > 
> > > I think this is what you were asking? If not, maybe try explaining the
> > > question a bit more.
> > > 
> > > Matt
> > > 
> > > > Christian.
> > > > 
> > > > > Matt
> > > > > 
> > > > > > Thanks,
> > > > > > Christian.
> > > > > > 
> > > > > > Am 19.05.21 um 01:58 schrieb Matthew Brost:
> > > > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > > > > 
> > > > > > > v2:
> > > > > > >     (Daniel Vetter):
> > > > > > >      - Expand logical order explaination
> > > > > > >      - Add dummy header
> > > > > > >      - Only allow N BBs in execbuf IOCTL
> > > > > > >      - Configure parallel submission per slot not per gem context
> > > > > > > 
> > > > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > > > ---
> > > > > > >     Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > > > >     Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > > > >     2 files changed, 196 insertions(+), 1 deletion(-)
> > > > > > >     create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > > 
> > > > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > > new file mode 100644
> > > > > > > index 000000000000..8c64b983ccad
> > > > > > > --- /dev/null
> > > > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > > @@ -0,0 +1,144 @@
> > > > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > > > +
> > > > > > > +/*
> > > > > > > + * i915_context_engines_parallel_submit:
> > > > > > > + *
> > > > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > > > + * the slots configuration).
> > > > > > > + *
> > > > > > > + * Their are two currently defined ways to control the placement of the
> > > > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > > > + * interface below above the flags.
> > > > > > > + *
> > > > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > > > + * placement configuration isn't supported on the platform / submission
> > > > > > > + * interface.
> > > > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > > > + * inteface.
> > > > > > > + */
> > > > > > > +struct i915_context_engines_parallel_submit {
> > > > > > > +       struct i915_user_extension base;
> > > > > > > +
> > > > > > > +       __u16 engine_index;     /* slot for parallel engine */
> > > > > > > +       __u16 width;            /* number of contexts per parallel engine */
> > > > > > > +       __u16 num_siblings;     /* number of siblings per context */
> > > > > > > +       __u16 mbz16;
> > > > > > > +/*
> > > > > > > + * Default placement behvavior (currently unsupported):
> > > > > > > + *
> > > > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > > > + *
> > > > > > > + * Example 1 pseudo code:
> > > > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > > + * set_engines(INVALID)
> > > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > > > + *             engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > > > + *
> > > > > > > + * Results in the following valid placements:
> > > > > > > + * CS0[0], CS1[0]
> > > > > > > + * CS0[0], CS1[1]
> > > > > > > + * CS0[1], CS1[0]
> > > > > > > + * CS0[1], CS1[1]
> > > > > > > + *
> > > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > > > + *
> > > > > > > + * Example 2 pseudo code:
> > > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > > + * set_engines(INVALID)
> > > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > > > + *             engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > > > + *
> > > > > > > + * Results in the following valid placements:
> > > > > > > + * CS[0], CS[1]
> > > > > > > + * CS[0], CS[2]
> > > > > > > + * CS[1], CS[0]
> > > > > > > + * CS[1], CS[2]
> > > > > > > + * CS[2], CS[0]
> > > > > > > + * CS[2], CS[1]
> > > > > > > + *
> > > > > > > + *
> > > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > > > +
> > > > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > > > + * engine classes.
> > > > > > > + */
> > > > > > > +
> > > > > > > +/*
> > > > > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > > > > + * of the siblings.
> > > > > > > + *
> > > > > > > + * All of the below examples are in logical space.
> > > > > > > + *
> > > > > > > + * Example 1 pseudo code:
> > > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > > + * set_engines(INVALID)
> > > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > > > > + *             engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > > > + *
> > > > > > > + * Results in the following valid placements:
> > > > > > > + * CS[0], CS[1]
> > > > > > > + *
> > > > > > > + * Example 2 pseudo code:
> > > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > > + * set_engines(INVALID)
> > > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > > > + *             engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > > > + *
> > > > > > > + * Results in the following valid placements:
> > > > > > > + * CS[0], CS[1]
> > > > > > > + * CS[2], CS[3]
> > > > > > > + *
> > > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > > + * VE[0] = CS[0], CS[2]
> > > > > > > + * VE[1] = CS[1], CS[3]
> > > > > > > + *
> > > > > > > + * This enables a use case where all engines are not equal and certain placement
> > > > > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > > > > + * case (logically contiguous placement, within a single engine class) is
> > > > > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > > > > + * bonding configurations but currently doesn't support this extension.
> > > > > > > + */
> > > > > > > +#define I915_PARALLEL_IMPLICT_BONDS                    (1<<0)
> > > > > > > +/*
> > > > > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > > > > + */
> > > > > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH             (1<<1)
> > > > > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS  (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > > > > +       __u64 flags;            /* all undefined flags must be zero */
> > > > > > > +       __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > > > > > +
> > > > > > > +       /*
> > > > > > > +        * width (i) * num_siblings (j) in length
> > > > > > > +        * index = j + i * num_siblings
> > > > > > > +        */
> > > > > > > +       struct i915_engine_class_instance engines[0];
> > > > > > > +} __attribute__ ((packed));
> > > > > > > +
> > > > > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > > index 7faa46cde088..64c539486ee4 100644
> > > > > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > > @@ -82,4 +82,55 @@ https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fspec.oneapi.com%2Flevel-zero%2Flatest%2Fcore%2Fapi.html%23ze-command-queue-priorit&amp;data=04%7C01%7Cchristian.koenig%40amd.com%7C49a7557f4e494090755608d91ae758a6%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637570403202969375%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=dn3PVdxYQpkpWIru5eAXHgbfuLDkppAA5daV5sHQF7s%3D&amp;reserved=0
> > > > > > >     New parallel submission uAPI
> > > > > > >     ============================
> > > > > > > -Details to come in a following patch.
> > > > > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > > > > +
> > > > > > > +The new parallel submission uAPI consists of 3 parts:
> > > > > > > +
> > > > > > > +* Export engines logical mapping
> > > > > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > > > > +  submission
> > > > > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > > > +
> > > > > > > +Export engines logical mapping
> > > > > > > +------------------------------
> > > > > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > > > > +submission interface currently only supports submitting multiple contexts to
> > > > > > > +engines in logical order which is a new requirement compared to execlists.
> > > > > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > > > > +
> > > > > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > > > > +logical instance has been returned and a new field,
> > > > > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > > > > +
> > > > > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > > > > +------------------------------------------------------------------------
> > > > > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > > > > +It is setup step that should be called before using any of the contexts. See
> > > > > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > > > > +support GuC submission. Execlist support can be added later if needed.
> > > > > > > +
> > > > > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > > > > +
> > > > > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > > > +-------------------------------------------------------------------
> > > > > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > > > > +the IOCTL.
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-20 19:44             ` Daniel Vetter
@ 2021-05-21 16:20               ` Matthew Brost
  -1 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-21 16:20 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Mesa Dev, Daniel Vetter,
	karl, Christian König

On Thu, May 20, 2021 at 09:44:59PM +0200, Daniel Vetter wrote:
> On Thu, May 20, 2021 at 08:10:59AM -0700, Matthew Brost wrote:
> > On Thu, May 20, 2021 at 11:54:25AM +0200, Daniel Vetter wrote:
> > > On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
> > > >
> > > > On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > > > > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > > >
> > > > > > v2:
> > > > > >  (Daniel Vetter):
> > > > > >   - Expand logical order explaination
> > > > > >   - Add dummy header
> > > > > >   - Only allow N BBs in execbuf IOCTL
> > > > > >   - Configure parallel submission per slot not per gem context
> > > > > >
> > > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > > ---
> > > > > >  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > > >  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > > >  2 files changed, 196 insertions(+), 1 deletion(-)
> > > > > >  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > >
> > > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > new file mode 100644
> > > > > > index 000000000000..8c64b983ccad
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > @@ -0,0 +1,144 @@
> > > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > > +
> > > > > > +/*
> > > > > > + * i915_context_engines_parallel_submit:
> > > > > > + *
> > > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > > + * the slots configuration).
> > > > > > + *
> > > > > > + * Their are two currently defined ways to control the placement of the
> > > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > > + * interface below above the flags.
> > > > > > + *
> > > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > > + * placement configuration isn't supported on the platform / submission
> > > > > > + * interface.
> > > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > > + * inteface.
> > > > > > + */
> > > > > > +struct i915_context_engines_parallel_submit {
> > > > > > +   struct i915_user_extension base;
> > > > > > +
> > > > > > +   __u16 engine_index;     /* slot for parallel engine */
> > > > > > +   __u16 width;            /* number of contexts per parallel engine */
> > > > > > +   __u16 num_siblings;     /* number of siblings per context */
> > > > > > +   __u16 mbz16;
> > > > >
> > > > > Ok the big picture looks reasonable now, the flags still confuse me.
> > > > >
> > > >
> > > > Yea, it is a bit confusing.
> > > >
> > > > > > +/*
> > > > > > + * Default placement behvavior (currently unsupported):
> > > > > > + *
> > > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > > + *
> > > > > > + * Example 1 pseudo code:
> > > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS0[0], CS1[0]
> > > > > > + * CS0[0], CS1[1]
> > > > > > + * CS0[1], CS1[0]
> > > > > > + * CS0[1], CS1[1]
> > > > > > + *
> > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > > + *
> > > > > > + * Example 2 pseudo code:
> > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS[0], CS[1]
> > > > > > + * CS[0], CS[2]
> > > > > > + * CS[1], CS[0]
> > > > > > + * CS[1], CS[2]
> > > > > > + * CS[2], CS[0]
> > > > > > + * CS[2], CS[1]
> > > > > > + *
> > > > > > + *
> > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > > +
> > > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > > + * engine classes.
> > > > > > + */
> > > > >
> > > > > So I don't really get what this does compared to setting the flag below.
> > > > > Is this just about running the batchbuffers the wrong way round, i.e. if
> > > > > you have (simplest case)
> > > > >
> > > > > width=2, num_sibglings=1, engines=CS[0], CS[1]
> > > > >
> > > > > Then both
> > > > > CS[0], CS[1]
> > > > > and
> > > > > CS[1], CS[0]
> > > > > are possible options for running 2 batches? Iow, the backend is allowed to
> > > > > run the batchbuffers the wrong way round, which gains us nothing, since we
> > > > > assume the batches take equally long and engines interchangeable. There is
> > > > > no scheduling scenario where this additional flexibility can help.
> > > > >
> > > > > Also we don't have flags to select the only available and then specify an
> > > > > entire pipe dream about what the non-flag mode does, without an
> > > > > implementation. What is this about?
> > > > >
> > > > > If it's just "because bonded allowed this" then I think we should just
> > > > > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > > > > welp.
> > > > >
> > > >
> > > > High level the flags came out of internal discussions how this interface
> > > > should look. The default placement behavior is theoretically possible
> > > > with execlists but has no use cases. The GuC supports / current use
> > > > cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
> > > >
> > > > Argued about for months and this is where we landed. At the end of the
> > > > day I think we needed to show that this interface supports more
> > > > placement rules than what the GuC supports / current use cases to future
> > > > proof this interface.
> > > >
> > > > For what is it worth it seems kinda backwards that we landed on the
> > > > default behavior not being supported in our current stack / HW.
> > > 
> > > Yeah I think that should be inverted, doesn't make sense.
> > > 
> > > What I still don't get (and I've read Tvrtko's reply with the example)
> > > is what exactly is the difference between implicit and not implicit
> > > mode? Can you do a single example where the only difference is whether
> > > this flag is set, and then explain with that what are the actual
> > > differences in scheduling options that the backend is allowed to pick
> > > for the set of N patches?
> > > 
> > > I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
> > > 
> > > > > > +
> > > > > > +/*
> > > > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > > > + * of the siblings.
> > > > > > + *
> > > > > > + * All of the below examples are in logical space.
> > > > > > + *
> > > > > > + * Example 1 pseudo code:
> > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > > > + *         engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS[0], CS[1]
> > > > > > + *
> > > > > > + * Example 2 pseudo code:
> > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > > + *         engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS[0], CS[1]
> > > > > > + * CS[2], CS[3]
> > > > > > + *
> > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > + * VE[0] = CS[0], CS[2]
> > > > > > + * VE[1] = CS[1], CS[3]
> > > > > > + *
> > > > > > + * This enables a use case where all engines are not equal and certain placement
> > > > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > > > + * case (logically contiguous placement, within a single engine class) is
> > > > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > > > + * bonding configurations but currently doesn't support this extension.
> > > > > > + */
> > > > > > +#define I915_PARALLEL_IMPLICT_BONDS                        (1<<0)
> > > > >
> > > > > Does this map to intel_context_set_nopreempt(), so we could implement it
> > > > > also in execlist?
> > > > >
> > > >
> > > > intel_context_set_nopreempt is preempt is part of how this would be
> > > > implemented for execlists. For GuC submission there is a algorithm
> > > > between the i915 and GuC that inserts same preemption points between
> > > > each set of N batches. I believe the rules are if context 1 can
> > > > preempted the rest of the contexts (2 - N) can safely be preempted. A go
> > > > / join algorithm, implemented with semaphores, around the batches
> > > > makes sure the i915 adheres to these rules.
> > > >
> > > > > Also is this just an artifact of the implementation, or is this somehow
> > > > > required functionality for userspace, i.e. the workload fails if e.g. GuC
> > > > > decides to preempt all LRC of a parallel virtual engine? Of course just
> > > > > preempting one is a bit a bug (but execlist I think happily does that).
> > > > >
> > > >
> > > > I think it is part of the implementation / HW limitations. Basically if
> > > > N batches are running in parallel if one of the batches gets preempted
> > > > it can hang all the other batches even if it gets restarted. Again the
> > > > idea behind this is only preempt any of these contexts between each set
> > > > of N batches. The GuC has no concept of batches only contexts hence the
> > > > aforementioned algorithm to insert same preemption points between each
> > > > set of batches.
> > > 
> > > Well backend preempting one but not the other is a bug. I don't think
> > > we need to talk about bugs :-)
> > >
> > 
> > I think it is more that backend can't preempt each context atomically as these
> > are running on independent engines. Let say the backend tries to preempt 2
> > engines at the same time and only 1 responds, now we are broken with certain
> > batches. With the algorithm implmented between the i915 and the Guc the GuC will
> > try to preempt the first context if that works, all the other contexts can be
> > preempted.
> 
> Ah right, we might have a workload with long non-preemptible sections, but
> I guess the MI_SEMAPHORE_WAIT can always preempt. So if GuC just tries on
> one of these, it will result in tears.
> 
> > > Now wrt a preempt mode in context creation, I think that makes sense.
> > > I'm just wondering whether this is correct here in the parallel
> > > submission (and why), or is it just an implementation artifact
> > > (current backends are buggy if we'd allow them to preempt) or what's
> > > going on.
> > >
> > > If this is just a case of "this is how current backends work,
> > > userspace doesn't actually care whether we allow preempt or not" then
> > > I think we should just document the behavior and that's it. Adding
> > > uapi for an option for which there's not even an implementation isn't
> > > great.
> > > 
> > 
> > I don't think it is a case of 'this is how current backends work...', I think
> > user space knows if it is ok for 1 of the batches to preempted and not the
> > others without breaking the batches.
> 
> Yeah this makes more sense as an explanation: Currently the backend (guc
> or execlist) figure out whether something can be preempted by just trying.
> Since we're dealing with N contexts that's a suboptimal approach, and we
> need a flag that indicates whether it's worth it or not.
> 
> So makes sense to me to have this. I guess userspace does actually need
> both modes for now, depending upon what it's doing?
> -Daniel

I agree that is makes sense to have - an explict flag saying it isn't safe to
preempt one of the N batches by itself or letting the driver do whatever it
wants regarding preemption. The current use case is it can't preempt a single
batch but it may change going forward. Lastly, there is overhead to non-preempt
mid batch feature so being able to turn it off seems reasonable to me.

Matt

> 
> > 
> > Matt
> > 
> > > But if we can actually choose, and userspace wants to, then I'm all
> > > fine with this. And we can always move this to a more generic place if
> > > other engines need preempt control later on too.
> > > 
> > > Cheers, Daniel
> > > 
> > > 
> > > > Matt
> > > >
> > > > > Cheers, Daniel
> > > > >
> > > > > > +/*
> > > > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > > > + */
> > > > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH         (1<<1)
> > > > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS      (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > > > +   __u64 flags;            /* all undefined flags must be zero */
> > > > > > +   __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > > > > +
> > > > > > +   /*
> > > > > > +    * width (i) * num_siblings (j) in length
> > > > > > +    * index = j + i * num_siblings
> > > > > > +    */
> > > > > > +   struct i915_engine_class_instance engines[0];
> > > > > > +} __attribute__ ((packed));
> > > > > > +
> > > > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > index 7faa46cde088..64c539486ee4 100644
> > > > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> > > > > >
> > > > > >  New parallel submission uAPI
> > > > > >  ============================
> > > > > > -Details to come in a following patch.
> > > > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > > > +
> > > > > > +The new parallel submission uAPI consists of 3 parts:
> > > > > > +
> > > > > > +* Export engines logical mapping
> > > > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > > > +  submission
> > > > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > > +
> > > > > > +Export engines logical mapping
> > > > > > +------------------------------
> > > > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > > > +submission interface currently only supports submitting multiple contexts to
> > > > > > +engines in logical order which is a new requirement compared to execlists.
> > > > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > > > +
> > > > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > > > +logical instance has been returned and a new field,
> > > > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > > > +
> > > > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > > > +------------------------------------------------------------------------
> > > > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > > > +It is setup step that should be called before using any of the contexts. See
> > > > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > > > +support GuC submission. Execlist support can be added later if needed.
> > > > > > +
> > > > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > > > +
> > > > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > > +-------------------------------------------------------------------
> > > > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > > > +the IOCTL.
> > > > > > --
> > > > > > 2.28.0
> > > > > >
> > > > > > _______________________________________________
> > > > > > Intel-gfx mailing list
> > > > > > Intel-gfx@lists.freedesktop.org
> > > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > > >
> > > > > --
> > > > > Daniel Vetter
> > > > > Software Engineer, Intel Corporation
> > > > > http://blog.ffwll.ch
> > > 
> > > 
> > > 
> > > --
> > > Daniel Vetter
> > > Software Engineer, Intel Corporation
> > > http://blog.ffwll.ch
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-21 16:20               ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-21 16:20 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Mesa Dev, Daniel Vetter,
	karl, Christian König

On Thu, May 20, 2021 at 09:44:59PM +0200, Daniel Vetter wrote:
> On Thu, May 20, 2021 at 08:10:59AM -0700, Matthew Brost wrote:
> > On Thu, May 20, 2021 at 11:54:25AM +0200, Daniel Vetter wrote:
> > > On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
> > > >
> > > > On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > > > > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > > >
> > > > > > v2:
> > > > > >  (Daniel Vetter):
> > > > > >   - Expand logical order explaination
> > > > > >   - Add dummy header
> > > > > >   - Only allow N BBs in execbuf IOCTL
> > > > > >   - Configure parallel submission per slot not per gem context
> > > > > >
> > > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > > ---
> > > > > >  Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > > >  Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > > >  2 files changed, 196 insertions(+), 1 deletion(-)
> > > > > >  create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > >
> > > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > new file mode 100644
> > > > > > index 000000000000..8c64b983ccad
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > @@ -0,0 +1,144 @@
> > > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > > +
> > > > > > +/*
> > > > > > + * i915_context_engines_parallel_submit:
> > > > > > + *
> > > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > > + * the slots configuration).
> > > > > > + *
> > > > > > + * Their are two currently defined ways to control the placement of the
> > > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > > + * interface below above the flags.
> > > > > > + *
> > > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > > + * placement configuration isn't supported on the platform / submission
> > > > > > + * interface.
> > > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > > + * inteface.
> > > > > > + */
> > > > > > +struct i915_context_engines_parallel_submit {
> > > > > > +   struct i915_user_extension base;
> > > > > > +
> > > > > > +   __u16 engine_index;     /* slot for parallel engine */
> > > > > > +   __u16 width;            /* number of contexts per parallel engine */
> > > > > > +   __u16 num_siblings;     /* number of siblings per context */
> > > > > > +   __u16 mbz16;
> > > > >
> > > > > Ok the big picture looks reasonable now, the flags still confuse me.
> > > > >
> > > >
> > > > Yea, it is a bit confusing.
> > > >
> > > > > > +/*
> > > > > > + * Default placement behvavior (currently unsupported):
> > > > > > + *
> > > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > > + *
> > > > > > + * Example 1 pseudo code:
> > > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS0[0], CS1[0]
> > > > > > + * CS0[0], CS1[1]
> > > > > > + * CS0[1], CS1[0]
> > > > > > + * CS0[1], CS1[1]
> > > > > > + *
> > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > > + *
> > > > > > + * Example 2 pseudo code:
> > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS[0], CS[1]
> > > > > > + * CS[0], CS[2]
> > > > > > + * CS[1], CS[0]
> > > > > > + * CS[1], CS[2]
> > > > > > + * CS[2], CS[0]
> > > > > > + * CS[2], CS[1]
> > > > > > + *
> > > > > > + *
> > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > > +
> > > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > > + * engine classes.
> > > > > > + */
> > > > >
> > > > > So I don't really get what this does compared to setting the flag below.
> > > > > Is this just about running the batchbuffers the wrong way round, i.e. if
> > > > > you have (simplest case)
> > > > >
> > > > > width=2, num_sibglings=1, engines=CS[0], CS[1]
> > > > >
> > > > > Then both
> > > > > CS[0], CS[1]
> > > > > and
> > > > > CS[1], CS[0]
> > > > > are possible options for running 2 batches? Iow, the backend is allowed to
> > > > > run the batchbuffers the wrong way round, which gains us nothing, since we
> > > > > assume the batches take equally long and engines interchangeable. There is
> > > > > no scheduling scenario where this additional flexibility can help.
> > > > >
> > > > > Also we don't have flags to select the only available and then specify an
> > > > > entire pipe dream about what the non-flag mode does, without an
> > > > > implementation. What is this about?
> > > > >
> > > > > If it's just "because bonded allowed this" then I think we should just
> > > > > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > > > > welp.
> > > > >
> > > >
> > > > High level the flags came out of internal discussions how this interface
> > > > should look. The default placement behavior is theoretically possible
> > > > with execlists but has no use cases. The GuC supports / current use
> > > > cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
> > > >
> > > > Argued about for months and this is where we landed. At the end of the
> > > > day I think we needed to show that this interface supports more
> > > > placement rules than what the GuC supports / current use cases to future
> > > > proof this interface.
> > > >
> > > > For what is it worth it seems kinda backwards that we landed on the
> > > > default behavior not being supported in our current stack / HW.
> > > 
> > > Yeah I think that should be inverted, doesn't make sense.
> > > 
> > > What I still don't get (and I've read Tvrtko's reply with the example)
> > > is what exactly is the difference between implicit and not implicit
> > > mode? Can you do a single example where the only difference is whether
> > > this flag is set, and then explain with that what are the actual
> > > differences in scheduling options that the backend is allowed to pick
> > > for the set of N patches?
> > > 
> > > I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
> > > 
> > > > > > +
> > > > > > +/*
> > > > > > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > > > > > + * Each context must have the same number sibling and bonds are implictly create
> > > > > > + * of the siblings.
> > > > > > + *
> > > > > > + * All of the below examples are in logical space.
> > > > > > + *
> > > > > > + * Example 1 pseudo code:
> > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > > > > > + *         engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS[0], CS[1]
> > > > > > + *
> > > > > > + * Example 2 pseudo code:
> > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > > + *         engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS[0], CS[1]
> > > > > > + * CS[2], CS[3]
> > > > > > + *
> > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > + * VE[0] = CS[0], CS[2]
> > > > > > + * VE[1] = CS[1], CS[3]
> > > > > > + *
> > > > > > + * This enables a use case where all engines are not equal and certain placement
> > > > > > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > > > > > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > > > > > + * case (logically contiguous placement, within a single engine class) is
> > > > > > + * supported when using GuC submission. Execlist mode could support all possible
> > > > > > + * bonding configurations but currently doesn't support this extension.
> > > > > > + */
> > > > > > +#define I915_PARALLEL_IMPLICT_BONDS                        (1<<0)
> > > > >
> > > > > Does this map to intel_context_set_nopreempt(), so we could implement it
> > > > > also in execlist?
> > > > >
> > > >
> > > > intel_context_set_nopreempt is preempt is part of how this would be
> > > > implemented for execlists. For GuC submission there is a algorithm
> > > > between the i915 and GuC that inserts same preemption points between
> > > > each set of N batches. I believe the rules are if context 1 can
> > > > preempted the rest of the contexts (2 - N) can safely be preempted. A go
> > > > / join algorithm, implemented with semaphores, around the batches
> > > > makes sure the i915 adheres to these rules.
> > > >
> > > > > Also is this just an artifact of the implementation, or is this somehow
> > > > > required functionality for userspace, i.e. the workload fails if e.g. GuC
> > > > > decides to preempt all LRC of a parallel virtual engine? Of course just
> > > > > preempting one is a bit a bug (but execlist I think happily does that).
> > > > >
> > > >
> > > > I think it is part of the implementation / HW limitations. Basically if
> > > > N batches are running in parallel if one of the batches gets preempted
> > > > it can hang all the other batches even if it gets restarted. Again the
> > > > idea behind this is only preempt any of these contexts between each set
> > > > of N batches. The GuC has no concept of batches only contexts hence the
> > > > aforementioned algorithm to insert same preemption points between each
> > > > set of batches.
> > > 
> > > Well backend preempting one but not the other is a bug. I don't think
> > > we need to talk about bugs :-)
> > >
> > 
> > I think it is more that backend can't preempt each context atomically as these
> > are running on independent engines. Let say the backend tries to preempt 2
> > engines at the same time and only 1 responds, now we are broken with certain
> > batches. With the algorithm implmented between the i915 and the Guc the GuC will
> > try to preempt the first context if that works, all the other contexts can be
> > preempted.
> 
> Ah right, we might have a workload with long non-preemptible sections, but
> I guess the MI_SEMAPHORE_WAIT can always preempt. So if GuC just tries on
> one of these, it will result in tears.
> 
> > > Now wrt a preempt mode in context creation, I think that makes sense.
> > > I'm just wondering whether this is correct here in the parallel
> > > submission (and why), or is it just an implementation artifact
> > > (current backends are buggy if we'd allow them to preempt) or what's
> > > going on.
> > >
> > > If this is just a case of "this is how current backends work,
> > > userspace doesn't actually care whether we allow preempt or not" then
> > > I think we should just document the behavior and that's it. Adding
> > > uapi for an option for which there's not even an implementation isn't
> > > great.
> > > 
> > 
> > I don't think it is a case of 'this is how current backends work...', I think
> > user space knows if it is ok for 1 of the batches to preempted and not the
> > others without breaking the batches.
> 
> Yeah this makes more sense as an explanation: Currently the backend (guc
> or execlist) figure out whether something can be preempted by just trying.
> Since we're dealing with N contexts that's a suboptimal approach, and we
> need a flag that indicates whether it's worth it or not.
> 
> So makes sense to me to have this. I guess userspace does actually need
> both modes for now, depending upon what it's doing?
> -Daniel

I agree that is makes sense to have - an explict flag saying it isn't safe to
preempt one of the N batches by itself or letting the driver do whatever it
wants regarding preemption. The current use case is it can't preempt a single
batch but it may change going forward. Lastly, there is overhead to non-preempt
mid batch feature so being able to turn it off seems reasonable to me.

Matt

> 
> > 
> > Matt
> > 
> > > But if we can actually choose, and userspace wants to, then I'm all
> > > fine with this. And we can always move this to a more generic place if
> > > other engines need preempt control later on too.
> > > 
> > > Cheers, Daniel
> > > 
> > > 
> > > > Matt
> > > >
> > > > > Cheers, Daniel
> > > > >
> > > > > > +/*
> > > > > > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > > > > > + * points on all hardware contexts between each set of BBs. An example use case
> > > > > > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > > > > > + * BB must be submitted on each hardware context in the parallel gem context.
> > > > > > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > > > > > + */
> > > > > > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH         (1<<1)
> > > > > > +#define __I915_PARALLEL_UNKNOWN_FLAGS      (-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > > > > > +   __u64 flags;            /* all undefined flags must be zero */
> > > > > > +   __u64 mbz64[3];         /* reserved for future use; must be zero */
> > > > > > +
> > > > > > +   /*
> > > > > > +    * width (i) * num_siblings (j) in length
> > > > > > +    * index = j + i * num_siblings
> > > > > > +    */
> > > > > > +   struct i915_engine_class_instance engines[0];
> > > > > > +} __attribute__ ((packed));
> > > > > > +
> > > > > > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > index 7faa46cde088..64c539486ee4 100644
> > > > > > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > > > > > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> > > > > >
> > > > > >  New parallel submission uAPI
> > > > > >  ============================
> > > > > > -Details to come in a following patch.
> > > > > > +The existing bonding uAPI is completely broken with GuC submission because
> > > > > > +whether a submission is a single context submit or parallel submit isn't known
> > > > > > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > > > > > +contexts in parallel with the GuC the context must be explictly registered with
> > > > > > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > > > > > +These interfaces doesn't support dynamically changing between N contexts as the
> > > > > > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > > > > > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > > > > > +
> > > > > > +The new parallel submission uAPI consists of 3 parts:
> > > > > > +
> > > > > > +* Export engines logical mapping
> > > > > > +* A 'set_parallel' extension to configure contexts for parallel
> > > > > > +  submission
> > > > > > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > > +
> > > > > > +Export engines logical mapping
> > > > > > +------------------------------
> > > > > > +Certain use cases require BBs to be placed on engine instances in logical order
> > > > > > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > > > > > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > > > > > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > > > > > +submission interface currently only supports submitting multiple contexts to
> > > > > > +engines in logical order which is a new requirement compared to execlists.
> > > > > > +Lastly, all current platforms have at most 2 instances and the logical order is
> > > > > > +the same a uABI order. This will change on platforms with more than 2 instances.
> > > > > > +
> > > > > > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > > > > > +logical instance has been returned and a new field,
> > > > > > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > > > > > +
> > > > > > +A 'set_parallel' extension to configure contexts for parallel submission
> > > > > > +------------------------------------------------------------------------
> > > > > > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > > > > > +It is setup step that should be called before using any of the contexts. See
> > > > > > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > > > > > +similar existing examples. Once a slot is configured for parallel submission the
> > > > > > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > > > > > +support GuC submission. Execlist support can be added later if needed.
> > > > > > +
> > > > > > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > > > > > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > > > > > +
> > > > > > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > > > > > +-------------------------------------------------------------------
> > > > > > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > > > > > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > > > > > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > > > > > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > > > > > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > > > > > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > > > > > +the IOCTL.
> > > > > > --
> > > > > > 2.28.0
> > > > > >
> > > > > > _______________________________________________
> > > > > > Intel-gfx mailing list
> > > > > > Intel-gfx@lists.freedesktop.org
> > > > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > > > >
> > > > > --
> > > > > Daniel Vetter
> > > > > Software Engineer, Intel Corporation
> > > > > http://blog.ffwll.ch
> > > 
> > > 
> > > 
> > > --
> > > Daniel Vetter
> > > Software Engineer, Intel Corporation
> > > http://blog.ffwll.ch
> 
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-20 19:41             ` Daniel Vetter
@ 2021-05-21 16:26               ` Matthew Brost
  -1 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-21 16:26 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: Tvrtko Ursulin, intel-gfx, dri-devel, Jason Ekstrand,
	Daniel Vetter, Mesa Dev, karl, Christian König

On Thu, May 20, 2021 at 09:41:20PM +0200, Daniel Vetter wrote:
> On Thu, May 20, 2021 at 11:57:44AM +0100, Tvrtko Ursulin wrote:
> > 
> > On 20/05/2021 10:54, Daniel Vetter wrote:
> > > On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
> > > > 
> > > > On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > > > > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > > > 
> > > > > > v2:
> > > > > >   (Daniel Vetter):
> > > > > >    - Expand logical order explaination
> > > > > >    - Add dummy header
> > > > > >    - Only allow N BBs in execbuf IOCTL
> > > > > >    - Configure parallel submission per slot not per gem context
> > > > > > 
> > > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > > ---
> > > > > >   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > > >   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > > >   2 files changed, 196 insertions(+), 1 deletion(-)
> > > > > >   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > 
> > > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > new file mode 100644
> > > > > > index 000000000000..8c64b983ccad
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > @@ -0,0 +1,144 @@
> > > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > > +
> > > > > > +/*
> > > > > > + * i915_context_engines_parallel_submit:
> > > > > > + *
> > > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > > + * the slots configuration).
> > > > > > + *
> > > > > > + * Their are two currently defined ways to control the placement of the
> > > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > > + * interface below above the flags.
> > > > > > + *
> > > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > > + * placement configuration isn't supported on the platform / submission
> > > > > > + * interface.
> > > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > > + * inteface.
> > > > > > + */
> > > > > > +struct i915_context_engines_parallel_submit {
> > > > > > +   struct i915_user_extension base;
> > > > > > +
> > > > > > +   __u16 engine_index;     /* slot for parallel engine */
> > > > > > +   __u16 width;            /* number of contexts per parallel engine */
> > > > > > +   __u16 num_siblings;     /* number of siblings per context */
> > > > > > +   __u16 mbz16;
> > > > > 
> > > > > Ok the big picture looks reasonable now, the flags still confuse me.
> > > > > 
> > > > 
> > > > Yea, it is a bit confusing.
> > > > 
> > > > > > +/*
> > > > > > + * Default placement behvavior (currently unsupported):
> > > > > > + *
> > > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > > + *
> > > > > > + * Example 1 pseudo code:
> > > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS0[0], CS1[0]
> > > > > > + * CS0[0], CS1[1]
> > > > > > + * CS0[1], CS1[0]
> > > > > > + * CS0[1], CS1[1]
> > > > > > + *
> > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > > + *
> > > > > > + * Example 2 pseudo code:
> > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS[0], CS[1]
> > > > > > + * CS[0], CS[2]
> > > > > > + * CS[1], CS[0]
> > > > > > + * CS[1], CS[2]
> > > > > > + * CS[2], CS[0]
> > > > > > + * CS[2], CS[1]
> > > > > > + *
> > > > > > + *
> > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > > +
> > > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > > + * engine classes.
> > > > > > + */
> > > > > 
> > > > > So I don't really get what this does compared to setting the flag below.
> > > > > Is this just about running the batchbuffers the wrong way round, i.e. if
> > > > > you have (simplest case)
> > > > > 
> > > > > width=2, num_sibglings=1, engines=CS[0], CS[1]
> > > > > 
> > > > > Then both
> > > > > CS[0], CS[1]
> > > > > and
> > > > > CS[1], CS[0]
> > > > > are possible options for running 2 batches? Iow, the backend is allowed to
> > > > > run the batchbuffers the wrong way round, which gains us nothing, since we
> > > > > assume the batches take equally long and engines interchangeable. There is
> > > > > no scheduling scenario where this additional flexibility can help.
> > > > > 
> > > > > Also we don't have flags to select the only available and then specify an
> > > > > entire pipe dream about what the non-flag mode does, without an
> > > > > implementation. What is this about?
> > > > > 
> > > > > If it's just "because bonded allowed this" then I think we should just
> > > > > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > > > > welp.
> > > > > 
> > > > 
> > > > High level the flags came out of internal discussions how this interface
> > > > should look. The default placement behavior is theoretically possible
> > > > with execlists but has no use cases. The GuC supports / current use
> > > > cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
> > > > 
> > > > Argued about for months and this is where we landed. At the end of the
> > > > day I think we needed to show that this interface supports more
> > > > placement rules than what the GuC supports / current use cases to future
> > > > proof this interface.
> > > > 
> > > > For what is it worth it seems kinda backwards that we landed on the
> > > > default behavior not being supported in our current stack / HW.
> > > 
> > > Yeah I think that should be inverted, doesn't make sense.
> > > 
> > > What I still don't get (and I've read Tvrtko's reply with the example)
> > > is what exactly is the difference between implicit and not implicit
> > > mode? Can you do a single example where the only difference is whether
> > > this flag is set, and then explain with that what are the actual
> > > differences in scheduling options that the backend is allowed to pick
> > > for the set of N patches?
> > > 
> > > I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
> > 
> > 2-wide compute context:
> > 
> >  .engine_map([-1, -1])
> >  .load_balance(0: [cs0, cs1, cs2, cs3]) // place virtual engine at slot 0
> >  .load_balance(1: [cs0, cs1, cs2, cs3])
> >  .set_parallel()
> > 
> > This tells the scheduler any two of the four possible engines can be used. cs0 + cs3 is fine, cs3 + cs1 also, ... any. Only implicit rule is they have to be different and that works for all.
> > 
> > 2-wide "implicit bonds mode" aka media fixed function limitation:
> > 
> >  .engine_map([-1, -1])
> >  .load_balance(0: [cs0, cs2])
> >  .load_balance(1: [cs1, cs3])
> >  .set_parallel(flags = implicit_bond)
> > 
> > Think of implicit flag creating a "link" between vertical columns in each virtual engine slot. So valid pairs end up cs0 + cs1 and cs2 + cs3 only.
> > 
> > You can also think of the implicit flag as a shortcut to avoid specifying bonds via the existing extension. In which case context setup would be written along the lines of:
> > 
> >  .engine_map([-1, -1])
> >  .load_balance(0: [cs0, cs2])
> >  .load_balance(1: [cs1, cs3])
> >  .bond(1: master = cs0, bond = [cs1])
> >  .bond(1: master = cs2, bond = [cs3])
> >  .set_parallel()
> > 
> > So the implicit flag is just a shortcut to avoid typing the bonds. Not really needed as explained in my previous reply.
> 
> Ah now I get both what this means, why it exists and where it's all come
> from. With the backstory makes a bunch more sense now. Thanks for
> explaining again.
> 
> > This was at least the "old" set_parallel. I see this latest RFC changed
> > things a bit which I don't really follow yet.
> > 
> > It's not perfect but needs to add very little (just one context
> > extension, on top of multi batch execbuf which is needed anyways),
> > doesn't need to deprecate anything, didn't require rewrites of the UMD,
> > and it all works today and in the future.
> > 
> > I did not really like this new uapi for all the reasons I listed
> > already, but as not many people were seeing the advantage of not
> > churning on the uapi, if we are churning already I did suggests a
> > different idea. I mean if we are churning we might as well go full in.
> > So that proposal, which didn't get any traction, was along the lines of:
> > 
> >  .engine_map([-1])
> >  .load_balance_wide(0: width=2, engines=[[cs0, cs2], [cs1, cs3]])
> > 
> > This would create an explicit wide virtual engine which should work for
> > GuC fine I think. For execlists it may require a bit of extra glue but I
> > don't think too much.
> > 
> > Advantage is there is one engine in the map now and it is N-wide by
> > definition.
> > 
> > Since no one did bite on that idea back then, I didn't really pursue is
> > to see if it works for all use cases. But I think it should even if it
> > probably requires further thinking to be sure.
> > 
> > If we apply it to compute use case..
> > 
> >  .engine_map([-1])
> >  .load_balance_wide(0: width=2, engines=[[cs0, cs1, cs2, cs3], [cs0, cs1, cs2, cs3]])
> > 
> > This means the only implicit wart in there is that cs0 + cs0 obviously
> > shouldn't be picked. But that should be fine both for execlists and
> > hopefully for the GuC.
> 
> Yeah. Another option would be to simply allow any valid pair to be listed.
> Gets maybe a bit too long for full combinatorials. Or we do an N-out-of-M
> load balance, and you just specifiy the one vector for the engine set that
> gets fully combined.
> 
> Either way I think simple to add if/when compute comes around and asks for
> it.

I agree with this, with flags + an extendable engine list we really can make
this interface describe any placement rules we want. I think what we have in
placement at moment is good.

Matt 

> -Daniel
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-21 16:26               ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-21 16:26 UTC (permalink / raw)
  To: Daniel Vetter
  Cc: intel-gfx, dri-devel, Jason Ekstrand, Daniel Vetter, Mesa Dev,
	karl, Christian König

On Thu, May 20, 2021 at 09:41:20PM +0200, Daniel Vetter wrote:
> On Thu, May 20, 2021 at 11:57:44AM +0100, Tvrtko Ursulin wrote:
> > 
> > On 20/05/2021 10:54, Daniel Vetter wrote:
> > > On Wed, May 19, 2021 at 7:19 PM Matthew Brost <matthew.brost@intel.com> wrote:
> > > > 
> > > > On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote:
> > > > > On Tue, May 18, 2021 at 04:58:30PM -0700, Matthew Brost wrote:
> > > > > > Add entry fpr i915 new parallel submission uAPI plan.
> > > > > > 
> > > > > > v2:
> > > > > >   (Daniel Vetter):
> > > > > >    - Expand logical order explaination
> > > > > >    - Add dummy header
> > > > > >    - Only allow N BBs in execbuf IOCTL
> > > > > >    - Configure parallel submission per slot not per gem context
> > > > > > 
> > > > > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > > Cc: Tony Ye <tony.ye@intel.com>
> > > > > > CC: Carl Zhang <carl.zhang@intel.com>
> > > > > > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > > > > > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > > > > > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > > > > > ---
> > > > > >   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> > > > > >   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> > > > > >   2 files changed, 196 insertions(+), 1 deletion(-)
> > > > > >   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > 
> > > > > > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > new file mode 100644
> > > > > > index 000000000000..8c64b983ccad
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > > > > > @@ -0,0 +1,144 @@
> > > > > > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > > > > > +
> > > > > > +/*
> > > > > > + * i915_context_engines_parallel_submit:
> > > > > > + *
> > > > > > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > > > > > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > > > > > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > > > > > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > > > > > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > > > > > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > > > > > + * the slots configuration).
> > > > > > + *
> > > > > > + * Their are two currently defined ways to control the placement of the
> > > > > > + * hardware contexts on physical engines: default behavior (no flags) and
> > > > > > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > > > > > + * future as new hardware / use cases arise. Details of how to use this
> > > > > > + * interface below above the flags.
> > > > > > + *
> > > > > > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > > > > > + * placement configuration isn't supported on the platform / submission
> > > > > > + * interface.
> > > > > > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > > > > > + * inteface.
> > > > > > + */
> > > > > > +struct i915_context_engines_parallel_submit {
> > > > > > +   struct i915_user_extension base;
> > > > > > +
> > > > > > +   __u16 engine_index;     /* slot for parallel engine */
> > > > > > +   __u16 width;            /* number of contexts per parallel engine */
> > > > > > +   __u16 num_siblings;     /* number of siblings per context */
> > > > > > +   __u16 mbz16;
> > > > > 
> > > > > Ok the big picture looks reasonable now, the flags still confuse me.
> > > > > 
> > > > 
> > > > Yea, it is a bit confusing.
> > > > 
> > > > > > +/*
> > > > > > + * Default placement behvavior (currently unsupported):
> > > > > > + *
> > > > > > + * Rather than restricting parallel submission to a single class with a
> > > > > > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> > > > > > + * enables parallel submission across multiple engine classes. In this case each
> > > > > > + * context's logical engine mask indicates where that context can placed. It is
> > > > > > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > > > > > + * if one context is running CS0 no other contexts can run on CS0).
> > > > > > + *
> > > > > > + * Example 1 pseudo code:
> > > > > > + * CSX[Y] = engine class X, logical instance Y
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > > > > > + *         engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS0[0], CS1[0]
> > > > > > + * CS0[0], CS1[1]
> > > > > > + * CS0[1], CS1[0]
> > > > > > + * CS0[1], CS1[1]
> > > > > > + *
> > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > + * VE[0] = CS0[0], CS0[1]
> > > > > > + * VE[1] = CS1[0], CS1[1]
> > > > > > + *
> > > > > > + * Example 2 pseudo code:
> > > > > > + * CS[X] = generic engine of same class, logical instance X
> > > > > > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > > > > > + * set_engines(INVALID)
> > > > > > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > > > > > + *         engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > > > > > + *
> > > > > > + * Results in the following valid placements:
> > > > > > + * CS[0], CS[1]
> > > > > > + * CS[0], CS[2]
> > > > > > + * CS[1], CS[0]
> > > > > > + * CS[1], CS[2]
> > > > > > + * CS[2], CS[0]
> > > > > > + * CS[2], CS[1]
> > > > > > + *
> > > > > > + *
> > > > > > + * This can also be though of as 2 virtual engines:
> > > > > > + * VE[0] = CS[0], CS[1], CS[2]
> > > > > > + * VE[1] = CS[0], CS[1], CS[2]
> > > > > > +
> > > > > > + * This enables a use case where all engines are created equally, we don't care
> > > > > > + * where they are scheduled, we just want a certain number of resources, for
> > > > > > + * those resources to be scheduled in parallel, and possibly across multiple
> > > > > > + * engine classes.
> > > > > > + */
> > > > > 
> > > > > So I don't really get what this does compared to setting the flag below.
> > > > > Is this just about running the batchbuffers the wrong way round, i.e. if
> > > > > you have (simplest case)
> > > > > 
> > > > > width=2, num_sibglings=1, engines=CS[0], CS[1]
> > > > > 
> > > > > Then both
> > > > > CS[0], CS[1]
> > > > > and
> > > > > CS[1], CS[0]
> > > > > are possible options for running 2 batches? Iow, the backend is allowed to
> > > > > run the batchbuffers the wrong way round, which gains us nothing, since we
> > > > > assume the batches take equally long and engines interchangeable. There is
> > > > > no scheduling scenario where this additional flexibility can help.
> > > > > 
> > > > > Also we don't have flags to select the only available and then specify an
> > > > > entire pipe dream about what the non-flag mode does, without an
> > > > > implementation. What is this about?
> > > > > 
> > > > > If it's just "because bonded allowed this" then I think we should just
> > > > > unceremonously ditch this. Bummer for the nice kerenldoc you wrote, but
> > > > > welp.
> > > > > 
> > > > 
> > > > High level the flags came out of internal discussions how this interface
> > > > should look. The default placement behavior is theoretically possible
> > > > with execlists but has no use cases. The GuC supports / current use
> > > > cases are a subset of what is possible with I915_PARALLEL_IMPLICT_BONDS.
> > > > 
> > > > Argued about for months and this is where we landed. At the end of the
> > > > day I think we needed to show that this interface supports more
> > > > placement rules than what the GuC supports / current use cases to future
> > > > proof this interface.
> > > > 
> > > > For what is it worth it seems kinda backwards that we landed on the
> > > > default behavior not being supported in our current stack / HW.
> > > 
> > > Yeah I think that should be inverted, doesn't make sense.
> > > 
> > > What I still don't get (and I've read Tvrtko's reply with the example)
> > > is what exactly is the difference between implicit and not implicit
> > > mode? Can you do a single example where the only difference is whether
> > > this flag is set, and then explain with that what are the actual
> > > differences in scheduling options that the backend is allowed to pick
> > > for the set of N patches?
> > > 
> > > I'm feeling a bit dense, but I'm really not seeing what's even going on here :-(
> > 
> > 2-wide compute context:
> > 
> >  .engine_map([-1, -1])
> >  .load_balance(0: [cs0, cs1, cs2, cs3]) // place virtual engine at slot 0
> >  .load_balance(1: [cs0, cs1, cs2, cs3])
> >  .set_parallel()
> > 
> > This tells the scheduler any two of the four possible engines can be used. cs0 + cs3 is fine, cs3 + cs1 also, ... any. Only implicit rule is they have to be different and that works for all.
> > 
> > 2-wide "implicit bonds mode" aka media fixed function limitation:
> > 
> >  .engine_map([-1, -1])
> >  .load_balance(0: [cs0, cs2])
> >  .load_balance(1: [cs1, cs3])
> >  .set_parallel(flags = implicit_bond)
> > 
> > Think of implicit flag creating a "link" between vertical columns in each virtual engine slot. So valid pairs end up cs0 + cs1 and cs2 + cs3 only.
> > 
> > You can also think of the implicit flag as a shortcut to avoid specifying bonds via the existing extension. In which case context setup would be written along the lines of:
> > 
> >  .engine_map([-1, -1])
> >  .load_balance(0: [cs0, cs2])
> >  .load_balance(1: [cs1, cs3])
> >  .bond(1: master = cs0, bond = [cs1])
> >  .bond(1: master = cs2, bond = [cs3])
> >  .set_parallel()
> > 
> > So the implicit flag is just a shortcut to avoid typing the bonds. Not really needed as explained in my previous reply.
> 
> Ah now I get both what this means, why it exists and where it's all come
> from. With the backstory makes a bunch more sense now. Thanks for
> explaining again.
> 
> > This was at least the "old" set_parallel. I see this latest RFC changed
> > things a bit which I don't really follow yet.
> > 
> > It's not perfect but needs to add very little (just one context
> > extension, on top of multi batch execbuf which is needed anyways),
> > doesn't need to deprecate anything, didn't require rewrites of the UMD,
> > and it all works today and in the future.
> > 
> > I did not really like this new uapi for all the reasons I listed
> > already, but as not many people were seeing the advantage of not
> > churning on the uapi, if we are churning already I did suggests a
> > different idea. I mean if we are churning we might as well go full in.
> > So that proposal, which didn't get any traction, was along the lines of:
> > 
> >  .engine_map([-1])
> >  .load_balance_wide(0: width=2, engines=[[cs0, cs2], [cs1, cs3]])
> > 
> > This would create an explicit wide virtual engine which should work for
> > GuC fine I think. For execlists it may require a bit of extra glue but I
> > don't think too much.
> > 
> > Advantage is there is one engine in the map now and it is N-wide by
> > definition.
> > 
> > Since no one did bite on that idea back then, I didn't really pursue is
> > to see if it works for all use cases. But I think it should even if it
> > probably requires further thinking to be sure.
> > 
> > If we apply it to compute use case..
> > 
> >  .engine_map([-1])
> >  .load_balance_wide(0: width=2, engines=[[cs0, cs1, cs2, cs3], [cs0, cs1, cs2, cs3]])
> > 
> > This means the only implicit wart in there is that cs0 + cs0 obviously
> > shouldn't be picked. But that should be fine both for execlists and
> > hopefully for the GuC.
> 
> Yeah. Another option would be to simply allow any valid pair to be listed.
> Gets maybe a bit too long for full combinatorials. Or we do an N-out-of-M
> load balance, and you just specifiy the one vector for the engine set that
> gets fully combined.
> 
> Either way I think simple to add if/when compute comes around and asks for
> it.

I agree with this, with flags + an extendable engine list we really can make
this interface describe any placement rules we want. I think what we have in
placement at moment is good.

Matt 

> -Daniel
> -- 
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
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^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-21 12:00     ` Tvrtko Ursulin
@ 2021-05-21 16:48       ` Matthew Brost
  -1 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-21 16:48 UTC (permalink / raw)
  To: Tvrtko Ursulin
  Cc: intel-gfx, dri-devel, jason.ekstrand, daniel.vetter, mesa-dev,
	karl, christian.koenig

On Fri, May 21, 2021 at 01:00:54PM +0100, Tvrtko Ursulin wrote:
> 
> On 19/05/2021 00:58, Matthew Brost wrote:
> > Add entry fpr i915 new parallel submission uAPI plan.
> > 
> > v2:
> >   (Daniel Vetter):
> >    - Expand logical order explaination
> >    - Add dummy header
> >    - Only allow N BBs in execbuf IOCTL
> >    - Configure parallel submission per slot not per gem context
> > 
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Tony Ye <tony.ye@intel.com>
> > CC: Carl Zhang <carl.zhang@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> >   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> >   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> >   2 files changed, 196 insertions(+), 1 deletion(-)
> >   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > 
> > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > new file mode 100644
> > index 000000000000..8c64b983ccad
> > --- /dev/null
> > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > @@ -0,0 +1,144 @@
> > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > +
> > +/*
> > + * i915_context_engines_parallel_submit:
> > + *
> > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > + * the slots configuration).
> 
> 1)
> Expand the term slot here with "slot in the context engine map" least once
> for clarity.
> 

Sure.

> 2)
> About where execbuf will implicitly be finding batches - suggest to also
> cover first/last flag here. I know you have it in the readme but I think it
> is good if uapi header is as self-contained as possible.
>

Yep, good idea.

> > + *
> > + * Their are two currently defined ways to control the placement of the
> > + * hardware contexts on physical engines: default behavior (no flags) and
> > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > + * future as new hardware / use cases arise. Details of how to use this
> > + * interface below above the flags.
> > + *
> > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > + * placement configuration isn't supported on the platform / submission
> > + * interface.
> > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > + * inteface.
> > + */
> > +struct i915_context_engines_parallel_submit {
> > +	struct i915_user_extension base;
> > +
> > +	__u16 engine_index;	/* slot for parallel engine */
> > +	__u16 width;		/* number of contexts per parallel engine */
> > +	__u16 num_siblings;	/* number of siblings per context */
> > +	__u16 mbz16;
> > +/*
> > + * Default placement behvavior (currently unsupported):
> > + *
> > + * Rather than restricting parallel submission to a single class with a
> > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> 
> What do you mean with logically contiguous here? It sounds ambiguous versus
> logical vs "normal" engine instance numbers.
>

This is a little backwards. I think when I wrote this originally the implicit
placement comments were first. I can reword this.
 
> > + * enables parallel submission across multiple engine classes. In this case each
> > + * context's logical engine mask indicates where that context can placed. It is
> > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > + * if one context is running CS0 no other contexts can run on CS0).
> 
> I think talk about logical context and its mask is too implementation detail
> at the uapi level. Instead I would suggest more userspace programmer centric
> description.

Ok, can you give me suggestion? Writing DOC isn't really my strength.

> 
> > + *
> > + * Example 1 pseudo code:
> > + * CSX[Y] = engine class X, logical instance Y
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > + *
> > + * Results in the following valid placements:
> > + * CS0[0], CS1[0]
> > + * CS0[0], CS1[1]
> > + * CS0[1], CS1[0]
> > + * CS0[1], CS1[1]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS0[0], CS0[1]
> > + * VE[1] = CS1[0], CS1[1]
> 
> Ah okay so essentially similar to what I was proposing a year ago. But then
> it is no longer "set_parallel" really. It is one slot in the engine map,
> right, with the idea to super class intel_context in the implementation?
>

Yes, it is bascially a super class intel_context. In the implementation is
parent-child with the parent having a linked list of child intel_contexts.
 
> So really a wide virtual engine, as opposed to single one. In which case I
> think it makes sense to stay close to the existing naming of the
> load_balance extension for consistency. Load_balance_wide?
> Load_balance_parallel? Multi?

I like the way is named but I also don't want to argue about this as I don't
really care. If someone else says this should be renamed, let's do it.
 
> 
> I also have to say the notation "CS0[0]" - I who know this problem space am
> finding it hard to penetrate what that actually means. (Also uppercase IMO
> makes it hard to read, but maybe it is just me.)
>

Yea, now I think about it CS0[0] is bad because of using numbers twice. How
about CSX[0] & CSY[1]? I used upper case because in the i915 all engine classes
defines are upper case but agree it might be easier to read it lower case.
 
> Looking a bit lower below, extension seems to be taking a 2d array of
> class:instance pairs, right? If so then reading these docs in order, or even
> just looking further down, I don't think that is explicitly called out
> clearly enough.
> 
> So I think a paragraph or two explaining clearly how the 2d array of engines
> corresponds to the allowed engines for full virtual engine width. Or maybe
> just a 2d diagram?
> 
>   2-wide virtual engine:
>     .engines = [
>       /* channel 0 allowed engines: */  [cs0, cs1],
>       /* channel 1 allowed engines: */  [cs0, cs1]
>      ]
> 
> Not sure if that's better.
> 

Yes, it is a 2-d array. Agree the explaination could be better.

> Also to be noted, this only allows uniform number of allowed engines per
> channel. I am not saying we need the non-uniform setup today but with bonds
> there isn't this limitation.
>

Not exactly. You could do something like this.

witdth = 2
siblings = 2
engines = CSX[0], CSX[1], CSY[0], INVALID

This would allow a placement of:

CSX[0], CSY[0]
CSX[1], CSY[0]

In this case the siblings is just a max value of each entry.

Matt
 
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[0], CS[2]
> > + * CS[1], CS[0]
> > + * CS[1], CS[2]
> > + * CS[2], CS[0]
> > + * CS[2], CS[1]
> 
> And now here you use different notation than above (CS0[0] vs CS[0]) which
> is confusing.
>

Yea, a little bit. I do explain the notation in both examples though but will
make this uniform. Now that I think about it CS0[0] is bad too because of using
numbers twice. How about CSX[0] & CSY[1]?
 
> > + *
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[1], CS[2]
> > + * VE[1] = CS[0], CS[1], CS[2]
> > +
> > + * This enables a use case where all engines are created equally, we don't care
> > + * where they are scheduled, we just want a certain number of resources, for
> > + * those resources to be scheduled in parallel, and possibly across multiple
> > + * engine classes.
> > + */
> > +
> > +/*
> > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > + * Each context must have the same number sibling and bonds are implictly create
> > + * of the siblings.
> > + *
> > + * All of the below examples are in logical space.
> > + *
> > + * Example 1 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[2], CS[3]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[2]
> > + * VE[1] = CS[1], CS[3]
> > + *
> > + * This enables a use case where all engines are not equal and certain placement
> > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > + * case (logically contiguous placement, within a single engine class) is
> > + * supported when using GuC submission. Execlist mode could support all possible
> > + * bonding configurations but currently doesn't support this extension.
> > + */
> > +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> > +/*
> > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > + * points on all hardware contexts between each set of BBs. An example use case
> > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > + * BB must be submitted on each hardware context in the parallel gem context.
> > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > + */
> Is the part about execbuf2 enforcing num_batches == context_width still
> valid, I mean is the latest proposal supporting num_batches < context_width?
> Does media needs this option?
>

With the new uAPI num_batches == context_width regardless of this flag. This is
a stale comment that needs to be removed.
 
> I would also have this flag as a separate patch because it strictly isn't
> about parallel submission per-se but a specific hw limitation on top of it.
>

Yep, I do in the actual code but this in just the RFC header. Can break it out
in the RFC header but IMO it is better to have in a single patch to review.

Matt
 
> Regards,
> 
> Tvrtko
> 
> > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> > +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > +	__u64 flags;		/* all undefined flags must be zero */
> > +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> > +
> > +	/*
> > +	 * width (i) * num_siblings (j) in length
> > +	 * index = j + i * num_siblings
> > +	 */
> > +	struct i915_engine_class_instance engines[0];
> > +} __attribute__ ((packed));
> > +
> > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > index 7faa46cde088..64c539486ee4 100644
> > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> >   New parallel submission uAPI
> >   ============================
> > -Details to come in a following patch.
> > +The existing bonding uAPI is completely broken with GuC submission because
> > +whether a submission is a single context submit or parallel submit isn't known
> > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > +contexts in parallel with the GuC the context must be explictly registered with
> > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > +These interfaces doesn't support dynamically changing between N contexts as the
> > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > +
> > +The new parallel submission uAPI consists of 3 parts:
> > +
> > +* Export engines logical mapping
> > +* A 'set_parallel' extension to configure contexts for parallel
> > +  submission
> > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +
> > +Export engines logical mapping
> > +------------------------------
> > +Certain use cases require BBs to be placed on engine instances in logical order
> > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > +submission interface currently only supports submitting multiple contexts to
> > +engines in logical order which is a new requirement compared to execlists.
> > +Lastly, all current platforms have at most 2 instances and the logical order is
> > +the same a uABI order. This will change on platforms with more than 2 instances.
> > +
> > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > +logical instance has been returned and a new field,
> > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > +
> > +A 'set_parallel' extension to configure contexts for parallel submission
> > +------------------------------------------------------------------------
> > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > +It is setup step that should be called before using any of the contexts. See
> > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > +similar existing examples. Once a slot is configured for parallel submission the
> > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > +support GuC submission. Execlist support can be added later if needed.
> > +
> > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > +
> > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +-------------------------------------------------------------------
> > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > +the IOCTL.
> > 

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-21 16:48       ` Matthew Brost
  0 siblings, 0 replies; 54+ messages in thread
From: Matthew Brost @ 2021-05-21 16:48 UTC (permalink / raw)
  To: Tvrtko Ursulin
  Cc: intel-gfx, dri-devel, jason.ekstrand, daniel.vetter, mesa-dev,
	karl, christian.koenig

On Fri, May 21, 2021 at 01:00:54PM +0100, Tvrtko Ursulin wrote:
> 
> On 19/05/2021 00:58, Matthew Brost wrote:
> > Add entry fpr i915 new parallel submission uAPI plan.
> > 
> > v2:
> >   (Daniel Vetter):
> >    - Expand logical order explaination
> >    - Add dummy header
> >    - Only allow N BBs in execbuf IOCTL
> >    - Configure parallel submission per slot not per gem context
> > 
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Tony Ye <tony.ye@intel.com>
> > CC: Carl Zhang <carl.zhang@intel.com>
> > Cc: Daniel Vetter <daniel.vetter@intel.com>
> > Cc: Jason Ekstrand <jason@jlekstrand.net>
> > Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> > ---
> >   Documentation/gpu/rfc/i915_parallel_execbuf.h | 144 ++++++++++++++++++
> >   Documentation/gpu/rfc/i915_scheduler.rst      |  53 ++++++-
> >   2 files changed, 196 insertions(+), 1 deletion(-)
> >   create mode 100644 Documentation/gpu/rfc/i915_parallel_execbuf.h
> > 
> > diff --git a/Documentation/gpu/rfc/i915_parallel_execbuf.h b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > new file mode 100644
> > index 000000000000..8c64b983ccad
> > --- /dev/null
> > +++ b/Documentation/gpu/rfc/i915_parallel_execbuf.h
> > @@ -0,0 +1,144 @@
> > +#define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
> > +
> > +/*
> > + * i915_context_engines_parallel_submit:
> > + *
> > + * Setup a slot to allow multiple BBs to be submitted in a single execbuf IOCTL.
> > + * Those BBs will then be scheduled to run on the GPU in parallel. Multiple
> > + * hardware contexts are created internally in the i915 run these BBs. Once a
> > + * slot is configured for N BBs only N BBs can be submitted in each execbuf
> > + * IOCTL and this is implict behavior (e.g. the user doesn't tell the execbuf
> > + * IOCTL there are N BBs, the execbuf IOCTL know how many BBs there are based on
> > + * the slots configuration).
> 
> 1)
> Expand the term slot here with "slot in the context engine map" least once
> for clarity.
> 

Sure.

> 2)
> About where execbuf will implicitly be finding batches - suggest to also
> cover first/last flag here. I know you have it in the readme but I think it
> is good if uapi header is as self-contained as possible.
>

Yep, good idea.

> > + *
> > + * Their are two currently defined ways to control the placement of the
> > + * hardware contexts on physical engines: default behavior (no flags) and
> > + * I915_PARALLEL_IMPLICT_BONDS (a flag). More flags may be added the in the
> > + * future as new hardware / use cases arise. Details of how to use this
> > + * interface below above the flags.
> > + *
> > + * Returns -EINVAL if hardware context placement configuration invalid or if the
> > + * placement configuration isn't supported on the platform / submission
> > + * interface.
> > + * Returns -ENODEV if extension isn't supported on the platform / submission
> > + * inteface.
> > + */
> > +struct i915_context_engines_parallel_submit {
> > +	struct i915_user_extension base;
> > +
> > +	__u16 engine_index;	/* slot for parallel engine */
> > +	__u16 width;		/* number of contexts per parallel engine */
> > +	__u16 num_siblings;	/* number of siblings per context */
> > +	__u16 mbz16;
> > +/*
> > + * Default placement behvavior (currently unsupported):
> > + *
> > + * Rather than restricting parallel submission to a single class with a
> > + * logically contiguous placement (I915_PARALLEL_IMPLICT_BONDS), add a mode that
> 
> What do you mean with logically contiguous here? It sounds ambiguous versus
> logical vs "normal" engine instance numbers.
>

This is a little backwards. I think when I wrote this originally the implicit
placement comments were first. I can reword this.
 
> > + * enables parallel submission across multiple engine classes. In this case each
> > + * context's logical engine mask indicates where that context can placed. It is
> > + * implied in this mode that all contexts have mutual exclusive placement (e.g.
> > + * if one context is running CS0 no other contexts can run on CS0).
> 
> I think talk about logical context and its mask is too implementation detail
> at the uapi level. Instead I would suggest more userspace programmer centric
> description.

Ok, can you give me suggestion? Writing DOC isn't really my strength.

> 
> > + *
> > + * Example 1 pseudo code:
> > + * CSX[Y] = engine class X, logical instance Y
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
> > + *
> > + * Results in the following valid placements:
> > + * CS0[0], CS1[0]
> > + * CS0[0], CS1[1]
> > + * CS0[1], CS1[0]
> > + * CS0[1], CS1[1]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS0[0], CS0[1]
> > + * VE[1] = CS1[0], CS1[1]
> 
> Ah okay so essentially similar to what I was proposing a year ago. But then
> it is no longer "set_parallel" really. It is one slot in the engine map,
> right, with the idea to super class intel_context in the implementation?
>

Yes, it is bascially a super class intel_context. In the implementation is
parent-child with the parent having a linked list of child intel_contexts.
 
> So really a wide virtual engine, as opposed to single one. In which case I
> think it makes sense to stay close to the existing naming of the
> load_balance extension for consistency. Load_balance_wide?
> Load_balance_parallel? Multi?

I like the way is named but I also don't want to argue about this as I don't
really care. If someone else says this should be renamed, let's do it.
 
> 
> I also have to say the notation "CS0[0]" - I who know this problem space am
> finding it hard to penetrate what that actually means. (Also uppercase IMO
> makes it hard to read, but maybe it is just me.)
>

Yea, now I think about it CS0[0] is bad because of using numbers twice. How
about CSX[0] & CSY[1]? I used upper case because in the i915 all engine classes
defines are upper case but agree it might be easier to read it lower case.
 
> Looking a bit lower below, extension seems to be taking a 2d array of
> class:instance pairs, right? If so then reading these docs in order, or even
> just looking further down, I don't think that is explicitly called out
> clearly enough.
> 
> So I think a paragraph or two explaining clearly how the 2d array of engines
> corresponds to the allowed engines for full virtual engine width. Or maybe
> just a 2d diagram?
> 
>   2-wide virtual engine:
>     .engines = [
>       /* channel 0 allowed engines: */  [cs0, cs1],
>       /* channel 1 allowed engines: */  [cs0, cs1]
>      ]
> 
> Not sure if that's better.
> 

Yes, it is a 2-d array. Agree the explaination could be better.

> Also to be noted, this only allows uniform number of allowed engines per
> channel. I am not saying we need the non-uniform setup today but with bonds
> there isn't this limitation.
>

Not exactly. You could do something like this.

witdth = 2
siblings = 2
engines = CSX[0], CSX[1], CSY[0], INVALID

This would allow a placement of:

CSX[0], CSY[0]
CSX[1], CSY[0]

In this case the siblings is just a max value of each entry.

Matt
 
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=3,
> > + *		engines=CS[0],CS[1],CS[2],CS[0],CS[1],CS[2])
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[0], CS[2]
> > + * CS[1], CS[0]
> > + * CS[1], CS[2]
> > + * CS[2], CS[0]
> > + * CS[2], CS[1]
> 
> And now here you use different notation than above (CS0[0] vs CS[0]) which
> is confusing.
>

Yea, a little bit. I do explain the notation in both examples though but will
make this uniform. Now that I think about it CS0[0] is bad too because of using
numbers twice. How about CSX[0] & CSY[1]?
 
> > + *
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[1], CS[2]
> > + * VE[1] = CS[0], CS[1], CS[2]
> > +
> > + * This enables a use case where all engines are created equally, we don't care
> > + * where they are scheduled, we just want a certain number of resources, for
> > + * those resources to be scheduled in parallel, and possibly across multiple
> > + * engine classes.
> > + */
> > +
> > +/*
> > + * I915_PARALLEL_IMPLICT_BONDS - Create implict bonds between each context.
> > + * Each context must have the same number sibling and bonds are implictly create
> > + * of the siblings.
> > + *
> > + * All of the below examples are in logical space.
> > + *
> > + * Example 1 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=1,
> > + *		engines=CS[0],CS[1], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + *
> > + * Example 2 pseudo code:
> > + * CS[X] = generic engine of same class, logical instance X
> > + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
> > + * set_engines(INVALID)
> > + * set_parallel(engine_index=0, width=2, num_siblings=2,
> > + *		engines=CS[0],CS[2],CS[1],CS[3], flags=I915_PARALLEL_IMPLICT_BONDS)
> > + *
> > + * Results in the following valid placements:
> > + * CS[0], CS[1]
> > + * CS[2], CS[3]
> > + *
> > + * This can also be though of as 2 virtual engines:
> > + * VE[0] = CS[0], CS[2]
> > + * VE[1] = CS[1], CS[3]
> > + *
> > + * This enables a use case where all engines are not equal and certain placement
> > + * rules are required (i.e. split-frame requires all contexts to be placed in a
> > + * logically contiguous order on the VCS engines on gen11+ platforms). This use
> > + * case (logically contiguous placement, within a single engine class) is
> > + * supported when using GuC submission. Execlist mode could support all possible
> > + * bonding configurations but currently doesn't support this extension.
> > + */
> > +#define I915_PARALLEL_IMPLICT_BONDS			(1<<0)
> > +/*
> > + * Do not allow BBs to be preempted mid BB rather insert coordinated preemption
> > + * points on all hardware contexts between each set of BBs. An example use case
> > + * of this feature is split-frame on gen11+ hardware. When using this feature a
> > + * BB must be submitted on each hardware context in the parallel gem context.
> > + * The execbuf2 IOCTL enforces the user adheres to policy.
> > + */
> Is the part about execbuf2 enforcing num_batches == context_width still
> valid, I mean is the latest proposal supporting num_batches < context_width?
> Does media needs this option?
>

With the new uAPI num_batches == context_width regardless of this flag. This is
a stale comment that needs to be removed.
 
> I would also have this flag as a separate patch because it strictly isn't
> about parallel submission per-se but a specific hw limitation on top of it.
>

Yep, I do in the actual code but this in just the RFC header. Can break it out
in the RFC header but IMO it is better to have in a single patch to review.

Matt
 
> Regards,
> 
> Tvrtko
> 
> > +#define I915_PARALLEL_NO_PREEMPT_MID_BATCH		(1<<1)
> > +#define __I915_PARALLEL_UNKNOWN_FLAGS	(-(I915_PARALLEL_NO_PREEMPT_MID_BATCH << 1))
> > +	__u64 flags;		/* all undefined flags must be zero */
> > +	__u64 mbz64[3];		/* reserved for future use; must be zero */
> > +
> > +	/*
> > +	 * width (i) * num_siblings (j) in length
> > +	 * index = j + i * num_siblings
> > +	 */
> > +	struct i915_engine_class_instance engines[0];
> > +} __attribute__ ((packed));
> > +
> > diff --git a/Documentation/gpu/rfc/i915_scheduler.rst b/Documentation/gpu/rfc/i915_scheduler.rst
> > index 7faa46cde088..64c539486ee4 100644
> > --- a/Documentation/gpu/rfc/i915_scheduler.rst
> > +++ b/Documentation/gpu/rfc/i915_scheduler.rst
> > @@ -82,4 +82,55 @@ https://spec.oneapi.com/level-zero/latest/core/api.html#ze-command-queue-priorit
> >   New parallel submission uAPI
> >   ============================
> > -Details to come in a following patch.
> > +The existing bonding uAPI is completely broken with GuC submission because
> > +whether a submission is a single context submit or parallel submit isn't known
> > +until execbuf time activated via the I915_SUBMIT_FENCE. To submit multiple
> > +contexts in parallel with the GuC the context must be explictly registered with
> > +N contexts and all N contexts must be submitted in a single command to the GuC.
> > +These interfaces doesn't support dynamically changing between N contexts as the
> > +bonding uAPI does. Hence the need for a new parallel submission interface. Also
> > +the legacy bonding uAPI is quite confusing and not intuitive at all.
> > +
> > +The new parallel submission uAPI consists of 3 parts:
> > +
> > +* Export engines logical mapping
> > +* A 'set_parallel' extension to configure contexts for parallel
> > +  submission
> > +* Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +
> > +Export engines logical mapping
> > +------------------------------
> > +Certain use cases require BBs to be placed on engine instances in logical order
> > +(e.g. split-frame on gen11+). The logical mapping of engine instances can change
> > +based on fusing. Rather than making UMDs be aware of fusing, simply expose the
> > +logical mapping with the existing query engine info IOCTL. Also the GuC
> > +submission interface currently only supports submitting multiple contexts to
> > +engines in logical order which is a new requirement compared to execlists.
> > +Lastly, all current platforms have at most 2 instances and the logical order is
> > +the same a uABI order. This will change on platforms with more than 2 instances.
> > +
> > +A single bit will be added to drm_i915_engine_info.flags indicating that the
> > +logical instance has been returned and a new field,
> > +drm_i915_engine_info.logical_instance, returns the logical instance.
> > +
> > +A 'set_parallel' extension to configure contexts for parallel submission
> > +------------------------------------------------------------------------
> > +The 'set_parallel' extension configures a slot for parallel submission of N BBs.
> > +It is setup step that should be called before using any of the contexts. See
> > +I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE or I915_CONTEXT_ENGINES_EXT_BOND for
> > +similar existing examples. Once a slot is configured for parallel submission the
> > +execbuf2 IOCTL can be called submiting N BBs in a single IOCTL. Initially only
> > +support GuC submission. Execlist support can be added later if needed.
> > +
> > +Add I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT and
> > +i915_context_engines_parallel_submit to the uAPI to implement this extension.
> > +
> > +Extend execbuf2 IOCTL to support submitting N BBs in a single IOCTL
> > +-------------------------------------------------------------------
> > +Contexts that have been configured with the 'set_parallel' extension are allowed
> > +to submit N BBs in a single execbuf2 IOCTL. The BBs are either the last N
> > +objects in the drm_i915_gem_exec_object2 list or the first N if
> > +I915_EXEC_BATCH_FIRST is set. The number of BBs is implict based on the slot
> > +submitted and how it has been configured by 'set_parallel' or other extensions.
> > +No uAPI changes in the execbuf IOCTL but worth mentioning the new behavior of
> > +the IOCTL.
> > 
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
  2021-05-21 16:48       ` Matthew Brost
@ 2021-05-24 15:33         ` Tvrtko Ursulin
  -1 siblings, 0 replies; 54+ messages in thread
From: Tvrtko Ursulin @ 2021-05-24 15:33 UTC (permalink / raw)
  To: Matthew Brost
  Cc: intel-gfx, dri-devel, jason.ekstrand, daniel.vetter, mesa-dev,
	karl, christian.koenig


On 21/05/2021 17:48, Matthew Brost wrote:
> On Fri, May 21, 2021 at 01:00:54PM +0100, Tvrtko Ursulin wrote:

[snip]

>>> + * enables parallel submission across multiple engine classes. In this case each
>>> + * context's logical engine mask indicates where that context can placed. It is
>>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>>> + * if one context is running CS0 no other contexts can run on CS0).
>>
>> I think talk about logical context and its mask is too implementation detail
>> at the uapi level. Instead I would suggest more userspace programmer centric
>> description.
> 
> Ok, can you give me suggestion? Writing DOC isn't really my strength.

Yeah, not mine either. Maybe we need to hire a technical writer. :)

I think in general I would just talk a bit how until now submission was 
along a single engine only and this is adding a wide submission model, 
expanding how it works with more details and only then talking about 
logical contexts if needed.

It depends a bit whether our userspace clients still predominantly think 
in terms of engines, or is it contexts? I don't have an answer there.

It probably isn't the most important thing and probably with a few 
tweaks of what you have it can be good enough. Key probably is simply 
coming up with as intuitive as possible diagrams, with consistent 
naming, showing how the wide engine is built and how it works.

>>> + *
>>> + * Example 1 pseudo code:
>>> + * CSX[Y] = engine class X, logical instance Y
>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>> + * set_engines(INVALID)
>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
>>> + *
>>> + * Results in the following valid placements:
>>> + * CS0[0], CS1[0]
>>> + * CS0[0], CS1[1]
>>> + * CS0[1], CS1[0]
>>> + * CS0[1], CS1[1]
>>> + *
>>> + * This can also be though of as 2 virtual engines:
>>> + * VE[0] = CS0[0], CS0[1]
>>> + * VE[1] = CS1[0], CS1[1]
>>
>> Ah okay so essentially similar to what I was proposing a year ago. But then
>> it is no longer "set_parallel" really. It is one slot in the engine map,
>> right, with the idea to super class intel_context in the implementation?
>>
> 
> Yes, it is bascially a super class intel_context. In the implementation is
> parent-child with the parent having a linked list of child intel_contexts.
>   
>> So really a wide virtual engine, as opposed to single one. In which case I
>> think it makes sense to stay close to the existing naming of the
>> load_balance extension for consistency. Load_balance_wide?
>> Load_balance_parallel? Multi?
> 
> I like the way is named but I also don't want to argue about this as I don't
> really care. If someone else says this should be renamed, let's do it.

I don't care too much apart from a general desire for more consistency 
and fewer terms in use.

>> I also have to say the notation "CS0[0]" - I who know this problem space am
>> finding it hard to penetrate what that actually means. (Also uppercase IMO
>> makes it hard to read, but maybe it is just me.)
>>
> 
> Yea, now I think about it CS0[0] is bad because of using numbers twice. How
> about CSX[0] & CSY[1]? I used upper case because in the i915 all engine classes
> defines are upper case but agree it might be easier to read it lower case.

What would X and Y represent? Or if I paste this part:

  * VE[0] = CS0[0], CS0[1]
  * VE[1] = CS1[0], CS1[1]

Which index is engine instance and what is the other index?

>> Looking a bit lower below, extension seems to be taking a 2d array of
>> class:instance pairs, right? If so then reading these docs in order, or even
>> just looking further down, I don't think that is explicitly called out
>> clearly enough.
>>
>> So I think a paragraph or two explaining clearly how the 2d array of engines
>> corresponds to the allowed engines for full virtual engine width. Or maybe
>> just a 2d diagram?
>>
>>    2-wide virtual engine:
>>      .engines = [
>>        /* channel 0 allowed engines: */  [cs0, cs1],
>>        /* channel 1 allowed engines: */  [cs0, cs1]
>>       ]
>>
>> Not sure if that's better.
>>
> 
> Yes, it is a 2-d array. Agree the explaination could be better.
> 
>> Also to be noted, this only allows uniform number of allowed engines per
>> channel. I am not saying we need the non-uniform setup today but with bonds
>> there isn't this limitation.
>>
> 
> Not exactly. You could do something like this.
> 
> witdth = 2
> siblings = 2
> engines = CSX[0], CSX[1], CSY[0], INVALID
> 
> This would allow a placement of:
> 
> CSX[0], CSY[0]
> CSX[1], CSY[0]
> 
> In this case the siblings is just a max value of each entry.

Okay fair, did not think about that or saw it mentioned.

Regards,

Tvrtko

^ permalink raw reply	[flat|nested] 54+ messages in thread

* Re: [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan
@ 2021-05-24 15:33         ` Tvrtko Ursulin
  0 siblings, 0 replies; 54+ messages in thread
From: Tvrtko Ursulin @ 2021-05-24 15:33 UTC (permalink / raw)
  To: Matthew Brost
  Cc: intel-gfx, dri-devel, jason.ekstrand, daniel.vetter, mesa-dev,
	karl, christian.koenig


On 21/05/2021 17:48, Matthew Brost wrote:
> On Fri, May 21, 2021 at 01:00:54PM +0100, Tvrtko Ursulin wrote:

[snip]

>>> + * enables parallel submission across multiple engine classes. In this case each
>>> + * context's logical engine mask indicates where that context can placed. It is
>>> + * implied in this mode that all contexts have mutual exclusive placement (e.g.
>>> + * if one context is running CS0 no other contexts can run on CS0).
>>
>> I think talk about logical context and its mask is too implementation detail
>> at the uapi level. Instead I would suggest more userspace programmer centric
>> description.
> 
> Ok, can you give me suggestion? Writing DOC isn't really my strength.

Yeah, not mine either. Maybe we need to hire a technical writer. :)

I think in general I would just talk a bit how until now submission was 
along a single engine only and this is adding a wide submission model, 
expanding how it works with more details and only then talking about 
logical contexts if needed.

It depends a bit whether our userspace clients still predominantly think 
in terms of engines, or is it contexts? I don't have an answer there.

It probably isn't the most important thing and probably with a few 
tweaks of what you have it can be good enough. Key probably is simply 
coming up with as intuitive as possible diagrams, with consistent 
naming, showing how the wide engine is built and how it works.

>>> + *
>>> + * Example 1 pseudo code:
>>> + * CSX[Y] = engine class X, logical instance Y
>>> + * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
>>> + * set_engines(INVALID)
>>> + * set_parallel(engine_index=0, width=2, num_siblings=2,
>>> + *		engines=CS0[0],CS0[1],CS1[0],CS1[1])
>>> + *
>>> + * Results in the following valid placements:
>>> + * CS0[0], CS1[0]
>>> + * CS0[0], CS1[1]
>>> + * CS0[1], CS1[0]
>>> + * CS0[1], CS1[1]
>>> + *
>>> + * This can also be though of as 2 virtual engines:
>>> + * VE[0] = CS0[0], CS0[1]
>>> + * VE[1] = CS1[0], CS1[1]
>>
>> Ah okay so essentially similar to what I was proposing a year ago. But then
>> it is no longer "set_parallel" really. It is one slot in the engine map,
>> right, with the idea to super class intel_context in the implementation?
>>
> 
> Yes, it is bascially a super class intel_context. In the implementation is
> parent-child with the parent having a linked list of child intel_contexts.
>   
>> So really a wide virtual engine, as opposed to single one. In which case I
>> think it makes sense to stay close to the existing naming of the
>> load_balance extension for consistency. Load_balance_wide?
>> Load_balance_parallel? Multi?
> 
> I like the way is named but I also don't want to argue about this as I don't
> really care. If someone else says this should be renamed, let's do it.

I don't care too much apart from a general desire for more consistency 
and fewer terms in use.

>> I also have to say the notation "CS0[0]" - I who know this problem space am
>> finding it hard to penetrate what that actually means. (Also uppercase IMO
>> makes it hard to read, but maybe it is just me.)
>>
> 
> Yea, now I think about it CS0[0] is bad because of using numbers twice. How
> about CSX[0] & CSY[1]? I used upper case because in the i915 all engine classes
> defines are upper case but agree it might be easier to read it lower case.

What would X and Y represent? Or if I paste this part:

  * VE[0] = CS0[0], CS0[1]
  * VE[1] = CS1[0], CS1[1]

Which index is engine instance and what is the other index?

>> Looking a bit lower below, extension seems to be taking a 2d array of
>> class:instance pairs, right? If so then reading these docs in order, or even
>> just looking further down, I don't think that is explicitly called out
>> clearly enough.
>>
>> So I think a paragraph or two explaining clearly how the 2d array of engines
>> corresponds to the allowed engines for full virtual engine width. Or maybe
>> just a 2d diagram?
>>
>>    2-wide virtual engine:
>>      .engines = [
>>        /* channel 0 allowed engines: */  [cs0, cs1],
>>        /* channel 1 allowed engines: */  [cs0, cs1]
>>       ]
>>
>> Not sure if that's better.
>>
> 
> Yes, it is a 2-d array. Agree the explaination could be better.
> 
>> Also to be noted, this only allows uniform number of allowed engines per
>> channel. I am not saying we need the non-uniform setup today but with bonds
>> there isn't this limitation.
>>
> 
> Not exactly. You could do something like this.
> 
> witdth = 2
> siblings = 2
> engines = CSX[0], CSX[1], CSY[0], INVALID
> 
> This would allow a placement of:
> 
> CSX[0], CSY[0]
> CSX[1], CSY[0]
> 
> In this case the siblings is just a max value of each entry.

Okay fair, did not think about that or saw it mentioned.

Regards,

Tvrtko
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 54+ messages in thread

end of thread, other threads:[~2021-05-24 15:33 UTC | newest]

Thread overview: 54+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-05-18 23:58 [RFC 0/2] GuC submission / DRM scheduler integration plan + new uAPI Matthew Brost
2021-05-18 23:58 ` [Intel-gfx] " Matthew Brost
2021-05-18 23:47 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for GuC submission / DRM scheduler integration plan + new uAPI (rev2) Patchwork
2021-05-18 23:51 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-05-18 23:58 ` [RFC 1/2] drm/doc/rfc: i915 GuC submission / DRM scheduler Matthew Brost
2021-05-18 23:58   ` [Intel-gfx] " Matthew Brost
2021-05-18 23:58 ` [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan Matthew Brost
2021-05-18 23:58   ` [Intel-gfx] " Matthew Brost
2021-05-19 11:10   ` Daniel Vetter
2021-05-19 11:10     ` Daniel Vetter
2021-05-19 15:29     ` Tvrtko Ursulin
2021-05-19 15:29       ` Tvrtko Ursulin
2021-05-19 17:11     ` Matthew Brost
2021-05-19 17:11       ` Matthew Brost
2021-05-20  9:54       ` Daniel Vetter
2021-05-20  9:54         ` Daniel Vetter
2021-05-20 10:57         ` Tvrtko Ursulin
2021-05-20 10:57           ` Tvrtko Ursulin
2021-05-20 19:41           ` Daniel Vetter
2021-05-20 19:41             ` Daniel Vetter
2021-05-21 12:12             ` Tvrtko Ursulin
2021-05-21 12:12               ` Tvrtko Ursulin
2021-05-21 16:26             ` Matthew Brost
2021-05-21 16:26               ` Matthew Brost
2021-05-20 15:10         ` Matthew Brost
2021-05-20 15:10           ` Matthew Brost
2021-05-20 19:44           ` Daniel Vetter
2021-05-20 19:44             ` Daniel Vetter
2021-05-21 16:20             ` Matthew Brost
2021-05-21 16:20               ` Matthew Brost
2021-05-19 11:45   ` [Mesa-dev] " Christian König
2021-05-19 11:45     ` [Intel-gfx] " Christian König
2021-05-19 16:51     ` Matthew Brost
2021-05-19 16:51       ` [Intel-gfx] " Matthew Brost
2021-05-20 11:11       ` Christian König
2021-05-20 11:11         ` [Intel-gfx] " Christian König
2021-05-20 15:39         ` Matthew Brost
2021-05-20 15:39           ` [Intel-gfx] " Matthew Brost
2021-05-20 21:38           ` Jason Ekstrand
2021-05-20 21:38             ` Jason Ekstrand
2021-05-21  8:35             ` Christian König
2021-05-21  8:35               ` Christian König
2021-05-21 16:14               ` Matthew Brost
2021-05-21 16:14                 ` Matthew Brost
2021-05-19 13:57   ` Marcin Ślusarz
2021-05-19 13:57     ` [Intel-gfx] " Marcin Ślusarz
2021-05-21 12:00   ` [Intel-gfx] " Tvrtko Ursulin
2021-05-21 12:00     ` Tvrtko Ursulin
2021-05-21 16:48     ` Matthew Brost
2021-05-21 16:48       ` Matthew Brost
2021-05-24 15:33       ` Tvrtko Ursulin
2021-05-24 15:33         ` Tvrtko Ursulin
2021-05-19  0:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success for GuC submission / DRM scheduler integration plan + new uAPI (rev2) Patchwork
2021-05-20  1:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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