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From: Mark Rutland <mark.rutland@arm.com>
To: Fuad Tabba <tabba@google.com>
Cc: linux-arm-kernel@lists.infradead.org, will@kernel.org,
	catalin.marinas@arm.com, maz@kernel.org, ardb@kernel.org,
	james.morse@arm.com, alexandru.elisei@arm.com,
	suzuki.poulose@arm.com, robin.murphy@arm.com
Subject: Re: [PATCH v3 11/18] arm64: dcache_by_line_op to take end parameter instead of size
Date: Thu, 20 May 2021 16:48:26 +0100	[thread overview]
Message-ID: <20210520154826.GO17233@C02TD0UTHF1T.local> (raw)
In-Reply-To: <20210520124406.2731873-12-tabba@google.com>

On Thu, May 20, 2021 at 01:43:59PM +0100, Fuad Tabba wrote:
> To be consistent with other functions with similar names and
> functionality in cacheflush.h, cache.S, and cachetlb.rst, change
> to specify the range in terms of start and end, as opposed to
> start and size.
> 
> No functional change intended.
> 
> Reported-by: Will Deacon <will@kernel.org>
> Signed-off-by: Fuad Tabba <tabba@google.com>

Acked-by: Mark Rutland <mark.rutland@arm.com>

Mark.

> ---
>  arch/arm64/include/asm/assembler.h | 27 +++++++++++++--------------
>  arch/arm64/kvm/hyp/nvhe/cache.S    |  1 +
>  arch/arm64/mm/cache.S              |  5 +++++
>  3 files changed, 19 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
> index ced791124b28..c4cecf85dccf 100644
> --- a/arch/arm64/include/asm/assembler.h
> +++ b/arch/arm64/include/asm/assembler.h
> @@ -397,40 +397,39 @@ alternative_endif
>  
>  /*
>   * Macro to perform a data cache maintenance for the interval
> - * [addr, addr + size)
> + * [start, end)
>   *
>   * 	op:		operation passed to dc instruction
>   * 	domain:		domain used in dsb instruciton
> - * 	addr:		starting virtual address of the region
> - * 	size:		size of the region
> + * 	start:          starting virtual address of the region
> + * 	end:            end virtual address of the region
>   * 	fixup:		optional label to branch to on user fault
> - * 	Corrupts:	addr, size, tmp1, tmp2
> + * 	Corrupts:       start, end, tmp1, tmp2
>   */
> -	.macro dcache_by_line_op op, domain, addr, size, tmp1, tmp2, fixup
> +	.macro dcache_by_line_op op, domain, start, end, tmp1, tmp2, fixup
>  	dcache_line_size \tmp1, \tmp2
> -	add	\size, \addr, \size
>  	sub	\tmp2, \tmp1, #1
> -	bic	\addr, \addr, \tmp2
> +	bic	\start, \start, \tmp2
>  .Ldcache_op\@:
>  	.ifc	\op, cvau
> -	__dcache_op_workaround_clean_cache \op, \addr
> +	__dcache_op_workaround_clean_cache \op, \start
>  	.else
>  	.ifc	\op, cvac
> -	__dcache_op_workaround_clean_cache \op, \addr
> +	__dcache_op_workaround_clean_cache \op, \start
>  	.else
>  	.ifc	\op, cvap
> -	sys	3, c7, c12, 1, \addr	// dc cvap
> +	sys	3, c7, c12, 1, \start	// dc cvap
>  	.else
>  	.ifc	\op, cvadp
> -	sys	3, c7, c13, 1, \addr	// dc cvadp
> +	sys	3, c7, c13, 1, \start	// dc cvadp
>  	.else
> -	dc	\op, \addr
> +	dc	\op, \start
>  	.endif
>  	.endif
>  	.endif
>  	.endif
> -	add	\addr, \addr, \tmp1
> -	cmp	\addr, \size
> +	add	\start, \start, \tmp1
> +	cmp	\start, \end
>  	b.lo	.Ldcache_op\@
>  	dsb	\domain
>  
> diff --git a/arch/arm64/kvm/hyp/nvhe/cache.S b/arch/arm64/kvm/hyp/nvhe/cache.S
> index 36cef6915428..3bcfa3cac46f 100644
> --- a/arch/arm64/kvm/hyp/nvhe/cache.S
> +++ b/arch/arm64/kvm/hyp/nvhe/cache.S
> @@ -8,6 +8,7 @@
>  #include <asm/alternative.h>
>  
>  SYM_FUNC_START_PI(__flush_dcache_area)
> +	add	x1, x0, x1
>  	dcache_by_line_op civac, sy, x0, x1, x2, x3
>  	ret
>  SYM_FUNC_END_PI(__flush_dcache_area)
> diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
> index 5170d9ab450a..3b5461a32b85 100644
> --- a/arch/arm64/mm/cache.S
> +++ b/arch/arm64/mm/cache.S
> @@ -115,6 +115,7 @@ SYM_FUNC_END(invalidate_icache_range)
>   *	- size    - size in question
>   */
>  SYM_FUNC_START_PI(__flush_dcache_area)
> +	add	x1, x0, x1
>  	dcache_by_line_op civac, sy, x0, x1, x2, x3
>  	ret
>  SYM_FUNC_END_PI(__flush_dcache_area)
> @@ -133,6 +134,7 @@ alternative_if ARM64_HAS_CACHE_IDC
>  	dsb	ishst
>  	ret
>  alternative_else_nop_endif
> +	add	x1, x0, x1
>  	dcache_by_line_op cvau, ish, x0, x1, x2, x3
>  	ret
>  SYM_FUNC_END(__clean_dcache_area_pou)
> @@ -194,6 +196,7 @@ SYM_FUNC_START_PI(__clean_dcache_area_poc)
>   *	- start   - virtual start address of region
>   *	- size    - size in question
>   */
> +	add	x1, x0, x1
>  	dcache_by_line_op cvac, sy, x0, x1, x2, x3
>  	ret
>  SYM_FUNC_END_PI(__clean_dcache_area_poc)
> @@ -212,6 +215,7 @@ SYM_FUNC_START_PI(__clean_dcache_area_pop)
>  	alternative_if_not ARM64_HAS_DCPOP
>  	b	__clean_dcache_area_poc
>  	alternative_else_nop_endif
> +	add	x1, x0, x1
>  	dcache_by_line_op cvap, sy, x0, x1, x2, x3
>  	ret
>  SYM_FUNC_END_PI(__clean_dcache_area_pop)
> @@ -225,6 +229,7 @@ SYM_FUNC_END_PI(__clean_dcache_area_pop)
>   *	- size    - size in question
>   */
>  SYM_FUNC_START_PI(__dma_flush_area)
> +	add	x1, x0, x1
>  	dcache_by_line_op civac, sy, x0, x1, x2, x3
>  	ret
>  SYM_FUNC_END_PI(__dma_flush_area)
> -- 
> 2.31.1.751.gd2f1c929bd-goog
> 

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  reply	other threads:[~2021-05-20 15:50 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-20 12:43 [PATCH v3 00/18] Tidy up cache.S Fuad Tabba
2021-05-20 12:43 ` [PATCH v3 01/18] arm64: assembler: replace `kaddr` with `addr` Fuad Tabba
2021-05-20 12:43 ` [PATCH v3 02/18] arm64: assembler: add conditional cache fixups Fuad Tabba
2021-05-20 12:43 ` [PATCH v3 03/18] arm64: Apply errata to swsusp_arch_suspend_exit Fuad Tabba
2021-05-20 12:46   ` Mark Rutland
2021-05-20 12:43 ` [PATCH v3 04/18] arm64: assembler: user_alt label optional Fuad Tabba
2021-05-20 12:57   ` Mark Rutland
2021-05-21 11:46     ` Fuad Tabba
2021-05-21 13:05       ` Mark Rutland
2021-05-20 12:43 ` [PATCH v3 05/18] arm64: Do not enable uaccess for flush_icache_range Fuad Tabba
2021-05-20 14:02   ` Mark Rutland
2021-05-20 15:37     ` Mark Rutland
2021-05-21 12:18       ` Mark Rutland
2021-05-25 11:18   ` Catalin Marinas
2021-05-20 12:43 ` [PATCH v3 06/18] arm64: Do not enable uaccess for invalidate_icache_range Fuad Tabba
2021-05-20 14:13   ` Mark Rutland
2021-05-25 11:18   ` Catalin Marinas
2021-05-20 12:43 ` [PATCH v3 07/18] arm64: Downgrade flush_icache_range to invalidate Fuad Tabba
2021-05-20 14:15   ` Mark Rutland
2021-05-25 11:18   ` Catalin Marinas
2021-05-20 12:43 ` [PATCH v3 08/18] arm64: Move documentation of dcache_by_line_op Fuad Tabba
2021-05-20 14:17   ` Mark Rutland
2021-05-20 12:43 ` [PATCH v3 09/18] arm64: Fix comments to refer to correct function __flush_icache_range Fuad Tabba
2021-05-20 14:18   ` Mark Rutland
2021-05-20 12:43 ` [PATCH v3 10/18] arm64: __inval_dcache_area to take end parameter instead of size Fuad Tabba
2021-05-20 15:46   ` Mark Rutland
2021-05-20 12:43 ` [PATCH v3 11/18] arm64: dcache_by_line_op " Fuad Tabba
2021-05-20 15:48   ` Mark Rutland [this message]
2021-05-20 12:44 ` [PATCH v3 12/18] arm64: __flush_dcache_area " Fuad Tabba
2021-05-20 16:06   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 13/18] arm64: __clean_dcache_area_poc " Fuad Tabba
2021-05-20 16:16   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 14/18] arm64: __clean_dcache_area_pop " Fuad Tabba
2021-05-20 16:19   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 15/18] arm64: __clean_dcache_area_pou " Fuad Tabba
2021-05-20 16:24   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 16/18] arm64: sync_icache_aliases " Fuad Tabba
2021-05-20 16:34   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 17/18] arm64: Fix cache maintenance function comments Fuad Tabba
2021-05-20 16:48   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 18/18] arm64: Rename arm64-internal cache maintenance functions Fuad Tabba
2021-05-20 17:01   ` Mark Rutland

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