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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id f20sm4988976wmh.41.2021.05.20.19.42.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 19:42:17 -0700 (PDT) From: Bin Meng To: Gerd Hoffmann , qemu-devel@nongnu.org Subject: [PATCH 1/2] hw/usb: hcd-xhci-pci: Raise MSI/MSI-X interrupts only when told to Date: Fri, 21 May 2021 10:42:23 +0800 Message-Id: <20210521024224.2277634-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=bmeng.cn@gmail.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Ruimei Yan Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Ruimei Yan At present MSI / MSI-X interrupts are triggered regardless of the irq level. We should have checked the level to determine whether the interrupt needs to be delivered. The level check logic was present in early versions of the xhci model, but got dropped later by a rework of interrupt handling under commit 4c4abe7cc903 ("xhci: rework interrupt handling"). Fixes: 4c4abe7cc903 ("xhci: rework interrupt handling") Signed-off-by: Ruimei Yan Signed-off-by: Bin Meng --- hw/usb/hcd-xhci-pci.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c index 9421734d0f..b6acd1790c 100644 --- a/hw/usb/hcd-xhci-pci.c +++ b/hw/usb/hcd-xhci-pci.c @@ -67,12 +67,13 @@ static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) msi_enabled(pci_dev))) { pci_set_irq(pci_dev, level); } - if (msix_enabled(pci_dev)) { + + if (msix_enabled(pci_dev) && level) { msix_notify(pci_dev, n); return; } - if (msi_enabled(pci_dev)) { + if (msi_enabled(pci_dev) && level) { msi_notify(pci_dev, n); return; } -- 2.25.1