From: Vinod Koul <vkoul@kernel.org>
To: Rob Clark <robdclark@gmail.com>
Cc: linux-arm-msm@vger.kernel.org,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Vinod Koul <vkoul@kernel.org>, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
Jonathan Marek <jonathan@marek.ca>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Abhinav Kumar <abhinavk@codeaurora.org>,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org
Subject: [RFC PATCH 08/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl
Date: Fri, 21 May 2021 18:19:40 +0530 [thread overview]
Message-ID: <20210521124946.3617862-12-vkoul@kernel.org> (raw)
In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org>
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 2d4645e01ebf..aeea6add61ee 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -25,6 +25,8 @@
#define CTL_MERGE_3D_ACTIVE 0x0E4
#define CTL_INTF_ACTIVE 0x0F4
#define CTL_MERGE_3D_FLUSH 0x100
+#define CTL_DSC_ACTIVE 0x0E8
+#define CTL_DSC_FLUSH 0x104
#define CTL_INTF_FLUSH 0x110
#define CTL_INTF_MASTER 0x134
#define CTL_FETCH_PIPE_ACTIVE 0x0FC
@@ -34,6 +36,7 @@
#define DPU_REG_RESET_TIMEOUT_US 2000
#define MERGE_3D_IDX 23
+#define DSC_IDX 22
#define INTF_IDX 31
#define CTL_INVALID_BIT 0xffff
@@ -120,6 +123,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
{
+ DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) | BIT(3));
if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
@@ -128,7 +132,7 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,
ctx->pending_intf_flush_mask);
- DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
+ DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask | BIT(DSC_IDX));
}
static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
@@ -507,6 +511,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
if (cfg->merge_3d)
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
BIT(cfg->merge_3d - MERGE_3D_0));
+ DPU_REG_WRITE(c, CTL_DSC_ACTIVE, BIT(0) | BIT(1) | BIT(2) | BIT(3));
}
static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
--
2.26.3
WARNING: multiple messages have this Message-ID
From: Vinod Koul <vkoul@kernel.org>
To: Rob Clark <robdclark@gmail.com>
Cc: Jonathan Marek <jonathan@marek.ca>,
David Airlie <airlied@linux.ie>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
Abhinav Kumar <abhinavk@codeaurora.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Vinod Koul <vkoul@kernel.org>,
dri-devel@lists.freedesktop.org,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
freedreno@lists.freedesktop.org
Subject: [RFC PATCH 08/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl
Date: Fri, 21 May 2021 18:19:40 +0530 [thread overview]
Message-ID: <20210521124946.3617862-12-vkoul@kernel.org> (raw)
In-Reply-To: <20210521124946.3617862-1-vkoul@kernel.org>
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 2d4645e01ebf..aeea6add61ee 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -25,6 +25,8 @@
#define CTL_MERGE_3D_ACTIVE 0x0E4
#define CTL_INTF_ACTIVE 0x0F4
#define CTL_MERGE_3D_FLUSH 0x100
+#define CTL_DSC_ACTIVE 0x0E8
+#define CTL_DSC_FLUSH 0x104
#define CTL_INTF_FLUSH 0x110
#define CTL_INTF_MASTER 0x134
#define CTL_FETCH_PIPE_ACTIVE 0x0FC
@@ -34,6 +36,7 @@
#define DPU_REG_RESET_TIMEOUT_US 2000
#define MERGE_3D_IDX 23
+#define DSC_IDX 22
#define INTF_IDX 31
#define CTL_INVALID_BIT 0xffff
@@ -120,6 +123,7 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
{
+ DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, BIT(0) | BIT(1) | BIT(2) | BIT(3));
if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
@@ -128,7 +132,7 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
DPU_REG_WRITE(&ctx->hw, CTL_INTF_FLUSH,
ctx->pending_intf_flush_mask);
- DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask);
+ DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, ctx->pending_flush_mask | BIT(DSC_IDX));
}
static inline void dpu_hw_ctl_trigger_flush(struct dpu_hw_ctl *ctx)
@@ -507,6 +511,7 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
if (cfg->merge_3d)
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
BIT(cfg->merge_3d - MERGE_3D_0));
+ DPU_REG_WRITE(c, CTL_DSC_ACTIVE, BIT(0) | BIT(1) | BIT(2) | BIT(3));
}
static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
--
2.26.3
next prev parent reply other threads:[~2021-05-21 12:51 UTC|newest]
Thread overview: 91+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-21 12:49 [RFC PATCH 00/13] drm/msm: Add Display Stream Compression Support Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 01/13] drm/dsc: Add dsc pps header init function Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 15:29 ` Daniel Vetter
2021-05-21 15:29 ` Daniel Vetter
2021-05-24 7:26 ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 02/13] dt-bindings: msm/dsi: Document Display Stream Compression (DSC) parameters Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 13:18 ` Rob Herring
2021-05-21 13:18 ` Rob Herring
2021-05-21 13:23 ` Vinod Koul
2021-05-21 13:23 ` Vinod Koul
2021-05-21 14:42 ` Bjorn Andersson
2021-05-21 14:42 ` Bjorn Andersson
2021-05-24 7:30 ` Vinod Koul
2021-05-24 7:30 ` Vinod Koul
2021-05-24 15:08 ` Bjorn Andersson
2021-05-24 15:08 ` Bjorn Andersson
2021-05-26 5:32 ` Vinod Koul
2021-05-26 5:32 ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 03/13] drm/msm/disp/dpu1: Add support for DSC Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-27 23:49 ` Dmitry Baryshkov
2021-05-27 23:49 ` Dmitry Baryshkov
2021-05-21 12:49 ` [RFC PATCH 03/13] drm/msm/dsi: add support for dsc data Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-27 23:45 ` Dmitry Baryshkov
2021-05-27 23:45 ` Dmitry Baryshkov
2021-06-02 11:06 ` Vinod Koul
2021-06-02 11:06 ` Vinod Koul
2021-05-28 10:29 ` Dmitry Baryshkov
2021-05-28 10:29 ` Dmitry Baryshkov
2021-06-02 11:17 ` Vinod Koul
2021-06-02 11:17 ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 04/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 04/13] drm/msm/disp/dpu1: Add support for DSC Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-28 10:31 ` Dmitry Baryshkov
2021-05-28 10:31 ` Dmitry Baryshkov
2021-05-21 12:49 ` [RFC PATCH 05/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 05/13] drm/msm/dsi: add support for dsc data Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 06/13] drm/msm/disp/dpu1: Add DSC support in RM Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-28 10:33 ` Dmitry Baryshkov
2021-05-28 10:33 ` Dmitry Baryshkov
2021-05-21 12:49 ` [RFC PATCH 07/13] drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 12:49 ` Vinod Koul [this message]
2021-05-21 12:49 ` [RFC PATCH 08/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 09/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-28 10:36 ` Dmitry Baryshkov
2021-05-28 10:36 ` Dmitry Baryshkov
2021-05-21 12:49 ` [RFC PATCH 09/13] drm/msm/disp/dpu1: Dont " Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 10/13] drm/msm/disp/dpu1: Add support for DSC in encoder Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 11/13] drm/msm/disp/dpu1: Add support for DSC in topology Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-28 10:39 ` Dmitry Baryshkov
2021-05-28 10:39 ` Dmitry Baryshkov
2021-05-28 22:23 ` abhinavk
2021-05-28 22:23 ` abhinavk
2021-05-28 22:29 ` Dmitry Baryshkov
2021-05-28 22:29 ` Dmitry Baryshkov
2021-05-21 12:49 ` [RFC PATCH 12/13] drm/msm/dsi: Add support for DSC configuration Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 12:49 ` [RFC PATCH 13/13] drm/msm/dsi: Pass DSC params to drm_panel Vinod Koul
2021-05-21 12:49 ` Vinod Koul
2021-05-21 14:09 ` [Freedreno] [RFC PATCH 00/13] drm/msm: Add Display Stream Compression Support Jeffrey Hugo
2021-05-21 14:09 ` Jeffrey Hugo
2021-05-26 5:46 ` Vinod Koul
2021-05-26 5:46 ` Vinod Koul
2021-05-26 15:00 ` Jeffrey Hugo
2021-05-26 15:00 ` Jeffrey Hugo
2021-05-27 23:30 ` Rob Clark
2021-05-27 23:30 ` Rob Clark
2021-06-02 11:01 ` Vinod Koul
2021-06-02 11:01 ` Vinod Koul
2021-06-03 23:40 ` abhinavk
2021-06-03 23:40 ` abhinavk
2021-06-17 8:06 ` Vinod Koul
2021-06-17 8:06 ` Vinod Koul
2021-06-04 2:36 ` Rob Clark
2021-06-04 2:36 ` Rob Clark
2021-06-02 10:56 ` Vinod Koul
2021-06-02 10:56 ` Vinod Koul
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