From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38B94C47076 for ; Fri, 21 May 2021 16:43:01 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A72F960698 for ; Fri, 21 May 2021 16:43:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A72F960698 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=IF9blM3A4/RuvIMn+hviRzkP7KnTHMcqIj5nfARRoG8=; b=gnjjJ0gxujTHZ8yOT+MzwP9klg UU4w77344O1ggNv+HofTkRqtwP4beTf4iRn+enY3mwFB+KgsgH/4pEoqOv4gD08ByUT6JtQyP/92V NM56IFWXzXARJTfoBZrpc/YE27FLcm8kBMG5tI1ZCuAJlim077+ji7h06f4AOi3qyLE5RlM+Uv+Rn VwdXk8yTGsNZa3uZHY5Jse2L7QwpuD+VlUiMgalITYvn8DjR17FXJ87vC2DuQ4TqH1KtH7lIXEl2p NtKk/nY1k8hhUZ2VwIhvL6gCHl6fyGCUDExkVnNIntHTZjiETvIZ97Bn/ZQ8nRvir9yEsWEhaCsq1 Jr/rZ0Ew==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1lk8DF-000Ipv-Oe; Fri, 21 May 2021 16:41:25 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1lk8D5-000InF-VE for linux-arm-kernel@desiato.infradead.org; Fri, 21 May 2021 16:41:18 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=In-Reply-To:Content-Type:MIME-Version :References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=gXEH1c6l5fgSRvSNuV71mRCITt0wX12cgTLdcYjAnmw=; b=dHk+5QBZ/WLaBvQu1jxpWNE+v5 5O3SxObSYJrYjmG8CLwr1/0uOuw22CBKYFSwFcOsGcF/Ab/PQYkMDIeWE+X2bZ8IFr1l4ydd49HwK PHxHcTdD0waTCIaXpyc29E5KXRE+S3hB2ZpCB4FBEQC9MMpc9MV8hw0H2VVyB8Ia4rTLM25rGp/a1 IdQxSCmmbQlG5fFCT9GOa2RwrIygLFT9vJaumYCB29TaHowxjaNG2dkbVOwRfWnrHmZoCb5G38lcL ABBXCvATjuj7JS/Fe3rTk230khP/PKZE31T6JgRysvNJSjM55bkqYz/+tOd0PwWZpVtb0Nbzssyq+ s5/M7zww==; Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1lk8D2-00HHiH-Uo for linux-arm-kernel@lists.infradead.org; Fri, 21 May 2021 16:41:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C24061480; Fri, 21 May 2021 09:41:09 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.33.243]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 68D6E3F73B; Fri, 21 May 2021 09:41:08 -0700 (PDT) Date: Fri, 21 May 2021 17:41:05 +0100 From: Mark Rutland To: Joey Gouly Cc: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, james.morse@arm.com, maz@kernel.org, will@kernel.org, nd@arm.com Subject: Re: [PATCH v2 14/19] arm64: entry: handle all vectors with C Message-ID: <20210521164105.GC9239@C02TD0UTHF1T.local> References: <20210519123902.2452-1-mark.rutland@arm.com> <20210519123902.2452-15-mark.rutland@arm.com> <20210521155952.GD35816@e124191.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210521155952.GD35816@e124191.cambridge.arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210521_094113_115744_941D83EE X-CRM114-Status: GOOD ( 41.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, May 21, 2021 at 04:59:52PM +0100, Joey Gouly wrote: > Hi Mark, > > I like these clean ups to entry.S! > > On Wed, May 19, 2021 at 01:38:57PM +0100, Mark Rutland wrote: > > We have 16 architectural exception vectors, and depending on kernel > > configuration we handle 8 or 12 of these with C code, and we handle 8 or > > 4 of these as sepcial cases in the entry assembly. > > > > It would be nicer if the entry assembly were uniform for all exceptions, > > and we deferred any specific handling of the exceptions to C code. This > > way the entry assembly can be more easily templated without ifdeffery or > > special cases, and it's easier to modify the handling of these cases in > > future (e.g. to dump additional registers other context). > > > > This patch reworks the entry code so that we always have a C handle for > s/handle/handler/ > > every architectural exception vector, with the entry assembly being > > completely uniform. We now have to handle exceptions from EL1t and EL1h, > > and also have to handle exceptions from AArch32 even when the kernel is > > built without CONFIG_COMPAT. To make this clear and to simplify > > templating, we rename the top-level exception handlers with a consistent > > naming scheme: > > > > asm: __ > > c: ___handler > > > > .. where: > > > > is `el1t`, `el1h`, or `el0` > > Is there a reason against using `el0t`? `el0t` is used in the Arm ARM. > It would get rid of the weird empty arguments in the `kernel_ventry` > and `entry_handler` macros. To be honest, I simply hadn't thought about it, as I'd only needed to distingish EL1h and EL1t. Now that you say it, it does make sense to me do use `el0t` for consistency, so I'll take a look at that. > > > is `64` or `32` > > is `sync`, `irq`, `fiq`, or `error` > > > > ... e.g. > > > > asm: el1h_64_sync > > c: el1h_64_sync_handler > > > > ... with lower-level handlers simply using "el1" and "compat" as today. > > > > For unexpected exceptions, this information is passed to > > panic_unandled(), so it can report the specific vector an unexpected > > exception was taken from, e.g. > > > > | Unexpected 64-bit el1t sync exception > > > > For vectors we never expect to enter legitimately, the C code is > > gnerated using a macro to avoid code duplication. > > > > The `kernel_ventry` and `entry_handler` assembly macros are update to > s/update/updated/ > > handle the new naming scheme. In theory it should be possible to > > generate the entry functions at the same time as the vectors using a > > single table, but this will require reworking the linker script to split > > the two into separate sections, so for now we duplicate the two. > > > > Signed-off-by: Mark Rutland > > Cc: Catalin Marinas > > Cc: James Morse > > Cc: Marc Zyngier > > Cc: Will Deacon > > --- > > arch/arm64/include/asm/exception.h | 31 +++++--- > > arch/arm64/kernel/entry-common.c | 51 +++++++------ > > arch/arm64/kernel/entry.S | 146 ++++++++++++------------------------- > > 3 files changed, 92 insertions(+), 136 deletions(-) > > > > diff --git a/arch/arm64/include/asm/exception.h b/arch/arm64/include/asm/exception.h > > index 4284ee57a9a5..40a3a20dca1c 100644 > > --- a/arch/arm64/include/asm/exception.h > > +++ b/arch/arm64/include/asm/exception.h > > @@ -31,18 +31,25 @@ static inline u32 disr_to_esr(u64 disr) > > return esr; > > } > > > > -asmlinkage void el1_sync_handler(struct pt_regs *regs); > > -asmlinkage void el1_irq_handler(struct pt_regs *regs); > > -asmlinkage void el1_fiq_handler(struct pt_regs *regs); > > -asmlinkage void el1_error_handler(struct pt_regs *regs); > > -asmlinkage void el0_sync_handler(struct pt_regs *regs); > > -asmlinkage void el0_irq_handler(struct pt_regs *regs); > > -asmlinkage void el0_fiq_handler(struct pt_regs *regs); > > -asmlinkage void el0_error_handler(struct pt_regs *regs); > > -asmlinkage void el0_sync_compat_handler(struct pt_regs *regs); > > -asmlinkage void el0_irq_compat_handler(struct pt_regs *regs); > > -asmlinkage void el0_fiq_compat_handler(struct pt_regs *regs); > > -asmlinkage void el0_error_compat_handler(struct pt_regs *regs); > > +asmlinkage void el1t_64_sync_handler(struct pt_regs *regs); > > +asmlinkage void el1t_64_irq_handler(struct pt_regs *regs); > > +asmlinkage void el1t_64_fiq_handler(struct pt_regs *regs); > > +asmlinkage void el1t_64_error_handler(struct pt_regs *regs); > > + > > +asmlinkage void el1h_64_sync_handler(struct pt_regs *regs); > > +asmlinkage void el1h_64_irq_handler(struct pt_regs *regs); > > +asmlinkage void el1h_64_fiq_handler(struct pt_regs *regs); > > +asmlinkage void el1h_64_error_handler(struct pt_regs *regs); > > + > > +asmlinkage void el0_64_sync_handler(struct pt_regs *regs); > > +asmlinkage void el0_64_irq_handler(struct pt_regs *regs); > > +asmlinkage void el0_64_fiq_handler(struct pt_regs *regs); > > +asmlinkage void el0_64_error_handler(struct pt_regs *regs); > > + > > +asmlinkage void el0_32_sync_handler(struct pt_regs *regs); > > +asmlinkage void el0_32_irq_handler(struct pt_regs *regs); > > +asmlinkage void el0_32_fiq_handler(struct pt_regs *regs); > > +asmlinkage void el0_32_error_handler(struct pt_regs *regs); > > > > asmlinkage void call_on_irq_stack(struct pt_regs *regs, > > void (*func)(struct pt_regs *)); > > Can you remove `bad_mode` from this header? (Further down, not shown here) > > Also there is a reference to `bad_mode` in `traps.c`. Sure; I'll rip both of those out. > > static void noinstr el1_abort(struct pt_regs *regs, unsigned long esr) > > { > > unsigned long far = read_sysreg(far_el1); > > @@ -271,7 +271,7 @@ static void noinstr el1_inv(struct pt_regs *regs, unsigned long esr) > > { > > enter_from_kernel_mode(regs); > > local_daif_inherit(regs); > > - bad_mode(regs, 0, esr); > > + __panic_unhandled(regs, "el1h sync", esr); > > local_daif_mask(); > > exit_to_kernel_mode(regs); > > This is never going to actually exit to kernel mode, is it? The panic > should stop that. Correct. Now that __panic_unhandled() does NMI entry work, we can remove el1_inv() and have el1h_64_sync_handler() call __panic_unhandled() directly. I'll do that as a followup patch, since it's a slight (but deliberate) behavioural change. > Minor comments / questions, but otherwise: > > Reviewed-by: Joey Gouly Thanks! Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel