From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-21.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 932E7C04FF3 for ; Mon, 24 May 2021 09:26:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6D06E610C7 for ; Mon, 24 May 2021 09:26:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232549AbhEXJ1m (ORCPT ); Mon, 24 May 2021 05:27:42 -0400 Received: from mga06.intel.com ([134.134.136.31]:49299 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232545AbhEXJ1l (ORCPT ); Mon, 24 May 2021 05:27:41 -0400 IronPort-SDR: WvoqCkZJaT9HajsEpKNI64TcTtcXMkNvPnULzO8QU6IqqFm5F82uWX4iSGnh0XEozg3czIm7Bi 0ybqJzR9V0cw== X-IronPort-AV: E=McAfee;i="6200,9189,9993"; a="263104318" X-IronPort-AV: E=Sophos;i="5.82,319,1613462400"; d="scan'208";a="263104318" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2021 02:26:10 -0700 IronPort-SDR: dDXyde/0bQZfpEFSxfwGo+Y0yTNs1UEuEcj+Qdq8kH2EuYDScl8kiNjknrbj6PhAOK0qCyzt+v vNcylzO0IXTw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,319,1613462400"; d="scan'208";a="478450457" Received: from inlubt0177.iind.intel.com ([10.223.67.91]) by fmsmga002.fm.intel.com with ESMTP; 24 May 2021 02:26:08 -0700 From: lakshmi.sowjanya.d@intel.com To: linus.walleij@linaro.org Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, lakshmi.bai.raja.subramanian@intel.com, tamal.saha@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH 1/2] dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver Date: Mon, 24 May 2021 14:56:04 +0530 Message-Id: <20210524092605.734-2-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210524092605.734-1-lakshmi.sowjanya.d@intel.com> References: <20210524092605.734-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org From: "D, Lakshmi Sowjanya" Add Device Tree bindings documentation for Intel Keem Bay SoC's pin controller. Add entry for INTEL Keem Bay pinctrl driver in MAINTAINERS file Signed-off-by: Vineetha G. Jaya Kumaran Signed-off-by: Vijayakannan Ayyathurai Signed-off-by: D, Lakshmi Sowjanya Acked-by: Mark Gross --- .../pinctrl/intel,pinctrl-keembay.yaml | 135 ++++++++++++++++++ MAINTAINERS | 5 + 2 files changed, 140 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml new file mode 100644 index 000000000000..8d45eddf972f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/intel,pinctrl-keembay.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay pin controller Device Tree Bindings + +maintainers: + - Lakshmi Sowjanya D + +description: | + Intel Keem Bay SoC integrates a pin controller which enables control + of pin directions, input/output values and configuration + for a total of 80 pins. + +properties: + compatible: + const: intel,keembay-pinctrl + + reg: + maxItems: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + interrupts: + description: + Specifies the interrupt lines to be used by the controller. + maxItems: 8 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + +patternProperties: + '^.$': + type: object + + description: + Child nodes can be specified to contain pin configuration information, + which can then be utilized by pinctrl client devices. + The following properties are supported. + + properties: + pins: + description: | + The name(s) of the pins to be configured in the child node. + Supported pin names are "GPIO0" up to "GPIO79". + + bias-disable: + type: boolean + + bias-pull-down: + type: boolean + + bias-pull-up: + type: boolean + + drive-strength: + enum: [2, 4, 8, 12] + + bias-bus-hold: + type: boolean + + input-schmitt-enable: + type: boolean + + slew-rate: + description: | + 0: Fast + 1: Slow + enum: [0, 1] + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + - interrupts + - interrupt-controller + - '#interrupt-cells' + +examples: + - | + #include + #include + // Example 1 + pinctrl@600B0000 { + compatible = "intel,keembay-pinctrl"; + reg = <0x600b0000 0x88>, + <0x600b0190 0x1ac>; + gpio-controller; + #gpio-cells = <0x2>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + }; + + // Example 2 + pinctrl@600C0000 { + compatible = "intel,keembay-pinctrl"; + reg = <0x600c0000 0x88>, + <0x600c0190 0x1ac>; + gpio-controller; + #gpio-cells = <0x2>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-controller; + #interrupt-cells = <2>; + + spi_pinconf { + pins = "GPIO10", "GPIO11"; + drive-strength = <4>; + bias-pull-down; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 81e1edeceae4..1991899c12e1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14445,6 +14445,11 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git F: drivers/pinctrl/intel/ +PIN CONTROLLER - KEEMBAY +M: Lakshmi Sowjanya D +S: Supported +F: drivers/pinctrl/pinctrl-keembay* + PIN CONTROLLER - MEDIATEK M: Sean Wang L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) -- 2.17.1