From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEE0DC2B9F7 for ; Mon, 24 May 2021 16:53:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B6F4761406 for ; Mon, 24 May 2021 16:53:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B6F4761406 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HSEIDIfnfWmjg8tYkhLaotuUTGIyPrntSXTHwiqiYlY=; b=LCuD1MvR3hlpa6 WklDAd2oGYsJ24n+bI8bNG4GRDfxph4Itf6p+Ck/wVidqCQBxM3UINzbd/2fkdLVUSV+SEbYWSNI3 hLjGuVCUz39ELa6bj2e3gHJLgZjUJULnaPlVUGcVO3orvvSr+FpMLOtG1o+hFDU5kgJuExkhGKj0g 03AGmCBYhueSfILMZKnJoWQ7bnQJ2IvmV4X5W33gAbG6Lj0CK6SoIwU1NoCWeHYjTBnJpu+H0Owvx XqX9LMUnwJtemb7geCSZQJ/tigZnLVfw2d5FNMOfeL1j/3gN5txHhcIb19cwGKfkyVGeJ55UD9AVU vu/cAKsWoF3RRj/BypZw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1llDn2-001AV8-GG; Mon, 24 May 2021 16:50:53 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1ll7HN-000oTZ-Cv for linux-arm-kernel@lists.infradead.org; Mon, 24 May 2021 09:53:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 491BD31B; Mon, 24 May 2021 02:53:27 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.38.161]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E04FC3F719; Mon, 24 May 2021 02:53:24 -0700 (PDT) Date: Mon, 24 May 2021 10:53:16 +0100 From: Mark Rutland To: Ard Biesheuvel Cc: Fuad Tabba , Linux ARM , Will Deacon , Catalin Marinas , Marc Zyngier , James Morse , Alexandru Elisei , Suzuki K Poulose , Robin Murphy Subject: Re: [PATCH v4 04/18] arm64: Do not enable uaccess for flush_icache_range Message-ID: <20210524095316.GA1040@C02TD0UTHF1T.local> References: <20210524083001.2586635-1-tabba@google.com> <20210524083001.2586635-5-tabba@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210524_025345_578436_5B6EB206 X-CRM114-Status: GOOD ( 28.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, May 24, 2021 at 11:41:53AM +0200, Ard Biesheuvel wrote: > On Mon, 24 May 2021 at 11:20, Fuad Tabba wrote: > > > > Hi Ard, > > > > > > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > > > > index 2d881f34dd9d..7c54bcbf5a36 100644 > > > > --- a/arch/arm64/mm/cache.S > > > > +++ b/arch/arm64/mm/cache.S > > > > @@ -14,6 +14,34 @@ > > > > #include > > > > #include > > > > > > > > +/* > > > > + * __flush_cache_range(start,end) [fixup] > > > > + * > > > > + * Ensure that the I and D caches are coherent within specified region. > > > > + * This is typically used when code has been written to a memory region, > > > > + * and will be executed. > > > > + * > > > > + * - start - virtual start address of region > > > > + * - end - virtual end address of region > > > > + * - fixup - optional label to branch to on user fault > > > > + */ > > > > +.macro __flush_cache_range, fixup > > > > +alternative_if ARM64_HAS_CACHE_IDC > > > > + dsb ishst > > > > > > Should this perhaps be dsb ish? IIUC, ishst does not synchronize on > > > completion of cache maintenance, and while that is implicit on this > > > code path, I'd still assume it needs to complete before carrying on. > > > Or does IDC not require this? > > > > I'm not sure; ishst in this patch is unchanged (just moved to the > > macro). Reading the Arm ARM (B2-143) I think that ishst is correct: > > > > """ > > CTR_EL0.{DIC, IDC} == {0, 1} > > > > The write is complete for the shareability domain. Subsequently the > > location has been invalidated to the Point of unification (PoU) from > > the instruction cache, and that invalidation is complete for the > > shareability domain. > > > > CTR_EL0.{DIC, IDC} == {1, 1} > > > > The write is complete for the shareability domain. > > """ > > > > Does my interpretation sound right to you? > > > > Thanks for digging that up. > > So IDC does guarantee that completing the store is sufficient for the > I-side to observe it, so I think your interpretation is correct. FWIW, that's muy understanding too. Ths idea with IDC is that when instructions fetches look in data/unified caches these lookups are made coherently (and the results may then be allocated into I-caches), so there's no architectural requirement for data cache maintenance, but we need to ensure completion for ordering against instruction fetches. The requirement is similar to that for translation table updates, where until ARMv7's multiprocessing extension we required data cache maintenance, but these days the fetches are coherent on the data side, and for similar ordering reasons we complete writes with DSB ISHST. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel