From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Anshuman Gupta <anshuman.gupta@intel.com>, Huang Sean Z <sean.z.huang@intel.com>, dri-devel@lists.freedesktop.org, Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>, Gaurav Kumar <kumar.gaurav@intel.com>, Bommu Krishnaiah <krishnaiah.bommu@intel.com> Subject: [PATCH v4 15/17] drm/i915/pxp: Add plane decryption support Date: Mon, 24 May 2021 22:48:01 -0700 [thread overview] Message-ID: <20210525054803.7387-16-daniele.ceraolospurio@intel.com> (raw) In-Reply-To: <20210525054803.7387-1-daniele.ceraolospurio@intel.com> From: Anshuman Gupta <anshuman.gupta@intel.com> Add support to enable/disable PLANE_SURF Decryption Request bit. It requires only to enable plane decryption support when following condition met. 1. PXP session is enabled. 2. Buffer object is protected. v2: - Used gen fb obj user_flags instead gem_object_metadata. [Krishna] v3: - intel_pxp_gem_object_status() API changes. v4: use intel_pxp_is_active (Daniele) v5: rebase and use the new protected object status checker (Daniele) v6: used plane state for plane_decryption to handle async flip as suggested by Ville. v7: check pxp session while plane decrypt state computation. [Ville] removed pointless code. [Ville] v8 (Daniele): update PXP check Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Cc: Huang Sean Z <sean.z.huang@intel.com> Cc: Gaurav Kumar <kumar.gaurav@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> --- .../gpu/drm/i915/display/intel_atomic_plane.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ .../gpu/drm/i915/display/intel_display_types.h | 3 +++ .../gpu/drm/i915/display/skl_universal_plane.c | 15 ++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 1 + 5 files changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 36f52a1d7552..88b3272c0b00 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -41,6 +41,7 @@ #include "intel_display_types.h" #include "intel_pm.h" #include "intel_sprite.h" +#include "pxp/intel_pxp.h" static void intel_plane_state_reset(struct intel_plane_state *plane_state, struct intel_plane *plane) @@ -383,6 +384,14 @@ intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id) return NULL; } +static int bo_has_valid_encryption(const struct drm_i915_gem_object *obj) +{ + struct drm_i915_private *i915 = to_i915(obj->base.dev); + + return i915_gem_object_has_valid_protection(obj) && + intel_pxp_is_active(&i915->gt.pxp); +} + int intel_plane_atomic_check(struct intel_atomic_state *state, struct intel_plane *plane) { @@ -397,6 +406,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, intel_atomic_get_old_crtc_state(state, crtc); struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + const struct drm_framebuffer *fb; if (new_crtc_state && new_crtc_state->bigjoiner_slave) { struct intel_plane *master_plane = @@ -413,6 +423,12 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, new_master_plane_state, crtc); + fb = new_plane_state->hw.fb; + if (fb) + new_plane_state->decrypt = bo_has_valid_encryption(intel_fb_obj(fb)); + else + new_plane_state->decrypt = old_plane_state->decrypt; + new_plane_state->uapi.visible = false; if (!new_crtc_state) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0bb2e582c87f..f7f5374114ad 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -9767,6 +9767,10 @@ static int intel_atomic_check_async(struct intel_atomic_state *state) drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n"); return -EINVAL; } + + /* plane decryption is allow to change only in synchronous flips */ + if (old_plane_state->decrypt != new_plane_state->decrypt) + return -EINVAL; } return 0; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ce05475ad560..6b5dab9e1c40 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -621,6 +621,9 @@ struct intel_plane_state { struct intel_fb_view view; + /* Plane pxp decryption state */ + bool decrypt; + /* plane control register */ u32 ctl; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 59e032f3687a..2c8e88e8ad83 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -18,6 +18,7 @@ #include "intel_sprite.h" #include "skl_scaler.h" #include "skl_universal_plane.h" +#include "pxp/intel_pxp.h" static const u32 skl_plane_formats[] = { DRM_FORMAT_C8, @@ -997,7 +998,7 @@ skl_program_plane(struct intel_plane *plane, u8 alpha = plane_state->hw.alpha >> 8; u32 plane_color_ctl = 0, aux_dist = 0; unsigned long irqflags; - u32 keymsk, keymax; + u32 keymsk, keymax, plane_surf; u32 plane_ctl = plane_state->ctl; plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -1086,8 +1087,16 @@ skl_program_plane(struct intel_plane *plane, * the control register just before the surface register. */ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + surf_addr); + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr; + + /* + * FIXME: pxp session invalidation can hit any time even at time of commit + * or after the commit, display content will be garbage. + */ + if (plane_state->decrypt) + plane_surf |= PLANE_SURF_DECRYPT; + + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 297671d78076..b3eaf45ae3ab 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7284,6 +7284,7 @@ enum { #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) #define PLANE_SURF(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) +#define PLANE_SURF_DECRYPT REG_BIT(2) #define _PLANE_OFFSET_1_B 0x711a4 #define _PLANE_OFFSET_2_B 0x712a4 -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> To: intel-gfx@lists.freedesktop.org Cc: Huang Sean Z <sean.z.huang@intel.com>, dri-devel@lists.freedesktop.org, Gaurav Kumar <kumar.gaurav@intel.com>, Bommu Krishnaiah <krishnaiah.bommu@intel.com> Subject: [Intel-gfx] [PATCH v4 15/17] drm/i915/pxp: Add plane decryption support Date: Mon, 24 May 2021 22:48:01 -0700 [thread overview] Message-ID: <20210525054803.7387-16-daniele.ceraolospurio@intel.com> (raw) In-Reply-To: <20210525054803.7387-1-daniele.ceraolospurio@intel.com> From: Anshuman Gupta <anshuman.gupta@intel.com> Add support to enable/disable PLANE_SURF Decryption Request bit. It requires only to enable plane decryption support when following condition met. 1. PXP session is enabled. 2. Buffer object is protected. v2: - Used gen fb obj user_flags instead gem_object_metadata. [Krishna] v3: - intel_pxp_gem_object_status() API changes. v4: use intel_pxp_is_active (Daniele) v5: rebase and use the new protected object status checker (Daniele) v6: used plane state for plane_decryption to handle async flip as suggested by Ville. v7: check pxp session while plane decrypt state computation. [Ville] removed pointless code. [Ville] v8 (Daniele): update PXP check Cc: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Cc: Huang Sean Z <sean.z.huang@intel.com> Cc: Gaurav Kumar <kumar.gaurav@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> --- .../gpu/drm/i915/display/intel_atomic_plane.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ .../gpu/drm/i915/display/intel_display_types.h | 3 +++ .../gpu/drm/i915/display/skl_universal_plane.c | 15 ++++++++++++--- drivers/gpu/drm/i915/i915_reg.h | 1 + 5 files changed, 36 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 36f52a1d7552..88b3272c0b00 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -41,6 +41,7 @@ #include "intel_display_types.h" #include "intel_pm.h" #include "intel_sprite.h" +#include "pxp/intel_pxp.h" static void intel_plane_state_reset(struct intel_plane_state *plane_state, struct intel_plane *plane) @@ -383,6 +384,14 @@ intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id) return NULL; } +static int bo_has_valid_encryption(const struct drm_i915_gem_object *obj) +{ + struct drm_i915_private *i915 = to_i915(obj->base.dev); + + return i915_gem_object_has_valid_protection(obj) && + intel_pxp_is_active(&i915->gt.pxp); +} + int intel_plane_atomic_check(struct intel_atomic_state *state, struct intel_plane *plane) { @@ -397,6 +406,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, intel_atomic_get_old_crtc_state(state, crtc); struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + const struct drm_framebuffer *fb; if (new_crtc_state && new_crtc_state->bigjoiner_slave) { struct intel_plane *master_plane = @@ -413,6 +423,12 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, new_master_plane_state, crtc); + fb = new_plane_state->hw.fb; + if (fb) + new_plane_state->decrypt = bo_has_valid_encryption(intel_fb_obj(fb)); + else + new_plane_state->decrypt = old_plane_state->decrypt; + new_plane_state->uapi.visible = false; if (!new_crtc_state) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 0bb2e582c87f..f7f5374114ad 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -9767,6 +9767,10 @@ static int intel_atomic_check_async(struct intel_atomic_state *state) drm_dbg_kms(&i915->drm, "Color range cannot be changed in async flip\n"); return -EINVAL; } + + /* plane decryption is allow to change only in synchronous flips */ + if (old_plane_state->decrypt != new_plane_state->decrypt) + return -EINVAL; } return 0; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ce05475ad560..6b5dab9e1c40 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -621,6 +621,9 @@ struct intel_plane_state { struct intel_fb_view view; + /* Plane pxp decryption state */ + bool decrypt; + /* plane control register */ u32 ctl; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 59e032f3687a..2c8e88e8ad83 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -18,6 +18,7 @@ #include "intel_sprite.h" #include "skl_scaler.h" #include "skl_universal_plane.h" +#include "pxp/intel_pxp.h" static const u32 skl_plane_formats[] = { DRM_FORMAT_C8, @@ -997,7 +998,7 @@ skl_program_plane(struct intel_plane *plane, u8 alpha = plane_state->hw.alpha >> 8; u32 plane_color_ctl = 0, aux_dist = 0; unsigned long irqflags; - u32 keymsk, keymax; + u32 keymsk, keymax, plane_surf; u32 plane_ctl = plane_state->ctl; plane_ctl |= skl_plane_ctl_crtc(crtc_state); @@ -1086,8 +1087,16 @@ skl_program_plane(struct intel_plane *plane, * the control register just before the surface register. */ intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl); - intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), - intel_plane_ggtt_offset(plane_state) + surf_addr); + plane_surf = intel_plane_ggtt_offset(plane_state) + surf_addr; + + /* + * FIXME: pxp session invalidation can hit any time even at time of commit + * or after the commit, display content will be garbage. + */ + if (plane_state->decrypt) + plane_surf |= PLANE_SURF_DECRYPT; + + intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), plane_surf); spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 297671d78076..b3eaf45ae3ab 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7284,6 +7284,7 @@ enum { #define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) #define PLANE_SURF(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) +#define PLANE_SURF_DECRYPT REG_BIT(2) #define _PLANE_OFFSET_1_B 0x711a4 #define _PLANE_OFFSET_2_B 0x712a4 -- 2.29.2 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2021-05-25 5:48 UTC|newest] Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-25 5:47 [PATCH v4 00/17] drm/i915: Introduce Intel PXP Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-05-25 5:47 ` [PATCH v4 01/17] drm/i915/pxp: Define PXP component interface Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-05-25 5:47 ` [PATCH v4 02/17] mei: pxp: export pavp client to me client bus Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-06-02 19:10 ` Rodrigo Vivi 2021-06-02 19:10 ` [Intel-gfx] " Rodrigo Vivi 2021-05-25 5:47 ` [PATCH v4 03/17] drm/i915/pxp: define PXP device flag and kconfig Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-05-25 5:47 ` [PATCH v4 04/17] drm/i915/gt: Export the pinned context constructor and destructor Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-06-01 20:20 ` Rodrigo Vivi 2021-06-01 20:20 ` [Intel-gfx] " Rodrigo Vivi 2021-06-01 21:23 ` Daniele Ceraolo Spurio 2021-06-01 21:23 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-06-02 18:18 ` Rodrigo Vivi 2021-06-02 18:18 ` [Intel-gfx] " Rodrigo Vivi 2021-05-25 5:47 ` [PATCH v4 05/17] drm/i915/pxp: allocate a vcs context for pxp usage Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-06-01 20:24 ` Rodrigo Vivi 2021-06-01 20:24 ` Rodrigo Vivi 2021-05-25 5:47 ` [PATCH v4 06/17] drm/i915/pxp: Implement funcs to create the TEE channel Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-06-01 20:26 ` Rodrigo Vivi 2021-06-01 20:26 ` [Intel-gfx] " Rodrigo Vivi 2021-06-03 0:07 ` Teres Alexis, Alan Previn 2021-06-03 0:07 ` Teres Alexis, Alan Previn 2021-05-25 5:47 ` [PATCH v4 07/17] drm/i915/pxp: set KCR reg init Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-05-25 5:47 ` [PATCH v4 08/17] drm/i915/pxp: Create the arbitrary session after boot Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-06-01 20:32 ` Rodrigo Vivi 2021-06-01 20:32 ` [Intel-gfx] " Rodrigo Vivi 2021-05-25 5:47 ` [PATCH v4 09/17] drm/i915/pxp: Implement arb session teardown Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-05-25 20:24 ` kernel test robot 2021-05-25 20:24 ` kernel test robot 2021-05-25 20:24 ` [Intel-gfx] " kernel test robot 2021-05-25 5:47 ` [PATCH v4 10/17] drm/i915/pxp: Implement PXP irq handler Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-06-02 16:06 ` Rodrigo Vivi 2021-06-02 16:06 ` Rodrigo Vivi 2021-06-02 16:08 ` Rodrigo Vivi 2021-06-02 16:08 ` Rodrigo Vivi 2021-05-25 5:47 ` [PATCH v4 11/17] drm/i915/pxp: interface for marking contexts as using protected content Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-05-27 10:10 ` Daniel Vetter 2021-05-27 10:10 ` Daniel Vetter 2021-05-25 5:47 ` [PATCH v4 12/17] drm/i915/pxp: start the arb session on demand Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-06-02 18:14 ` Rodrigo Vivi 2021-06-02 18:14 ` Rodrigo Vivi 2021-06-10 22:44 ` Daniele Ceraolo Spurio 2021-06-10 22:44 ` Daniele Ceraolo Spurio 2021-06-11 8:38 ` Rodrigo Vivi 2021-06-11 8:38 ` Rodrigo Vivi 2021-05-25 5:47 ` [PATCH v4 13/17] drm/i915/pxp: Enable PXP power management Daniele Ceraolo Spurio 2021-05-25 5:47 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-06-02 16:20 ` Rodrigo Vivi 2021-06-02 16:20 ` [Intel-gfx] " Rodrigo Vivi 2021-06-10 22:58 ` Daniele Ceraolo Spurio 2021-06-10 22:58 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-06-11 8:44 ` Rodrigo Vivi 2021-06-11 8:44 ` [Intel-gfx] " Rodrigo Vivi 2021-05-25 5:48 ` [PATCH v4 14/17] drm/i915/pxp: User interface for Protected buffer Daniele Ceraolo Spurio 2021-05-25 5:48 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-05-25 13:32 ` Daniel Vetter 2021-05-25 13:32 ` [Intel-gfx] " Daniel Vetter 2021-05-27 2:03 ` Daniele Ceraolo Spurio 2021-05-27 2:03 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-05-25 18:36 ` Tang, CQ 2021-05-25 18:36 ` Tang, CQ 2021-05-27 2:13 ` Daniele Ceraolo Spurio 2021-05-27 2:13 ` Daniele Ceraolo Spurio 2021-05-25 5:48 ` Daniele Ceraolo Spurio [this message] 2021-05-25 5:48 ` [Intel-gfx] [PATCH v4 15/17] drm/i915/pxp: Add plane decryption support Daniele Ceraolo Spurio 2021-06-02 18:23 ` Rodrigo Vivi 2021-06-02 18:23 ` [Intel-gfx] " Rodrigo Vivi 2021-05-25 5:48 ` [PATCH v4 16/17] drm/i915/pxp: black pixels on pxp disabled Daniele Ceraolo Spurio 2021-05-25 5:48 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-06-02 19:00 ` Rodrigo Vivi 2021-06-02 19:00 ` [Intel-gfx] " Rodrigo Vivi 2021-05-25 5:48 ` [PATCH v4 17/17] drm/i915/pxp: enable PXP for integrated Gen12 Daniele Ceraolo Spurio 2021-05-25 5:48 ` [Intel-gfx] " Daniele Ceraolo Spurio 2021-05-25 6:18 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Introduce Intel PXP Patchwork 2021-05-25 6:20 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2021-05-25 6:23 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork 2021-05-25 6:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2021-05-25 8:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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