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From: Vladimir Oltean <vladimir.oltean@nxp.com>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: Vladimir Oltean <olteanv@gmail.com>,
	Jakub Kicinski <kuba@kernel.org>,
	"David S. Miller" <davem@davemloft.net>,
	"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
	Andrew Lunn <andrew@lunn.ch>,
	Vivien Didelot <vivien.didelot@gmail.com>
Subject: Re: [PATCH net-next 03/13] net: dsa: sja1105: the 0x1F0000 SGMII "base address" is actually MDIO_MMD_VEND2
Date: Tue, 25 May 2021 09:12:56 +0000	[thread overview]
Message-ID: <20210525091255.yewlypibydfbux6b@skbuf> (raw)
In-Reply-To: <65e73b63-2c9b-b847-9221-91f23d2511d3@gmail.com>

On Mon, May 24, 2021 at 07:19:17PM -0700, Florian Fainelli wrote:
> 
> 
> On 5/24/2021 4:22 PM, Vladimir Oltean wrote:
> > From: Vladimir Oltean <vladimir.oltean@nxp.com>
> > 
> > Looking at the SGMII PCS from SJA1110, which is accessed indirectly
> > through a different base address as can be seen in the next patch, it
> > appears odd that the address accessed through indirection still
> > references the base address from the SJA1105S register map (first MDIO
> > register is at 0x1f0000), when it could index the SGMII registers
> > starting from zero.
> > 
> > Except that the 0x1f0000 is not a base address at all, it seems. It is
> > 0x1f << 16 | 0x0000, and 0x1f is coding for the vendor-specific MMD2.
> > So, it turns out, the Synopsys PCS implements all its registers inside
> > the vendor-specific MMDs 1 and 2 (0x1e and 0x1f). This explains why the
> > PCS has no overlaps (for the other MMDs) with other register regions of
> > the switch (because no other MMDs are implemented).
> > 
> > Change the code to remove the SGMII "base address" and explicitly encode
> > the MMD for reads/writes. This will become necessary for SJA1110 support.
> > 
> > Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> > ---
> 
> [snip]
> >  
> > @@ -1905,7 +1904,9 @@ int sja1105_static_config_reload(struct sja1105_private *priv,
> >  		mac[i].speed = SJA1105_SPEED_AUTO;
> >  
> >  		if (sja1105_supports_sgmii(priv, i))
> > -			bmcr[i] = sja1105_sgmii_read(priv, i, MII_BMCR);
> > +			bmcr[i] = sja1105_sgmii_read(priv, i,
> > +						     MDIO_MMD_VEND2,
> > +						     MDIO_CTRL1);
> 
> This appears different from what you had before?

MDIO_CTRL1 is the clause 45 alias of MII_BMCR, all in all it is still a
cosmetic change in line with the patch's idea of expressing accesses as
clause 45. I didn't replace the "bmcr" variable names because that would
have introduced more noise than I would have liked.

  reply	other threads:[~2021-05-25  9:13 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-24 23:22 [PATCH net-next 00/13] Add NXP SJA1110 support to the sja1105 DSA driver Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 01/13] net: dsa: sja1105: be compatible with "ethernet-ports" OF node name Vladimir Oltean
2021-05-25  2:13   ` Florian Fainelli
2021-05-24 23:22 ` [PATCH net-next 02/13] net: dsa: sja1105: allow SGMII PCS configuration to be per port Vladimir Oltean
2021-05-25  2:16   ` Florian Fainelli
2021-05-26 12:39     ` Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 03/13] net: dsa: sja1105: the 0x1F0000 SGMII "base address" is actually MDIO_MMD_VEND2 Vladimir Oltean
2021-05-25  2:19   ` Florian Fainelli
2021-05-25  9:12     ` Vladimir Oltean [this message]
2021-05-25  2:40   ` Andrew Lunn
2021-05-24 23:22 ` [PATCH net-next 04/13] net: dsa: sja1105: cache the phy-mode port property Vladimir Oltean
2021-05-25  2:19   ` Florian Fainelli
2021-05-24 23:22 ` [PATCH net-next 05/13] net: dsa: sja1105: add a PHY interface type compatibility matrix Vladimir Oltean
2021-05-25  2:23   ` Florian Fainelli
2021-05-26 12:37     ` Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 06/13] net: dsa: sja1105: add a translation table for port speeds Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 07/13] net: dsa: sja1105: always keep RGMII ports in the MAC role Vladimir Oltean
2021-05-25  2:24   ` Florian Fainelli
2021-05-24 23:22 ` [PATCH net-next 08/13] net: dsa: sja1105: some table entries are always present when read dynamically Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 09/13] dt-bindings: net: dsa: sja1105: add compatible strings for SJA1110 Vladimir Oltean
2021-05-25  2:24   ` Florian Fainelli
2021-05-25 11:57     ` Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 10/13] net: dsa: sja1105: add support for the SJA1110 switch family Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 11/13] net: dsa: sja1105: register the MDIO buses for 100base-T1 and 100base-TX Vladimir Oltean
2021-05-25  2:18   ` Andrew Lunn
2021-05-25 11:54     ` Vladimir Oltean
2021-05-25 13:16       ` Andrew Lunn
2021-05-25 13:21         ` Vladimir Oltean
2021-05-25 13:43           ` Andrew Lunn
2021-05-26 11:52             ` Vladimir Oltean
2021-05-25  2:27   ` Florian Fainelli
2021-05-24 23:22 ` [PATCH net-next 12/13] net: dsa: sja1105: expose the SGMII PCS as an mdio_device Vladimir Oltean
2021-05-25  2:33   ` Andrew Lunn
2021-05-25  2:35   ` Florian Fainelli
2021-05-25 11:50     ` Vladimir Oltean
2021-05-24 23:22 ` [PATCH net-next 13/13] net: dsa: sja1105: add support for the SJA1110 SGMII/2500base-x PCS Vladimir Oltean
2021-05-25  2:39   ` Florian Fainelli
2021-05-25 11:47     ` Vladimir Oltean
2021-05-25  2:03 ` [PATCH net-next 00/13] Add NXP SJA1110 support to the sja1105 DSA driver Andrew Lunn
2021-05-26 12:51   ` Vladimir Oltean

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