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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 113/114] linux-user/aarch64: Enable hwcap bits for sve2 and related extensions
Date: Tue, 25 May 2021 16:07:35 +0100	[thread overview]
Message-ID: <20210525150736.32695-19-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210525150736.32695-1-peter.maydell@linaro.org>

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-92-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 linux-user/elfload.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 0e832b2649f..1ab97e38e08 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -648,8 +648,18 @@ static uint32_t get_elf_hwcap2(void)
     uint32_t hwcaps = 0;
 
     GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP);
+    GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2);
+    GET_FEATURE_ID(aa64_sve2_aes, ARM_HWCAP2_A64_SVEAES);
+    GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL);
+    GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM);
+    GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3);
+    GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4);
     GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2);
     GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT);
+    GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM);
+    GET_FEATURE_ID(aa64_sve_f32mm, ARM_HWCAP2_A64_SVEF32MM);
+    GET_FEATURE_ID(aa64_sve_f64mm, ARM_HWCAP2_A64_SVEF64MM);
+    GET_FEATURE_ID(aa64_i8mm, ARM_HWCAP2_A64_I8MM);
     GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG);
     GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI);
     GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE);
-- 
2.20.1



  parent reply	other threads:[~2021-05-25 16:45 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-25 15:07 [PULL 095/114] target/arm: Implement SVE2 FCVTLT Peter Maydell
2021-05-25 15:07 ` [PULL 096/114] target/arm: Implement SVE2 FCVTXNT, FCVTX Peter Maydell
2021-05-25 15:07 ` [PULL 097/114] target/arm: Implement SVE2 FLOGB Peter Maydell
2021-05-25 15:07 ` [PULL 098/114] target/arm: Share table of sve load functions Peter Maydell
2021-05-25 15:07 ` [PULL 099/114] target/arm: Tidy do_ldrq Peter Maydell
2021-05-25 15:07 ` [PULL 100/114] target/arm: Implement SVE2 LD1RO Peter Maydell
2021-05-25 15:07 ` [PULL 101/114] target/arm: Implement 128-bit ZIP, UZP, TRN Peter Maydell
2021-05-25 15:07 ` [PULL 102/114] target/arm: Implement SVE2 bitwise shift immediate Peter Maydell
2021-05-25 15:07 ` [PULL 103/114] target/arm: Move endian adjustment macros to vec_internal.h Peter Maydell
2021-05-25 15:07 ` [PULL 104/114] target/arm: Implement SVE2 fp multiply-add long Peter Maydell
2021-05-25 15:07 ` [PULL 105/114] target/arm: Implement aarch64 SUDOT, USDOT Peter Maydell
2021-05-25 15:07 ` [PULL 106/114] target/arm: Split out do_neon_ddda_fpst Peter Maydell
2021-05-25 15:07 ` [PULL 107/114] target/arm: Remove unused fpst from VDOT_scalar Peter Maydell
2021-05-25 15:07 ` [PULL 108/114] target/arm: Fix decode for VDOT (indexed) Peter Maydell
2021-05-25 15:07 ` [PULL 109/114] target/arm: Split out do_neon_ddda Peter Maydell
2021-05-25 15:07 ` [PULL 110/114] target/arm: Split decode of VSDOT and VUDOT Peter Maydell
2021-05-25 15:07 ` [PULL 111/114] target/arm: Implement aarch32 VSUDOT, VUSDOT Peter Maydell
2021-05-25 15:07 ` [PULL 112/114] target/arm: Implement integer matrix multiply accumulate Peter Maydell
2021-05-25 15:07 ` Peter Maydell [this message]
2021-05-25 15:07 ` [PULL 114/114] target/arm: Enable SVE2 and related extensions Peter Maydell

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