From: Kishon Vijay Abraham I <kishon@ti.com> To: Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org> Cc: <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Kishon Vijay Abraham I <kishon@ti.com>, Lokesh Vutla <lokeshvutla@ti.com> Subject: [PATCH v3 3/5] arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES Date: Wed, 26 May 2021 19:59:19 +0530 [thread overview] Message-ID: <20210526142921.12127-4-kishon@ti.com> (raw) In-Reply-To: <20210526142921.12127-1-kishon@ti.com> AM642 EVM has a x4 lane PCIe connector. Enable PCIe in RC mode here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index dad0efa961ed..8c27f563a390 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/mux/ti-serdes.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/net/ti-dp83867.h> @@ -466,3 +468,31 @@ &mailbox0_cluster7 { status = "disabled"; }; + +&serdes_ln_ctrl { + idle-states = <AM64_SERDES0_LANE0_PCIE0>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie0_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com> To: Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org> Cc: <linux-arm-kernel@lists.infradead.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, Kishon Vijay Abraham I <kishon@ti.com>, Lokesh Vutla <lokeshvutla@ti.com> Subject: [PATCH v3 3/5] arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES Date: Wed, 26 May 2021 19:59:19 +0530 [thread overview] Message-ID: <20210526142921.12127-4-kishon@ti.com> (raw) In-Reply-To: <20210526142921.12127-1-kishon@ti.com> AM642 EVM has a x4 lane PCIe connector. Enable PCIe in RC mode here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts index dad0efa961ed..8c27f563a390 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/mux/ti-serdes.h> #include <dt-bindings/leds/common.h> #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/net/ti-dp83867.h> @@ -466,3 +468,31 @@ &mailbox0_cluster7 { status = "disabled"; }; + +&serdes_ln_ctrl { + idle-states = <AM64_SERDES0_LANE0_PCIE0>; +}; + +&serdes0 { + serdes0_pcie_link: phy@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>; + }; +}; + +&pcie0_rc { + reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; +}; + +&pcie0_ep { + phys = <&serdes0_pcie_link>; + phy-names = "pcie-phy"; + num-lanes = <1>; + status = "disabled"; +}; -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-05-26 14:29 UTC|newest] Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-05-26 14:29 [PATCH v3 0/5] AM64: EVM/SK: Enable PCIe and USB Kishon Vijay Abraham I 2021-05-26 14:29 ` Kishon Vijay Abraham I 2021-05-26 14:29 ` [PATCH v3 1/5] arm64: dts: ti: k3-am64-main: Add SERDES DT node Kishon Vijay Abraham I 2021-05-26 14:29 ` Kishon Vijay Abraham I 2021-05-26 18:44 ` Nishanth Menon 2021-05-26 18:44 ` Nishanth Menon 2021-06-03 12:50 ` Kishon Vijay Abraham I 2021-06-03 12:50 ` Kishon Vijay Abraham I 2021-05-26 14:29 ` [PATCH v3 2/5] arm64: dts: ti: k3-am64-main: Add PCIe " Kishon Vijay Abraham I 2021-05-26 14:29 ` Kishon Vijay Abraham I 2021-05-26 18:51 ` Nishanth Menon 2021-05-26 18:51 ` Nishanth Menon 2021-06-03 14:18 ` Kishon Vijay Abraham I 2021-06-03 14:18 ` Kishon Vijay Abraham I 2021-05-26 14:29 ` Kishon Vijay Abraham I [this message] 2021-05-26 14:29 ` [PATCH v3 3/5] arm64: dts: ti: k3-am642-evm: Enable PCIe and SERDES Kishon Vijay Abraham I 2021-05-26 14:29 ` [PATCH v3 4/5] arm64: dts: ti: k3-am642-sk: Enable USB Super-Speed HOST port Kishon Vijay Abraham I 2021-05-26 14:29 ` Kishon Vijay Abraham I 2021-05-26 14:29 ` [PATCH v3 5/5] arm64: dts: ti: k3-am642-sk: Disable PCIe Kishon Vijay Abraham I 2021-05-26 14:29 ` Kishon Vijay Abraham I
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